* [PATCH v4 1/2] dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) @ 2025-02-17 20:21 ` Patrick Wildt 0 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-02-17 20:21 UTC (permalink / raw) To: linux-rockchip Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Jimmy Hon Document board compatible bindings for the MNT Reform 2 with it's RCORE SoM, which is based on Firefly's iCore-3588Q. Signed-off-by: Patrick Wildt <patrick@blueri.se> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes for v4: - Added acked-by Changes for v3: - Split DT as it's based on a Firefly iCore-3588Q SoM Changes for v2: - No changes Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 522a6f0450ea..e21c5c8fc2a3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -178,6 +178,13 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Firefly iCore-3588Q-based boards + items: + - enum: + - mntre,reform2-rcore + - const: firefly,icore-3588q + - const: rockchip,rk3588 + - description: Firefly Core-3588J-based boards items: - enum: -- 2.48.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 1/2] dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) @ 2025-02-17 20:21 ` Patrick Wildt 0 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-02-17 20:21 UTC (permalink / raw) To: linux-rockchip Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Jimmy Hon Document board compatible bindings for the MNT Reform 2 with it's RCORE SoM, which is based on Firefly's iCore-3588Q. Signed-off-by: Patrick Wildt <patrick@blueri.se> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes for v4: - Added acked-by Changes for v3: - Split DT as it's based on a Firefly iCore-3588Q SoM Changes for v2: - No changes Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 522a6f0450ea..e21c5c8fc2a3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -178,6 +178,13 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Firefly iCore-3588Q-based boards + items: + - enum: + - mntre,reform2-rcore + - const: firefly,icore-3588q + - const: rockchip,rk3588 + - description: Firefly Core-3588J-based boards items: - enum: -- 2.48.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 2025-02-17 20:21 ` Patrick Wildt @ 2025-02-17 20:22 ` Patrick Wildt -1 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-02-17 20:22 UTC (permalink / raw) To: linux-rockchip Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Jimmy Hon MNT Reform 2 is an open source laptop with replaceable CPU modules, including a version with the RK3588-based MNT RCORE[1], which is based on Firefly's iCore-3588Q SoM: - Rockchip RK3588 - Quad A76 and Quad A55 CPU - 6 TOPS NPU - up to 32GB LPDDR4x RAM - SD Card slot - Gigabit ethernet port - HDMI port - 2x mPCIe ports for WiFi or NVMe - 3x USB 3.0 Type-A HOST port [1] https://shop.mntre.com/products/mnt-reform Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Patrick Wildt <patrick@blueri.se> --- Changes for v4: - Added chassis-type. - Removed unused nodes. - Sorted nodes alphabetically. Changes for v3: - Split DT as it's based on a Firefly iCore-3588Q SoM. Changes for v2: - Aligned with bindings and schemas to appease DTB check warnings. - Aligned with format of other RK3588 boards for consistency. arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ 3 files changed, 788 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index def1222c1907..88381d9a20e3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 000000000000..898a7b29692f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 000000000000..936dd959524f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 10000 0>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + max-frequency = <40000000>; + no-sdio; + no-mmc; + no-1-8-v; + cap-sd-highspeed; + vqmmc-supply = <&vcc3v3_pcie30>; + vmmc-supply = <&vcc3v3_pcie30>; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; -- 2.48.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 @ 2025-02-17 20:22 ` Patrick Wildt 0 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-02-17 20:22 UTC (permalink / raw) To: linux-rockchip Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Jimmy Hon MNT Reform 2 is an open source laptop with replaceable CPU modules, including a version with the RK3588-based MNT RCORE[1], which is based on Firefly's iCore-3588Q SoM: - Rockchip RK3588 - Quad A76 and Quad A55 CPU - 6 TOPS NPU - up to 32GB LPDDR4x RAM - SD Card slot - Gigabit ethernet port - HDMI port - 2x mPCIe ports for WiFi or NVMe - 3x USB 3.0 Type-A HOST port [1] https://shop.mntre.com/products/mnt-reform Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Patrick Wildt <patrick@blueri.se> --- Changes for v4: - Added chassis-type. - Removed unused nodes. - Sorted nodes alphabetically. Changes for v3: - Split DT as it's based on a Firefly iCore-3588Q SoM. Changes for v2: - Aligned with bindings and schemas to appease DTB check warnings. - Aligned with format of other RK3588 boards for consistency. arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ 3 files changed, 788 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index def1222c1907..88381d9a20e3 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 000000000000..898a7b29692f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 000000000000..936dd959524f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 10000 0>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + max-frequency = <40000000>; + no-sdio; + no-mmc; + no-1-8-v; + cap-sd-highspeed; + vqmmc-supply = <&vcc3v3_pcie30>; + vmmc-supply = <&vcc3v3_pcie30>; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; -- 2.48.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 2025-02-17 20:22 ` Patrick Wildt @ 2025-02-22 23:38 ` Heiko Stuebner -1 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2025-02-22 23:38 UTC (permalink / raw) To: linux-rockchip, Patrick Wildt Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon Hi Patrick, Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > MNT Reform 2 is an open source laptop with replaceable CPU modules, > including a version with the RK3588-based MNT RCORE[1], which is based > on Firefly's iCore-3588Q SoM: > > - Rockchip RK3588 > - Quad A76 and Quad A55 CPU > - 6 TOPS NPU > - up to 32GB LPDDR4x RAM > - SD Card slot > - Gigabit ethernet port > - HDMI port > - 2x mPCIe ports for WiFi or NVMe > - 3x USB 3.0 Type-A HOST port > > [1] https://shop.mntre.com/products/mnt-reform > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > Signed-off-by: Patrick Wildt <patrick@blueri.se> bureaucracy question, what is Lukas' relationship with the patch? Two options: (1) Lukas initially developed the patch, then the "From:" should be set accordingly (2) Both of you developed it together, then we should have a Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> up there Some more style things below... > --- > Changes for v4: > - Added chassis-type. > - Removed unused nodes. > - Sorted nodes alphabetically. > Changes for v3: > - Split DT as it's based on a Firefly iCore-3588Q SoM. > Changes for v2: > - Aligned with bindings and schemas to appease DTB check warnings. > - Aligned with format of other RK3588 boards for consistency. > > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ > .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ > 3 files changed, 788 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index def1222c1907..88381d9a20e3 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > new file mode 100644 > index 000000000000..898a7b29692f > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > @@ -0,0 +1,451 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/pinctrl/rockchip.h> > + > +#include "rk3588.dtsi" > + > +/ { > + compatible = "firefly,icore-3588q", "rockchip,rk3588"; > + > + aliases { > + mmc0 = &sdhci; > + }; > +}; > + > +&cpu_b0 { > + cpu-supply = <&vdd_cpu_big0_s0>; > + mem-supply = <&vdd_cpu_big0_s0>; you don't need the unspecified mem-supply for the cpu cores, that is vendor-kernel voodoo and not part of the upstream binding. Same for all cores. > +}; > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > new file mode 100644 > index 000000000000..936dd959524f > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 MNT Research GmbH > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <dt-bindings/soc/rockchip,vop2.h> > +#include <dt-bindings/usb/pd.h> > + > +#include "rk3588-firefly-icore-3588q.dtsi" > + > +/ { > + model = "MNT Reform 2 with RCORE RK3588 Module"; > + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; > + chassis-type = "laptop"; > + > + aliases { > + ethernet0 = &gmac0; > + mmc1 = &sdmmc; > + }; > + > + chosen { > + stdout-path = "serial2:1500000n8"; > + }; > + > + backlight: backlight { > + compatible = "pwm-backlight"; > + pwms = <&pwm8 0 10000 0>; > + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; > + brightness-levels = <0 8 16 32 64 128 160 200 255>; > + default-brightness-level = <128>; please sort standard properties alphabetically (compatible at the top, status at the bottom, rest alphabetically) > + }; > + > +&pcie2x1l2 { > + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; > + pinctrl-0 = <&pcie2_0_rst>; more sorting > + status = "okay"; > +}; > + > +&pcie3x4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie3_reset>; > + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <1>; again sorting > + vpcie3v3-supply = <&vcc3v3_pcie30>; > + status = "okay"; > +}; > + > +&sdmmc { > + bus-width = <4>; > + max-frequency = <40000000>; > + no-sdio; > + no-mmc; > + no-1-8-v; > + cap-sd-highspeed; > + vqmmc-supply = <&vcc3v3_pcie30>; > + vmmc-supply = <&vcc3v3_pcie30>; > + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; > + disable-wp; more sorting > + status = "okay"; > +}; > + Heiko ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 @ 2025-02-22 23:38 ` Heiko Stuebner 0 siblings, 0 replies; 10+ messages in thread From: Heiko Stuebner @ 2025-02-22 23:38 UTC (permalink / raw) To: linux-rockchip, Patrick Wildt Cc: linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon Hi Patrick, Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > MNT Reform 2 is an open source laptop with replaceable CPU modules, > including a version with the RK3588-based MNT RCORE[1], which is based > on Firefly's iCore-3588Q SoM: > > - Rockchip RK3588 > - Quad A76 and Quad A55 CPU > - 6 TOPS NPU > - up to 32GB LPDDR4x RAM > - SD Card slot > - Gigabit ethernet port > - HDMI port > - 2x mPCIe ports for WiFi or NVMe > - 3x USB 3.0 Type-A HOST port > > [1] https://shop.mntre.com/products/mnt-reform > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > Signed-off-by: Patrick Wildt <patrick@blueri.se> bureaucracy question, what is Lukas' relationship with the patch? Two options: (1) Lukas initially developed the patch, then the "From:" should be set accordingly (2) Both of you developed it together, then we should have a Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> up there Some more style things below... > --- > Changes for v4: > - Added chassis-type. > - Removed unused nodes. > - Sorted nodes alphabetically. > Changes for v3: > - Split DT as it's based on a Firefly iCore-3588Q SoM. > Changes for v2: > - Aligned with bindings and schemas to appease DTB check warnings. > - Aligned with format of other RK3588 boards for consistency. > > arch/arm64/boot/dts/rockchip/Makefile | 1 + > .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ > .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ > 3 files changed, 788 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index def1222c1907..88381d9a20e3 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > new file mode 100644 > index 000000000000..898a7b29692f > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > @@ -0,0 +1,451 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/pinctrl/rockchip.h> > + > +#include "rk3588.dtsi" > + > +/ { > + compatible = "firefly,icore-3588q", "rockchip,rk3588"; > + > + aliases { > + mmc0 = &sdhci; > + }; > +}; > + > +&cpu_b0 { > + cpu-supply = <&vdd_cpu_big0_s0>; > + mem-supply = <&vdd_cpu_big0_s0>; you don't need the unspecified mem-supply for the cpu cores, that is vendor-kernel voodoo and not part of the upstream binding. Same for all cores. > +}; > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > new file mode 100644 > index 000000000000..936dd959524f > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 MNT Research GmbH > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <dt-bindings/soc/rockchip,vop2.h> > +#include <dt-bindings/usb/pd.h> > + > +#include "rk3588-firefly-icore-3588q.dtsi" > + > +/ { > + model = "MNT Reform 2 with RCORE RK3588 Module"; > + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; > + chassis-type = "laptop"; > + > + aliases { > + ethernet0 = &gmac0; > + mmc1 = &sdmmc; > + }; > + > + chosen { > + stdout-path = "serial2:1500000n8"; > + }; > + > + backlight: backlight { > + compatible = "pwm-backlight"; > + pwms = <&pwm8 0 10000 0>; > + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; > + brightness-levels = <0 8 16 32 64 128 160 200 255>; > + default-brightness-level = <128>; please sort standard properties alphabetically (compatible at the top, status at the bottom, rest alphabetically) > + }; > + > +&pcie2x1l2 { > + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; > + pinctrl-0 = <&pcie2_0_rst>; more sorting > + status = "okay"; > +}; > + > +&pcie3x4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie3_reset>; > + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <1>; again sorting > + vpcie3v3-supply = <&vcc3v3_pcie30>; > + status = "okay"; > +}; > + > +&sdmmc { > + bus-width = <4>; > + max-frequency = <40000000>; > + no-sdio; > + no-mmc; > + no-1-8-v; > + cap-sd-highspeed; > + vqmmc-supply = <&vcc3v3_pcie30>; > + vmmc-supply = <&vcc3v3_pcie30>; > + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; > + disable-wp; more sorting > + status = "okay"; > +}; > + Heiko _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 2025-02-22 23:38 ` Heiko Stuebner @ 2025-03-01 10:32 ` Patrick Wildt -1 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-03-01 10:32 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip, linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon On Sun, Feb 23, 2025 at 12:38:40AM +0100, Heiko Stuebner wrote: > Hi Patrick, > > Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > > MNT Reform 2 is an open source laptop with replaceable CPU modules, > > including a version with the RK3588-based MNT RCORE[1], which is based > > on Firefly's iCore-3588Q SoM: > > > > - Rockchip RK3588 > > - Quad A76 and Quad A55 CPU > > - 6 TOPS NPU > > - up to 32GB LPDDR4x RAM > > - SD Card slot > > - Gigabit ethernet port > > - HDMI port > > - 2x mPCIe ports for WiFi or NVMe > > - 3x USB 3.0 Type-A HOST port > > > > [1] https://shop.mntre.com/products/mnt-reform > > > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > > Signed-off-by: Patrick Wildt <patrick@blueri.se> > > bureaucracy question, what is Lukas' relationship with the patch? > Two options: > (1) Lukas initially developed the patch, then the "From:" should be > set accordingly > (2) Both of you developed it together, then we should have a > Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> > up there > Thanks, will send a v5 with Co-developed-by tag added! :) > > Some more style things below... > Are there further execptions to the alphabetical rule? For regulators I often see min before max, which I think makes sense to understand the range but isn't technically alphabetical. The same for pinctrl-0 and pinctrl-names. Thanks, Patrick > > > --- > > Changes for v4: > > - Added chassis-type. > > - Removed unused nodes. > > - Sorted nodes alphabetically. > > Changes for v3: > > - Split DT as it's based on a Firefly iCore-3588Q SoM. > > Changes for v2: > > - Aligned with bindings and schemas to appease DTB check warnings. > > - Aligned with format of other RK3588 boards for consistency. > > > > arch/arm64/boot/dts/rockchip/Makefile | 1 + > > .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ > > .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ > > 3 files changed, 788 insertions(+) > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > > index def1222c1907..88381d9a20e3 100644 > > --- a/arch/arm64/boot/dts/rockchip/Makefile > > +++ b/arch/arm64/boot/dts/rockchip/Makefile > > @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > new file mode 100644 > > index 000000000000..898a7b29692f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > @@ -0,0 +1,451 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/pinctrl/rockchip.h> > > + > > +#include "rk3588.dtsi" > > + > > +/ { > > + compatible = "firefly,icore-3588q", "rockchip,rk3588"; > > + > > + aliases { > > + mmc0 = &sdhci; > > + }; > > +}; > > + > > +&cpu_b0 { > > + cpu-supply = <&vdd_cpu_big0_s0>; > > + mem-supply = <&vdd_cpu_big0_s0>; > > you don't need the unspecified mem-supply for the cpu cores, > that is vendor-kernel voodoo and not part of the upstream binding. > > Same for all cores. > > > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > new file mode 100644 > > index 000000000000..936dd959524f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > @@ -0,0 +1,336 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > > + * Copyright (c) 2024 MNT Research GmbH > > + */ > > + > > +/dts-v1/; > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/input/input.h> > > +#include <dt-bindings/pinctrl/rockchip.h> > > +#include <dt-bindings/soc/rockchip,vop2.h> > > +#include <dt-bindings/usb/pd.h> > > + > > +#include "rk3588-firefly-icore-3588q.dtsi" > > + > > +/ { > > + model = "MNT Reform 2 with RCORE RK3588 Module"; > > + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; > > + chassis-type = "laptop"; > > + > > + aliases { > > + ethernet0 = &gmac0; > > + mmc1 = &sdmmc; > > + }; > > + > > + chosen { > > + stdout-path = "serial2:1500000n8"; > > + }; > > + > > + backlight: backlight { > > + compatible = "pwm-backlight"; > > + pwms = <&pwm8 0 10000 0>; > > + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; > > + brightness-levels = <0 8 16 32 64 128 160 200 255>; > > + default-brightness-level = <128>; > > please sort standard properties alphabetically (compatible at the top, > status at the bottom, rest alphabetically) > > > + }; > > + > > +&pcie2x1l2 { > > + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; > > + pinctrl-0 = <&pcie2_0_rst>; > > more sorting > > > + status = "okay"; > > +}; > > + > > > +&pcie3x4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie3_reset>; > > + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; > > + num-lanes = <1>; > > again sorting > > > + vpcie3v3-supply = <&vcc3v3_pcie30>; > > + status = "okay"; > > +}; > > + > > > +&sdmmc { > > + bus-width = <4>; > > + max-frequency = <40000000>; > > + no-sdio; > > + no-mmc; > > + no-1-8-v; > > + cap-sd-highspeed; > > + vqmmc-supply = <&vcc3v3_pcie30>; > > + vmmc-supply = <&vcc3v3_pcie30>; > > + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; > > + disable-wp; > > more sorting > > > + status = "okay"; > > +}; > > + > > > Heiko > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 @ 2025-03-01 10:32 ` Patrick Wildt 0 siblings, 0 replies; 10+ messages in thread From: Patrick Wildt @ 2025-03-01 10:32 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip, linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon On Sun, Feb 23, 2025 at 12:38:40AM +0100, Heiko Stuebner wrote: > Hi Patrick, > > Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > > MNT Reform 2 is an open source laptop with replaceable CPU modules, > > including a version with the RK3588-based MNT RCORE[1], which is based > > on Firefly's iCore-3588Q SoM: > > > > - Rockchip RK3588 > > - Quad A76 and Quad A55 CPU > > - 6 TOPS NPU > > - up to 32GB LPDDR4x RAM > > - SD Card slot > > - Gigabit ethernet port > > - HDMI port > > - 2x mPCIe ports for WiFi or NVMe > > - 3x USB 3.0 Type-A HOST port > > > > [1] https://shop.mntre.com/products/mnt-reform > > > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > > Signed-off-by: Patrick Wildt <patrick@blueri.se> > > bureaucracy question, what is Lukas' relationship with the patch? > Two options: > (1) Lukas initially developed the patch, then the "From:" should be > set accordingly > (2) Both of you developed it together, then we should have a > Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> > up there > Thanks, will send a v5 with Co-developed-by tag added! :) > > Some more style things below... > Are there further execptions to the alphabetical rule? For regulators I often see min before max, which I think makes sense to understand the range but isn't technically alphabetical. The same for pinctrl-0 and pinctrl-names. Thanks, Patrick > > > --- > > Changes for v4: > > - Added chassis-type. > > - Removed unused nodes. > > - Sorted nodes alphabetically. > > Changes for v3: > > - Split DT as it's based on a Firefly iCore-3588Q SoM. > > Changes for v2: > > - Aligned with bindings and schemas to appease DTB check warnings. > > - Aligned with format of other RK3588 boards for consistency. > > > > arch/arm64/boot/dts/rockchip/Makefile | 1 + > > .../rockchip/rk3588-firefly-icore-3588q.dtsi | 451 ++++++++++++++++++ > > .../boot/dts/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ > > 3 files changed, 788 insertions(+) > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > > index def1222c1907..88381d9a20e3 100644 > > --- a/arch/arm64/boot/dts/rockchip/Makefile > > +++ b/arch/arm64/boot/dts/rockchip/Makefile > > @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > new file mode 100644 > > index 000000000000..898a7b29692f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi > > @@ -0,0 +1,451 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/pinctrl/rockchip.h> > > + > > +#include "rk3588.dtsi" > > + > > +/ { > > + compatible = "firefly,icore-3588q", "rockchip,rk3588"; > > + > > + aliases { > > + mmc0 = &sdhci; > > + }; > > +}; > > + > > +&cpu_b0 { > > + cpu-supply = <&vdd_cpu_big0_s0>; > > + mem-supply = <&vdd_cpu_big0_s0>; > > you don't need the unspecified mem-supply for the cpu cores, > that is vendor-kernel voodoo and not part of the upstream binding. > > Same for all cores. > > > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > new file mode 100644 > > index 000000000000..936dd959524f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts > > @@ -0,0 +1,336 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > > + * Copyright (c) 2024 MNT Research GmbH > > + */ > > + > > +/dts-v1/; > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/input/input.h> > > +#include <dt-bindings/pinctrl/rockchip.h> > > +#include <dt-bindings/soc/rockchip,vop2.h> > > +#include <dt-bindings/usb/pd.h> > > + > > +#include "rk3588-firefly-icore-3588q.dtsi" > > + > > +/ { > > + model = "MNT Reform 2 with RCORE RK3588 Module"; > > + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; > > + chassis-type = "laptop"; > > + > > + aliases { > > + ethernet0 = &gmac0; > > + mmc1 = &sdmmc; > > + }; > > + > > + chosen { > > + stdout-path = "serial2:1500000n8"; > > + }; > > + > > + backlight: backlight { > > + compatible = "pwm-backlight"; > > + pwms = <&pwm8 0 10000 0>; > > + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; > > + brightness-levels = <0 8 16 32 64 128 160 200 255>; > > + default-brightness-level = <128>; > > please sort standard properties alphabetically (compatible at the top, > status at the bottom, rest alphabetically) > > > + }; > > + > > +&pcie2x1l2 { > > + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; > > + pinctrl-0 = <&pcie2_0_rst>; > > more sorting > > > + status = "okay"; > > +}; > > + > > > +&pcie3x4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie3_reset>; > > + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; > > + num-lanes = <1>; > > again sorting > > > + vpcie3v3-supply = <&vcc3v3_pcie30>; > > + status = "okay"; > > +}; > > + > > > +&sdmmc { > > + bus-width = <4>; > > + max-frequency = <40000000>; > > + no-sdio; > > + no-mmc; > > + no-1-8-v; > > + cap-sd-highspeed; > > + vqmmc-supply = <&vcc3v3_pcie30>; > > + vmmc-supply = <&vcc3v3_pcie30>; > > + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; > > + disable-wp; > > more sorting > > > + status = "okay"; > > +}; > > + > > > Heiko > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 2025-03-01 10:32 ` Patrick Wildt @ 2025-03-01 11:10 ` Heiko Stübner -1 siblings, 0 replies; 10+ messages in thread From: Heiko Stübner @ 2025-03-01 11:10 UTC (permalink / raw) To: Patrick Wildt Cc: linux-rockchip, linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon Am Samstag, 1. März 2025, 11:32:06 MEZ schrieb Patrick Wildt: > On Sun, Feb 23, 2025 at 12:38:40AM +0100, Heiko Stuebner wrote: > > Hi Patrick, > > > > Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > > > MNT Reform 2 is an open source laptop with replaceable CPU modules, > > > including a version with the RK3588-based MNT RCORE[1], which is based > > > on Firefly's iCore-3588Q SoM: > > > > > > - Rockchip RK3588 > > > - Quad A76 and Quad A55 CPU > > > - 6 TOPS NPU > > > - up to 32GB LPDDR4x RAM > > > - SD Card slot > > > - Gigabit ethernet port > > > - HDMI port > > > - 2x mPCIe ports for WiFi or NVMe > > > - 3x USB 3.0 Type-A HOST port > > > > > > [1] https://shop.mntre.com/products/mnt-reform > > > > > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > > > Signed-off-by: Patrick Wildt <patrick@blueri.se> > > > > bureaucracy question, what is Lukas' relationship with the patch? > > Two options: > > (1) Lukas initially developed the patch, then the "From:" should be > > set accordingly > > (2) Both of you developed it together, then we should have a > > Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> > > up there > > > > Thanks, will send a v5 with Co-developed-by tag added! :) > > > > > Some more style things below... > > > > Are there further execptions to the alphabetical rule? For regulators > I often see min before max, which I think makes sense to understand > the range but isn't technically alphabetical. The same for pinctrl-0 > and pinctrl-names. The "preferred" rules are in [0], and in recent times I've come to appreciate not needing to explain exceptions ;-) . But I do see them as guidelines, especially in a leaf-dt (for a device) concessions are possible. So yes, I can definitly see min before max as beneficial and if you want to sort that way, that is fine by me Heiko [0] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 @ 2025-03-01 11:10 ` Heiko Stübner 0 siblings, 0 replies; 10+ messages in thread From: Heiko Stübner @ 2025-03-01 11:10 UTC (permalink / raw) To: Patrick Wildt Cc: linux-rockchip, linux-arm-kernel, devicetree, Kever Yang, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jimmy Hon Am Samstag, 1. März 2025, 11:32:06 MEZ schrieb Patrick Wildt: > On Sun, Feb 23, 2025 at 12:38:40AM +0100, Heiko Stuebner wrote: > > Hi Patrick, > > > > Am Montag, 17. Februar 2025, 21:22:28 MEZ schrieb Patrick Wildt: > > > MNT Reform 2 is an open source laptop with replaceable CPU modules, > > > including a version with the RK3588-based MNT RCORE[1], which is based > > > on Firefly's iCore-3588Q SoM: > > > > > > - Rockchip RK3588 > > > - Quad A76 and Quad A55 CPU > > > - 6 TOPS NPU > > > - up to 32GB LPDDR4x RAM > > > - SD Card slot > > > - Gigabit ethernet port > > > - HDMI port > > > - 2x mPCIe ports for WiFi or NVMe > > > - 3x USB 3.0 Type-A HOST port > > > > > > [1] https://shop.mntre.com/products/mnt-reform > > > > > > Signed-off-by: Lukas F. Hartmann <lukas@mntre.com> > > > Signed-off-by: Patrick Wildt <patrick@blueri.se> > > > > bureaucracy question, what is Lukas' relationship with the patch? > > Two options: > > (1) Lukas initially developed the patch, then the "From:" should be > > set accordingly > > (2) Both of you developed it together, then we should have a > > Co-Developed-by: Lukas F. Hartmann <lukas@mntre.com> > > up there > > > > Thanks, will send a v5 with Co-developed-by tag added! :) > > > > > Some more style things below... > > > > Are there further execptions to the alphabetical rule? For regulators > I often see min before max, which I think makes sense to understand > the range but isn't technically alphabetical. The same for pinctrl-0 > and pinctrl-names. The "preferred" rules are in [0], and in recent times I've come to appreciate not needing to explain exceptions ;-) . But I do see them as guidelines, especially in a leaf-dt (for a device) concessions are possible. So yes, I can definitly see min before max as beneficial and if you want to sort that way, that is fine by me Heiko [0] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-03-01 11:14 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-02-17 20:21 [PATCH v4 1/2] dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) Patrick Wildt 2025-02-17 20:21 ` Patrick Wildt 2025-02-17 20:22 ` [PATCH v4 2/2] arm64: dts: rockchip: add MNT Reform 2 Patrick Wildt 2025-02-17 20:22 ` Patrick Wildt 2025-02-22 23:38 ` Heiko Stuebner 2025-02-22 23:38 ` Heiko Stuebner 2025-03-01 10:32 ` Patrick Wildt 2025-03-01 10:32 ` Patrick Wildt 2025-03-01 11:10 ` Heiko Stübner 2025-03-01 11:10 ` Heiko Stübner
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