From: Chris Wilson <chris@chris-wilson.co.uk>
To: Dave Airlie <airlied@gmail.com>, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH] drm: micro optimise cache flushing
Date: Wed, 19 Sep 2012 08:50:18 +0100 [thread overview]
Message-ID: <275ffc$6li573@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1348017161-27475-1-git-send-email-airlied@gmail.com>
On Wed, 19 Sep 2012 11:12:41 +1000, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> We hit this a lot with i915 and although we'd like to engineer things to hit
> it a lot less, this commit at least makes it consume a few less cycles.
>
> from something containing
> movzwl 0x0(%rip),%r10d
> to
> add %r8,%rdx
>
> I only noticed it while using perf to profile something else.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
I would have thought this is something the compiler should, with the
appropriate hints, be smart enough to decide for itself as boot_cpu_data
should be constant once defined. *shrug*
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-09-19 7:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-19 1:12 [PATCH] drm: micro optimise cache flushing Dave Airlie
2012-09-19 7:50 ` Chris Wilson [this message]
2012-09-20 10:02 ` Jani Nikula
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