[PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk

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* [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
@ 2018-03-20  2:06 ` Lin Huang
  0 siblings, 0 replies; 14+ messages in thread
From: Lin Huang @ 2018-03-20  2:06 UTC (permalink / raw)
  To: heiko
  Cc: dbasehore, shawn.lin, briannorris, linux-rockchip, dianders,
	linux-clk, Lin Huang

Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.

Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- add more detail in commit message
Changes in v3:
- None

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3e57c6e..bca10d6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(9), 7, GFLAGS,
 			&rk3399_uart3_fracmux),
 
-	COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(3), 4, GFLAGS),
 
@@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(31), 8, GFLAGS),
 
 	/* sdio & sdmmc */
-	COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+	COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
 			RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(12), 13, GFLAGS),
 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
@ 2018-03-20  2:06 ` Lin Huang
  0 siblings, 0 replies; 14+ messages in thread
From: Lin Huang @ 2018-03-20  2:06 UTC (permalink / raw)
  To: heiko-4mtYJXux2i+zQB+pC5nmwQ
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, Lin Huang,
	shawn.lin-TNX95d0MmH7DzftRWevZcw,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.

Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v2:
- add more detail in commit message
Changes in v3:
- None

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3e57c6e..bca10d6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(9), 7, GFLAGS,
 			&rk3399_uart3_fracmux),
 
-	COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(3), 4, GFLAGS),
 
@@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(31), 8, GFLAGS),
 
 	/* sdio & sdmmc */
-	COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+	COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
 			RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(12), 13, GFLAGS),
 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:06   ` Lin Huang
  0 siblings, 0 replies; 14+ messages in thread
From: Lin Huang @ 2018-03-20  2:06 UTC (permalink / raw)
  To: heiko
  Cc: dbasehore, shawn.lin, briannorris, linux-rockchip, dianders,
	linux-clk, Lin Huang

These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.

NOTE: on none of the boards currently in mainline do we expect
CPLL to be anything other than 800 MHz, but some future boards
might have it. It's still good to be explicit about the clock
rates to make diffing against future boards easier and also to
rely less on BIOS muxing.

Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v2:
- None
Changes in v3:
- Update commit message

 arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
 arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 18f546f..84e367b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -588,7 +588,10 @@
 		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-		<&cru ACLK_VIO>;
+		<&cru ACLK_VIO>,
+		<&cru ACLK_GIC_PRE>,
+		<&cru PCLK_DDR>,
+		<&cru ACLK_HDCP>;
 	assigned-clock-rates =
 		<600000000>, <800000000>,
 		<1000000000>,
@@ -597,6 +600,9 @@
 		<100000000>, <100000000>,
 		<50000000>, <800000000>,
 		<100000000>, <50000000>,
+		<400000000>,
+		<200000000>,
+		<200000000>,
 		<400000000>;
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4550c0f..b358533 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,6 +315,8 @@
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		assigned-clocks = <&cru HCLK_SD>;
+		assigned-clock-rates = <200000000>;
 		fifo-depth = <0x100>;
 		power-domains = <&power RK3399_PD_SD>;
 		resets = <&cru SRST_SDMMC>;
@@ -466,8 +468,10 @@
 		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 		clock-names = "core-clk", "pclk", "spdif", "grf";
-		phys = <&tcphy0_dp>, <&tcphy1_dp>;
+		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+		assigned-clock-rates = <100000000>, <200000000>;
 		power-domains = <&power RK3399_PD_HDCP>;
+		phys = <&tcphy0_dp>, <&tcphy1_dp>;
 		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 		reset-names = "spdif", "dptx", "apb", "core";
@@ -1323,7 +1327,10 @@
 			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-			<&cru ACLK_VIO>;
+			<&cru ACLK_VIO>,
+			<&cru ACLK_GIC_PRE>,
+			<&cru PCLK_DDR>,
+			<&cru ACLK_HDCP>;
 		assigned-clock-rates =
 			 <594000000>,  <800000000>,
 			<1000000000>,
@@ -1332,6 +1339,9 @@
 			 <100000000>,  <100000000>,
 			  <50000000>, <600000000>,
 			 <100000000>,   <50000000>,
+			 <400000000>,
+			 <200000000>,
+			 <200000000>,
 			 <400000000>;
 	};
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:06   ` Lin Huang
  0 siblings, 0 replies; 14+ messages in thread
From: Lin Huang @ 2018-03-20  2:06 UTC (permalink / raw)
  To: heiko-4mtYJXux2i+zQB+pC5nmwQ
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, Lin Huang,
	shawn.lin-TNX95d0MmH7DzftRWevZcw,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.

NOTE: on none of the boards currently in mainline do we expect
CPLL to be anything other than 800 MHz, but some future boards
might have it. It's still good to be explicit about the clock
rates to make diffing against future boards easier and also to
rely less on BIOS muxing.

Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- None
Changes in v3:
- Update commit message

 arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
 arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 18f546f..84e367b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -588,7 +588,10 @@
 		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-		<&cru ACLK_VIO>;
+		<&cru ACLK_VIO>,
+		<&cru ACLK_GIC_PRE>,
+		<&cru PCLK_DDR>,
+		<&cru ACLK_HDCP>;
 	assigned-clock-rates =
 		<600000000>, <800000000>,
 		<1000000000>,
@@ -597,6 +600,9 @@
 		<100000000>, <100000000>,
 		<50000000>, <800000000>,
 		<100000000>, <50000000>,
+		<400000000>,
+		<200000000>,
+		<200000000>,
 		<400000000>;
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4550c0f..b358533 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,6 +315,8 @@
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		assigned-clocks = <&cru HCLK_SD>;
+		assigned-clock-rates = <200000000>;
 		fifo-depth = <0x100>;
 		power-domains = <&power RK3399_PD_SD>;
 		resets = <&cru SRST_SDMMC>;
@@ -466,8 +468,10 @@
 		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 		clock-names = "core-clk", "pclk", "spdif", "grf";
-		phys = <&tcphy0_dp>, <&tcphy1_dp>;
+		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+		assigned-clock-rates = <100000000>, <200000000>;
 		power-domains = <&power RK3399_PD_HDCP>;
+		phys = <&tcphy0_dp>, <&tcphy1_dp>;
 		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 		reset-names = "spdif", "dptx", "apb", "core";
@@ -1323,7 +1327,10 @@
 			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-			<&cru ACLK_VIO>;
+			<&cru ACLK_VIO>,
+			<&cru ACLK_GIC_PRE>,
+			<&cru PCLK_DDR>,
+			<&cru ACLK_HDCP>;
 		assigned-clock-rates =
 			 <594000000>,  <800000000>,
 			<1000000000>,
@@ -1332,6 +1339,9 @@
 			 <100000000>,  <100000000>,
 			  <50000000>, <600000000>,
 			 <100000000>,   <50000000>,
+			 <400000000>,
+			 <200000000>,
+			 <200000000>,
 			 <400000000>;
 	};
 
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:12     ` Shawn Lin
  0 siblings, 0 replies; 14+ messages in thread
From: Shawn Lin @ 2018-03-20  2:12 UTC (permalink / raw)
  To: Lin Huang
  Cc: heiko, shawn.lin, dbasehore, briannorris, linux-rockchip,
	dianders, linux-clk

On 2018/3/20 10:06, Lin Huang wrote:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
> 
> NOTE: on none of the boards currently in mainline do we expect
> CPLL to be anything other than 800 MHz, but some future boards
> might have it. It's still good to be explicit about the clock
> rates to make diffing against future boards easier and also to
> rely less on BIOS muxing.
> 
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401

Should remove Change-Id for future patch(es), thought Heiko may help
do it when applied.

Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> Changes in v2:
> - None
> Changes in v3:
> - Update commit message
> 
>   arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
>   2 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 18f546f..84e367b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -588,7 +588,10 @@
>   		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>   		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>   		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
> -		<&cru ACLK_VIO>;
> +		<&cru ACLK_VIO>,
> +		<&cru ACLK_GIC_PRE>,
> +		<&cru PCLK_DDR>,
> +		<&cru ACLK_HDCP>;
>   	assigned-clock-rates =
>   		<600000000>, <800000000>,
>   		<1000000000>,
> @@ -597,6 +600,9 @@
>   		<100000000>, <100000000>,
>   		<50000000>, <800000000>,
>   		<100000000>, <50000000>,
> +		<400000000>,
> +		<200000000>,
> +		<200000000>,
>   		<400000000>;
>   };
>   
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4550c0f..b358533 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -315,6 +315,8 @@
>   		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
>   			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
>   		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> +		assigned-clocks = <&cru HCLK_SD>;
> +		assigned-clock-rates = <200000000>;
>   		fifo-depth = <0x100>;
>   		power-domains = <&power RK3399_PD_SD>;
>   		resets = <&cru SRST_SDMMC>;
> @@ -466,8 +468,10 @@
>   		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
>   			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
>   		clock-names = "core-clk", "pclk", "spdif", "grf";
> -		phys = <&tcphy0_dp>, <&tcphy1_dp>;
> +		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
> +		assigned-clock-rates = <100000000>, <200000000>;
>   		power-domains = <&power RK3399_PD_HDCP>;
> +		phys = <&tcphy0_dp>, <&tcphy1_dp>;
>   		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
>   			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
>   		reset-names = "spdif", "dptx", "apb", "core";
> @@ -1323,7 +1327,10 @@
>   			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>   			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>   			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
> -			<&cru ACLK_VIO>;
> +			<&cru ACLK_VIO>,
> +			<&cru ACLK_GIC_PRE>,
> +			<&cru PCLK_DDR>,
> +			<&cru ACLK_HDCP>;
>   		assigned-clock-rates =
>   			 <594000000>,  <800000000>,
>   			<1000000000>,
> @@ -1332,6 +1339,9 @@
>   			 <100000000>,  <100000000>,
>   			  <50000000>, <600000000>,
>   			 <100000000>,   <50000000>,
> +			 <400000000>,
> +			 <200000000>,
> +			 <200000000>,
>   			 <400000000>;
>   	};
>   
> 


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:12     ` Shawn Lin
  0 siblings, 0 replies; 14+ messages in thread
From: Shawn Lin @ 2018-03-20  2:12 UTC (permalink / raw)
  To: Lin Huang
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
	shawn.lin-TNX95d0MmH7DzftRWevZcw,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

On 2018/3/20 10:06, Lin Huang wrote:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
> 
> NOTE: on none of the boards currently in mainline do we expect
> CPLL to be anything other than 800 MHz, but some future boards
> might have it. It's still good to be explicit about the clock
> rates to make diffing against future boards easier and also to
> rely less on BIOS muxing.
> 
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401

Should remove Change-Id for future patch(es), thought Heiko may help
do it when applied.

Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> Changes in v2:
> - None
> Changes in v3:
> - Update commit message
> 
>   arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
>   2 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 18f546f..84e367b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -588,7 +588,10 @@
>   		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>   		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>   		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
> -		<&cru ACLK_VIO>;
> +		<&cru ACLK_VIO>,
> +		<&cru ACLK_GIC_PRE>,
> +		<&cru PCLK_DDR>,
> +		<&cru ACLK_HDCP>;
>   	assigned-clock-rates =
>   		<600000000>, <800000000>,
>   		<1000000000>,
> @@ -597,6 +600,9 @@
>   		<100000000>, <100000000>,
>   		<50000000>, <800000000>,
>   		<100000000>, <50000000>,
> +		<400000000>,
> +		<200000000>,
> +		<200000000>,
>   		<400000000>;
>   };
>   
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4550c0f..b358533 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -315,6 +315,8 @@
>   		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
>   			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
>   		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> +		assigned-clocks = <&cru HCLK_SD>;
> +		assigned-clock-rates = <200000000>;
>   		fifo-depth = <0x100>;
>   		power-domains = <&power RK3399_PD_SD>;
>   		resets = <&cru SRST_SDMMC>;
> @@ -466,8 +468,10 @@
>   		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
>   			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
>   		clock-names = "core-clk", "pclk", "spdif", "grf";
> -		phys = <&tcphy0_dp>, <&tcphy1_dp>;
> +		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
> +		assigned-clock-rates = <100000000>, <200000000>;
>   		power-domains = <&power RK3399_PD_HDCP>;
> +		phys = <&tcphy0_dp>, <&tcphy1_dp>;
>   		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
>   			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
>   		reset-names = "spdif", "dptx", "apb", "core";
> @@ -1323,7 +1327,10 @@
>   			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>   			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>   			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
> -			<&cru ACLK_VIO>;
> +			<&cru ACLK_VIO>,
> +			<&cru ACLK_GIC_PRE>,
> +			<&cru PCLK_DDR>,
> +			<&cru ACLK_HDCP>;
>   		assigned-clock-rates =
>   			 <594000000>,  <800000000>,
>   			<1000000000>,
> @@ -1332,6 +1339,9 @@
>   			 <100000000>,  <100000000>,
>   			  <50000000>, <600000000>,
>   			 <100000000>,   <50000000>,
> +			 <400000000>,
> +			 <200000000>,
> +			 <200000000>,
>   			 <400000000>;
>   	};
>   
> 

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:23       ` hl
  0 siblings, 0 replies; 14+ messages in thread
From: hl @ 2018-03-20  2:23 UTC (permalink / raw)
  To: Shawn Lin
  Cc: dbasehore, heiko, briannorris, dianders, linux-rockchip,
	linux-clk



On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> On 2018/3/20 10:06, Lin Huang wrote:
>> These clocks do not assign default clock frequency, and use the
>> default cru register value to get frequency, so if cpll increase
>> frequency, these clocks also increase their frequency, that may
>> exceed their signed off frequency. So assign default clock for
>> them to avoid it.
>>
>> NOTE: on none of the boards currently in mainline do we expect
>> CPLL to be anything other than 800 MHz, but some future boards
>> might have it. It's still good to be explicit about the clock
>> rates to make diffing against future boards easier and also to
>> rely less on BIOS muxing.
>>
>> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
>
> Should remove Change-Id for future patch(es), thought Heiko may help
> do it when applied.
>
Opp, sorry for that.
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>> ---
>> Changes in v2:
>> - None
>> Changes in v3:
>> - Update commit message
>>
>>   arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
>>   arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
>>   2 files changed, 19 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> index 18f546f..84e367b 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> @@ -588,7 +588,10 @@
>>           <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>>           <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>>           <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
>> -        <&cru ACLK_VIO>;
>> +        <&cru ACLK_VIO>,
>> +        <&cru ACLK_GIC_PRE>,
>> +        <&cru PCLK_DDR>,
>> +        <&cru ACLK_HDCP>;
>>       assigned-clock-rates =
>>           <600000000>, <800000000>,
>>           <1000000000>,
>> @@ -597,6 +600,9 @@
>>           <100000000>, <100000000>,
>>           <50000000>, <800000000>,
>>           <100000000>, <50000000>,
>> +        <400000000>,
>> +        <200000000>,
>> +        <200000000>,
>>           <400000000>;
>>   };
>>   diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index 4550c0f..b358533 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -315,6 +315,8 @@
>>           clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
>>                <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
>>           clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
>> +        assigned-clocks = <&cru HCLK_SD>;
>> +        assigned-clock-rates = <200000000>;
>>           fifo-depth = <0x100>;
>>           power-domains = <&power RK3399_PD_SD>;
>>           resets = <&cru SRST_SDMMC>;
>> @@ -466,8 +468,10 @@
>>           clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
>>                <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
>>           clock-names = "core-clk", "pclk", "spdif", "grf";
>> -        phys = <&tcphy0_dp>, <&tcphy1_dp>;
>> +        assigned-clocks = <&cru SCLK_DP_CORE>, <&cru 
>> SCLK_SPDIF_REC_DPTX>;
>> +        assigned-clock-rates = <100000000>, <200000000>;
>>           power-domains = <&power RK3399_PD_HDCP>;
>> +        phys = <&tcphy0_dp>, <&tcphy1_dp>;
>>           resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
>>                <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
>>           reset-names = "spdif", "dptx", "apb", "core";
>> @@ -1323,7 +1327,10 @@
>>               <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>>               <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>>               <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
>> -            <&cru ACLK_VIO>;
>> +            <&cru ACLK_VIO>,
>> +            <&cru ACLK_GIC_PRE>,
>> +            <&cru PCLK_DDR>,
>> +            <&cru ACLK_HDCP>;
>>           assigned-clock-rates =
>>                <594000000>,  <800000000>,
>>               <1000000000>,
>> @@ -1332,6 +1339,9 @@
>>                <100000000>,  <100000000>,
>>                 <50000000>, <600000000>,
>>                <100000000>,   <50000000>,
>> +             <400000000>,
>> +             <200000000>,
>> +             <200000000>,
>>                <400000000>;
>>       };
>>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  2:23       ` hl
  0 siblings, 0 replies; 14+ messages in thread
From: hl @ 2018-03-20  2:23 UTC (permalink / raw)
  To: Shawn Lin
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA



On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> On 2018/3/20 10:06, Lin Huang wrote:
>> These clocks do not assign default clock frequency, and use the
>> default cru register value to get frequency, so if cpll increase
>> frequency, these clocks also increase their frequency, that may
>> exceed their signed off frequency. So assign default clock for
>> them to avoid it.
>>
>> NOTE: on none of the boards currently in mainline do we expect
>> CPLL to be anything other than 800 MHz, but some future boards
>> might have it. It's still good to be explicit about the clock
>> rates to make diffing against future boards easier and also to
>> rely less on BIOS muxing.
>>
>> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
>
> Should remove Change-Id for future patch(es), thought Heiko may help
> do it when applied.
>
Opp, sorry for that.
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>> ---
>> Changes in v2:
>> - None
>> Changes in v3:
>> - Update commit message
>>
>>   arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi |  8 +++++++-
>>   arch/arm64/boot/dts/rockchip/rk3399.dtsi     | 14 ++++++++++++--
>>   2 files changed, 19 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> index 18f546f..84e367b 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
>> @@ -588,7 +588,10 @@
>>           <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>>           <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>>           <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
>> -        <&cru ACLK_VIO>;
>> +        <&cru ACLK_VIO>,
>> +        <&cru ACLK_GIC_PRE>,
>> +        <&cru PCLK_DDR>,
>> +        <&cru ACLK_HDCP>;
>>       assigned-clock-rates =
>>           <600000000>, <800000000>,
>>           <1000000000>,
>> @@ -597,6 +600,9 @@
>>           <100000000>, <100000000>,
>>           <50000000>, <800000000>,
>>           <100000000>, <50000000>,
>> +        <400000000>,
>> +        <200000000>,
>> +        <200000000>,
>>           <400000000>;
>>   };
>>   diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index 4550c0f..b358533 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -315,6 +315,8 @@
>>           clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
>>                <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
>>           clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
>> +        assigned-clocks = <&cru HCLK_SD>;
>> +        assigned-clock-rates = <200000000>;
>>           fifo-depth = <0x100>;
>>           power-domains = <&power RK3399_PD_SD>;
>>           resets = <&cru SRST_SDMMC>;
>> @@ -466,8 +468,10 @@
>>           clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
>>                <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
>>           clock-names = "core-clk", "pclk", "spdif", "grf";
>> -        phys = <&tcphy0_dp>, <&tcphy1_dp>;
>> +        assigned-clocks = <&cru SCLK_DP_CORE>, <&cru 
>> SCLK_SPDIF_REC_DPTX>;
>> +        assigned-clock-rates = <100000000>, <200000000>;
>>           power-domains = <&power RK3399_PD_HDCP>;
>> +        phys = <&tcphy0_dp>, <&tcphy1_dp>;
>>           resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
>>                <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
>>           reset-names = "spdif", "dptx", "apb", "core";
>> @@ -1323,7 +1327,10 @@
>>               <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
>>               <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
>>               <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
>> -            <&cru ACLK_VIO>;
>> +            <&cru ACLK_VIO>,
>> +            <&cru ACLK_GIC_PRE>,
>> +            <&cru PCLK_DDR>,
>> +            <&cru ACLK_HDCP>;
>>           assigned-clock-rates =
>>                <594000000>,  <800000000>,
>>               <1000000000>,
>> @@ -1332,6 +1339,9 @@
>>                <100000000>,  <100000000>,
>>                 <50000000>, <600000000>,
>>                <100000000>,   <50000000>,
>> +             <400000000>,
>> +             <200000000>,
>> +             <200000000>,
>>                <400000000>;
>>       };
>>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  7:00         ` Heiko Stübner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stübner @ 2018-03-20  7:00 UTC (permalink / raw)
  To: hl; +Cc: Shawn Lin, dbasehore, briannorris, dianders, linux-rockchip,
	linux-clk

Am Dienstag, 20. März 2018, 03:23:41 CET schrieb hl:
> On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> > On 2018/3/20 10:06, Lin Huang wrote:
> >> These clocks do not assign default clock frequency, and use the
> >> default cru register value to get frequency, so if cpll increase
> >> frequency, these clocks also increase their frequency, that may
> >> exceed their signed off frequency. So assign default clock for
> >> them to avoid it.
> >> 
> >> NOTE: on none of the boards currently in mainline do we expect
> >> CPLL to be anything other than 800 MHz, but some future boards
> >> might have it. It's still good to be explicit about the clock
> >> rates to make diffing against future boards easier and also to
> >> rely less on BIOS muxing.
> >> 
> >> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> > 
> > Should remove Change-Id for future patch(es), thought Heiko may help
> > do it when applied.
> 
> Opp, sorry for that.

Yep, I can drop the changeId when applying

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-20  7:00         ` Heiko Stübner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stübner @ 2018-03-20  7:00 UTC (permalink / raw)
  To: hl
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, Shawn Lin,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

Am Dienstag, 20. März 2018, 03:23:41 CET schrieb hl:
> On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> > On 2018/3/20 10:06, Lin Huang wrote:
> >> These clocks do not assign default clock frequency, and use the
> >> default cru register value to get frequency, so if cpll increase
> >> frequency, these clocks also increase their frequency, that may
> >> exceed their signed off frequency. So assign default clock for
> >> them to avoid it.
> >> 
> >> NOTE: on none of the boards currently in mainline do we expect
> >> CPLL to be anything other than 800 MHz, but some future boards
> >> might have it. It's still good to be explicit about the clock
> >> rates to make diffing against future boards easier and also to
> >> rely less on BIOS muxing.
> >> 
> >> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> > 
> > Should remove Change-Id for future patch(es), thought Heiko may help
> > do it when applied.
> 
> Opp, sorry for that.

Yep, I can drop the changeId when applying

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-23  8:45     ` Heiko Stuebner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2018-03-23  8:45 UTC (permalink / raw)
  To: Lin Huang
  Cc: dbasehore, shawn.lin, briannorris, linux-rockchip, dianders,
	linux-clk

Am Dienstag, 20. März 2018, 03:06:29 CET schrieb Lin Huang:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
> 
> NOTE: on none of the boards currently in mainline do we expect
> CPLL to be anything other than 800 MHz, but some future boards
> might have it. It's still good to be explicit about the clock
> rates to make diffing against future boards easier and also to
> rely less on BIOS muxing.
> 
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

applied for 4.17 (but will most likely move to 4.18) with some changes:
- dropped Change-Id
- fixed duplicate assigned clocks for dp node
- grouped aclk_vio and aclk_hdcp into one line in cru nodes
- moved assigned clocks


Heiko

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
@ 2018-03-23  8:45     ` Heiko Stuebner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2018-03-23  8:45 UTC (permalink / raw)
  To: Lin Huang
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw,
	shawn.lin-TNX95d0MmH7DzftRWevZcw,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

Am Dienstag, 20. März 2018, 03:06:29 CET schrieb Lin Huang:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
> 
> NOTE: on none of the boards currently in mainline do we expect
> CPLL to be anything other than 800 MHz, but some future boards
> might have it. It's still good to be explicit about the clock
> rates to make diffing against future boards easier and also to
> rely less on BIOS muxing.
> 
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

applied for 4.17 (but will most likely move to 4.18) with some changes:
- dropped Change-Id
- fixed duplicate assigned clocks for dp node
- grouped aclk_vio and aclk_hdcp into one line in cru nodes
- moved assigned clocks


Heiko

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
@ 2018-03-23  8:26   ` Heiko Stuebner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2018-03-23  8:26 UTC (permalink / raw)
  To: Lin Huang
  Cc: dbasehore, shawn.lin, briannorris, linux-rockchip, dianders,
	linux-clk

Am Dienstag, 20. März 2018, 03:06:28 CET schrieb Lin Huang:
> Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
> and these two PLL may change their frequency. If we do not
> assign right id to pclk_ddr and hclk_sd, they will alway use
> default cur register value, and may get the frequency
> exceed their signed off frequency. So assign correct Id
> for them, then we can assign frequency for them in dts.
> 
> Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

applied for 4.17 after dropping the Change-Id

Thanks
Heiko

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
@ 2018-03-23  8:26   ` Heiko Stuebner
  0 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2018-03-23  8:26 UTC (permalink / raw)
  To: Lin Huang
  Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw,
	shawn.lin-TNX95d0MmH7DzftRWevZcw,
	briannorris-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA

Am Dienstag, 20. März 2018, 03:06:28 CET schrieb Lin Huang:
> Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
> and these two PLL may change their frequency. If we do not
> assign right id to pclk_ddr and hclk_sd, they will alway use
> default cur register value, and may get the frequency
> exceed their signed off frequency. So assign correct Id
> for them, then we can assign frequency for them in dts.
> 
> Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

applied for 4.17 after dropping the Change-Id

Thanks
Heiko

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2018-03-23  8:45 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-03-20  2:06 [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang
2018-03-20  2:06 ` Lin Huang
2018-03-20  2:06 ` [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang
2018-03-20  2:06   ` Lin Huang
2018-03-20  2:12   ` Shawn Lin
2018-03-20  2:12     ` Shawn Lin
2018-03-20  2:23     ` hl
2018-03-20  2:23       ` hl
2018-03-20  7:00       ` Heiko Stübner
2018-03-20  7:00         ` Heiko Stübner
2018-03-23  8:45   ` Heiko Stuebner
2018-03-23  8:45     ` Heiko Stuebner
2018-03-23  8:26 ` [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Heiko Stuebner
2018-03-23  8:26   ` Heiko Stuebner

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