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* [Intel-gfx] [PATCH v3] drm/i915: Bump up CDCLK to eliminate underruns on TGL
@ 2020-01-09 22:05 Stanislav Lisovskiy
  2020-01-09 22:33 ` Matt Roper
                   ` (7 more replies)
  0 siblings, 8 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-01-09 22:05 UTC (permalink / raw)
  To: intel-gfx

There seems to be some undocumented bandwidth
bottleneck/dependency which scales with CDCLK,
causing FIFO underruns when CDCLK is too low,
even when it's correct from BSpec point of view.

Currently for TGL platforms we calculate
min_cdclk initially based on pixel_rate divided
by 2, accounting for also plane requirements,
however in some cases the lowest possible CDCLK
doesn't work and causing the underruns.
We've found experimentally that raising cdclk to
at least  pixel_rate (rather than pixel_rate/2)
eliminates these underruns, so let's use this as a
temporary workaround until the hardware team
can suggest a more precise remedy.

Explicitly stating here that this seems to be currently
rather a Hack, than final solution.

v2: Use clamp operation instead of min(Matt Roper)

v3: - Fixed commit message(Matt Roper)
    - Now using pixel_rate instead of max_cdclk(Jani Nikula)
    - Switched to max from clamp(Ville Syrjälä)
    Hopefully this hybrid satisfies everyone :)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/issues/402
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7d1ab1e5b7c3..0ce5926006ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2004,6 +2004,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	/* Account for additional needs from the planes */
 	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
+	/*
+	 * HACK. Currently for TGL platforms we calculate
+	 * min_cdclk initially based on pixel_rate divided
+	 * by 2, accounting for also plane requirements,
+	 * however in some cases the lowest possible CDCLK
+	 * doesn't work and causing the underruns.
+	 * Explicitly stating here that this seems to be currently
+	 * rather a Hack, than final solution.
+	 */
+	if (IS_TIGERLAKE(dev_priv))
+		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
 	if (min_cdclk > dev_priv->max_cdclk_freq) {
 		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
 			      min_cdclk, dev_priv->max_cdclk_freq);
-- 
2.24.1.485.gad05a3d8e5

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^ permalink raw reply related	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2020-01-14 17:26 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-01-09 22:05 [Intel-gfx] [PATCH v3] drm/i915: Bump up CDCLK to eliminate underruns on TGL Stanislav Lisovskiy
2020-01-09 22:33 ` Matt Roper
2020-01-10  0:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Bump up CDCLK to eliminate underruns on TGL (rev3) Patchwork
2020-01-10 21:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-12 18:27   ` Lisovskiy, Stanislav
2020-01-10 23:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Bump up CDCLK to eliminate underruns on TGL (rev4) Patchwork
2020-01-13  8:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Bump up CDCLK to eliminate underruns on TGL (rev3) Patchwork
2020-01-13  8:32   ` Lisovskiy, Stanislav
2020-01-13  8:54     ` Peres, Martin
2020-01-13  9:02       ` Saarinen, Jani
2020-01-13  9:02       ` Lisovskiy, Stanislav
2020-01-13  9:20 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-01-13 11:59 ` [Intel-gfx] [PATCH v3] drm/i915: Bump up CDCLK to eliminate underruns on TGL Jani Nikula
2020-01-14 17:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Bump up CDCLK to eliminate underruns on TGL (rev4) Patchwork

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