[Qemu-devel] [PATCH v2] Adding support for LPD and LPDG instructions

[Qemu-devel] [PATCH v2] Adding support for LPD and LPDG instructions

[Eric Bischoff]

Second version of the patch, setting CC to zero.
I am not too satisfied, I had to create a cout_zero() helper, but
I could not find a better solution.

[Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Eric Bischoff]

From: Eric Bischoff <ebischoff@nerim.net>

LPD = LOAD PAIR DISJOINT
---
 target/s390x/insn-data.def |  4 +++-
 target/s390x/translate.c   | 21 +++++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 075ff59..e427988 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -504,7 +504,9 @@
     C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
     C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
     C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
-/* LOAD PAIR DISJOINT TODO */
+/* LOAD PAIR DISJOINT */
+    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, zero)
+    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, zero)
 /* LOAD POSITIVE */
     C(0x1000, LPR,     RR_a,  Z,   0, r2_32s, new, r1_32, abs, abs32)
     C(0xb900, LPGR,    RRE,   Z,   0, r2, r1, 0, abs, abs64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 01c6217..a363efb 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4158,6 +4158,11 @@ static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
    the original inputs), update the various cc data structures in order to
    be able to compute the new condition code.  */
 
+static void cout_zero(DisasContext *s, DisasOps *o)
+{
+    gen_op_movi_cc(s, 0);
+}
+
 static void cout_abs32(DisasContext *s, DisasOps *o)
 {
     gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
@@ -4420,6 +4425,22 @@ static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_wout_r1_D32 SPEC_r1_even
 
+static void wout_r3_P32(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg32_i64(r3, o->out);
+    store_reg32_i64(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P32 SPEC_r3_even
+
+static void wout_r3_P64(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg(r3, o->out);
+    store_reg(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P64 SPEC_r3_even
+
 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     store_freg32_i64(get_field(f, r1), o->out);
-- 
2.10.2

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Richard Henderson]

On 02/27/2017 10:22 PM, Eric Bischoff wrote:
> From: Eric Bischoff <ebischoff@nerim.net>
>
> LPD = LOAD PAIR DISJOINT
> ---
>  target/s390x/insn-data.def |  4 +++-
>  target/s390x/translate.c   | 21 +++++++++++++++++++++
>  2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 075ff59..e427988 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -504,7 +504,9 @@
>      C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
>      C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
>      C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
> -/* LOAD PAIR DISJOINT TODO */
> +/* LOAD PAIR DISJOINT */
> +    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, zero)
> +    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, zero)

The think is, in order to be able to say that the two loads were interlocked, 
which is what you're doing with CC=0, we need to provide some atomicity.

In general, this is going to require that you check parallel_cpus, and if true, 
signal cpu_loop_exit_atomic.

As a special case, it would be possible to check for two loads that happen to 
be sequential and perform them as an atomic read.  Whether that happens often 
enough to be worthwhile I don't know.


r~

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Éric Bischoff]

Le mardi 28 février 2017, 06:10:45 CET Richard Henderson a écrit :
> On 02/27/2017 10:22 PM, Eric Bischoff wrote:
> > From: Eric Bischoff <ebischoff@nerim.net>
> > 
> > LPD = LOAD PAIR DISJOINT
> > ---
> > 
> >  target/s390x/insn-data.def |  4 +++-
> >  target/s390x/translate.c   | 21 +++++++++++++++++++++
> >  2 files changed, 24 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> > index 075ff59..e427988 100644
> > --- a/target/s390x/insn-data.def
> > +++ b/target/s390x/insn-data.def
> > @@ -504,7 +504,9 @@
> > 
> >      C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
> >      C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
> >      C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
> > 
> > -/* LOAD PAIR DISJOINT TODO */
> > +/* LOAD PAIR DISJOINT */
> > +    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, zero)
> > +    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, zero)
> 
> The think is, in order to be able to say that the two loads were
> interlocked, which is what you're doing with CC=0, we need to provide some
> atomicity.
> 
> In general, this is going to require that you check parallel_cpus, and if
> true, signal cpu_loop_exit_atomic.
> 
> As a special case, it would be possible to check for two loads that happen
> to be sequential and perform them as an atomic read.  Whether that happens
> often enough to be worthwhile I don't know.

Understood now.

I'm working on a v3 patch based on the code kindly sent in private mail by 
Richard.


-- 
Eric Bischoff - SUSE Manager QA Engineer
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip 
Upmanyu, Graham Norton, HRB 21284 (AG Nürnberg)

[Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Eric Bischoff]

From: Eric Bischoff <ebischoff@nerim.net>

LPD = LOAD PAIR DISJOINT
Fourth patch
---
 target/s390x/insn-data.def |  4 ++-
 target/s390x/translate.c   | 63 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 075ff59..72d1017 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -504,7 +504,9 @@
     C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
     C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
     C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
-/* LOAD PAIR DISJOINT TODO */
+/* LOAD PAIR DISJOINT */
+    C(0xc804, LPD,     SSF,   ILA, 0, 0, 0, r3_P32, lpd32, 0)
+    C(0xc805, LPDG,    SSF,   ILA, 0, 0, 0, r3_P64, lpd64, 0)
 /* LOAD POSITIVE */
     C(0x1000, LPR,     RR_a,  Z,   0, r2_32s, new, r1_32, abs, abs32)
     C(0xb900, LPGR,    RRE,   Z,   0, r2, r1, 0, abs, abs64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 01c6217..239d12b 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2558,6 +2558,7 @@ static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
     tcg_temp_free_i32(r3);
     return NO_EXIT;
 }
+
 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);
@@ -2750,6 +2751,52 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_lpd32(DisasContext *s, DisasOps *o)
+{
+    TCGv_i64 a1, a2;
+
+    /* In a parallel context, stop the world and single step.  */
+    if (parallel_cpus) {
+        potential_page_fault(s);
+        gen_helper_exit_atomic(cpu_env);
+        return EXIT_NORETURN;
+    }
+
+    /* In a serial context, perform the two loads and indicate
+       that we performed them while interlocked.  */
+    a1 = get_address(s, 0, get_field(s->fields, b1), get_field(s->fields, d1));
+    a2 = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+    o->out = tcg_temp_new_i64();
+    tcg_gen_qemu_ld32s(o->out, a1, get_mem_index(s));
+    o->out2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld32s(o->out2, a2, get_mem_index(s));
+    gen_op_movi_cc(s, 0);
+    return NO_EXIT;
+}
+
+static ExitStatus op_lpd64(DisasContext *s, DisasOps *o)
+{
+    TCGv_i64 a1, a2;
+
+    /* In a parallel context, stop the world and single step.  */
+    if (parallel_cpus) {
+        potential_page_fault(s);
+        gen_helper_exit_atomic(cpu_env);
+        return EXIT_NORETURN;
+    }
+
+    /* In a serial context, perform the two loads and indicate
+       that we performed them while interlocked.  */
+    a1 = get_address(s, 0, get_field(s->fields, b1), get_field(s->fields, d1));
+    a2 = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+    o->out = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(o->out, a1, get_mem_index(s));
+    o->out2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(o->out2, a2, get_mem_index(s));
+    gen_op_movi_cc(s, 0);
+    return NO_EXIT;
+}
+
 #ifndef CONFIG_USER_ONLY
 static ExitStatus op_lura(DisasContext *s, DisasOps *o)
 {
@@ -4420,6 +4467,22 @@ static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_wout_r1_D32 SPEC_r1_even
 
+static void wout_r3_P32(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg32_i64(r3, o->out);
+    store_reg32_i64(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P32 SPEC_r3_even
+
+static void wout_r3_P64(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg(r3, o->out);
+    store_reg(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P64 SPEC_r3_even
+
 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     store_freg32_i64(get_field(f, r1), o->out);
-- 
2.10.2

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Richard Henderson]

On 02/28/2017 11:01 PM, Eric Bischoff wrote:
> From: Eric Bischoff <ebischoff@nerim.net>
>
> LPD = LOAD PAIR DISJOINT
> Fourth patch
> ---
>  target/s390x/insn-data.def |  4 ++-
>  target/s390x/translate.c   | 63 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 66 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Richard Henderson]

On 02/28/2017 11:01 PM, Eric Bischoff wrote:
> From: Eric Bischoff <ebischoff@nerim.net>
>
> LPD = LOAD PAIR DISJOINT
> Fourth patch
> ---
>  target/s390x/insn-data.def |  4 ++-
>  target/s390x/translate.c   | 63 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 66 insertions(+), 1 deletion(-)

Oh, I'm also missing a Signed-off-by.


r~

[Qemu-devel] [PATCHv3] Adding support for LPD and LPDG instructions

[Eric Bischoff]

Third patch, trying to do real interlocking

[Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Eric Bischoff]

From: Eric Bischoff <ebischoff@nerim.net>

LPD = LOAD PAIR DISJOINT
Third patch
---
 target/s390x/insn-data.def |  4 ++-
 target/s390x/translate.c   | 63 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 075ff59..72d1017 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -504,7 +504,9 @@
     C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
     C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
     C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
-/* LOAD PAIR DISJOINT TODO */
+/* LOAD PAIR DISJOINT */
+    C(0xc804, LPD,     SSF,   ILA, 0, 0, 0, r3_P32, lpd32, 0)
+    C(0xc805, LPDG,    SSF,   ILA, 0, 0, 0, r3_P64, lpd64, 0)
 /* LOAD POSITIVE */
     C(0x1000, LPR,     RR_a,  Z,   0, r2_32s, new, r1_32, abs, abs32)
     C(0xb900, LPGR,    RRE,   Z,   0, r2, r1, 0, abs, abs64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 01c6217..28a53ec 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -2558,6 +2558,7 @@ static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
     tcg_temp_free_i32(r3);
     return NO_EXIT;
 }
+
 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
 {
     check_privileged(s);
@@ -2750,6 +2751,52 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_lpd32(DisasContext *s, DisasOps *o)
+{
+    TCGv_i64 a1, a2;
+
+    /* In a parallel context, stop the world and single step.  */
+      if (parallel_cpus) {
+           potential_page_fault(s);
+           gen_helper_exit_atomic(cpu_env);
+           return EXIT_NORETURN;
+      }
+
+    /* In a serial context, perform the two loads and indicate
+       that we performed them while interlocked.  */
+    a1 = get_address(s, 0, get_field(s->fields, b1), get_field(s->fields, d1));
+    a2 = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+    o->out = tcg_temp_new_i64();
+    tcg_gen_qemu_ld32s(o->out, a1, get_mem_index(s));
+    o->out2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld32s(o->out2, a2, get_mem_index(s));
+    gen_op_movi_cc(s, 0);
+    return NO_EXIT;
+}
+
+static ExitStatus op_lpd64(DisasContext *s, DisasOps *o)
+{
+    TCGv_i64 a1, a2;
+
+    /* In a parallel context, stop the world and single step.  */
+    if (parallel_cpus) {
+         potential_page_fault(s);
+         gen_helper_exit_atomic(cpu_env);
+         return EXIT_NORETURN;
+    }
+
+    /* In a serial context, perform the two loads and indicate
+       that we performed them while interlocked.  */
+    a1 = get_address(s, 0, get_field(s->fields, b1), get_field(s->fields, d1));
+    a2 = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+    o->out = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(o->out, a1, get_mem_index(s));
+    o->out2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(o->out2, a2, get_mem_index(s));
+    gen_op_movi_cc(s, 0);
+    return NO_EXIT;
+}
+
 #ifndef CONFIG_USER_ONLY
 static ExitStatus op_lura(DisasContext *s, DisasOps *o)
 {
@@ -4420,6 +4467,22 @@ static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_wout_r1_D32 SPEC_r1_even
 
+static void wout_r3_P32(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg32_i64(r3, o->out);
+    store_reg32_i64(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P32 SPEC_r3_even
+
+static void wout_r3_P64(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg(r3, o->out);
+    store_reg(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P64 SPEC_r3_even
+
 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     store_freg32_i64(get_field(f, r1), o->out);
-- 
2.10.2

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20170228113535.7099-2-ebischoff@suse.com
Type: series
Subject: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20170228113535.7099-2-ebischoff@suse.com -> patchew/20170228113535.7099-2-ebischoff@suse.com
Switched to a new branch 'test'
f7359bd Adding support for LPD and LPDG instructions

=== OUTPUT BEGIN ===
Checking PATCH 1/1: Adding support for LPD and LPDG instructions...
ERROR: suspect code indent for conditional statements (6, 11)
#46: FILE: target/s390x/translate.c:2759:
+      if (parallel_cpus) {
+           potential_page_fault(s);

ERROR: suspect code indent for conditional statements (4, 9)
#69: FILE: target/s390x/translate.c:2782:
+    if (parallel_cpus) {
+         potential_page_fault(s);

ERROR: Missing Signed-off-by: line(s)

total: 3 errors, 0 warnings, 91 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Éric Bischoff]

Le samedi 25 février 2017, 10:42:43 CET Richard Henderson a écrit :
> On 02/23/2017 10:58 PM, Eric Bischoff wrote:
> > +/* LOAD PAIR DISJOINT */
> > +    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, 0)
> > +    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, 0)
> 
> Missing is the update to the condition codes.
> I think just setting CC = 3 (not loaded interlocked) is probably fine.

Hi Richard,


thanks a lot for the feedback.

When trying on real hardware, I was always getting CC == 0 (loaded 
interlocked). It seems to be the usual and simplest case, where fetch was 
immediately succesful.

Case CC == 3 makes it needed to use a loop:

       2. When the resulting condition code is 3, the pro-
          gram may branch back to reexecute the LOAD
          PAIR DISJOINT instruction. However, after
          repeated unsuccessful attempts to attain an
          interlocked fetch, the program should use an
          alternate means of serializing access to the stor-
          age operands. It is recommended that the pro-
          gram reexecute the LOAD PAIR DISJOINT no
          more than 10 times before branching to the alter-
          nate path.

Therefore I think that setting CC = 0 is the correct emulation.

I assumed that putting 0 in last column of C() macro was the way to set CC = 
0. I apologize if that was wrong, and if so, please tell me, and I'll correct.


Best,

-- 
Éric Bischoff

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Éric Bischoff]

Le samedi 25 février 2017, 10:42:43 CET Richard Henderson a écrit :
> On 02/23/2017 10:58 PM, Eric Bischoff wrote:
> > +/* LOAD PAIR DISJOINT */
> > +    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, 0)
> > +    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, 0)
> 
> Missing is the update to the condition codes.
> I think just setting CC = 3 (not loaded interlocked) is probably fine.

I tested and 0 at the end of C macro means "do nothing with CC".

I indeed need to set CC (but to 0, not to 3). New patch coming.


-- 
Eric Bischoff - SUSE Manager QA Engineer
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip 
Upmanyu, Graham Norton, HRB 21284 (AG Nürnberg)Le dimanche 26 février 2017, 

[Qemu-devel] (no subject)

[Eric Bischoff]

(forgot to CC the list, already sent to Richard Henderson and Alexander Graf)

[Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Eric Bischoff]

From: Eric Bischoff <ebischoff@nerim.net>

LPD = LOAD PAIR DISJOINT
---
 target/s390x/insn-data.def |  4 +++-
 target/s390x/translate.c   | 16 ++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 075ff59..5a0231f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -504,7 +504,9 @@
     C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
     C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
     C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
-/* LOAD PAIR DISJOINT TODO */
+/* LOAD PAIR DISJOINT */
+    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, 0)
+    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, 0)
 /* LOAD POSITIVE */
     C(0x1000, LPR,     RR_a,  Z,   0, r2_32s, new, r1_32, abs, abs32)
     C(0xb900, LPGR,    RRE,   Z,   0, r2, r1, 0, abs, abs64)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 01c6217..70397b6 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -4420,6 +4420,22 @@ static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_wout_r1_D32 SPEC_r1_even
 
+static void wout_r3_P32(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg32_i64(r3, o->out);
+    store_reg32_i64(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P32 SPEC_r3_even
+
+static void wout_r3_P64(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+    int r3 = get_field(f, r3);
+    store_reg(r3, o->out);
+    store_reg(r3 + 1, o->out2);
+}
+#define SPEC_wout_r3_P64 SPEC_r3_even
+
 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     store_freg32_i64(get_field(f, r1), o->out);
-- 
2.10.2