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From: Marc Zyngier <maz@kernel.org>
To: Sumit Garg <sumit.garg@linaro.org>
Cc: mark.rutland@arm.com, daniel.thompson@linaro.org,
	jason@lakedaemon.net, catalin.marinas@arm.com,
	ito-yuichi@fujitsu.com, dianders@chromium.org,
	linux-kernel@vger.kernel.org, julien.thierry.kdev@gmail.com,
	jason.wessel@windriver.com, kgdb-bugreport@lists.sourceforge.net,
	tglx@linutronix.de, msys.mizuma@gmail.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 2/5] irqchip/gic-v3: Enable support for SGIs to act as NMIs
Date: Mon, 19 Oct 2020 13:07:53 +0100	[thread overview]
Message-ID: <294754db12f4cd8a8ec9329a44e1cf02@kernel.org> (raw)
In-Reply-To: <1602673931-28782-3-git-send-email-sumit.garg@linaro.org>

On 2020-10-14 12:12, Sumit Garg wrote:
> Add support to handle SGIs as regular NMIs. As SGIs or IPIs defaults to 
> a

There is nothing "regular" about NMIs. Drop "or IPIs". 
s/defaults/default/

> special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
> handler update in case of SGIs.
> 
> Also, enable NMI support prior to gic_smp_init() as allocation of SGIs
> as IRQs/NMIs happen as part of this routine.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c 
> b/drivers/irqchip/irq-gic-v3.c
> index 16fecc0..5efc865 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -477,6 +477,11 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  	if (WARN_ON(gic_irq(d) >= 8192))
>  		return -EINVAL;
> 
> +	if (get_intid_range(d) == SGI_RANGE) {
> +		gic_irq_set_prio(d, GICD_INT_NMI_PRI);
> +		return 0;
> +	}
> +

Please follow the existing control flow, or rework it to be organised by 
range.

>  	/* desc lock should already be held */
>  	if (gic_irq_in_rdist(d)) {
>  		u32 idx = gic_get_ppi_index(d);
> @@ -514,6 +519,11 @@ static void gic_irq_nmi_teardown(struct irq_data 
> *d)
>  	if (WARN_ON(gic_irq(d) >= 8192))
>  		return;
> 
> +	if (get_intid_range(d) == SGI_RANGE) {
> +		gic_irq_set_prio(d, GICD_INT_DEF_PRI);
> +		return;
> +	}

Same here.

> +
>  	/* desc lock should already be held */
>  	if (gic_irq_in_rdist(d)) {
>  		u32 idx = gic_get_ppi_index(d);
> @@ -1708,6 +1718,7 @@ static int __init gic_init_bases(void __iomem 
> *dist_base,
> 
>  	gic_dist_init();
>  	gic_cpu_init();
> +	gic_enable_nmi_support();
>  	gic_smp_init();
>  	gic_cpu_pm_init();
> 
> @@ -1719,8 +1730,6 @@ static int __init gic_init_bases(void __iomem 
> *dist_base,
>  			gicv2m_init(handle, gic_data.domain);
>  	}
> 
> -	gic_enable_nmi_support();
> -
>  	return 0;
> 
>  out_free:

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Sumit Garg <sumit.garg@linaro.org>
Cc: catalin.marinas@arm.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org, tglx@linutronix.de,
	jason@lakedaemon.net, mark.rutland@arm.com,
	julien.thierry.kdev@gmail.com, dianders@chromium.org,
	daniel.thompson@linaro.org, jason.wessel@windriver.com,
	msys.mizuma@gmail.com, ito-yuichi@fujitsu.com,
	kgdb-bugreport@lists.sourceforge.net,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 2/5] irqchip/gic-v3: Enable support for SGIs to act as NMIs
Date: Mon, 19 Oct 2020 13:07:53 +0100	[thread overview]
Message-ID: <294754db12f4cd8a8ec9329a44e1cf02@kernel.org> (raw)
In-Reply-To: <1602673931-28782-3-git-send-email-sumit.garg@linaro.org>

On 2020-10-14 12:12, Sumit Garg wrote:
> Add support to handle SGIs as regular NMIs. As SGIs or IPIs defaults to 
> a

There is nothing "regular" about NMIs. Drop "or IPIs". 
s/defaults/default/

> special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
> handler update in case of SGIs.
> 
> Also, enable NMI support prior to gic_smp_init() as allocation of SGIs
> as IRQs/NMIs happen as part of this routine.
> 
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
>  drivers/irqchip/irq-gic-v3.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c 
> b/drivers/irqchip/irq-gic-v3.c
> index 16fecc0..5efc865 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -477,6 +477,11 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  	if (WARN_ON(gic_irq(d) >= 8192))
>  		return -EINVAL;
> 
> +	if (get_intid_range(d) == SGI_RANGE) {
> +		gic_irq_set_prio(d, GICD_INT_NMI_PRI);
> +		return 0;
> +	}
> +

Please follow the existing control flow, or rework it to be organised by 
range.

>  	/* desc lock should already be held */
>  	if (gic_irq_in_rdist(d)) {
>  		u32 idx = gic_get_ppi_index(d);
> @@ -514,6 +519,11 @@ static void gic_irq_nmi_teardown(struct irq_data 
> *d)
>  	if (WARN_ON(gic_irq(d) >= 8192))
>  		return;
> 
> +	if (get_intid_range(d) == SGI_RANGE) {
> +		gic_irq_set_prio(d, GICD_INT_DEF_PRI);
> +		return;
> +	}

Same here.

> +
>  	/* desc lock should already be held */
>  	if (gic_irq_in_rdist(d)) {
>  		u32 idx = gic_get_ppi_index(d);
> @@ -1708,6 +1718,7 @@ static int __init gic_init_bases(void __iomem 
> *dist_base,
> 
>  	gic_dist_init();
>  	gic_cpu_init();
> +	gic_enable_nmi_support();
>  	gic_smp_init();
>  	gic_cpu_pm_init();
> 
> @@ -1719,8 +1730,6 @@ static int __init gic_init_bases(void __iomem 
> *dist_base,
>  			gicv2m_init(handle, gic_data.domain);
>  	}
> 
> -	gic_enable_nmi_support();
> -
>  	return 0;
> 
>  out_free:

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

  parent reply	other threads:[~2020-10-19 12:09 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-14 11:12 [PATCH v5 0/5] arm64: Add framework to turn an IPI as NMI Sumit Garg
2020-10-14 11:12 ` Sumit Garg
2020-10-14 11:12 ` [PATCH v5 1/5] arm64: Add framework to turn " Sumit Garg
2020-10-14 11:12   ` Sumit Garg
2020-10-15  1:15   ` Masayoshi Mizuma
2020-10-15  1:15     ` Masayoshi Mizuma
2020-10-19 11:37   ` Marc Zyngier
2020-10-19 11:37     ` Marc Zyngier
2020-10-20  6:43     ` Sumit Garg
2020-10-20  6:43       ` Sumit Garg
2020-10-20 10:08       ` Marc Zyngier
2020-10-20 10:08         ` Marc Zyngier
2020-10-20 11:22         ` Sumit Garg
2020-10-20 11:22           ` Sumit Garg
2020-10-20 12:25           ` Daniel Thompson
2020-10-20 12:25             ` Daniel Thompson
2020-10-20 12:32             ` Marc Zyngier
2020-10-20 12:32               ` Marc Zyngier
2020-10-21  5:22               ` Sumit Garg
2020-10-21  5:22                 ` Sumit Garg
2020-10-21 10:27           ` Marc Zyngier
2020-10-21 10:27             ` Marc Zyngier
2020-10-22 11:52             ` Sumit Garg
2020-10-22 11:52               ` Sumit Garg
2020-10-19 11:56   ` Marc Zyngier
2020-10-19 11:56     ` Marc Zyngier
2020-10-20  7:07     ` Sumit Garg
2020-10-20  7:07       ` Sumit Garg
2020-10-14 11:12 ` [PATCH v5 2/5] irqchip/gic-v3: Enable support for SGIs to act as NMIs Sumit Garg
2020-10-14 11:12   ` Sumit Garg
2020-10-15  1:16   ` Masayoshi Mizuma
2020-10-15  1:16     ` Masayoshi Mizuma
2020-10-19 12:07   ` Marc Zyngier [this message]
2020-10-19 12:07     ` Marc Zyngier
2020-10-20  7:24     ` Sumit Garg
2020-10-20  7:24       ` Sumit Garg
2020-10-14 11:12 ` [PATCH v5 3/5] arm64: smp: Allocate and setup IPI as NMI Sumit Garg
2020-10-14 11:12   ` Sumit Garg
2020-10-15  1:16   ` Masayoshi Mizuma
2020-10-15  1:16     ` Masayoshi Mizuma
2020-10-19 11:59   ` Marc Zyngier
2020-10-19 11:59     ` Marc Zyngier
2020-10-20  7:16     ` Sumit Garg
2020-10-20  7:16       ` Sumit Garg
2020-10-14 11:12 ` [PATCH v5 4/5] arm64: kgdb: Round up cpus using " Sumit Garg
2020-10-14 11:12   ` Sumit Garg
2020-10-19 12:15   ` Marc Zyngier
2020-10-19 12:15     ` Marc Zyngier
2020-10-20  8:51     ` Sumit Garg
2020-10-20  8:51       ` Sumit Garg
2020-10-14 11:12 ` [PATCH v5 5/5] arm64: ipi_nmi: Add support for NMI backtrace Sumit Garg
2020-10-14 11:12   ` Sumit Garg
2020-10-15  1:17   ` Masayoshi Mizuma
2020-10-15  1:17     ` Masayoshi Mizuma
2020-10-19 12:20   ` Marc Zyngier
2020-10-19 12:20     ` Marc Zyngier
2020-10-20  9:13     ` Sumit Garg
2020-10-20  9:13       ` Sumit Garg
2020-10-21 10:32       ` Marc Zyngier
2020-10-21 10:32         ` Marc Zyngier
2020-10-21 11:28         ` Sumit Garg
2020-10-21 11:28           ` Sumit Garg

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