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From: Konrad Dybcio <konradybcio@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
	kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
	konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org,
	quic_msarkar@quicinc.com, quic_devipriy@quicinc.com,
	dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org,
	neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
Date: Thu, 19 Sep 2024 17:37:33 +0200	[thread overview]
Message-ID: <2acbaedc-e577-4685-875c-ba599d845b19@kernel.org> (raw)
In-Reply-To: <b36819ed-0e4a-4820-8c38-ac9d2c6f0f28@quicinc.com>

On 19.09.2024 4:03 PM, Qiang Yu wrote:
> 
> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote:
>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote:
>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane
>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module.
>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg.
> Yes, PCIe3 use a different phy that supports 8 lanes and provides
> additional register set, txz and rxz. It is not a bifurcation mode which
> actually combines two same phys like PCIe6a. It's also not just different
> number of lanes. Will explain this in commit msg.

Krzysztof, this PHY is new and has a different hardware revision (v6.30 as
opposed to v6.20? of the other ones)

Konrad

WARNING: multiple messages have this Message-ID (diff)
From: Konrad Dybcio <konradybcio@kernel.org>
To: Qiang Yu <quic_qianyu@quicinc.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
	kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
	konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org,
	quic_msarkar@quicinc.com, quic_devipriy@quicinc.com,
	dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org,
	neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
Date: Thu, 19 Sep 2024 17:37:33 +0200	[thread overview]
Message-ID: <2acbaedc-e577-4685-875c-ba599d845b19@kernel.org> (raw)
In-Reply-To: <b36819ed-0e4a-4820-8c38-ac9d2c6f0f28@quicinc.com>

On 19.09.2024 4:03 PM, Qiang Yu wrote:
> 
> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote:
>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote:
>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane
>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module.
>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg.
> Yes, PCIe3 use a different phy that supports 8 lanes and provides
> additional register set, txz and rxz. It is not a bifurcation mode which
> actually combines two same phys like PCIe6a. It's also not just different
> number of lanes. Will explain this in commit msg.

Krzysztof, this PHY is new and has a different hardware revision (v6.30 as
opposed to v6.20? of the other ones)

Konrad

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2024-09-19 15:37 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-13  8:37 [PATCH v2 0/5] Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13  8:37 ` Qiang Yu
2024-09-13  8:37 ` [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-09-13  8:37   ` Qiang Yu
2024-09-13 13:37   ` Manivannan Sadhasivam
2024-09-13 13:37     ` Manivannan Sadhasivam
2024-09-19 13:47     ` Qiang Yu
2024-09-19 13:47       ` Qiang Yu
2024-09-16 15:15   ` Krzysztof Kozlowski
2024-09-16 15:15     ` Krzysztof Kozlowski
2024-09-19 14:03     ` Qiang Yu
2024-09-19 14:03       ` Qiang Yu
2024-09-19 15:37       ` Konrad Dybcio [this message]
2024-09-19 15:37         ` Konrad Dybcio
2024-09-20 11:22         ` Krzysztof Kozlowski
2024-09-20 11:22           ` Krzysztof Kozlowski
2024-09-13  8:37 ` [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100 Qiang Yu
2024-09-13  8:37   ` Qiang Yu
2024-09-13 12:30   ` Dmitry Baryshkov
2024-09-13 12:30     ` Dmitry Baryshkov
2024-09-13 13:36     ` Manivannan Sadhasivam
2024-09-13 13:36       ` Manivannan Sadhasivam
2024-09-16 15:20       ` Krzysztof Kozlowski
2024-09-16 15:20         ` Krzysztof Kozlowski
2024-09-16 15:20   ` Krzysztof Kozlowski
2024-09-16 15:20     ` Krzysztof Kozlowski
2024-09-13  8:37 ` [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-09-13  8:37   ` Qiang Yu
2024-09-13 12:28   ` Dmitry Baryshkov
2024-09-13 12:28     ` Dmitry Baryshkov
2024-09-16 23:29   ` Konrad Dybcio
2024-09-16 23:29     ` Konrad Dybcio
2024-09-13  8:37 ` [PATCH v2 4/5] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-09-13  8:37   ` Qiang Yu
2024-09-13  8:37 ` [PATCH v2 5/5] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13  8:37   ` Qiang Yu
2024-09-13 12:35   ` Dmitry Baryshkov
2024-09-13 12:35     ` Dmitry Baryshkov
2024-09-13 13:57   ` Manivannan Sadhasivam
2024-09-13 13:57     ` Manivannan Sadhasivam
2024-09-19 14:05     ` Qiang Yu
2024-09-19 14:05       ` Qiang Yu
2024-09-14  3:59 ` [PATCH v2 0/5] " Krishna Chaitanya Chundru
2024-09-14  3:59   ` Krishna Chaitanya Chundru
2024-09-19 14:14   ` Qiang Yu
2024-09-19 14:14     ` Qiang Yu
2024-09-22 17:09     ` Manivannan Sadhasivam
2024-09-22 17:09       ` Manivannan Sadhasivam

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