From: Krzysztof Kozlowski <krzk@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com,
quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org,
kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
Date: Fri, 20 Sep 2024 13:22:35 +0200 [thread overview]
Message-ID: <cd40d57c-51d2-480e-80ef-7d87dd96a6b2@kernel.org> (raw)
In-Reply-To: <2acbaedc-e577-4685-875c-ba599d845b19@kernel.org>
On 19/09/2024 17:37, Konrad Dybcio wrote:
> On 19.09.2024 4:03 PM, Qiang Yu wrote:
>>
>> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote:
>>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane
>>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module.
>>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg.
>> Yes, PCIe3 use a different phy that supports 8 lanes and provides
>> additional register set, txz and rxz. It is not a bifurcation mode which
>> actually combines two same phys like PCIe6a. It's also not just different
>> number of lanes. Will explain this in commit msg.
>
> Krzysztof, this PHY is new and has a different hardware revision (v6.30 as
> opposed to v6.20? of the other ones)
It's fine for me then, but I expect commit msg to say this. For I am a
bear of very little brain, and I forget the topic right after I close
the email.
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
Qiang Yu <quic_qianyu@quicinc.com>
Cc: manivannan.sadhasivam@linaro.org, vkoul@kernel.org,
kishon@kernel.org, robh@kernel.org, andersson@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com,
quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org,
kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
Date: Fri, 20 Sep 2024 13:22:35 +0200 [thread overview]
Message-ID: <cd40d57c-51d2-480e-80ef-7d87dd96a6b2@kernel.org> (raw)
In-Reply-To: <2acbaedc-e577-4685-875c-ba599d845b19@kernel.org>
On 19/09/2024 17:37, Konrad Dybcio wrote:
> On 19.09.2024 4:03 PM, Qiang Yu wrote:
>>
>> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote:
>>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane
>>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module.
>>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg.
>> Yes, PCIe3 use a different phy that supports 8 lanes and provides
>> additional register set, txz and rxz. It is not a bifurcation mode which
>> actually combines two same phys like PCIe6a. It's also not just different
>> number of lanes. Will explain this in commit msg.
>
> Krzysztof, this PHY is new and has a different hardware revision (v6.30 as
> opposed to v6.20? of the other ones)
It's fine for me then, but I expect commit msg to say this. For I am a
bear of very little brain, and I forget the topic right after I close
the email.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2024-09-20 11:22 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-13 8:37 [PATCH v2 0/5] Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 8:37 ` [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 13:37 ` Manivannan Sadhasivam
2024-09-13 13:37 ` Manivannan Sadhasivam
2024-09-19 13:47 ` Qiang Yu
2024-09-19 13:47 ` Qiang Yu
2024-09-16 15:15 ` Krzysztof Kozlowski
2024-09-16 15:15 ` Krzysztof Kozlowski
2024-09-19 14:03 ` Qiang Yu
2024-09-19 14:03 ` Qiang Yu
2024-09-19 15:37 ` Konrad Dybcio
2024-09-19 15:37 ` Konrad Dybcio
2024-09-20 11:22 ` Krzysztof Kozlowski [this message]
2024-09-20 11:22 ` Krzysztof Kozlowski
2024-09-13 8:37 ` [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100 Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 12:30 ` Dmitry Baryshkov
2024-09-13 12:30 ` Dmitry Baryshkov
2024-09-13 13:36 ` Manivannan Sadhasivam
2024-09-13 13:36 ` Manivannan Sadhasivam
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-16 15:20 ` Krzysztof Kozlowski
2024-09-13 8:37 ` [PATCH v2 3/5] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 12:28 ` Dmitry Baryshkov
2024-09-13 12:28 ` Dmitry Baryshkov
2024-09-16 23:29 ` Konrad Dybcio
2024-09-16 23:29 ` Konrad Dybcio
2024-09-13 8:37 ` [PATCH v2 4/5] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 8:37 ` [PATCH v2 5/5] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-09-13 8:37 ` Qiang Yu
2024-09-13 12:35 ` Dmitry Baryshkov
2024-09-13 12:35 ` Dmitry Baryshkov
2024-09-13 13:57 ` Manivannan Sadhasivam
2024-09-13 13:57 ` Manivannan Sadhasivam
2024-09-19 14:05 ` Qiang Yu
2024-09-19 14:05 ` Qiang Yu
2024-09-14 3:59 ` [PATCH v2 0/5] " Krishna Chaitanya Chundru
2024-09-14 3:59 ` Krishna Chaitanya Chundru
2024-09-19 14:14 ` Qiang Yu
2024-09-19 14:14 ` Qiang Yu
2024-09-22 17:09 ` Manivannan Sadhasivam
2024-09-22 17:09 ` Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cd40d57c-51d2-480e-80ef-7d87dd96a6b2@kernel.org \
--to=krzk@kernel.org \
--cc=abel.vesa@linaro.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=kishon@kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mturquette@baylibre.com \
--cc=neil.armstrong@linaro.org \
--cc=quic_devipriy@quicinc.com \
--cc=quic_msarkar@quicinc.com \
--cc=quic_qianyu@quicinc.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.