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From: "Chee, Tien Fong" <tien.fong.chee@altera.com>
To: Chen Huei Lok <chen.huei.lok@altera.com>, u-boot@lists.denx.de
Cc: Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,
	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
	Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
	Dinesh Maniyam <dinesh.maniyam@altera.com>,
	Boon Khai Ng <boon.khai.ng@altera.com>,
	Kok Kiang Hea <kok.kiang.hea@altera.com>
Subject: Re: [PATCH v2 4/8] configs: socfpga: n5x: enable required configs for DDR retention
Date: Thu, 14 May 2026 11:22:05 +0800	[thread overview]
Message-ID: <310fffa8-8196-497f-a292-96c9a70dd672@altera.com> (raw)
In-Reply-To: <20260428070017.16807-5-chen.huei.lok@altera.com>

Hi Lok,


On 28/4/2026 3:00 pm, Chen Huei Lok wrote:
> Enable required configs to support DDR retention. Including generic
> firmware loader for loading backup calibration data, and SHA384/512
> checking.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
> Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
> ---
>   configs/socfpga_n5x_defconfig | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
> index b6df9946ef3..273e74c6499 100644
> --- a/configs/socfpga_n5x_defconfig
> +++ b/configs/socfpga_n5x_defconfig
> @@ -90,4 +90,8 @@ CONFIG_WDT=y
>   # CONFIG_SPL_USE_TINY_PRINTF is not set
>   CONFIG_PANIC_HANG=y
>   CONFIG_SPL_CRC32=y
> +CONFIG_SHA512_ALGO=y
> +CONFIG_SHA384=y
> +CONFIG_FS_LOADER=y
> +CONFIG_SPL_ENV_SUPPORT=y
>   # CONFIG_TOOLS_MKEFICAPSULE is not set


Please document the rationale for introducing DDR retention and describe

how HA384/SHA512, FS_LOADER, and CONFIG_SPL_ENV_SUPPORT are adapted to 
support DDR retention (e.g., required init/order changes, state handoff, 
buffer placement, and

failure modes).

It appears FS_LOADER may be missing pieces needed for DDR retention 
(such as handling retained memory regions or re-init sequencing).

Consider restructuring this as a series that first enables DDR retention 
for N5X, then adds the required support in FS_LOADER and SPL env 
handling in follow-up patches.


Best regards,

Tien Fong


  reply	other threads:[~2026-05-14  3:22 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-28  7:00 [PATCH v2 0/8] socfpga: n5x: Update Boot Support for N5X Chen Huei Lok
2026-04-28  7:00 ` [PATCH v2 1/8] configs: socfpga: n5x: replace defconfig with ATF variant and simplify VAB Chen Huei Lok
2026-04-28  7:00 ` [PATCH v2 2/8] arm: dts: socfpga: n5x: enable DT register settings and update GMAC nodes Chen Huei Lok
2026-04-28  7:00 ` [PATCH v2 3/8] configs: socfpga: n5x: enable CMD_MTD and SPL SDRAM support Chen Huei Lok
2026-05-14  3:00   ` Chee, Tien Fong
2026-04-28  7:00 ` [PATCH v2 4/8] configs: socfpga: n5x: enable required configs for DDR retention Chen Huei Lok
2026-05-14  3:22   ` Chee, Tien Fong [this message]
2026-04-28  7:00 ` [PATCH v2 5/8] configs: socfpga: n5x: enable ISSI QSPI Chen Huei Lok
2026-04-28  7:00 ` [PATCH v2 6/8] arm: socfpga: n5x: switch firewall setup to driver model Chen Huei Lok
2026-05-14  3:36   ` Chee, Tien Fong
2026-04-28  7:00 ` [PATCH v2 7/8] arch: arm: dts: n5x: switch to using upstream Linux DT config Chen Huei Lok
2026-04-28  7:00 ` [PATCH v2 8/8] arm: socfpga: n5x: update SPL data save and restore implementation Chen Huei Lok
  -- strict thread matches above, loose matches on Subject: below --
2026-04-28  6:49 [PATCH v2 0/8] socfpga: n5x: Update Boot Support for N5X Chen Huei Lok
2026-04-28  6:49 ` [PATCH v2 4/8] configs: socfpga: n5x: enable required configs for DDR retention Chen Huei Lok

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