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From: Heiko Stübner <heiko@sntech.de>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH -next v17 05/20] riscv: Disable Vector Instructions for kernel itself
Date: Fri, 31 Mar 2023 12:56:11 +0200	[thread overview]
Message-ID: <3227690.44csPzL39Z@diego> (raw)
In-Reply-To: <20230327164941.20491-6-andy.chiu@sifive.com>

Am Montag, 27. M?rz 2023, 18:49:25 CEST schrieb Andy Chiu:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> Disable vector instructions execution for kernel mode at its entrances.

nit: Might be nice to just add the simple explanation from the code-
comments that this helps for example to find illegal vector uses in the
kernel space, similar to the fpu.

> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>

> ---
>  arch/riscv/kernel/entry.S |  6 +++---
>  arch/riscv/kernel/head.S  | 12 ++++++------
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 3fbb100bc9e4..e9ae284a55c1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -48,10 +48,10 @@ _save_context:
>  	 * Disable user-mode memory access as it should only be set in the
>  	 * actual user copy routines.
>  	 *
> -	 * Disable the FPU to detect illegal usage of floating point in kernel
> -	 * space.
> +	 * Disable the FPU/Vector to detect illegal usage of floating point
> +	 * or vector in kernel space.
>  	 */
> -	li t0, SR_SUM | SR_FS
> +	li t0, SR_SUM | SR_FS_VS
>  
>  	REG_L s0, TASK_TI_USER_SP(tp)
>  	csrrc s1, CSR_STATUS, t0
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 3fd6a4bd9c3e..e16bb2185d55 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -140,10 +140,10 @@ secondary_start_sbi:
>  	.option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  	/* Set trap vector to spin forever to help debug */
> @@ -234,10 +234,10 @@ pmp_done:
>  .option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  #ifdef CONFIG_RISCV_BOOT_SPINWAIT
> 






WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	"Vincent Chen" <vincent.chen@sifive.com>,
	"Han-Kuan Chen" <hankuan.chen@sifive.com>,
	"Andy Chiu" <andy.chiu@sifive.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Nicolas Saenz Julienne" <nsaenzju@redhat.com>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Frederic Weisbecker" <frederic@kernel.org>,
	"Andrew Bresticker" <abrestic@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Masahiro Yamada" <masahiroy@kernel.org>,
	"Alexandre Ghiti" <alexandre.ghiti@canonical.com>,
	"Andy Chiu" <andy.chiu@sifive.com>
Subject: Re: [PATCH -next v17 05/20] riscv: Disable Vector Instructions for kernel itself
Date: Fri, 31 Mar 2023 12:56:11 +0200	[thread overview]
Message-ID: <3227690.44csPzL39Z@diego> (raw)
In-Reply-To: <20230327164941.20491-6-andy.chiu@sifive.com>

Am Montag, 27. März 2023, 18:49:25 CEST schrieb Andy Chiu:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> Disable vector instructions execution for kernel mode at its entrances.

nit: Might be nice to just add the simple explanation from the code-
comments that this helps for example to find illegal vector uses in the
kernel space, similar to the fpu.

> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>

> ---
>  arch/riscv/kernel/entry.S |  6 +++---
>  arch/riscv/kernel/head.S  | 12 ++++++------
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 3fbb100bc9e4..e9ae284a55c1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -48,10 +48,10 @@ _save_context:
>  	 * Disable user-mode memory access as it should only be set in the
>  	 * actual user copy routines.
>  	 *
> -	 * Disable the FPU to detect illegal usage of floating point in kernel
> -	 * space.
> +	 * Disable the FPU/Vector to detect illegal usage of floating point
> +	 * or vector in kernel space.
>  	 */
> -	li t0, SR_SUM | SR_FS
> +	li t0, SR_SUM | SR_FS_VS
>  
>  	REG_L s0, TASK_TI_USER_SP(tp)
>  	csrrc s1, CSR_STATUS, t0
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 3fd6a4bd9c3e..e16bb2185d55 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -140,10 +140,10 @@ secondary_start_sbi:
>  	.option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  	/* Set trap vector to spin forever to help debug */
> @@ -234,10 +234,10 @@ pmp_done:
>  .option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  #ifdef CONFIG_RISCV_BOOT_SPINWAIT
> 





_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com,
	"Vincent Chen" <vincent.chen@sifive.com>,
	"Han-Kuan Chen" <hankuan.chen@sifive.com>,
	"Andy Chiu" <andy.chiu@sifive.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Nicolas Saenz Julienne" <nsaenzju@redhat.com>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Frederic Weisbecker" <frederic@kernel.org>,
	"Andrew Bresticker" <abrestic@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Masahiro Yamada" <masahiroy@kernel.org>,
	"Alexandre Ghiti" <alexandre.ghiti@canonical.com>,
	"Andy Chiu" <andy.chiu@sifive.com>
Subject: Re: [PATCH -next v17 05/20] riscv: Disable Vector Instructions for kernel itself
Date: Fri, 31 Mar 2023 12:56:11 +0200	[thread overview]
Message-ID: <3227690.44csPzL39Z@diego> (raw)
In-Reply-To: <20230327164941.20491-6-andy.chiu@sifive.com>

Am Montag, 27. März 2023, 18:49:25 CEST schrieb Andy Chiu:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> Disable vector instructions execution for kernel mode at its entrances.

nit: Might be nice to just add the simple explanation from the code-
comments that this helps for example to find illegal vector uses in the
kernel space, similar to the fpu.

> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>

> ---
>  arch/riscv/kernel/entry.S |  6 +++---
>  arch/riscv/kernel/head.S  | 12 ++++++------
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 3fbb100bc9e4..e9ae284a55c1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -48,10 +48,10 @@ _save_context:
>  	 * Disable user-mode memory access as it should only be set in the
>  	 * actual user copy routines.
>  	 *
> -	 * Disable the FPU to detect illegal usage of floating point in kernel
> -	 * space.
> +	 * Disable the FPU/Vector to detect illegal usage of floating point
> +	 * or vector in kernel space.
>  	 */
> -	li t0, SR_SUM | SR_FS
> +	li t0, SR_SUM | SR_FS_VS
>  
>  	REG_L s0, TASK_TI_USER_SP(tp)
>  	csrrc s1, CSR_STATUS, t0
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 3fd6a4bd9c3e..e16bb2185d55 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -140,10 +140,10 @@ secondary_start_sbi:
>  	.option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  	/* Set trap vector to spin forever to help debug */
> @@ -234,10 +234,10 @@ pmp_done:
>  .option pop
>  
>  	/*
> -	 * Disable FPU to detect illegal usage of
> -	 * floating point in kernel space
> +	 * Disable FPU & VECTOR to detect illegal usage of
> +	 * floating point or vector in kernel space
>  	 */
> -	li t0, SR_FS
> +	li t0, SR_FS_VS
>  	csrc CSR_STATUS, t0
>  
>  #ifdef CONFIG_RISCV_BOOT_SPINWAIT
> 





  reply	other threads:[~2023-03-31 10:56 UTC|newest]

Thread overview: 129+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-27 16:49 [PATCH -next v17 00/20] riscv: Add vector ISA support Andy Chiu
2023-03-27 16:49 ` Andy Chiu
2023-03-27 16:49 ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 01/20] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 02/20] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:45   ` Heiko Stübner
2023-03-31 10:45     ` Heiko Stübner
2023-03-31 10:45     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 03/20] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 16:03   ` Heiko Stübner
2023-03-31 16:03     ` Heiko Stübner
2023-03-31 16:03     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 04/20] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:53   ` Heiko Stübner
2023-03-31 10:53     ` Heiko Stübner
2023-03-31 10:53     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 05/20] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:56   ` Heiko Stübner [this message]
2023-03-31 10:56     ` Heiko Stübner
2023-03-31 10:56     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 06/20] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:56   ` Heiko Stübner
2023-03-31 10:56     ` Heiko Stübner
2023-03-31 10:56     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:02   ` Heiko Stübner
2023-03-31 11:02     ` Heiko Stübner
2023-03-31 11:02     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:05   ` Heiko Stübner
2023-03-31 11:05     ` Heiko Stübner
2023-03-31 11:05     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 09/20] riscv: Add task switch support for vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:19   ` Heiko Stübner
2023-03-31 11:19     ` Heiko Stübner
2023-03-31 11:19     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 10/20] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-28 17:22   ` Conor Dooley
2023-03-28 17:22     ` Conor Dooley
2023-03-28 17:22     ` Conor Dooley
2023-03-31 14:38     ` Andy Chiu
2023-03-31 14:38       ` Andy Chiu
2023-03-31 14:38       ` Andy Chiu
2023-03-31 13:08   ` Heiko Stübner
2023-03-31 13:08     ` Heiko Stübner
2023-03-31 13:08     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 11/20] riscv: Add ptrace vector support Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-28  5:53   ` Rolf Eike Beer
2023-03-28  5:53     ` Rolf Eike Beer
2023-03-28  5:53     ` Rolf Eike Beer
2023-03-28  6:46     ` Andy Chiu
2023-03-28  6:46       ` Andy Chiu
2023-03-28  6:46       ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 12/20] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:21   ` Heiko Stübner
2023-04-01 22:21     ` Heiko Stübner
2023-04-01 22:21     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 13/20] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:20   ` Heiko Stübner
2023-04-01 22:20     ` Heiko Stübner
2023-04-01 22:20     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 14/20] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:19   ` Heiko Stübner
2023-04-01 22:19     ` Heiko Stübner
2023-04-01 22:19     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 15/20] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:43   ` Heiko Stübner
2023-03-31 13:43     ` Heiko Stübner
2023-03-31 13:43     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:38   ` Heiko Stübner
2023-03-31 13:38     ` Heiko Stübner
2023-03-31 13:38     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 17/20] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:36   ` Heiko Stübner
2023-03-31 13:36     ` Heiko Stübner
2023-03-31 13:36     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 18/20] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 17:36   ` Anup Patel
2023-03-27 17:36     ` Anup Patel
2023-03-27 17:36     ` Anup Patel
2023-03-27 16:49 ` [PATCH -next v17 19/20] riscv: detect assembler support for .option arch Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:33   ` Heiko Stübner
2023-03-31 13:33     ` Heiko Stübner
2023-03-31 13:33     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 20/20] riscv: Enable Vector code to be built Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:32   ` Heiko Stübner
2023-03-31 13:32     ` Heiko Stübner
2023-03-31 13:32     ` Heiko Stübner

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