[PATCH v10 0/3] Add resets for ADSP based audio clock controller driver

[PATCH v10 0/3] Add resets for ADSP based audio clock controller driver

[Mohammad Rafi Shaik]

Add resets and remove qdsp6ss clock controller for audioreach based platforms.

Changes since v9:
    -- Drop "clk: qcom: lpassaudiocc-sc7280: Modify qcom_cc_probe" patch.
    -- Update Fixes tag in Add the required gdsc's in lpass_cc_sc7280_desc patch.
    -- Add the max_register value in Skip qdsp6ss clock registration patch.
Changes since v8:
    -- Add the required gdsc's in lpass_cc_sc7280_desc structure.
    -- Modify qcom_cc_probe to qcom_cc_probe_by_index.
    -- Update the commit message for v8,4/5 patch, which is not required for new logic.
    -- Drop "Add binding headers for lpasscc" patch.
    -- Drop "Skip lpass_aon_cc_pll config" patch.
Changes since v7:
    -- Modiy AHB clock probing method in "Merge lpasscc into lpass_aon patch".
    -- Fix Typo errors in "Merge lpasscc into lpass_aon patch".
    -- Update commit message in "Merge lpasscc into lpass_aon patch"
Changes since v6:
    -- Update commit message in "Merge lpasscc into lpass_aon patch" patch.
    -- Drop "Skip lpasscorecc registration" patch.
    -- Add comment in the code in "Skip lpass_aon_cc_pll config" patch.
Changes since v5:
    -- Fix compilation issue.
Changes since v4:
    -- Update Fixes tag in Merge lpasscc into lpass_aon patch.
    -- Revert removal of clk_regmap structure in Merge lpasscc into lpass_aon patch.
Changes since v3:
    -- Remove duplicate clock resets patch.
    -- Add binding headers for q6 clocks.
    -- Create new patch for merging lpasscc q6 clocks into lpass_aon.
    -- Create new patches for handling conflicts of ADSP and bypass solution.
Changes since v2:
    -- Revert removing qdsp6ss clock control.
    -- Add Conditional check for qdsp6ss clock registration.
Changes since v1:
    -- Update commit message.
    -- Remove qdsp6ss clock control.

Mohammad Rafi Shaik (1):
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in
    lpass_cc_sc7280_desc

Srinivasa Rao Mandadapu (2):
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode
    property
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration

 .../bindings/clock/qcom,sc7280-lpasscc.yaml       |  7 +++++++
 drivers/clk/qcom/lpassaudiocc-sc7280.c            |  2 ++
 drivers/clk/qcom/lpasscc-sc7280.c                 | 15 ++++++++++-----
 3 files changed, 19 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH v10 1/3] dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property

[Mohammad Rafi Shaik]

From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

When this property is set, the remoteproc is used to boot the
LPASS and therefore qdsp6ss clocks would be used to bring LPASS
out of reset, hence they are directly controlled by the remoteproc.

This is a cleanup done to handle overlap of regmap of lpasscc
and adsp remoteproc blocks.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
 .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml     | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 6151fdebbff8..97c6bd96e0cb 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -41,6 +41,12 @@ properties:
       - const: qdsp6ss
       - const: top_cc
 
+  qcom,adsp-pil-mode:
+    description:
+      Indicates if the LPASS would be brought out of reset using
+      remoteproc peripheral loader.
+    type: boolean
+
 required:
   - compatible
   - reg
@@ -60,6 +66,7 @@ examples:
       reg-names = "qdsp6ss", "top_cc";
       clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
       clock-names = "iface";
+      qcom,adsp-pil-mode;
       #clock-cells = <1>;
     };
 ...
-- 
2.25.1

[PATCH v10 2/3] clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration

[Mohammad Rafi Shaik]

From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver,
skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled.

Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
 drivers/clk/qcom/lpasscc-sc7280.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index 5c1e17bd0d76..24aeed6bcf0e 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -17,6 +17,8 @@
 #include "clk-branch.h"
 #include "common.h"
 
+#define QDSP6SS_MAX_REGISTER		0x3f
+
 static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
 	.halt_reg = 0x0,
 	.halt_check = BRANCH_HALT,
@@ -118,12 +120,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
 		goto destroy_pm_clk;
 	}
 
-	lpass_regmap_config.name = "qdsp6ss";
-	desc = &lpass_qdsp6ss_sc7280_desc;
+	if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
+		lpass_regmap_config.name = "qdsp6ss";
+		lpass_regmap_config.max_register = QDSP6SS_MAX_REGISTER;
+		desc = &lpass_qdsp6ss_sc7280_desc;
 
-	ret = qcom_cc_probe_by_index(pdev, 0, desc);
-	if (ret)
-		goto destroy_pm_clk;
+		ret = qcom_cc_probe_by_index(pdev, 0, desc);
+		if (ret)
+			goto destroy_pm_clk;
+	}
 
 	lpass_regmap_config.name = "top_cc";
 	desc = &lpass_cc_top_sc7280_desc;
-- 
2.25.1

Re: [PATCH v10 2/3] clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration

[Stephen Boyd]

Quoting Mohammad Rafi Shaik (2023-03-31 08:28:04)
> diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
> index 5c1e17bd0d76..24aeed6bcf0e 100644
> --- a/drivers/clk/qcom/lpasscc-sc7280.c
> +++ b/drivers/clk/qcom/lpasscc-sc7280.c
> @@ -17,6 +17,8 @@
>  #include "clk-branch.h"
>  #include "common.h"
>  
> +#define QDSP6SS_MAX_REGISTER           0x3f

You can drop the define and just put the raw number in the one place
this is used.

> +
>  static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
>         .halt_reg = 0x0,
>         .halt_check = BRANCH_HALT,
> @@ -118,12 +120,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
>                 goto destroy_pm_clk;
>         }
>  
> -       lpass_regmap_config.name = "qdsp6ss";
> -       desc = &lpass_qdsp6ss_sc7280_desc;
> +       if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
> +               lpass_regmap_config.name = "qdsp6ss";
> +               lpass_regmap_config.max_register = QDSP6SS_MAX_REGISTER;
> +               desc = &lpass_qdsp6ss_sc7280_desc;
>

Re: [PATCH v10 2/3] clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration

[Mohammad Rafi Shaik]

On 4/1/2023 12:16 AM, Stephen Boyd wrote:
> Quoting Mohammad Rafi Shaik (2023-03-31 08:28:04)
>> diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
>> index 5c1e17bd0d76..24aeed6bcf0e 100644
>> --- a/drivers/clk/qcom/lpasscc-sc7280.c
>> +++ b/drivers/clk/qcom/lpasscc-sc7280.c
>> @@ -17,6 +17,8 @@
>>   #include "clk-branch.h"
>>   #include "common.h"
>>   
>> +#define QDSP6SS_MAX_REGISTER           0x3f
> You can drop the define and just put the raw number in the one place
> this is used.
Thanks for comment,

okay, will drop the define.
>> +
>>   static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
>>          .halt_reg = 0x0,
>>          .halt_check = BRANCH_HALT,
>> @@ -118,12 +120,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
>>                  goto destroy_pm_clk;
>>          }
>>   
>> -       lpass_regmap_config.name = "qdsp6ss";
>> -       desc = &lpass_qdsp6ss_sc7280_desc;
>> +       if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
>> +               lpass_regmap_config.name = "qdsp6ss";
>> +               lpass_regmap_config.max_register = QDSP6SS_MAX_REGISTER;
>> +               desc = &lpass_qdsp6ss_sc7280_desc;
>>

[PATCH v10 3/3] clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc

[Mohammad Rafi Shaik]

Add GDSCs in lpass_cc_sc7280_desc struct.
When qcom,adsp-pil-mode is enabled, GDSCs required to solve
dependencies in lpass_audiocc probe().

Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon")
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 drivers/clk/qcom/lpassaudiocc-sc7280.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 1339f9211a14..134eb1529ede 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -696,6 +696,8 @@ static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
 	.config = &lpass_audio_cc_sc7280_regmap_config,
 	.clks = lpass_cc_sc7280_clocks,
 	.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
+	.gdscs = lpass_aon_cc_sc7280_gdscs,
+	.num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
 };
 
 static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
-- 
2.25.1

Re: [PATCH v10 0/3] Add resets for ADSP based audio clock controller driver

[Stephen Boyd]

Quoting Mohammad Rafi Shaik (2023-03-31 08:28:02)
> Add resets and remove qdsp6ss clock controller for audioreach based platforms.

Does this supersede the v1 patch series[1]?

> 
> Changes since v9:
>     -- Drop "clk: qcom: lpassaudiocc-sc7280: Modify qcom_cc_probe" patch.
>     -- Update Fixes tag in Add the required gdsc's in lpass_cc_sc7280_desc patch.
>     -- Add the max_register value in Skip qdsp6ss clock registration patch.

[1] https://lore.kernel.org/linux-clk/20230327163249.1081824-1-quic_mohs@quicinc.com/