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From: Marc Zyngier <maz@kernel.org>
To: Vincent Guittot <vincent.guittot@linaro.org>
Cc: Sumit Garg <sumit.garg@linaro.org>,
	Android Kernel Team <kernel-team@android.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Russell King <linux@arm.linux.org.uk>,
	Jason Cooper <jason@lakedaemon.net>,
	Saravana Kannan <saravanak@google.com>,
	Andrew Lunn <andrew@lunn.ch>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Will Deacon <will@kernel.org>,
	Valentin Schneider <Valentin.Schneider@arm.com>,
	LAK <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 03/16] arm64: Allow IPIs to be handled as normal interrupts
Date: Mon, 19 Oct 2020 14:04:19 +0100	[thread overview]
Message-ID: <353f13b0dcc6c7ea1b44012d9632a0cc@kernel.org> (raw)
In-Reply-To: <CAKfTPtDjPpri5Gt6kLeFp_B_zJUZ5DYXEqtJ+0VKohU-y9bFEQ@mail.gmail.com>

Hi Vincent,

On 2020-10-19 13:42, Vincent Guittot wrote:
> Hi Marc,
> 
> On Tue, 1 Sep 2020 at 16:44, Marc Zyngier <maz@kernel.org> wrote:
>> 
>> In order to deal with IPIs as normal interrupts, let's add
>> a new way to register them with the architecture code.
>> 
>> set_smp_ipi_range() takes a range of interrupts, and allows
>> the arch code to request them as if the were normal interrupts.
>> A standard handler is then called by the core IRQ code to deal
>> with the IPI.
>> 
>> This means that we don't need to call irq_enter/irq_exit, and
>> that we don't need to deal with set_irq_regs either. So let's
>> move the dispatcher into its own function, and leave handle_IPI()
>> as a compatibility function.
>> 
>> On the sending side, let's make use of ipi_send_mask, which
>> already exists for this purpose.
>> 
>> One of the major difference is that we end up, in some cases
>> (such as when performing IRQ time accounting on the scheduler
>> IPI), end up with nested irq_enter()/irq_exit() pairs.
>> Other than the (relatively small) overhead, there should be
>> no consequences to it (these pairs are designed to nest
>> correctly, and the accounting shouldn't be off).
> 
> While rebasing on mainline, I have faced a performance regression for
> the benchmark:
> perf bench sched pipe
> on my arm64 dual quad core (hikey) and my 2 nodes x 112 CPUS (thx2)
> 
> The regression comes from:
> commit: d3afc7f12987 ("arm64: Allow IPIs to be handled as normal 
> interrupts")

That's interesting, as this patch doesn't really change anything (most
of the potential overhead comes in later). The only potential overhead
I can see is that the scheduler_ipi() call is now wrapped around
irq_enter()/irq_exit().

> 
>           v5.9              + this patch
> hikey :   48818(+/- 0.31)   37503(+/- 0.15%)  -23.2%
> thx2  :  132410(+/- 1.72)  122646(+/- 1.92%)   -7.4%
> 
> By + this patch,  I mean merging branch from this patch. Whereas
> merging the previous:
> commit: 83cfac95c018 ("genirq: Allow interrupts to be excluded from
> /proc/interrupts")
>  It doesn't show any regression

Since you are running perf, can you spot where the overhead occurs?

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Vincent Guittot <vincent.guittot@linaro.org>
Cc: LAK <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Russell King <linux@arm.linux.org.uk>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Sumit Garg <sumit.garg@linaro.org>,
	Valentin Schneider <Valentin.Schneider@arm.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Andrew Lunn <andrew@lunn.ch>,
	Saravana Kannan <saravanak@google.com>,
	Android Kernel Team <kernel-team@android.com>
Subject: Re: [PATCH v3 03/16] arm64: Allow IPIs to be handled as normal interrupts
Date: Mon, 19 Oct 2020 14:04:19 +0100	[thread overview]
Message-ID: <353f13b0dcc6c7ea1b44012d9632a0cc@kernel.org> (raw)
In-Reply-To: <CAKfTPtDjPpri5Gt6kLeFp_B_zJUZ5DYXEqtJ+0VKohU-y9bFEQ@mail.gmail.com>

Hi Vincent,

On 2020-10-19 13:42, Vincent Guittot wrote:
> Hi Marc,
> 
> On Tue, 1 Sep 2020 at 16:44, Marc Zyngier <maz@kernel.org> wrote:
>> 
>> In order to deal with IPIs as normal interrupts, let's add
>> a new way to register them with the architecture code.
>> 
>> set_smp_ipi_range() takes a range of interrupts, and allows
>> the arch code to request them as if the were normal interrupts.
>> A standard handler is then called by the core IRQ code to deal
>> with the IPI.
>> 
>> This means that we don't need to call irq_enter/irq_exit, and
>> that we don't need to deal with set_irq_regs either. So let's
>> move the dispatcher into its own function, and leave handle_IPI()
>> as a compatibility function.
>> 
>> On the sending side, let's make use of ipi_send_mask, which
>> already exists for this purpose.
>> 
>> One of the major difference is that we end up, in some cases
>> (such as when performing IRQ time accounting on the scheduler
>> IPI), end up with nested irq_enter()/irq_exit() pairs.
>> Other than the (relatively small) overhead, there should be
>> no consequences to it (these pairs are designed to nest
>> correctly, and the accounting shouldn't be off).
> 
> While rebasing on mainline, I have faced a performance regression for
> the benchmark:
> perf bench sched pipe
> on my arm64 dual quad core (hikey) and my 2 nodes x 112 CPUS (thx2)
> 
> The regression comes from:
> commit: d3afc7f12987 ("arm64: Allow IPIs to be handled as normal 
> interrupts")

That's interesting, as this patch doesn't really change anything (most
of the potential overhead comes in later). The only potential overhead
I can see is that the scheduler_ipi() call is now wrapped around
irq_enter()/irq_exit().

> 
>           v5.9              + this patch
> hikey :   48818(+/- 0.31)   37503(+/- 0.15%)  -23.2%
> thx2  :  132410(+/- 1.72)  122646(+/- 1.92%)   -7.4%
> 
> By + this patch,  I mean merging branch from this patch. Whereas
> merging the previous:
> commit: 83cfac95c018 ("genirq: Allow interrupts to be excluded from
> /proc/interrupts")
>  It doesn't show any regression

Since you are running perf, can you spot where the overhead occurs?

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2020-10-19 13:05 UTC|newest]

Thread overview: 170+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-01 14:43 [PATCH v3 00/16] arm/arm64: Turning IPIs into normal interrupts Marc Zyngier
2020-09-01 14:43 ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 01/16] genirq: Add fasteoi IPI flow Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 02/16] genirq: Allow interrupts to be excluded from /proc/interrupts Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 03/16] arm64: Allow IPIs to be handled as normal interrupts Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-11 15:05   ` Catalin Marinas
2020-09-11 15:05     ` Catalin Marinas
2020-10-19 12:42   ` Vincent Guittot
2020-10-19 12:42     ` Vincent Guittot
2020-10-19 13:04     ` Marc Zyngier [this message]
2020-10-19 13:04       ` Marc Zyngier
2020-10-19 15:43       ` Vincent Guittot
2020-10-19 15:43         ` Vincent Guittot
2020-10-19 16:00         ` Valentin Schneider
2020-10-19 16:00           ` Valentin Schneider
2020-10-27 10:12         ` Vincent Guittot
2020-10-27 10:12           ` Vincent Guittot
2020-10-27 10:37           ` Marc Zyngier
2020-10-27 10:37             ` Marc Zyngier
2020-10-27 10:50             ` Vincent Guittot
2020-10-27 10:50               ` Vincent Guittot
2020-10-27 11:21               ` Vincent Guittot
2020-10-27 11:21                 ` Vincent Guittot
2020-10-27 12:06                 ` Marc Zyngier
2020-10-27 12:06                   ` Marc Zyngier
2020-10-27 13:17                   ` Vincent Guittot
2020-10-27 13:17                     ` Vincent Guittot
     [not found]                     ` <c66367b0-e8a0-2b7b-13c3-c9413462357c@huawei.com>
2021-05-06 11:44                       ` Marc Zyngier
2021-05-06 11:44                         ` Marc Zyngier
2021-05-07  7:30                         ` He Ying
2021-05-07  7:30                           ` He Ying
2021-05-07  8:56                           ` Marc Zyngier
2021-05-07  8:56                             ` Marc Zyngier
2021-05-07  9:31                             ` He Ying
2021-05-07  9:31                               ` He Ying
2020-09-01 14:43 ` [PATCH v3 04/16] ARM: " Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 05/16] irqchip/gic-v3: Describe the SGI range Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 06/16] irqchip/gic-v3: Configure SGIs as standard interrupts Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 07/16] irqchip/gic: Refactor SMP configuration Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-14 13:06   ` Marek Szyprowski
2020-09-14 13:06     ` Marek Szyprowski
2020-09-14 13:13     ` Marc Zyngier
2020-09-14 13:13       ` Marc Zyngier
2020-09-14 13:26       ` Marek Szyprowski
2020-09-14 13:26         ` Marek Szyprowski
2020-09-14 15:09         ` Marc Zyngier
2020-09-14 15:09           ` Marc Zyngier
2020-09-15  6:48           ` Marek Szyprowski
2020-09-15  6:48             ` Marek Szyprowski
2020-09-15  8:07             ` Marc Zyngier
2020-09-15  8:07               ` Marc Zyngier
2020-09-15  8:35               ` Marek Szyprowski
2020-09-15  8:35                 ` Marek Szyprowski
2020-09-15  9:48                 ` Marc Zyngier
2020-09-15  9:48                   ` Marc Zyngier
2020-09-16 14:16     ` Jon Hunter
2020-09-16 14:16       ` Jon Hunter
2020-09-16 15:10       ` Marc Zyngier
2020-09-16 15:10         ` Marc Zyngier
2020-09-16 15:46         ` Jon Hunter
2020-09-16 15:46           ` Jon Hunter
2020-09-16 15:55           ` Marc Zyngier
2020-09-16 15:55             ` Marc Zyngier
2020-09-16 15:58             ` Jon Hunter
2020-09-16 15:58               ` Jon Hunter
2020-09-16 16:22               ` Marc Zyngier
2020-09-16 16:22                 ` Marc Zyngier
2020-09-16 16:28                 ` Marc Zyngier
2020-09-16 16:28                   ` Marc Zyngier
2020-09-16 19:08                   ` Jon Hunter
2020-09-16 19:08                     ` Jon Hunter
2020-09-16 19:06                 ` Jon Hunter
2020-09-16 19:06                   ` Jon Hunter
2020-09-16 19:26                   ` Mikko Perttunen
2020-09-16 19:26                     ` Mikko Perttunen
2020-09-16 19:39                     ` Jon Hunter
2020-09-16 19:39                       ` Jon Hunter
2020-09-17  7:40         ` Linus Walleij
2020-09-17  7:40           ` Linus Walleij
2020-09-17  7:50           ` Marc Zyngier
2020-09-17  7:50             ` Marc Zyngier
2020-09-17  7:54             ` Jon Hunter
2020-09-17  7:54               ` Jon Hunter
2020-09-17  8:45               ` Marc Zyngier
2020-09-17  8:45                 ` Marc Zyngier
2020-09-17  8:49                 ` Jon Hunter
2020-09-17  8:49                   ` Jon Hunter
2020-09-17  8:54                   ` Marek Szyprowski
2020-09-17  8:54                     ` Marek Szyprowski
2020-09-17  9:09                     ` Jon Hunter
2020-09-17  9:09                       ` Jon Hunter
2020-09-17  9:13                       ` Marek Szyprowski
2020-09-17  9:13                         ` Marek Szyprowski
2020-09-17  9:29                         ` Marc Zyngier
2020-09-17  9:29                           ` Marc Zyngier
2020-09-17 14:53                     ` Jon Hunter
2020-09-17 14:53                       ` Jon Hunter
2020-09-17 18:24                       ` Jon Hunter
2020-09-17 18:24                         ` Jon Hunter
2020-09-18  8:24                         ` Marc Zyngier
2020-09-18  8:24                           ` Marc Zyngier
2020-09-17  8:56                   ` Marc Zyngier
2020-09-17  8:56                     ` Marc Zyngier
2020-09-17 10:11                   ` Linus Walleij
2020-09-17 10:11                     ` Linus Walleij
2020-09-16 14:03   ` Linus Walleij
2020-09-16 14:03     ` Linus Walleij
2020-09-16 14:14     ` Marc Zyngier
2020-09-16 14:14       ` Marc Zyngier
2020-09-18  9:58   ` James Morse
2020-09-18  9:58     ` James Morse
2020-09-18 10:21     ` Marc Zyngier
2020-09-18 10:21       ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 09/16] irqchip/gic-common: Don't enable SGIs by default Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 10/16] irqchip/bcm2836: Configure mailbox interrupts as standard interrupts Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-14 14:32   ` Marek Szyprowski
2020-09-14 14:32     ` Marek Szyprowski
2020-09-14 16:10     ` Marc Zyngier
2020-09-14 16:10       ` Marc Zyngier
2020-09-14 19:13       ` Marek Szyprowski
2020-09-14 19:13         ` Marek Szyprowski
2020-09-01 14:43 ` [PATCH v3 11/16] irqchip/hip04: Configure IPIs " Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 12/16] irqchip/armada-370-xp: " Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 13/16] arm64: Kill __smp_cross_call and co Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-11 15:06   ` Catalin Marinas
2020-09-11 15:06     ` Catalin Marinas
2020-09-01 14:43 ` [PATCH v3 14/16] arm64: Remove custom IRQ stat accounting Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-11 15:06   ` Catalin Marinas
2020-09-11 15:06     ` Catalin Marinas
2020-09-01 14:43 ` [PATCH v3 15/16] ARM: Kill __smp_cross_call and co Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-01 14:43 ` [PATCH v3 16/16] ARM: Remove custom IRQ stat accounting Marc Zyngier
2020-09-01 14:43   ` Marc Zyngier
2020-09-02  7:41   ` kernel test robot
2020-09-02  7:41     ` kernel test robot
2020-09-02  7:41     ` kernel test robot
2020-09-02 20:20     ` Marc Zyngier
2020-09-02 20:20       ` Marc Zyngier
2020-09-02 20:20       ` Marc Zyngier
2020-09-24  9:00   ` Guillaume Tucker
2020-09-24  9:00     ` Guillaume Tucker
2020-09-24  9:29     ` Marc Zyngier
2020-09-24  9:29       ` Marc Zyngier
2020-09-24 13:09       ` Guillaume Tucker
2020-09-24 13:09         ` Guillaume Tucker
2020-09-28  9:00         ` Guillaume Tucker
2020-09-28  9:00           ` Guillaume Tucker
2020-09-24 13:34     ` Fabio Estevam
2020-09-24 13:34       ` Fabio Estevam
2020-09-24 14:19       ` Guillaume Tucker
2020-09-24 14:19         ` Guillaume Tucker
2020-09-07  6:06 ` [PATCH v3 00/16] arm/arm64: Turning IPIs into normal interrupts hasegawa-hitomi
2020-09-07  6:06   ` hasegawa-hitomi
2020-09-16 16:54 ` Florian Fainelli
2020-09-16 16:54   ` Florian Fainelli

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