[PATCH v3 0/4] rockchip: PCIe gated reference clock support

[PATCH v3 0/4] rockchip: PCIe gated reference clock support

[Daniele Briguglio]

The rk3588-rock-5-itx u-boot dtsi describes the PCIe reference
clocks (pcie30x4_refclk, pcie30x2_refclk on the M.2 M-key slots)
as "gated-fixed-clock" instances supplied by regulators.  Drive
those refclks from u-boot so the PCIe PHY can lock its PLL.

v1 [1] worked around the lack of a "gated-fixed-clock" driver in
u-boot by dropping the refclk references from pcie3x4/pcie3x2 in
a board-local dtsi override.  Jonas pointed out that the u-boot
dtsi is propagated to the OS via EFI handoff, making the dtsi
override approach brittle.

v2 [2] added a proper UCLASS_CLK driver for "gated-fixed-clock"
and enabled it in the rock-5-itx defconfig.  Jonas tested v2 on a
radxa rock-3b (RK3568) and surfaced:

  - an ordering bug in pcie_dw_rockchip: clk_enable_bulk() runs
    after generic_phy_init() and generic_phy_power_on(), so the
    PHY tries to lock its PLL before the gated refclk is
    enabled.  On boards where the refclk supply is
    regulator-always-on (the universal pattern in the in-tree
    DTs) this is masked; on rock-3b the PI6C supply is gated and
    the PHY init times out.
  - two stray clk_release_bulk() calls.  clk_release_bulk() is
    not a memory release (the bulk array is devm-allocated); it
    loops clk_disable() over the bulk.  In parse_dt() the clocks
    are acquired but never enabled, so the call disables clocks
    that are off.  In probe() after init_port() failure the
    inner err_disable_clks path balances the enable, so the
    outer call is a double-disable.  With the new gated-fixed-
    clock driver both cases desync the regulator enable_count,
    which on rock-5-itx with one M.2 populated would pull power
    from the populated slot when the empty one fails.

v3 keeps the v2 driver (plus the MAINTAINERS entry I forgot in
v2), fixes pcie_dw_rockchip, and switches the per-board defconfig
knob to a Kconfig imply so other boards pick up the driver
automatically as their DTs move to the binding.

Changes since v2:
  - patch 1: add MAINTAINERS entry for drivers/clk/clk-gated-fixed.c
  - new patch 2: pci: pcie_dw_rockchip: enable clocks before PHY init
  - new patch 3: pci: pcie_dw_rockchip: drop clk_release_bulk calls
  - new patch 4: pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and
    switch PHY to imply
  - dropped the rock-5-itx defconfig patch (Kconfig imply pulls
    CLK_GATED_FIXED in automatically)

Testing:
  - patch 1 validated end-to-end on a NanoPC T6 LTS via the
    synthetic-DT approach Jonas suggested: a fake
    "gated-fixed-clock" node with a fake "regulator-fixed" supply
    injected into the board's u-boot dtsi and wired as an
    additional "ref" clock of pcie3x4.  Probe and enable trigger
    when pcie_dw_rockchip runs clk_enable_bulk, and NVMe
    enumerates through the synthetic refclk path.
  - patches 2 and 3 reported and validated by Jonas on radxa
    rock-3b (RK3568) where the PI6C refclk supply is gated and
    the regulator enable_count must stay balanced.
  - I don't have free access to a rock-5-itx at the moment (the
    one I maintain serves a production mirror), so v3 has been
    build-tested only on the real target.

[1] https://lore.kernel.org/u-boot/20260518-rock-5-itx-pcie-refclk-dtsi-v1-1-faf8626039fc@superkali.me/
[2] https://lore.kernel.org/u-boot/20260519-rock-5-itx-pcie-refclk-dtsi-v2-0-738b67857cac@superkali.me/

Signed-off-by: Daniele Briguglio <hello@superkali.me>
---
Daniele Briguglio (4):
      clk: add gated-fixed-clock driver
      pci: pcie_dw_rockchip: enable clocks before PHY init
      pci: pcie_dw_rockchip: drop clk_release_bulk calls
      pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and switch PHY to imply

 MAINTAINERS                    |  5 +++
 drivers/clk/Kconfig            |  9 +++++
 drivers/clk/Makefile           |  1 +
 drivers/clk/clk-gated-fixed.c  | 84 ++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/Kconfig            |  3 +-
 drivers/pci/pcie_dw_rockchip.c | 23 ++++++------
 6 files changed, 112 insertions(+), 13 deletions(-)
---
base-commit: 38dbe637c9dfcadbd1bc201bfbb27f96b2ad525a
change-id: 20260518-rock-5-itx-pcie-refclk-dtsi-17ad4b21df1d

Best regards,
--  
Daniele Briguglio <hello@superkali.me>

[PATCH v3 1/4] clk: add gated-fixed-clock driver

[Daniele Briguglio]

Add a UCLASS_CLK driver matching the Linux DT binding documented at
Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml, a
fixed-rate oscillator whose output is enabled by toggling a
regulator supply.  The optional enable-gpios variant is not
implemented.

The first user in U-Boot will be rk3588-rock-5-itx, where the PCIe3
ports reference a PI6C 100MHz oscillator declared with this
compatible and pcie_dw_rockchip currently fails clk_get_by_index()
with -ENODEV on every boot since v2026.04.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Daniele Briguglio <hello@superkali.me>
---
 MAINTAINERS                   |  5 +++
 drivers/clk/Kconfig           |  9 +++++
 drivers/clk/Makefile          |  1 +
 drivers/clk/clk-gated-fixed.c | 84 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 99 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ea646f618..67ba55d83 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1268,6 +1268,11 @@ F:	tools/fwumdata_src/fwumdata.c
 F:	tools/fwumdata_src/fwumdata.h
 F:	tools/fwumdata_src/mkfwumdata.c
 
+GATED FIXED-RATE CLOCK DRIVER
+M:	Daniele Briguglio <hello@superkali.me>
+S:	Maintained
+F:	drivers/clk/clk-gated-fixed.c
+
 GATEWORKS_SC
 M:	Tim Harvey <tharvey@gateworks.com>
 S:	Maintained
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c2da7b393..0c2f4698e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -94,6 +94,15 @@ config CLK_COMPOSITE_CCF
 	  Enable this option if you want to (re-)use the Linux kernel's Common
 	  Clock Framework [CCF] composite code in U-Boot's clock driver.
 
+config CLK_GATED_FIXED
+	bool "Regulator-gated fixed-rate clock driver"
+	depends on CLK && DM_REGULATOR
+	help
+	  Enable this option to add a driver for fixed-rate clocks whose
+	  output is gated by a regulator supply, described in the device
+	  tree with the "gated-fixed-clock" compatible.  Typical use is
+	  external PCIe reference clock generators on Rockchip boards.
+
 config CLK_GPIO
 	bool "GPIO-controlled clock gate driver"
 	depends on CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f0c0d8a5..338ddc029 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_factor.o
 obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-fixed-factor.o
 obj-$(CONFIG_$(PHASE_)CLK_COMPOSITE_CCF) += clk-composite.o
+obj-$(CONFIG_$(PHASE_)CLK_GATED_FIXED) += clk-gated-fixed.o
 obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o
 obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o
 
diff --git a/drivers/clk/clk-gated-fixed.c b/drivers/clk/clk-gated-fixed.c
new file mode 100644
index 000000000..d52f278d7
--- /dev/null
+++ b/drivers/clk/clk-gated-fixed.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2026 Daniele Briguglio <hello@superkali.me>
+ *
+ * Clock driver for a fixed-rate oscillator gated by a regulator
+ * supply (Linux DT binding "gated-fixed-clock").
+ */
+
+#define LOG_CATEGORY UCLASS_CLK
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <power/regulator.h>
+#include <dm/device_compat.h>
+
+struct clk_gated_fixed_priv {
+	struct udevice	*supply;
+	ulong		rate;
+};
+
+static int clk_gated_fixed_enable(struct clk *clk)
+{
+	struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev);
+
+	return regulator_set_enable_if_allowed(priv->supply, true);
+}
+
+static int clk_gated_fixed_disable(struct clk *clk)
+{
+	struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev);
+
+	return regulator_set_enable_if_allowed(priv->supply, false);
+}
+
+static ulong clk_gated_fixed_get_rate(struct clk *clk)
+{
+	struct clk_gated_fixed_priv *priv = dev_get_priv(clk->dev);
+
+	return priv->rate;
+}
+
+static const struct clk_ops clk_gated_fixed_ops = {
+	.enable		= clk_gated_fixed_enable,
+	.disable	= clk_gated_fixed_disable,
+	.get_rate	= clk_gated_fixed_get_rate,
+};
+
+static int clk_gated_fixed_probe(struct udevice *dev)
+{
+	struct clk_gated_fixed_priv *priv = dev_get_priv(dev);
+	u32 rate;
+	int ret;
+
+	ret = dev_read_u32(dev, "clock-frequency", &rate);
+	if (ret) {
+		dev_err(dev, "missing clock-frequency: %d\n", ret);
+		return ret;
+	}
+	priv->rate = rate;
+
+	ret = device_get_supply_regulator(dev, "vdd-supply", &priv->supply);
+	if (ret) {
+		dev_err(dev, "failed to get vdd-supply: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id clk_gated_fixed_match[] = {
+	{ .compatible = "gated-fixed-clock" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gated_fixed_clock) = {
+	.name		= "gated_fixed_clock",
+	.id		= UCLASS_CLK,
+	.of_match	= clk_gated_fixed_match,
+	.probe		= clk_gated_fixed_probe,
+	.priv_auto	= sizeof(struct clk_gated_fixed_priv),
+	.ops		= &clk_gated_fixed_ops,
+};

-- 
2.47.3

[PATCH v3 2/4] pci: pcie_dw_rockchip: enable clocks before PHY init

[Daniele Briguglio]

rockchip_pcie_init_port() calls generic_phy_init() and
generic_phy_power_on() before clk_enable_bulk(), so the PCIe PHY
tries to lock its PLL while the external reference clock can still
be off.  Where the refclk is generated by an external oscillator
gated by a regulator that is not marked regulator-always-on (e.g.
the PI6C clock generator on radxa rock-3b modelled with the
gated-fixed-clock binding), this results in a PHY lock timeout:

  rockchip_pcie3phy phy@fe8c0000: lock failed 0x6890000
  rockchip_pcie3phy phy@fe8c0000: PHY: Failed to init phy@fe8c0000: -110.
  pcie_dw_rockchip pcie@fe280000: failed to init phy (ret=-110)

Move clk_enable_bulk() ahead of generic_phy_init() so that any
clock-frequency consumer (including external gated refclks) is
powered up before the PHY PLL attempts to lock.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Daniele Briguglio <hello@superkali.me>
---
 drivers/pci/pcie_dw_rockchip.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 61117fa95..8ea51e642 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -307,10 +307,16 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		return ret;
 	}
 
+	ret = clk_enable_bulk(&priv->clks);
+	if (ret) {
+		dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
+		goto err_disable_regulator;
+	}
+
 	ret = generic_phy_init(&priv->phy);
 	if (ret) {
 		dev_err(dev, "failed to init phy (ret=%d)\n", ret);
-		goto err_disable_regulator;
+		goto err_disable_clks;
 	}
 
 	ret = generic_phy_power_on(&priv->phy);
@@ -325,12 +331,6 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		goto err_power_off_phy;
 	}
 
-	ret = clk_enable_bulk(&priv->clks);
-	if (ret) {
-		dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
-		goto err_deassert_bulk;
-	}
-
 	/* LTSSM EN ctrl mode */
 	val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
 	val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
@@ -342,17 +342,17 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 
 	ret = rk_pcie_link_up(priv);
 	if (ret < 0)
-		goto err_link_up;
+		goto err_deassert_bulk;
 
 	return 0;
-err_link_up:
-	clk_disable_bulk(&priv->clks);
 err_deassert_bulk:
 	reset_assert_bulk(&priv->rsts);
 err_power_off_phy:
 	generic_phy_power_off(&priv->phy);
 err_exit_phy:
 	generic_phy_exit(&priv->phy);
+err_disable_clks:
+	clk_disable_bulk(&priv->clks);
 err_disable_regulator:
 	regulator_set_enable_if_allowed(priv->vpcie3v3, false);
 

-- 
2.47.3

[PATCH v3 3/4] pci: pcie_dw_rockchip: drop clk_release_bulk calls

[Daniele Briguglio]

clk_release_bulk() loops clk_disable() over the bulk; the bulk
array itself is devm_kcalloc()-allocated and freed at device
detach, so the function does not actually release memory.

In parse_dt() the clocks are acquired but never enabled, so the
existing call disables clocks that are off.  In probe() after
init_port() failure, the inner err_disable_clks: path added in
the previous patch has already balanced clk_enable_bulk() with
clk_disable_bulk(), so the outer call is a double-disable.

With the new gated-fixed-clock driver both cases trigger
regulator_set_enable_if_allowed(false) on regulators that were
either never enabled or just disabled, desynchronising the
regulator enable_count.  On rk3588-rock-5-itx with only one M.2
slot populated, the failing empty slot would decrement the
enable_count of the still-needed regulator twice and pull power
from the populated slot.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Daniele Briguglio <hello@superkali.me>
---
 drivers/pci/pcie_dw_rockchip.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 8ea51e642..c1e34df53 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -425,7 +425,7 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
 rockchip_pcie_parse_dt_err_phy_get_by_index:
 	/* regulators don't need release */
 rockchip_pcie_parse_dt_err_supply_regulator:
-	clk_release_bulk(&priv->clks);
+	/* clocks don't need release */
 rockchip_pcie_parse_dt_err_clk_get_bulk:
 	reset_release_bulk(&priv->rsts);
 rockchip_pcie_parse_dt_err_reset_get_bulk:
@@ -476,7 +476,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
 		return ret;
 
 rockchip_pcie_probe_err_init_port:
-	clk_release_bulk(&priv->clks);
 	reset_release_bulk(&priv->rsts);
 	dm_gpio_free(dev, &priv->rst_gpio);
 

-- 
2.47.3

[PATCH v3 4/4] pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and switch PHY to imply

[Daniele Briguglio]

Switch the PHY_ROCKCHIP_SNPS_PCIE3 dependency from select to
imply, and add imply CLK_GATED_FIXED so that boards using
gated-fixed-clock refclks pick up the driver automatically as
their DT moves to the binding, without each defconfig having to
touch the symbol.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Daniele Briguglio <hello@superkali.me>
---
 drivers/pci/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 39df0e776..77e0f820d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -414,7 +414,8 @@ config PCIE_DW_ROCKCHIP
 	bool "Rockchip DesignWare based PCIe controller"
 	depends on ARCH_ROCKCHIP
 	select PCIE_DW_COMMON
-	select PHY_ROCKCHIP_SNPS_PCIE3
+	imply CLK_GATED_FIXED
+	imply PHY_ROCKCHIP_SNPS_PCIE3
 	help
 	  Say Y here if you want to enable DW PCIe controller support on
 	  Rockchip SoCs.

-- 
2.47.3

Re: [PATCH v3 1/4] clk: add gated-fixed-clock driver

[Heiko Stübner]

Am Mittwoch, 20. Mai 2026, 08:05:27 Mitteleuropäische Sommerzeit schrieb Daniele Briguglio:
> Add a UCLASS_CLK driver matching the Linux DT binding documented at
> Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml, a
> fixed-rate oscillator whose output is enabled by toggling a
> regulator supply.  The optional enable-gpios variant is not
> implemented.
> 
> The first user in U-Boot will be rk3588-rock-5-itx, where the PCIe3
> ports reference a PI6C 100MHz oscillator declared with this
> compatible and pcie_dw_rockchip currently fails clk_get_by_index()
> with -ENODEV on every boot since v2026.04.
> 
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Daniele Briguglio <hello@superkali.me>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> # rock-5-itx

Re: [PATCH v3 2/4] pci: pcie_dw_rockchip: enable clocks before PHY init

[Heiko Stübner]

Am Mittwoch, 20. Mai 2026, 08:05:28 Mitteleuropäische Sommerzeit schrieb Daniele Briguglio:
> rockchip_pcie_init_port() calls generic_phy_init() and
> generic_phy_power_on() before clk_enable_bulk(), so the PCIe PHY
> tries to lock its PLL while the external reference clock can still
> be off.  Where the refclk is generated by an external oscillator
> gated by a regulator that is not marked regulator-always-on (e.g.
> the PI6C clock generator on radxa rock-3b modelled with the
> gated-fixed-clock binding), this results in a PHY lock timeout:
> 
>   rockchip_pcie3phy phy@fe8c0000: lock failed 0x6890000
>   rockchip_pcie3phy phy@fe8c0000: PHY: Failed to init phy@fe8c0000: -110.
>   pcie_dw_rockchip pcie@fe280000: failed to init phy (ret=-110)
> 
> Move clk_enable_bulk() ahead of generic_phy_init() so that any
> clock-frequency consumer (including external gated refclks) is
> powered up before the PHY PLL attempts to lock.
> 
> Reported-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Daniele Briguglio <hello@superkali.me>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> # rock-5-itx

Re: [PATCH v3 3/4] pci: pcie_dw_rockchip: drop clk_release_bulk calls

[Heiko Stübner]

Am Mittwoch, 20. Mai 2026, 08:05:29 Mitteleuropäische Sommerzeit schrieb Daniele Briguglio:
> clk_release_bulk() loops clk_disable() over the bulk; the bulk
> array itself is devm_kcalloc()-allocated and freed at device
> detach, so the function does not actually release memory.
> 
> In parse_dt() the clocks are acquired but never enabled, so the
> existing call disables clocks that are off.  In probe() after
> init_port() failure, the inner err_disable_clks: path added in
> the previous patch has already balanced clk_enable_bulk() with
> clk_disable_bulk(), so the outer call is a double-disable.
> 
> With the new gated-fixed-clock driver both cases trigger
> regulator_set_enable_if_allowed(false) on regulators that were
> either never enabled or just disabled, desynchronising the
> regulator enable_count.  On rk3588-rock-5-itx with only one M.2
> slot populated, the failing empty slot would decrement the
> enable_count of the still-needed regulator twice and pull power
> from the populated slot.
> 
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Daniele Briguglio <hello@superkali.me>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> # rock-5-itx


Though the whole clk handling is quite strange.
I would assume that it's always a
  - clk-request
      - clk-enable
          something
      - clk-disable
  - clk-release


That a clk-disable also hides in the clk-release is really surprising,
and I guess a lot of places in u-boot will encounter the same
imbalance - just mitigated by the fact that the double-disable
won't matter.

Directly in clk_get_bulk the problem is apparent ...
The function tries to get all the clocks, and on error calls
clk_release_all on the already gotten clocks.

All of these clocks never got enabled, but are getting double-disabled
by the clk_release_all() call.

Very very strange ;-)


Heiko

> ---
>  drivers/pci/pcie_dw_rockchip.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
> index 8ea51e642..c1e34df53 100644
> --- a/drivers/pci/pcie_dw_rockchip.c
> +++ b/drivers/pci/pcie_dw_rockchip.c
> @@ -425,7 +425,7 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
>  rockchip_pcie_parse_dt_err_phy_get_by_index:
>  	/* regulators don't need release */
>  rockchip_pcie_parse_dt_err_supply_regulator:
> -	clk_release_bulk(&priv->clks);
> +	/* clocks don't need release */
>  rockchip_pcie_parse_dt_err_clk_get_bulk:
>  	reset_release_bulk(&priv->rsts);
>  rockchip_pcie_parse_dt_err_reset_get_bulk:
> @@ -476,7 +476,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
>  		return ret;
>  
>  rockchip_pcie_probe_err_init_port:
> -	clk_release_bulk(&priv->clks);
>  	reset_release_bulk(&priv->rsts);
>  	dm_gpio_free(dev, &priv->rst_gpio);
>  
> 
> 

Re: [PATCH v3 4/4] pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and switch PHY to imply

[Heiko Stübner]

Am Mittwoch, 20. Mai 2026, 08:05:30 Mitteleuropäische Sommerzeit schrieb Daniele Briguglio:
> Switch the PHY_ROCKCHIP_SNPS_PCIE3 dependency from select to
> imply, and add imply CLK_GATED_FIXED so that boards using
> gated-fixed-clock refclks pick up the driver automatically as
> their DT moves to the binding, without each defconfig having to
> touch the symbol.
> 
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Daniele Briguglio <hello@superkali.me>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> # rock-5-itx

Re: [PATCH v3 3/4] pci: pcie_dw_rockchip: drop clk_release_bulk calls

[Daniele Briguglio]

> Though the whole clk handling is quite strange.
> I would assume that it's always a
>   - clk-request
>       - clk-enable
>           something
>       - clk-disable
>   - clk-release
>
> That a clk-disable also hides in the clk-release is really surprising,
> and I guess a lot of places in u-boot will encounter the same
> imbalance - just mitigated by the fact that the double-disable
> won't matter.
>
> Directly in clk_get_bulk the problem is apparent ...
> The function tries to get all the clocks, and on error calls
> clk_release_all on the already gotten clocks.
>
> All of these clocks never got enabled, but are getting double-disabled
> by the clk_release_all() call.
>
> Very very strange ;-)

Right. clk_release_bulk() hides a clk_disable(), and clk_get_bulk() does
the same in its own error path: it calls clk_release_all() on clocks it
only ever requested, never enabled. Everywhere else that double-disable
is a no-op, so nobody notices. The gated-fixed-clock driver is what makes
it bite, since there the disable actually toggles the regulator.

Thanks for the review, and for testing on the rock-5-itx.

Daniele