From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>,
bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
andrew@codeconstruct.com.au, vkoul@kernel.org, kishon@kernel.org,
linus.walleij@linaro.org, p.zabel@pengutronix.de,
linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org
Cc: elbadrym@google.com, romlem@google.com, anhphan@google.com,
wak@google.com, yuxiaozhang@google.com, BMC-SW@aspeedtech.com
Subject: Re: [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY
Date: Fri, 13 Jun 2025 11:44:47 +0200 [thread overview]
Message-ID: <36cb3578-1efb-4d2e-b50a-47e6dfd3bdd0@kernel.org> (raw)
In-Reply-To: <20250613033001.3153637-2-jacky_chou@aspeedtech.com>
On 13/06/2025 05:29, Jacky Chou wrote:
> Add device tree binding YAML documentation for the ASPEED PCIe PHY.
> This schema describes the required properties for the PCIe PHY node,
> including compatible strings and register space, and provides an
> example for reference.
>
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
> .../bindings/phy/aspeed-pcie-phy.yaml | 38 +++++++++++++++++++
Filename basedon compatible
A nit, subject: drop second/last, redundant "document for". The
"dt-bindings" prefix is already stating that these are documents.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> MAINTAINERS | 10 +++++
> 2 files changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> new file mode 100644
> index 000000000000..762bf7b0aedc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/aspeed-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED PCIe PHY
> +
> +maintainers:
> + - Jacky Chou <jacky_chou@aspeedtech.com>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + The ASPEED PCIe PHY provides the physical layer interface for PCIe
> + controllers in the SoC. This node represents the register block for the PCIe
> + PHY, which is typically accessed by PCIe Root Complex or Endpoint drivers
> + via syscon.
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-pcie-phy
> + - aspeed,ast2700-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
No phy cells? How is this a phy exactly?
No resources? This looks just incomplete.
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pcie-phy@1e6ed200 {
> + compatible = "aspeed,ast2600-pcie-phy";
> + reg = <0x1e6ed200 0x100>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a5a650812c16..68115443607d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3696,6 +3696,16 @@ S: Maintained
> F: Documentation/devicetree/bindings/media/aspeed,video-engine.yaml
> F: drivers/media/platform/aspeed/
>
> +ASPEED PCIE CONTROLLER DRIVER
> +M: Jacky Chou <jacky_chou@aspeedtech.com>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-pci@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml
> +F: Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> +F: Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> +F: drivers/pci/controller/pcie-aspeed.c
There is no such file... actually many above do not exist.
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>,
bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
andrew@codeconstruct.com.au, vkoul@kernel.org, kishon@kernel.org,
linus.walleij@linaro.org, p.zabel@pengutronix.de,
linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org
Cc: elbadrym@google.com, romlem@google.com, anhphan@google.com,
wak@google.com, yuxiaozhang@google.com, BMC-SW@aspeedtech.com
Subject: Re: [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY
Date: Fri, 13 Jun 2025 11:44:47 +0200 [thread overview]
Message-ID: <36cb3578-1efb-4d2e-b50a-47e6dfd3bdd0@kernel.org> (raw)
In-Reply-To: <20250613033001.3153637-2-jacky_chou@aspeedtech.com>
On 13/06/2025 05:29, Jacky Chou wrote:
> Add device tree binding YAML documentation for the ASPEED PCIe PHY.
> This schema describes the required properties for the PCIe PHY node,
> including compatible strings and register space, and provides an
> example for reference.
>
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
> .../bindings/phy/aspeed-pcie-phy.yaml | 38 +++++++++++++++++++
Filename basedon compatible
A nit, subject: drop second/last, redundant "document for". The
"dt-bindings" prefix is already stating that these are documents.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> MAINTAINERS | 10 +++++
> 2 files changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> new file mode 100644
> index 000000000000..762bf7b0aedc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/aspeed-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED PCIe PHY
> +
> +maintainers:
> + - Jacky Chou <jacky_chou@aspeedtech.com>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + The ASPEED PCIe PHY provides the physical layer interface for PCIe
> + controllers in the SoC. This node represents the register block for the PCIe
> + PHY, which is typically accessed by PCIe Root Complex or Endpoint drivers
> + via syscon.
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-pcie-phy
> + - aspeed,ast2700-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
No phy cells? How is this a phy exactly?
No resources? This looks just incomplete.
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pcie-phy@1e6ed200 {
> + compatible = "aspeed,ast2600-pcie-phy";
> + reg = <0x1e6ed200 0x100>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a5a650812c16..68115443607d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3696,6 +3696,16 @@ S: Maintained
> F: Documentation/devicetree/bindings/media/aspeed,video-engine.yaml
> F: drivers/media/platform/aspeed/
>
> +ASPEED PCIE CONTROLLER DRIVER
> +M: Jacky Chou <jacky_chou@aspeedtech.com>
> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
> +L: linux-pci@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml
> +F: Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> +F: Documentation/devicetree/bindings/phy/aspeed-pcie-phy.yaml
> +F: drivers/pci/controller/pcie-aspeed.c
There is no such file... actually many above do not exist.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2025-06-13 9:45 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 9:14 ` neil.armstrong
2025-06-13 9:14 ` neil.armstrong
2025-06-20 5:03 ` 回覆: " Jacky Chou
2025-06-20 5:03 ` Jacky Chou
2025-06-13 9:44 ` Krzysztof Kozlowski [this message]
2025-06-13 9:44 ` Krzysztof Kozlowski
2025-06-20 8:29 ` 回覆: " Jacky Chou
2025-06-20 8:29 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 9:46 ` Krzysztof Kozlowski
2025-06-13 9:46 ` Krzysztof Kozlowski
2025-06-20 8:32 ` 回覆: " Jacky Chou
2025-06-20 8:32 ` Jacky Chou
2025-06-13 15:58 ` Bjorn Helgaas
2025-06-13 15:58 ` Bjorn Helgaas
2025-06-20 5:27 ` Jacky Chou
2025-06-20 5:27 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 9:50 ` Krzysztof Kozlowski
2025-06-13 9:50 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-20 8:36 ` Jacky Chou
2025-06-25 21:04 ` Rob Herring
2025-06-25 21:04 ` Rob Herring
2025-06-27 9:59 ` 回覆: " Jacky Chou
2025-06-27 9:59 ` Jacky Chou
2025-06-13 3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 9:51 ` Krzysztof Kozlowski
2025-06-13 9:51 ` Krzysztof Kozlowski
2025-06-20 8:36 ` Jacky Chou
2025-06-20 8:36 ` Jacky Chou
2025-06-13 15:59 ` Bjorn Helgaas
2025-06-13 15:59 ` Bjorn Helgaas
2025-06-13 3:29 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-06-13 3:29 ` Jacky Chou
2025-06-13 15:54 ` Bjorn Helgaas
2025-06-13 15:54 ` Bjorn Helgaas
2025-06-20 5:24 ` 回覆: " Jacky Chou
2025-06-20 5:24 ` Jacky Chou
2025-06-24 15:28 ` Bjorn Helgaas
2025-06-24 15:28 ` Bjorn Helgaas
2025-06-25 8:27 ` 回覆: " Jacky Chou
2025-06-25 8:27 ` Jacky Chou
2025-06-25 22:16 ` Bjorn Helgaas
2025-06-25 22:16 ` Bjorn Helgaas
2025-06-27 10:02 ` Jacky Chou
2025-06-27 10:02 ` Jacky Chou
2025-06-13 3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-13 3:30 ` Jacky Chou
2025-06-18 12:15 ` Linus Walleij
2025-06-18 12:15 ` Linus Walleij
2025-06-20 7:09 ` Andrew Jeffery
2025-06-20 7:09 ` Andrew Jeffery
2025-06-13 3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13 3:30 ` Jacky Chou
2025-06-13 9:54 ` Krzysztof Kozlowski
2025-06-13 9:54 ` Krzysztof Kozlowski
2025-06-23 2:42 ` 回覆: " Jacky Chou
2025-06-23 2:42 ` Jacky Chou
2025-06-13 12:03 ` Ilpo Järvinen
2025-06-13 12:03 ` Ilpo Järvinen
2025-06-23 5:41 ` Jacky Chou
2025-06-23 5:41 ` Jacky Chou
2025-06-24 10:50 ` Ilpo Järvinen
2025-06-24 10:50 ` Ilpo Järvinen
2025-06-24 11:11 ` 回覆: " Jacky Chou
2025-06-24 11:11 ` Jacky Chou
2025-06-24 15:40 ` Bjorn Helgaas
2025-06-24 15:40 ` Bjorn Helgaas
2025-06-25 8:32 ` 回覆: " Jacky Chou
2025-06-25 8:32 ` Jacky Chou
2025-06-13 16:28 ` Bjorn Helgaas
2025-06-13 16:28 ` Bjorn Helgaas
2025-06-20 6:05 ` 回覆: " Jacky Chou
2025-06-20 6:05 ` Jacky Chou
2025-06-24 15:33 ` Bjorn Helgaas
2025-06-24 15:33 ` Bjorn Helgaas
2025-06-14 2:07 ` kernel test robot
2025-06-14 2:07 ` kernel test robot
2025-06-19 8:14 ` kernel test robot
2025-06-19 8:14 ` kernel test robot
2025-06-13 9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-13 9:18 ` neil.armstrong
2025-06-20 8:20 ` 回覆: " Jacky Chou
2025-06-20 8:20 ` Jacky Chou
2025-06-24 7:29 ` Neil Armstrong
2025-06-24 7:29 ` Neil Armstrong
2025-06-24 10:54 ` 回覆: " Jacky Chou
2025-06-24 10:54 ` Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)
2025-06-16 21:46 ` Rob Herring (Arm)
2025-06-16 21:46 ` Rob Herring (Arm)
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