From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 11:17:14 +0200 [thread overview]
Message-ID: <39c2f53b-8f53-ceb1-ae0c-81e5e53d01aa@baylibre.com> (raw)
In-Reply-To: <YvJ84qkuXdvVgXRm@sirena.org.uk>
On 09/08/2022 17:27, Mark Brown wrote:
> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>> At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
>> this resets the SPICC_CONREG register and notably the value set by the
>> Common Clock Framework.
>
>> This saves the datarate dividor value between message to keep the last
>> set value by the Common Clock Framework.
>
> When you say the value set by the clock framework does that mean that
> the clock driver is adjusting hardware inside the SPI controller IP
> block which is then getting reset by the SPI driver without the SPI
> driver knowing about it? That seems like a bad idea as you're finding
> here.
The SPI driver is explicitely triggering a reset at the end of each message
to get back to a clean HW state, but it does reset the content of the "legacy"
registers containing the power of 2 divider value, the new registers configuring
the new clock divider path (only on newer SoCs) doesn't get cleared.
>
>> This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
>> because we recalculated and wrote the rate for each xfer.
>
> Note that the rate might change per transfer.
It's taken in account, this case is when the rate doesn't change.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 11:17:14 +0200 [thread overview]
Message-ID: <39c2f53b-8f53-ceb1-ae0c-81e5e53d01aa@baylibre.com> (raw)
In-Reply-To: <YvJ84qkuXdvVgXRm@sirena.org.uk>
On 09/08/2022 17:27, Mark Brown wrote:
> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>> At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
>> this resets the SPICC_CONREG register and notably the value set by the
>> Common Clock Framework.
>
>> This saves the datarate dividor value between message to keep the last
>> set value by the Common Clock Framework.
>
> When you say the value set by the clock framework does that mean that
> the clock driver is adjusting hardware inside the SPI controller IP
> block which is then getting reset by the SPI driver without the SPI
> driver knowing about it? That seems like a bad idea as you're finding
> here.
The SPI driver is explicitely triggering a reset at the end of each message
to get back to a clean HW state, but it does reset the content of the "legacy"
registers containing the power of 2 divider value, the new registers configuring
the new clock divider path (only on newer SoCs) doesn't get cleared.
>
>> This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
>> because we recalculated and wrote the rate for each xfer.
>
> Note that the rate might change per transfer.
It's taken in account, this case is when the rate doesn't change.
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 11:17:14 +0200 [thread overview]
Message-ID: <39c2f53b-8f53-ceb1-ae0c-81e5e53d01aa@baylibre.com> (raw)
In-Reply-To: <YvJ84qkuXdvVgXRm@sirena.org.uk>
On 09/08/2022 17:27, Mark Brown wrote:
> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>> At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
>> this resets the SPICC_CONREG register and notably the value set by the
>> Common Clock Framework.
>
>> This saves the datarate dividor value between message to keep the last
>> set value by the Common Clock Framework.
>
> When you say the value set by the clock framework does that mean that
> the clock driver is adjusting hardware inside the SPI controller IP
> block which is then getting reset by the SPI driver without the SPI
> driver knowing about it? That seems like a bad idea as you're finding
> here.
The SPI driver is explicitely triggering a reset at the end of each message
to get back to a clean HW state, but it does reset the content of the "legacy"
registers containing the power of 2 divider value, the new registers configuring
the new clock divider path (only on newer SoCs) doesn't get cleared.
>
>> This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
>> because we recalculated and wrote the rate for each xfer.
>
> Note that the rate might change per transfer.
It's taken in account, this case is when the rate doesn't change.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-10 9:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 15:20 [PATCH] spi: meson-spicc: save pow2 datarate between messages Neil Armstrong
2022-08-09 15:20 ` Neil Armstrong
2022-08-09 15:20 ` Neil Armstrong
2022-08-09 15:27 ` Mark Brown
2022-08-09 15:27 ` Mark Brown
2022-08-09 15:27 ` Mark Brown
2022-08-10 9:17 ` Neil Armstrong [this message]
2022-08-10 9:17 ` Neil Armstrong
2022-08-10 9:17 ` Neil Armstrong
2022-08-10 12:37 ` Mark Brown
2022-08-10 12:37 ` Mark Brown
2022-08-10 12:37 ` Mark Brown
2022-08-10 14:01 ` Neil Armstrong
2022-08-10 14:01 ` Neil Armstrong
2022-08-10 14:01 ` Neil Armstrong
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:49 ` Mark Brown
2022-08-10 14:49 ` Mark Brown
2022-08-10 14:49 ` Mark Brown
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 16:10 ` Mark Brown
2022-08-10 16:10 ` Mark Brown
2022-08-10 16:10 ` Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=39c2f53b-8f53-ceb1-ae0c-81e5e53d01aa@baylibre.com \
--to=narmstrong@baylibre.com \
--cc=broonie@kernel.org \
--cc=da@libre.computer \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.