From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 16:01:33 +0200 [thread overview]
Message-ID: <518f22f4-1582-924c-9eaa-28ebbe53a632@baylibre.com> (raw)
In-Reply-To: <YvOmnDJA+ov49chC@sirena.org.uk>
On 10/08/2022 14:37, Mark Brown wrote:
> On Wed, Aug 10, 2022 at 11:17:14AM +0200, Neil Armstrong wrote:
>> On 09/08/2022 17:27, Mark Brown wrote:
>>> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>
>>> When you say the value set by the clock framework does that mean that
>>> the clock driver is adjusting hardware inside the SPI controller IP
>>> block which is then getting reset by the SPI driver without the SPI
>>> driver knowing about it? That seems like a bad idea as you're finding
>>> here.
>
>> The SPI driver is explicitely triggering a reset at the end of each message
>> to get back to a clean HW state, but it does reset the content of the "legacy"
>> registers containing the power of 2 divider value, the new registers configuring
>> the new clock divider path (only on newer SoCs) doesn't get cleared.
>
> Sure, but that doesn't really address the concern - is this something
> that the clk driver programmed or is this the driver forgetting to
> restore a register that it programmed itself? The commit message sounds
> like the former which is a much bigger problem.
It's what is programmed by the Clock Framework yes, it was designed as-is
so the Clock Framework takes the most accurate clock path but the reset case
wasn't taken in account.
Neil
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 16:01:33 +0200 [thread overview]
Message-ID: <518f22f4-1582-924c-9eaa-28ebbe53a632@baylibre.com> (raw)
In-Reply-To: <YvOmnDJA+ov49chC@sirena.org.uk>
On 10/08/2022 14:37, Mark Brown wrote:
> On Wed, Aug 10, 2022 at 11:17:14AM +0200, Neil Armstrong wrote:
>> On 09/08/2022 17:27, Mark Brown wrote:
>>> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>
>>> When you say the value set by the clock framework does that mean that
>>> the clock driver is adjusting hardware inside the SPI controller IP
>>> block which is then getting reset by the SPI driver without the SPI
>>> driver knowing about it? That seems like a bad idea as you're finding
>>> here.
>
>> The SPI driver is explicitely triggering a reset at the end of each message
>> to get back to a clean HW state, but it does reset the content of the "legacy"
>> registers containing the power of 2 divider value, the new registers configuring
>> the new clock divider path (only on newer SoCs) doesn't get cleared.
>
> Sure, but that doesn't really address the concern - is this something
> that the clk driver programmed or is this the driver forgetting to
> restore a register that it programmed itself? The commit message sounds
> like the former which is a much bigger problem.
It's what is programmed by the Clock Framework yes, it was designed as-is
so the Clock Framework takes the most accurate clock path but the reset case
wasn't taken in account.
Neil
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 16:01:33 +0200 [thread overview]
Message-ID: <518f22f4-1582-924c-9eaa-28ebbe53a632@baylibre.com> (raw)
In-Reply-To: <YvOmnDJA+ov49chC@sirena.org.uk>
On 10/08/2022 14:37, Mark Brown wrote:
> On Wed, Aug 10, 2022 at 11:17:14AM +0200, Neil Armstrong wrote:
>> On 09/08/2022 17:27, Mark Brown wrote:
>>> On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
>
>>> When you say the value set by the clock framework does that mean that
>>> the clock driver is adjusting hardware inside the SPI controller IP
>>> block which is then getting reset by the SPI driver without the SPI
>>> driver knowing about it? That seems like a bad idea as you're finding
>>> here.
>
>> The SPI driver is explicitely triggering a reset at the end of each message
>> to get back to a clean HW state, but it does reset the content of the "legacy"
>> registers containing the power of 2 divider value, the new registers configuring
>> the new clock divider path (only on newer SoCs) doesn't get cleared.
>
> Sure, but that doesn't really address the concern - is this something
> that the clk driver programmed or is this the driver forgetting to
> restore a register that it programmed itself? The commit message sounds
> like the former which is a much bigger problem.
It's what is programmed by the Clock Framework yes, it was designed as-is
so the Clock Framework takes the most accurate clock path but the reset case
wasn't taken in account.
Neil
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-10 14:01 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-09 15:20 [PATCH] spi: meson-spicc: save pow2 datarate between messages Neil Armstrong
2022-08-09 15:20 ` Neil Armstrong
2022-08-09 15:20 ` Neil Armstrong
2022-08-09 15:27 ` Mark Brown
2022-08-09 15:27 ` Mark Brown
2022-08-09 15:27 ` Mark Brown
2022-08-10 9:17 ` Neil Armstrong
2022-08-10 9:17 ` Neil Armstrong
2022-08-10 9:17 ` Neil Armstrong
2022-08-10 12:37 ` Mark Brown
2022-08-10 12:37 ` Mark Brown
2022-08-10 12:37 ` Mark Brown
2022-08-10 14:01 ` Neil Armstrong [this message]
2022-08-10 14:01 ` Neil Armstrong
2022-08-10 14:01 ` Neil Armstrong
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:31 ` Mark Brown
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:40 ` Neil Armstrong
2022-08-10 14:49 ` Mark Brown
2022-08-10 14:49 ` Mark Brown
2022-08-10 14:49 ` Mark Brown
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 15:51 ` Neil Armstrong
2022-08-10 16:10 ` Mark Brown
2022-08-10 16:10 ` Mark Brown
2022-08-10 16:10 ` Mark Brown
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