[Qemu-devel] [PATCH] Update MIPS status register with EXL and ERL bits at exception

[Qemu-devel] [PATCH] Update MIPS status register with EXL and ERL bits at exception

[Dirk Behme]

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- Fix missing 'or' in target-mips/helper.c while update of
hflags with HFLAG_ERL
- Update status register EXL and ERL flags directly if
entering or leaving exception, not only hflags. With old
mechanism, correct status register is returned only if read
from target with mfc0 instruction. This is because value of
status register is calculated at read time using hflags.
GDB, which directly seems to read  CP0_Status, doesn't get
the correct status register.
- Remove then EXL and ERL calculation based on hflags from
do_mfc0 because status register now has already the correct
value.

Signed-off-by: Dirk Behme <dirk.behme_at_gmail.com>


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--- ./target-mips/op_helper.c_orig	2006-06-19 18:14:13.000000000 +0200
+++ ./target-mips/op_helper.c	2006-06-19 18:37:05.000000000 +0200
@@ -219,10 +219,6 @@ void do_mfc0 (int reg, int sel)
         T0 = env->CP0_Status;
         if (env->hflags & MIPS_HFLAG_UM)
             T0 |= (1 << CP0St_UM);
-        if (env->hflags & MIPS_HFLAG_ERL)
-            T0 |= (1 << CP0St_ERL);
-        if (env->hflags & MIPS_HFLAG_EXL)
-            T0 |= (1 << CP0St_EXL);
         rn = "Status";
         break;
     case 13:
--- ./target-mips/op.c_orig	2006-06-19 18:08:40.000000000 +0200
+++ ./target-mips/op.c	2006-06-19 18:31:40.000000000 +0200
@@ -1104,9 +1104,11 @@ void op_eret (void)
     if (env->hflags & MIPS_HFLAG_ERL) {
         env->PC = env->CP0_ErrorEPC;
         env->hflags &= ~MIPS_HFLAG_ERL;
+	env->CP0_Status &= ~(1 << CP0St_ERL);
     } else {
         env->PC = env->CP0_EPC;
         env->hflags &= ~MIPS_HFLAG_EXL;
+	env->CP0_Status &= ~(1 << CP0St_EXL);
     }
     env->CP0_LLAddr = 1;
 }
--- ./target-mips/helper.c_orig	2006-06-19 18:09:36.000000000 +0200
+++ ./target-mips/helper.c	2006-06-19 18:28:23.000000000 +0200
@@ -332,7 +332,8 @@ void do_interrupt (CPUState *env)
         } else {
             env->CP0_ErrorEPC = env->PC;
         }
-        env->hflags = MIPS_HFLAG_ERL;
+        env->hflags |= MIPS_HFLAG_ERL;
+	env->CP0_Status &= (1 << CP0St_ERL);
         pc = 0xBFC00000;
         break;
     case EXCP_MCHECK:
@@ -396,6 +397,7 @@ void do_interrupt (CPUState *env)
             pc = 0x80000000;
         }
         env->hflags |= MIPS_HFLAG_EXL;
+	env->CP0_Status |= (1 << CP0St_EXL);
         pc += offset;
         env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
         if (env->hflags & MIPS_HFLAG_BMASK) {