[parisc-linux] How hp implemented 'undefined instruction'?

[parisc-linux] How hp implemented 'undefined instruction'?

[Joel Soete]

Hello all,

In cpu books (parisc2.0.pdf or pa11_acd.pdf), in some well defined conditions, an insn can be an 'undefined instruction'.

Those books said about this:
--- snip ---
Within each major opcode, there may be undefined opcode extensions and
modifiers (these are undefined instructions). Interpretation of these opcodes
is left to the implementor, but system integrity is not compromised.
An undefined instruction, or sequence of undefined instructions, executed at a
given privilege level has no effect on system state other than what would have
been produced by a sequence of defined instructions running at the same
privilege level. This limits the possible side-effects that could
result from undefined instructions.

Undefined operations are equivalently specified. These result from normally
defined instructions but with operands or specifiers that are explicitly
disallowed.
--- snip ---

In "Interpretation of these opcodes is left to the implementor", I understand HP's integration of those cpu n their system?

But the text make me thought they aren't trap?

Does system behave like it's some kind of nop?

TIA,
	Joel
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Re: [parisc-linux] How hp implemented 'undefined instruction'?

[Kyle McMartin]

On Sat, Aug 26, 2006 at 01:05:55PM +0000, Joel Soete wrote:
> Within each major opcode, there may be undefined opcode extensions and
> modifiers (these are undefined instructions). Interpretation of these 
> opcodes
> is left to the implementor, but system integrity is not compromised.
> An undefined instruction, or sequence of undefined instructions, executed 
> at a
> given privilege level has no effect on system state other than what would 
> have
> been produced by a sequence of defined instructions running at the same
> privilege level. This limits the possible side-effects that could
> result from undefined instructions.
> 
> Undefined operations are equivalently specified. These result from normally
> defined instructions but with operands or specifiers that are explicitly
> disallowed.
> --- snip ---

I believe what they mean here is "Implementation-specific" opcodes. If you
look in the PCXL2 ERS, there are unarchitected additions to the instruction
set.

I hand crafted a binary using some of these extended insns, and they didn't
cause a SIGILL on a PA8500 (vastly different from PCXL2...) I believe the
insn in question was a little endian LDW.

However, if you craft an insn outside of the defined major opcodes, you
definitely will get a SIGILL trap.

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Re: [parisc-linux] How hp implemented 'undefined instruction'?

[Michael S. Zick]

On Sat August 26 2006 14:40, Joel Soete wrote:
>

That seems to be two different situations.
Can be hard to understand even for native English readers.
 
> 
> Ok I understand what you mean but I thought to such e.g. ldcw:
> "The address must be 16-byte aligned. If the address is unaligned, the operation of the instruction is undefined."
> (just for example)
> 

Here, it is "the operation" (how it accomplishes its task) that is undefined.
The instruction definition lists the logical steps the instruction follows when
the operation is aligned.  
There is no list of logical steps for when it is not aligned.

> or may be a better example ssm/mtsm:
> "Setting the PSW Q-bit, PSW{60}, to 1 with this instruction, if it was not already 1, is an undefined operation."
> 

Here, it is what the "result of the operation" is that is undefined.
A software attempt to make a change 0 to 1 and how the hardware follows
that change attempt is not defined.

> I am still trying to understand this soft lockup bug and why this lock is not unlocked? 
>

Ah, yes, the key question.
The results of the tests that you are running now should help us understand the answer.

> (could it be because PSW_I bit is not enabled when we exepted? 
>

No.
But if it is not enabled during the "busy wait" the waiting cpu
will not "see" IPI messages while waiting for the lock.

The "busy wait" time should not be long enough to matter if the
lock is not broken.
If the "busy wait" time happens to be too long with the IPI
messages disabled, then things begin to break.

> The 'atomic' ldcw(,co) doesn't operate as we expect?) 
> 

My favorite theory is that the lock release does not operate
as we expect, but that is only a theory.

> Thanks,
> 	Joel
> 
Mike
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