[PATCH] sparc32: max_cache_size fallback

[PATCH] sparc32: max_cache_size fallback

[Krzysztof Helt]

[-- Attachment #1: Type: text/plain, Size: 601 bytes --]

From: Krzysztof Helt (krzysztof.h1@wp.pl)

It adds a fallback for CPU cache size detection. According to Sun
documentation, it is possible to have SMP system with SM40 modules.

Signed-off-by: Krzysztof Helt (krzysztof.h1@wp.pl)
---

It is added after sparc64 architecture.

Regards,
Krzysztof

----------------------------------------------------
Pensjonat Albatros? wypoczynek w pięknym zakątku Władysławowa.
O krok od plaży, atrakcyjne ceny, dobrze wyposażone pokoje.
Czegóż chcieć więcej? Zapamiętaj: albatros.gda.pl - Kliknij:
http://klik.wp.pl/?adr=www.albatros.gda.pl&sid=841

[-- Attachment #2: sparc32-max-cache-fix.patch --]
[-- Type: application/octet-stream, Size: 646 bytes --]

diff -urp linux-2.6.17/arch/sparc/kernel/smp.c linux-new/arch/sparc/kernel/smp.c
--- linux-2.6.17/arch/sparc/kernel/smp.c	2006-08-10 08:58:31.000000000 +0200
+++ linux-new/arch/sparc/kernel/smp.c	2006-08-12 19:11:20.000000000 +0200
@@ -79,6 +78,9 @@ void __cpuinit smp_store_cpu_info(int id
 		cache_nlines = 0x8000;
 		cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
 		max_cache_size = cache_line * cache_nlines;
+		/* this is for SM40 SuperSparc modules */
+		if (max_cache_size == 0)
+			max_cache_size = 36 * 1024;
 	}
 	if (cpu_data(id).mid < 0)
 		panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);

Re: [PATCH] sparc32: max_cache_size fallback

[David Miller]

From: "Krzysztof Helt" <krzysztof.h1@wp.pl>
Date: Sat, 12 Aug 2006 21:14:44 +0200

> From: Krzysztof Helt (krzysztof.h1@wp.pl)
> 
> It adds a fallback for CPU cache size detection. According to Sun
> documentation, it is possible to have SMP system with SM40 modules.
> 
> Signed-off-by: Krzysztof Helt (krzysztof.h1@wp.pl)
> ---
> 
> It is added after sparc64 architecture.

This new fallback is "36 * 1024", ie. 36K?  That doesn't make any
sense.  I thought the smallest SM40 cache size was 512K or something
like that.

If anything it should be a power of two, not some weird number
like 36K.

Re: [PATCH] sparc32: max_cache_size fallback

[Krzysztof Helt]

Dnia 26-08-2006 o godz. 1:24 David Miller napisa³(a):
> This new fallback is "36 * 1024", ie. 36K?  That doesn't make any
> sense.  I thought the smallest SM40 cache size was 512K or
something
> like that.
> 

According to the documentation I found ("Supersparc II Addendum"
by Sun), the Supersparc processors have 20KB  instruction cache
and 16 KB data cache on CPU. The SMX0 modules were modules
without the L2 cache so only cache on CPU is counted. 

That max_cache_size counting procedure counts only L2 cache as it
is much bigger than L1. Thus for SMX0 modules it may give 0 (I
have no such SMP machine to test). At least one SMP configuration
was sold with such CPUs - it was called SparcStation 10/402 (it
can be found mentioned on specrate listings).

I peeked into the i386 code and found that for original Pentium
the max_cache_size is set to 16KB. The Pentium has 8KB
instruction cache and 8KB data cache (both L1 as it has no L2 on
he CPU). So I did the same for the Supersparcs.


> If anything it should be a power of two, not some weird number
> like 36K.

I added 20KB and 16Kb and got 36KB total cache size.

Regards,
Krzysztof

----------------------------------------------------
Za³ó¿ konto. Przelewy - 0z³. Darmowe konto oszczêdno¶ciowe - 3,25%!
Sprawd¼ i wygraj Toyotê Aygo! >> Kliknij:
http://klik.wp.pl/?adr=http%3A%2F%2Fadv.reklama.wp.pl%2Fas%2Fing22.html&sid…4

Re: [PATCH] sparc32: max_cache_size fallback

[David Miller]

From: "Krzysztof Helt" <krzysztof.h1@wp.pl>
Date: Sat, 26 Aug 2006 10:59:23 +0200

> > If anything it should be a power of two, not some weird number
> > like 36K.
> 
> I added 20KB and 16Kb and got 36KB total cache size.

I think you should just use the data cache size on these
L2'less chips.

Re: [PATCH] sparc32: max_cache_size fallback

[Krzysztof Helt]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: multipart/mixed; boundary="part44f336e6137d9", Size: 45 bytes --]

This is a multi-part message in MIME format.

[-- Attachment #2: Type: text/plain, Size: 661 bytes --]

From: Krzysztof Helt (krzysztof.h1@wp.pl)

It adds a fallback for CPU cache size detection. According to Sun
documentation, it is possible to have SMP system with SM40 modules.
It counts only data cache after David Miller suggestion.

Signed-off-by: Krzysztof Helt (krzysztof.h1@wp.pl) 
---

I don't think that counting only data cache is right but it does
not matter as scheduler do not use values lesser than 64KB (it
uses 64KB instead).

Regards,
Krzysztof

----------------------------------------------------
Weekendowe trunkowanie czyli przepisy na drinki i nalewki - Kliknij:
http://klik.wp.pl/?adr=http%3A%2F%2Fadv.reklama.wp.pl%2Fas%2Fk23.html&sid=859

[-- Attachment #3: sparc32-max-cache-fix.patch --]
[-- Type: application/octet-stream, Size: 646 bytes --]

diff -urp linux-2.6.17/arch/sparc/kernel/smp.c linux-new/arch/sparc/kernel/smp.c
--- linux-2.6.17/arch/sparc/kernel/smp.c	2006-08-10 08:58:31.000000000 +0200
+++ linux-new/arch/sparc/kernel/smp.c	2006-08-12 19:11:20.000000000 +0200
@@ -79,6 +78,9 @@ void __cpuinit smp_store_cpu_info(int id
 		cache_nlines = 0x8000;
 		cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
 		max_cache_size = cache_line * cache_nlines;
+		/* this is for SM40 SuperSparc modules */
+		if (max_cache_size == 0)
+			max_cache_size = 16 * 1024;
 	}
 	if (cpu_data(id).mid < 0)
 		panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);