* Vitrual TLBs
@ 2006-11-20 7:02 Sameer Ahuja
2006-11-20 16:53 ` Anthony Liguori
0 siblings, 1 reply; 6+ messages in thread
From: Sameer Ahuja @ 2006-11-20 7:02 UTC (permalink / raw)
To: Sameer Ahuja, Tim Deegan, xen-devel; +Cc: sameer.ahuja81
Hi,
Does XEN have the concept of virtual TLBs?
Regards,
Sameer
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Vitrual TLBs
2006-11-20 7:02 Vitrual TLBs Sameer Ahuja
@ 2006-11-20 16:53 ` Anthony Liguori
2006-11-20 17:23 ` Liang Yang
0 siblings, 1 reply; 6+ messages in thread
From: Anthony Liguori @ 2006-11-20 16:53 UTC (permalink / raw)
To: Sameer Ahuja; +Cc: Tim Deegan, sameer.ahuja81, xen-devel
Sameer Ahuja wrote:
> Hi,
>
> Does XEN have the concept of virtual TLBs?
>
Not really.
Regards,
Anthony Liguori
> Regards,
> Sameer
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Vitrual TLBs
2006-11-20 16:53 ` Anthony Liguori
@ 2006-11-20 17:23 ` Liang Yang
2006-11-20 20:00 ` Anthony Liguori
0 siblings, 1 reply; 6+ messages in thread
From: Liang Yang @ 2006-11-20 17:23 UTC (permalink / raw)
To: Anthony Liguori, Sameer Ahuja; +Cc: Tim Deegan, sameer.ahuja81, xen-devel
AMD will provide support for nested paging that caches address translations
to reduce memory accesses in its latest quad-core CPUs. As the hypervisor
can get pretty bogged down managing all of this and the processor is
constantly switching from guest OS mode to hypervisor mode and back, Nesting
page tables and caching memory addresses are ways of freeing things up as it
cuts down on memory access time.
So Xen may not need such kind of virtual TLB anymore.
Liang
----- Original Message -----
From: "Anthony Liguori" <aliguori@us.ibm.com>
To: "Sameer Ahuja" <sameer.ahuja@nechclst.in>
Cc: "Tim Deegan" <Tim.Deegan@xensource.com>; <sameer.ahuja81@gmail.com>;
<xen-devel@lists.xensource.com>
Sent: Monday, November 20, 2006 9:53 AM
Subject: Re: [Xen-devel] Vitrual TLBs
> Sameer Ahuja wrote:
>> Hi,
>>
>> Does XEN have the concept of virtual TLBs?
>>
>
> Not really.
>
> Regards,
>
> Anthony Liguori
>
>> Regards,
>> Sameer
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel
>>
>>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Vitrual TLBs
2006-11-20 17:23 ` Liang Yang
@ 2006-11-20 20:00 ` Anthony Liguori
0 siblings, 0 replies; 6+ messages in thread
From: Anthony Liguori @ 2006-11-20 20:00 UTC (permalink / raw)
To: Liang Yang; +Cc: Tim Deegan, sameer.ahuja81, xen-devel, Sameer Ahuja
Liang Yang wrote:
> AMD will provide support for nested paging that caches address
> translations
> to reduce memory accesses in its latest quad-core CPUs. As the hypervisor
> can get pretty bogged down managing all of this and the processor is
> constantly switching from guest OS mode to hypervisor mode and back,
> Nesting
> page tables and caching memory addresses are ways of freeing things up
> as it
> cuts down on memory access time.
>
> So Xen may not need such kind of virtual TLB anymore.
If by virtual TLB you are actually referring to shadow paging (and I
would argue that they are very different concepts), then sorry, I
misunderstood the initial question.
Yes, Xen supports shadow paging. Both Intel and AMD are planning on
supporting hardware shadow paging too in future processors. I think it
remains to be see if the hardware shadow paging is flexible enough to
totally replace software shadow paging.
Regards,
Anthony Liguori
> Liang
>
> ----- Original Message -----
> From: "Anthony Liguori" <aliguori@us.ibm.com>
> To: "Sameer Ahuja" <sameer.ahuja@nechclst.in>
> Cc: "Tim Deegan" <Tim.Deegan@xensource.com>; <sameer.ahuja81@gmail.com>;
> <xen-devel@lists.xensource.com>
> Sent: Monday, November 20, 2006 9:53 AM
> Subject: Re: [Xen-devel] Vitrual TLBs
>
>
>> Sameer Ahuja wrote:
>>> Hi,
>>>
>>> Does XEN have the concept of virtual TLBs?
>>>
>>
>> Not really.
>>
>> Regards,
>>
>> Anthony Liguori
>>
>>> Regards,
>>> Sameer
>>>
>>> _______________________________________________
>>> Xen-devel mailing list
>>> Xen-devel@lists.xensource.com
>>> http://lists.xensource.com/xen-devel
>>>
>>>
>>
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel
>>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: Vitrual TLBs
@ 2006-11-21 3:49 Sameer Ahuja
0 siblings, 0 replies; 6+ messages in thread
From: Sameer Ahuja @ 2006-11-21 3:49 UTC (permalink / raw)
To: Liang Yang, Anthony Liguori; +Cc: Tim Deegan, sameer.ahuja81, xen-devel
Hi Liang,
Can you please share some more knowledge on this topic?
How these virtual TLB's are implemented?
Regards,
Sameer
-----Original Message-----
From: xen-devel-bounces@lists.xensource.com
[mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Liang Yang
Sent: Monday, November 20, 2006 10:53 PM
To: Anthony Liguori; Sameer Ahuja
Cc: Tim Deegan; sameer.ahuja81@gmail.com; xen-devel@lists.xensource.com
Subject: Re: [Xen-devel] Vitrual TLBs
AMD will provide support for nested paging that caches address
translations
to reduce memory accesses in its latest quad-core CPUs. As the
hypervisor
can get pretty bogged down managing all of this and the processor is
constantly switching from guest OS mode to hypervisor mode and back,
Nesting
page tables and caching memory addresses are ways of freeing things up
as it
cuts down on memory access time.
So Xen may not need such kind of virtual TLB anymore.
Liang
----- Original Message -----
From: "Anthony Liguori" <aliguori@us.ibm.com>
To: "Sameer Ahuja" <sameer.ahuja@nechclst.in>
Cc: "Tim Deegan" <Tim.Deegan@xensource.com>; <sameer.ahuja81@gmail.com>;
<xen-devel@lists.xensource.com>
Sent: Monday, November 20, 2006 9:53 AM
Subject: Re: [Xen-devel] Vitrual TLBs
> Sameer Ahuja wrote:
>> Hi,
>>
>> Does XEN have the concept of virtual TLBs?
>>
>
> Not really.
>
> Regards,
>
> Anthony Liguori
>
>> Regards,
>> Sameer
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel
>>
>>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: Vitrual TLBs
@ 2006-11-21 3:55 Sameer Ahuja
0 siblings, 0 replies; 6+ messages in thread
From: Sameer Ahuja @ 2006-11-21 3:55 UTC (permalink / raw)
To: Anthony Liguori, Liang Yang; +Cc: Tim Deegan, sameer.ahuja81, xen-devel
No Anthony, I didn't refer to shadow paging. I meant virtual TLB's only.
I know that shadow tables are maintained in XEN.
-----Original Message-----
From: Anthony Liguori [mailto:aliguori@us.ibm.com]
Sent: Tuesday, November 21, 2006 1:31 AM
To: Liang Yang
Cc: Sameer Ahuja; Tim Deegan; sameer.ahuja81@gmail.com;
xen-devel@lists.xensource.com
Subject: Re: [Xen-devel] Vitrual TLBs
Liang Yang wrote:
> AMD will provide support for nested paging that caches address
> translations
> to reduce memory accesses in its latest quad-core CPUs. As the
hypervisor
> can get pretty bogged down managing all of this and the processor is
> constantly switching from guest OS mode to hypervisor mode and back,
> Nesting
> page tables and caching memory addresses are ways of freeing things up
> as it
> cuts down on memory access time.
>
> So Xen may not need such kind of virtual TLB anymore.
If by virtual TLB you are actually referring to shadow paging (and I
would argue that they are very different concepts), then sorry, I
misunderstood the initial question.
Yes, Xen supports shadow paging. Both Intel and AMD are planning on
supporting hardware shadow paging too in future processors. I think it
remains to be see if the hardware shadow paging is flexible enough to
totally replace software shadow paging.
Regards,
Anthony Liguori
> Liang
>
> ----- Original Message -----
> From: "Anthony Liguori" <aliguori@us.ibm.com>
> To: "Sameer Ahuja" <sameer.ahuja@nechclst.in>
> Cc: "Tim Deegan" <Tim.Deegan@xensource.com>;
<sameer.ahuja81@gmail.com>;
> <xen-devel@lists.xensource.com>
> Sent: Monday, November 20, 2006 9:53 AM
> Subject: Re: [Xen-devel] Vitrual TLBs
>
>
>> Sameer Ahuja wrote:
>>> Hi,
>>>
>>> Does XEN have the concept of virtual TLBs?
>>>
>>
>> Not really.
>>
>> Regards,
>>
>> Anthony Liguori
>>
>>> Regards,
>>> Sameer
>>>
>>> _______________________________________________
>>> Xen-devel mailing list
>>> Xen-devel@lists.xensource.com
>>> http://lists.xensource.com/xen-devel
>>>
>>>
>>
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel
>>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2006-11-21 3:55 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-11-20 7:02 Vitrual TLBs Sameer Ahuja
2006-11-20 16:53 ` Anthony Liguori
2006-11-20 17:23 ` Liang Yang
2006-11-20 20:00 ` Anthony Liguori
-- strict thread matches above, loose matches on Subject: below --
2006-11-21 3:49 Sameer Ahuja
2006-11-21 3:55 Sameer Ahuja
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