From: Zoltan Menyhart <Zoltan.Menyhart@bull.net>
To: Jim Hull <jim.hull@hp.com>
Cc: 'KAMEZAWA Hiroyuki' <kamezawa.hiroyu@jp.fujitsu.com>,
'David Mosberger-Tang' <dmosberger@gmail.com>,
'LKML' <linux-kernel@vger.kernel.org>,
linux-ia64@vger.kernel.org, tony.luck@intel.com,
'Christoph Lameter' <clameter@sgi.com>
Subject: Re: [PATCH] flush icache before set_pte take6. [4/4] optimization
Date: Wed, 01 Aug 2007 09:27:37 +0000 [thread overview]
Message-ID: <46B05209.4050103@bull.net> (raw)
In-Reply-To: <019b01c7d395$27d692b0$3e3af40f@americas.hpqcorp.net>
Jim Hull wrote:
> Not just crazy, but wrong - this *can* happen on pre-Montecito. Even though
> L1D is write-through and L2 was mixed I/D, the L1 I-cache could contain
> stale instrutions if there are missing flushes.
I cannot agree with you.
In order to consider an L1 I-cache entry as valid, a corresponding
virtual -> physic address translation should be valid in one of the L1 ITLBs.
"See 6.1.1. Instruction TLBS" of the I2 Proc. Ref. Man. for SW Dev. & Opt.
You cannot have a valid L1 ITLB entry unless you have a corresponding valid
L2 ITLB entry.
When you remove a PTE (or switch off the exec bit) and you flush the L2 ITLB
matching the old translation (and you kill the corresponding L1 ITLBs),
you do invalidate the corresponding L1 I-cache entries.
Therefore CPU models without split L2 caches are safe.
Thanks,
Zoltan
WARNING: multiple messages have this Message-ID (diff)
From: Zoltan Menyhart <Zoltan.Menyhart@bull.net>
To: Jim Hull <jim.hull@hp.com>
Cc: "'KAMEZAWA Hiroyuki'" <kamezawa.hiroyu@jp.fujitsu.com>,
"'David Mosberger-Tang'" <dmosberger@gmail.com>,
"'LKML'" <linux-kernel@vger.kernel.org>,
linux-ia64@vger.kernel.org, tony.luck@intel.com,
"'Christoph Lameter'" <clameter@sgi.com>
Subject: Re: [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito
Date: Wed, 01 Aug 2007 11:27:37 +0200 [thread overview]
Message-ID: <46B05209.4050103@bull.net> (raw)
In-Reply-To: <019b01c7d395$27d692b0$3e3af40f@americas.hpqcorp.net>
Jim Hull wrote:
> Not just crazy, but wrong - this *can* happen on pre-Montecito. Even though
> L1D is write-through and L2 was mixed I/D, the L1 I-cache could contain
> stale instrutions if there are missing flushes.
I cannot agree with you.
In order to consider an L1 I-cache entry as valid, a corresponding
virtual -> physic address translation should be valid in one of the L1 ITLBs.
"See 6.1.1. Instruction TLBS" of the I2 Proc. Ref. Man. for SW Dev. & Opt.
You cannot have a valid L1 ITLB entry unless you have a corresponding valid
L2 ITLB entry.
When you remove a PTE (or switch off the exec bit) and you flush the L2 ITLB
matching the old translation (and you kill the corresponding L1 ITLBs),
you do invalidate the corresponding L1 I-cache entries.
Therefore CPU models without split L2 caches are safe.
Thanks,
Zoltan
next prev parent reply other threads:[~2007-08-01 9:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-31 2:35 [PATCH] flush icache before set_pte take6. [0/4] KAMEZAWA Hiroyuki
2007-07-31 2:35 ` KAMEZAWA Hiroyuki
2007-07-31 2:38 ` [PATCH] flush icache before set_pte take6. [1/4] migration fix KAMEZAWA Hiroyuki
2007-07-31 2:38 ` KAMEZAWA Hiroyuki
2007-07-31 2:39 ` [PATCH] flush icache before set_pte take6. [2/4] sync icache dcache KAMEZAWA Hiroyuki
2007-07-31 2:39 ` KAMEZAWA Hiroyuki
2007-07-31 2:40 ` [PATCH] flush icache before set_pte take6. [3/4] add montecito KAMEZAWA Hiroyuki
2007-07-31 2:40 ` [PATCH] flush icache before set_pte take6. [3/4] add montecito brand name KAMEZAWA Hiroyuki
2007-07-31 2:41 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for KAMEZAWA Hiroyuki
2007-07-31 2:41 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito KAMEZAWA Hiroyuki
2007-07-31 4:15 ` David Mosberger-Tang
2007-07-31 4:15 ` David Mosberger-Tang
2007-07-31 4:29 ` [PATCH] flush icache before set_pte take6. [4/4] optimization KAMEZAWA Hiroyuki
2007-07-31 4:29 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito KAMEZAWA Hiroyuki
2007-07-31 5:02 ` [PATCH] flush icache before set_pte take6. [4/4] optimization KAMEZAWA Hiroyuki
2007-07-31 5:02 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito KAMEZAWA Hiroyuki
2007-07-31 17:06 ` Jim Hull
2007-07-31 17:06 ` Jim Hull
2007-08-01 9:27 ` Zoltan Menyhart [this message]
2007-08-01 9:27 ` Zoltan Menyhart
2007-07-31 8:38 ` [PATCH] flush icache before set_pte take6. [4/4] optimization Zoltan Menyhart
2007-07-31 8:38 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito Zoltan Menyhart
2007-07-31 10:17 ` [PATCH] flush icache before set_pte take6. [4/4] optimization KAMEZAWA Hiroyuki
2007-07-31 10:17 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito KAMEZAWA Hiroyuki
2007-07-31 11:02 ` [PATCH] flush icache before set_pte take6. [4/4] optimization Zoltan Menyhart
2007-07-31 11:02 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito Zoltan Menyhart
2007-07-31 16:39 ` [PATCH] flush icache before set_pte take6. [3/4] add montecito brand name Luck, Tony
2007-07-31 16:39 ` Luck, Tony
2007-08-01 0:17 ` [PATCH] flush icache before set_pte take6. [3/4] add montecito KAMEZAWA Hiroyuki
2007-08-01 0:17 ` [PATCH] flush icache before set_pte take6. [3/4] add montecito brand name KAMEZAWA Hiroyuki
2007-07-31 16:44 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito Luck, Tony
2007-07-31 16:44 ` Luck, Tony
2007-08-01 9:38 ` [PATCH] flush icache before set_pte take6. [4/4] optimization Zoltan Menyhart
2007-08-01 9:38 ` [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito Zoltan Menyhart
2007-08-01 13:44 ` David Mosberger-Tang
2007-08-01 13:44 ` David Mosberger-Tang
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