[patch 1/2] PS3: Clear SPU Class 0 interrupts in handler

[patch 1/2] PS3: Clear SPU Class 0 interrupts in handler

[Geoff Levand]

From: Masato Noguchi <Masato.Noguchi@jp.sony.com>

Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt.

The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt
is delivered as a pulse.  The current spu interrupt handler assumes this
behavior and does not clear the interrupt status.

The PS3 hypervisor visualizes all SPU interrupts as level, and on return
from the interrupt handler the hypervisor will deliver a new virtual
interrupt for any unmasked interrupts which for which the status has not
been cleared.  This fix clears the interrupt status in the interrupt
handler.

Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---

Arnd, please consider for 2.6.24.
Tested on QS20, and seems OK.

 arch/powerpc/platforms/cell/spu_base.c |   23 +++++++++++++++--------
 include/asm-powerpc/spu.h              |    2 +-
 2 files changed, 16 insertions(+), 9 deletions(-)

--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -236,27 +236,34 @@ static irqreturn_t
 spu_irq_class_0(int irq, void *data)
 {
 	struct spu *spu;
+	unsigned long stat, mask;
 
 	spu = data;
-	spu->class_0_pending = 1;
+
+	mask = spu_int_mask_get(spu, 0);
+	stat = spu_int_stat_get(spu, 0);
+	stat &= mask;
+
+	spin_lock(&spu->register_lock);
+	spu->class_0_pending |= stat;
+	spin_unlock(&spu->register_lock);
+
 	spu->stop_callback(spu);
 
+	spu_int_stat_clear(spu, 0, stat);
+
 	return IRQ_HANDLED;
 }
 
 int
 spu_irq_class_0_bottom(struct spu *spu)
 {
-	unsigned long stat, mask;
 	unsigned long flags;
-
-	spu->class_0_pending = 0;
+	unsigned long stat;
 
 	spin_lock_irqsave(&spu->register_lock, flags);
-	mask = spu_int_mask_get(spu, 0);
-	stat = spu_int_stat_get(spu, 0);
-
-	stat &= mask;
+	stat = spu->class_0_pending;
+	spu->class_0_pending = 0;
 
 	if (stat & 1) /* invalid DMA alignment */
 		__spu_trap_dma_align(spu);
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -130,6 +130,7 @@ struct spu {
 	u64 flags;
 	u64 dar;
 	u64 dsisr;
+	u64 class_0_pending;
 	size_t ls_size;
 	unsigned int slb_replace;
 	struct mm_struct *mm;
@@ -138,7 +139,6 @@ struct spu {
 	unsigned long long timestamp;
 	pid_t pid;
 	pid_t tgid;
-	int class_0_pending;
 	spinlock_t register_lock;
 
 	void (* wbox_callback)(struct spu *spu);

Re: [patch 1/2] PS3: Clear SPU Class 0 interrupts in handler

[Arnd Bergmann]

On Tuesday 04 September 2007, Geoff Levand wrote:
> From: Masato Noguchi <Masato.Noguchi@jp.sony.com>
>=20
> Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt.
>=20
> The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt
> is delivered as a pulse. =C2=A0The current spu interrupt handler assumes =
this
> behavior and does not clear the interrupt status.
>=20
> The PS3 hypervisor visualizes all SPU interrupts as level, and on return
> from the interrupt handler the hypervisor will deliver a new virtual
> interrupt for any unmasked interrupts which for which the status has not
> been cleared. =C2=A0This fix clears the interrupt status in the interrupt
> handler.

Right, we have this one in the sdk3.0/2.6.22-arnd2 kernel since I pulled
in all of the ps3-linux tree, so it was already part of our testing,
and the explanation makes sense, so we should certainly have it
upstream.

Jeremy, please add this to your patch queue.

> Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>

Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>