From: "Krzysztof Helt" <krzysztof.h1@wp.pl>
To: linux-fbdev-devel <linux-fbdev-devel@lists.sourceforge.net>
Subject: (no subject)
Date: Fri, 17 Aug 2007 18:47:13 +0200 [thread overview]
Message-ID: <46c5d1110df9a@wp.pl> (raw)
[-- Attachment #1: Type: text/plain, Size: 119752 bytes --]
From: Krzysztof Helt <krzysztof.h1@wp.pl>
This patch fixes over 850 errors and warnings pointed
out by the checkpatch.pl script.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
---
I run the checkpatch.pl script on the whole drivers/video
directory. The most errors are in drivers which share code
with X11 (sis, nvidia). The cirrus driver had the most errors
as a non-X11 driver.
--- linux-2.6.23.old/drivers/video/cirrusfb.c 2007-07-09 01:
32:16.000000000 +0200
+++ linux-2.6.23/drivers/video/cirrusfb.c 2007-08-16 19:43:
03.000000000 +0200
@@ -59,7 +59,7 @@
#endif
#ifdef CONFIG_PPC_PREP
#include <asm/machdep.h>
-#define isPReP (machine_is(prep))
+#define isPReP(machine_is(prep))
#else
#define isPReP 0
#endif
@@ -67,7 +67,6 @@
#include "video/vga.h"
#include "video/cirrus.h"
-
/****************************************************************
*
*
* debugging and utility macros
@@ -82,7 +81,8 @@
/* debug output */
#ifdef CIRRUSFB_DEBUG
-#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt,
__FUNCTION__ , ## args)
+#define DPRINTK(fmt, args...) \
+ printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif
@@ -90,20 +90,19 @@
/* debugging assertions */
#ifndef CIRRUSFB_NDEBUG
#define assert(expr) \
- if(!(expr)) { \
- printk( "Assertion failed! %s,%s,%s,line=%d\n",\
- #expr,__FILE__,__FUNCTION__,__LINE__); \
- }
+ if (!(expr)) { \
+ printk("Assertion failed! %s,%s,%s,line=%d\n", \
+ #expr, __FILE__, __FUNCTION__, __LINE__); \
+ }
#else
#define assert(expr)
#endif
-#define MB_ (1024*1024)
+#define MB_ (1024 * 1024)
#define KB_ (1024)
#define MAX_NUM_BOARDS 7
-
/****************************************************************
*
*
* chipset information
@@ -123,7 +122,6 @@ typedef enum {
BT_LAGUNA, /* GD546x */
} cirrusfb_board_t;
-
/*
* per-board-type information, used for enumerating and
abstracting
* chip-specific information
@@ -139,7 +137,8 @@ static const struct cirrusfb_board_info_
/* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from
xorg code */
bool init_sr07 : 1; /* init SR07 during init_vgachip() */
bool init_sr1f : 1; /* write SR1F during init_vgachip() */
- bool scrn_start_bit19 : 1; /* construct bit 19 of screen
start address */
+ /* construct bit 19 of screen start address */
+ bool scrn_start_bit19 : 1;
/* initial SR07 value, then for each mode */
unsigned char sr07;
@@ -261,30 +260,28 @@ static const struct cirrusfb_board_info_
}
};
-
#ifdef CONFIG_PCI
#define CHIP(id, btype) \
{ PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
(btype) }
static struct pci_device_id cirrusfb_pci_table[] = {
- CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is
same id */
- CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso
likely */
- CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso
4 is 5446 */
- CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna
*/
- CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna
3D */
- CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna
3DA*/
+ CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is
same id */
+ CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso
likely */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4
is 5446 */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D
*/
+ CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna
3DA*/
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
#undef CHIP
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
static const struct zorro_device_id cirrusfb_zorro_table[] = {
{
@@ -294,7 +291,7 @@ static const struct zorro_device_id cirr
.id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
.driver_data = BT_PICCOLO,
}, {
- .id =
ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
+ .id =
ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
.driver_data = BT_PICASSO,
}, {
.id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
@@ -333,7 +330,6 @@ static const struct {
};
#endif /* CONFIG_ZORRO */
-
struct cirrusfb_regs {
__u32 line_length; /* in BYTES! */
__u32 visual;
@@ -364,17 +360,12 @@ struct cirrusfb_regs {
long VertBlankEnd;
};
-
-
#ifdef CIRRUSFB_DEBUG
typedef enum {
- CRT,
- SEQ
+ CRT,
+ SEQ
} cirrusfb_dbg_reg_class_t;
-#endif /* CIRRUSFB_DEBUG */
-
-
-
+#endif /* CIRRUSFB_DEBUG */
/* info about board */
struct cirrusfb_info {
@@ -405,9 +396,8 @@ struct cirrusfb_info {
void (*unmap)(struct cirrusfb_info *cinfo);
};
-
static unsigned cirrusfb_def_mode = 1;
-static int noaccel = 0;
+static int noaccel;
/*
* Predefined Video Modes
@@ -441,7 +431,7 @@ static const struct {
.lower_margin = 8,
.hsync_len = 96,
.vsync_len = 4,
- .sync = FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT,
+ .sync = FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
}
}, {
@@ -502,27 +492,29 @@ static const struct {
/****************************************************************
************/
/**** BEGIN PROTOTYPES
******************************************************/
-
/*--- Interface used by the world
------------------------------------------*/
-static int cirrusfb_init (void);
+static int cirrusfb_init(void);
#ifndef MODULE
-static int cirrusfb_setup (char *options);
+static int cirrusfb_setup(char *options);
#endif
-static int cirrusfb_open (struct fb_info *info, int user);
-static int cirrusfb_release (struct fb_info *info, int user);
-static int cirrusfb_setcolreg (unsigned regno, unsigned red,
unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info);
-static int cirrusfb_check_var (struct fb_var_screeninfo *var,
- struct fb_info *info);
-static int cirrusfb_set_par (struct fb_info *info);
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
- struct fb_info *info);
-static int cirrusfb_blank (int blank_mode, struct fb_info *info)
;
-static void cirrusfb_fillrect (struct fb_info *info, const
struct fb_fillrect *region);
-static void cirrusfb_copyarea(struct fb_info *info, const struct
fb_copyarea *area);
-static void cirrusfb_imageblit(struct fb_info *info, const
struct fb_image *image);
+static int cirrusfb_open(struct fb_info *info, int user);
+static int cirrusfb_release(struct fb_info *info, int user);
+static int cirrusfb_setcolreg(unsigned regno, unsigned red,
unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info);
+static int cirrusfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+static int cirrusfb_set_par(struct fb_info *info);
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+static int cirrusfb_blank(int blank_mode, struct fb_info *info);
+static void cirrusfb_fillrect(struct fb_info *info,
+ const struct fb_fillrect *region);
+static void cirrusfb_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area);
+static void cirrusfb_imageblit(struct fb_info *info,
+ const struct fb_image *image);
/* function table of the above functions */
static struct fb_ops cirrusfb_ops = {
@@ -540,68 +532,68 @@ static struct fb_ops cirrusfb_ops = {
};
/*--- Hardware Specific Routines
-------------------------------------------*/
-static int cirrusfb_decode_var (const struct fb_var_screeninfo
*var,
+static int cirrusfb_decode_var(const struct fb_var_screeninfo
*var,
struct cirrusfb_regs *regs,
const struct fb_info *info);
/*--- Internal routines
----------------------------------------------------*/
-static void init_vgachip (struct cirrusfb_info *cinfo);
-static void switch_monitor (struct cirrusfb_info *cinfo, int on)
;
-static void WGen (const struct cirrusfb_info *cinfo,
- int regnum, unsigned char val);
-static unsigned char RGen (const struct cirrusfb_info *cinfo,
int regnum);
-static void AttrOn (const struct cirrusfb_info *cinfo);
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned
char val);
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char
val);
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char
val);
-static void WClut (struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char red,
- unsigned char green,
- unsigned char blue);
+static void init_vgachip(struct cirrusfb_info *cinfo);
+static void switch_monitor(struct cirrusfb_info *cinfo, int on);
+static void WGen(const struct cirrusfb_info *cinfo,
+ int regnum, unsigned char val);
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int
regnum);
+static void AttrOn(const struct cirrusfb_info *cinfo);
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned
char val);
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
;
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char
val);
+static void WClut(struct cirrusfb_info *cinfo, unsigned char
regnum,
+ unsigned char red, unsigned char green, unsigned char
blue);
#if 0
-static void RClut (struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char *red,
- unsigned char *green,
- unsigned char *blue);
-#endif
-static void cirrusfb_WaitBLT (u8 __iomem *regbase);
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int
bits_per_pixel,
- u_short curx, u_short cury,
- u_short destx, u_short desty,
- u_short width, u_short height,
- u_short line_length);
-static void cirrusfb_RectFill (u8 __iomem *regbase, int
bits_per_pixel,
- u_short x, u_short y,
- u_short width, u_short height,
- u_char color, u_short line_length);
-
-static void bestclock (long freq, long *best,
- long *nom, long *den,
- long *div, long maxfreq);
+static void RClut(struct cirrusfb_info *cinfo, unsigned char
regnum,
+ unsigned char *red, unsigned char *green,
+ unsigned char *blue);
+#endif
+static void cirrusfb_WaitBLT(u8 __iomem *regbase);
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int
bits_per_pixel,
+ u_short curx, u_short cury,
+ u_short destx, u_short desty,
+ u_short width, u_short height,
+ u_short line_length);
+static void cirrusfb_RectFill(u8 __iomem *regbase, int
bits_per_pixel,
+ u_short x, u_short y,
+ u_short width, u_short height,
+ u_char color, u_short line_length);
+
+static void bestclock(long freq, long *best,
+ long *nom, long *den,
+ long *div, long maxfreq);
#ifdef CIRRUSFB_DEBUG
-static void cirrusfb_dump (void);
-static void cirrusfb_dbg_reg_dump (caddr_t regbase);
-static void cirrusfb_dbg_print_regs (caddr_t regbase,
cirrusfb_dbg_reg_class_t reg_class,...);
-static void cirrusfb_dbg_print_byte (const char *name, unsigned
char val);
+static void cirrusfb_dump(void);
+static void cirrusfb_dbg_reg_dump(caddr_t regbase);
+static void cirrusfb_dbg_print_regs(caddr_t regbase,
+ cirrusfb_dbg_reg_class_t reg_class, ...);
+static void cirrusfb_dbg_print_byte(const char *name, unsigned
char val);
#endif /* CIRRUSFB_DEBUG */
/*** END PROTOTYPES
********************************************************/
/****************************************************************
*************/
/*** BEGIN Interface Used by the World
***************************************/
-static int opencount = 0;
+static int opencount;
/*--- Open /dev/fbx
---------------------------------------------------------*/
-static int cirrusfb_open (struct fb_info *info, int user)
+static int cirrusfb_open(struct fb_info *info, int user)
{
if (opencount++ == 0)
- switch_monitor (info->par, 1);
+ switch_monitor(info->par, 1);
return 0;
}
/*--- Close /dev/fbx
--------------------------------------------------------*/
-static int cirrusfb_release (struct fb_info *info, int user)
+static int cirrusfb_release(struct fb_info *info, int user)
{
if (--opencount == 0)
- switch_monitor (info->par, 0);
+ switch_monitor(info->par, 0);
return 0;
}
@@ -610,11 +602,11 @@ static int cirrusfb_release (struct fb_i
/**** BEGIN Hardware specific Routines
**************************************/
/* Get a good MCLK value */
-static long cirrusfb_get_mclk (long freq, int bpp, long *div)
+static long cirrusfb_get_mclk(long freq, int bpp, long *div)
{
long mclk;
- assert (div != NULL);
+ assert(div != NULL);
/* Calculate MCLK, in case VCLK is high enough to require >
50MHz.
* Assume a 64-bit data path for now. The formula is:
@@ -624,23 +616,23 @@ static long cirrusfb_get_mclk (long freq
mclk = (mclk * 12) / 10;
if (mclk < 50000)
mclk = 50000;
- DPRINTK ("Use MCLK of %ld kHz\n", mclk);
+ DPRINTK("Use MCLK of %ld kHz\n", mclk);
/* Calculate value for SR1F. Multiply by 2 so we can round
up. */
mclk = ((mclk * 16) / 14318);
mclk = (mclk + 1) / 2;
- DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk);
+ DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
/* Determine if we should use MCLK instead of VCLK, and if
so, what we
* should divide it by to get VCLK */
switch (freq) {
case 24751 ... 25249:
*div = 2;
- DPRINTK ("Using VCLK = MCLK/2\n");
+ DPRINTK("Using VCLK = MCLK/2\n");
break;
case 49501 ... 50499:
*div = 1;
- DPRINTK ("Using VCLK = MCLK\n");
+ DPRINTK("Using VCLK = MCLK\n");
break;
default:
*div = 0;
@@ -691,37 +683,42 @@ static int cirrusfb_check_var(struct fb_
den = 1;
break; /* 4 bytes per pixel */
default:
- printk ("cirrusfb: mode %dx%dx%d rejected...color depth
not supported.\n",
+ printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
+ "color depth not supported.\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("EXIT - EINVAL error\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
if (var->xres * nom / den * var->yres > cinfo->size) {
- printk ("cirrusfb: mode %dx%dx%d rejected...resolution
too high to fit into video memory!\n",
+ printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
+ "resolution too high to fit into video memory!\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("EXIT - EINVAL error\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
/* use highest possible virtual resolution */
if (var->xres_virtual == -1 &&
var->yres_virtual == -1) {
- printk ("cirrusfb: using maximum available virtual
resolution\n");
+ printk(KERN_INFO
+ "cirrusfb: using maximum available virtual
resolution\n");
for (i = 0; modes[i].xres != -1; i++) {
if (modes[i].xres * nom / den * modes[i].yres <
cinfo->size / 2)
break;
}
if (modes[i].xres == -1) {
- printk ("cirrusfb: could not find a virtual
resolution that fits into video memory!!\n");
- DPRINTK ("EXIT - EINVAL error\n");
+ printk(KERN_ERR "cirrusfb: could not find a virtual "
+ "resolution that fits into video memory!!\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
var->xres_virtual = modes[i].xres;
var->yres_virtual = modes[i].yres;
- printk ("cirrusfb: virtual resolution set to maximum of
%dx%d\n",
- var->xres_virtual, var->yres_virtual);
+ printk(KERN_INFO "cirrusfb: virtual resolution set to "
+ "maximum of %dx%d\n", var->xres_virtual,
+ var->yres_virtual);
}
if (var->xres_virtual < var->xres)
@@ -760,7 +757,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 16:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 2;
var->green.offset = -3;
var->blue.offset = 8;
@@ -775,7 +772,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 24:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 8;
var->green.offset = 16;
var->blue.offset = 24;
@@ -790,7 +787,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 32:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 8;
var->green.offset = 16;
var->blue.offset = 24;
@@ -825,15 +822,16 @@ static int cirrusfb_check_var(struct fb_
yres = (yres + 1) / 2;
if (yres >= 1280) {
- printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >=
1280; special treatment required! (TODO)\n");
- DPRINTK ("EXIT - EINVAL error\n");
+ printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280;
"
+ "special treatment required! (TODO)\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
return 0;
}
-static int cirrusfb_decode_var (const struct fb_var_screeninfo
*var,
+static int cirrusfb_decode_var(const struct fb_var_screeninfo
*var,
struct cirrusfb_regs *regs,
const struct fb_info *info)
{
@@ -844,7 +842,7 @@ static int cirrusfb_decode_var (const st
int xres, hfront, hsync, hback;
int yres, vfront, vsync, vback;
- switch(var->bits_per_pixel) {
+ switch (var->bits_per_pixel) {
case 1:
regs->line_length = var->xres_virtual / 8;
regs->visual = FB_VISUAL_MONO10;
@@ -887,7 +885,7 @@ static int cirrusfb_decode_var (const st
/* convert from ps to kHz */
freq = 1000000000 / var->pixclock;
- DPRINTK ("desired pixclock: %ld kHz\n", freq);
+ DPRINTK("desired pixclock: %ld kHz\n", freq);
maxclock = cirrusfb_board_info[cinfo->btype].
maxclock[maxclockidx];
regs->multiplexing = 0;
@@ -902,8 +900,9 @@ static int cirrusfb_decode_var (const st
break;
default:
- printk (KERN_WARNING "cirrusfb: ERROR: Frequency
greater than maxclock (%ld kHz)\n", maxclock);
- DPRINTK ("EXIT - return -EINVAL\n");
+ printk(KERN_ERR "cirrusfb: Frequency greater "
+ "than maxclock (%ld kHz)\n", maxclock);
+ DPRINTK("EXIT - return -EINVAL\n");
return -EINVAL;
}
}
@@ -914,14 +913,16 @@ static int cirrusfb_decode_var (const st
case 16:
case 32:
if (regs->HorizRes <= 800)
- freq /= 2; /* Xbh has this type of clock for
32-bit */
+ /* Xbh has this type of clock for 32-bit */
+ freq /= 2;
break;
}
#endif
- bestclock (freq, ®s->freq, ®s->nom, ®s->den,
®s->div,
- maxclock);
- regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel,
®s->divMCLK);
+ bestclock(freq, ®s->freq, ®s->nom, ®s->den,
®s->div,
+ maxclock);
+ regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
+ ®s->divMCLK);
xres = var->xres;
hfront = var->right_margin;
@@ -948,7 +949,8 @@ static int cirrusfb_decode_var (const st
regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
regs->HorizDispEnd = xres / 8 - 1;
regs->HorizBlankStart = xres / 8;
- regs->HorizBlankEnd = regs->HorizTotal + 5; /* does not
count with "-5" */
+ /* does not count with "-5" */
+ regs->HorizBlankEnd = regs->HorizTotal + 5;
regs->HorizSyncStart = (xres + hfront) / 8 + 1;
regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
@@ -976,23 +978,23 @@ static int cirrusfb_decode_var (const st
return 0;
}
-
-static void cirrusfb_set_mclk (const struct cirrusfb_info
*cinfo, int val, int div)
+static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo,
int val,
+ int div)
{
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
if (div == 2) {
/* VCLK = MCLK/2 */
- unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E)
;
- vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1);
- vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f)
);
+ unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
+ vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f))
;
} else if (div == 1) {
/* VCLK = MCLK */
- unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E)
;
- vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1);
- vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f)
);
+ unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
+ vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f))
;
} else {
- vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
}
}
@@ -1001,7 +1003,7 @@ static void cirrusfb_set_mclk (const str
actually writes the values for a new video mode into the
hardware,
*****************************************************************
*********/
-static int cirrusfb_set_par_foo (struct fb_info *info)
+static int cirrusfb_set_par_foo(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_var_screeninfo *var = &info->var;
@@ -1011,15 +1013,15 @@ static int cirrusfb_set_par_foo (struct
int offset = 0, err;
const struct cirrusfb_board_info_rec *bi;
- DPRINTK ("ENTER\n");
- DPRINTK ("Requested mode: %dx%dx%d\n",
+ DPRINTK("ENTER\n");
+ DPRINTK("Requested mode: %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("pixclock: %d\n", var->pixclock);
+ DPRINTK("pixclock: %d\n", var->pixclock);
- init_vgachip (cinfo);
+ init_vgachip(cinfo);
err = cirrusfb_decode_var(var, ®s, info);
- if(err) {
+ if (err) {
/* should never happen */
DPRINTK("mode change aborted. invalid var.\n");
return -EINVAL;
@@ -1027,34 +1029,35 @@ static int cirrusfb_set_par_foo (struct
bi = &cirrusfb_board_info[cinfo->btype];
-
/* unlock register VGA_CRTC_H_TOTAL..CRT7 */
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); /*
previously: 0x00) */
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /*
previously: 0x00) */
/* if debugging is enabled, all parameters get output
before writing */
- DPRINTK ("CRT0: %ld\n", regs.HorizTotal);
- vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
+ DPRINTK("CRT0: %ld\n", regs.HorizTotal);
+ vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
- DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd);
- vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
+ DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
+ vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
- DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart);
- vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.
HorizBlankStart);
+ DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
+ vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.
HorizBlankStart);
- DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
/* + 128: Compatible read */
- vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.
HorizBlankEnd % 32));
+ /* + 128: Compatible read */
+ DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
+ vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
+ 128 + (regs.HorizBlankEnd % 32));
- DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart);
- vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.
HorizSyncStart);
+ DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
+ vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.
HorizSyncStart);
tmp = regs.HorizSyncEnd % 32;
if (regs.HorizBlankEnd & 32)
tmp += 128;
- DPRINTK ("CRT5: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp);
+ DPRINTK("CRT5: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
- DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal &
0xff));
+ DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff)
);
tmp = 16; /* LineCompare bit #9 */
if (regs.VertTotal & 256)
@@ -1071,34 +1074,34 @@ static int cirrusfb_set_par_foo (struct
tmp |= 64;
if (regs.VertSyncStart & 512)
tmp |= 128;
- DPRINTK ("CRT7: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp);
+ DPRINTK("CRT7: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
tmp = 0x40; /* LineCompare bit #8 */
if (regs.VertBlankStart & 512)
tmp |= 0x20;
if (var->vmode & FB_VMODE_DOUBLE)
tmp |= 0x80;
- DPRINTK ("CRT9: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp);
+ DPRINTK("CRT9: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
- DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.
VertSyncStart & 0xff));
+ DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart
& 0xff);
- DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd %
16 + 64 + 32));
+ DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd %
16 + 64 + 32);
- DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd &
0xff));
+ DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd &
0xff);
- DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.
VertBlankStart & 0xff));
+ DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.
VertBlankStart & 0xff);
- DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd
& 0xff));
+ DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd &
0xff);
- DPRINTK ("CRT18: 0xff\n");
- vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff);
+ DPRINTK("CRT18: 0xff\n");
+ vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
tmp = 0;
if (var->vmode & FB_VMODE_INTERLACED)
@@ -1112,57 +1115,63 @@ static int cirrusfb_set_par_foo (struct
if (regs.VertBlankEnd & 512)
tmp |= 128;
- DPRINTK ("CRT1a: %d\n", tmp);
- vga_wcrt (regbase, CL_CRT1A, tmp);
+ DPRINTK("CRT1a: %d\n", tmp);
+ vga_wcrt(regbase, CL_CRT1A, tmp);
/* set VCLK0 */
/* hardware RefClock: 14.31818 MHz */
/* formula: VClk = (OSC * N) / (D * (1+P)) */
/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325
MHz */
- vga_wseq (regbase, CL_SEQRB, regs.nom);
+ vga_wseq(regbase, CL_SEQRB, regs.nom);
tmp = regs.den << 1;
if (regs.div != 0)
tmp |= 1;
+ /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
if ((cinfo->btype == BT_SD64) ||
(cinfo->btype == BT_ALPINE) ||
(cinfo->btype == BT_GD5480))
- tmp |= 0x80; /* 6 bit denom; ONLY 5434!!! (bugged me
10 days) */
+ tmp |= 0x80;
- DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp);
- vga_wseq (regbase, CL_SEQR1B, tmp);
+ DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
+ vga_wseq(regbase, CL_SEQR1B, tmp);
if (regs.VertRes >= 1024)
/* 1280x1024 */
- vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7);
+ vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
else
/* mode control: VGA_CRTC_START_HI enable, ROTATE(?),
16bit
* address wrap, no compat. */
- vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3);
+ vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
-/* HAEH? vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20);
* previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
+/* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
+ * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
/* don't know if it would hurt to also program this if no
interlaced */
/* mode is used, but I feel better this way.. :-) */
if (var->vmode & FB_VMODE_INTERLACED)
- vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
+ vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
else
- vga_wcrt (regbase, VGA_CRTC_REGS, 0x00); /*
interlace control */
+ vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace
control */
- vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0);
+ vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
/* adjust horizontal/vertical sync type (low/high) */
- tmp = 0x03; /* enable display memory & CRTC I/O
address for color mode */
+ /* enable display memory & CRTC I/O address for color mode
*/
+ tmp = 0x03;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
tmp |= 0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
tmp |= 0x80;
- WGen (cinfo, VGA_MIS_W, tmp);
+ WGen(cinfo, VGA_MIS_W, tmp);
- vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0); /* Screen A
Preset Row-Scan register */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0); /* text
cursor on and start line */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31); /* text
cursor end line */
+ /* Screen A Preset Row-Scan register */
+ vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
+ /* text cursor on and start line */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
+ /* text cursor end line */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
/******************************************************
*
@@ -1172,8 +1181,8 @@ static int cirrusfb_set_par_foo (struct
/* programming for different color depths */
if (var->bits_per_pixel == 1) {
- DPRINTK ("cirrusfb: preparing for 1 bit deep display\n")
;
- vga_wgfx (regbase, VGA_GFX_MODE, 0); /* mode
register */
+ DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
+ vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register
*/
/* SR07 */
switch (cinfo->btype) {
@@ -1184,71 +1193,85 @@ static int cirrusfb_set_par_foo (struct
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
- DPRINTK (" (for GD54xx)\n");
- vga_wseq (regbase, CL_SEQR7,
+ DPRINTK(" (for GD54xx)\n");
+ vga_wseq(regbase, CL_SEQR7,
regs.multiplexing ?
bi->sr07_1bpp_mux : bi->sr07_1bpp);
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
/* Extended Sequencer Mode */
switch (cinfo->btype) {
case BT_SD64:
- /* setting the SEQRF on SD64 is not necessary (only
during init) */
- DPRINTK ("(for SD64)\n");
- vga_wseq (regbase, CL_SEQR1F, 0x1a); /* MCLK
select */
+ /* setting the SEQRF on SD64 is not necessary
+ * (only during init)
+ */
+ DPRINTK("(for SD64)\n");
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1a);
break;
case BT_PICCOLO:
- DPRINTK ("(for Piccolo)\n");
-/* ### ueberall 0x22? */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /*
##vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0
bei 1 bit? avoid FIFO underruns..? */
+ DPRINTK("(for Piccolo)\n");
+ /* ### ueberall 0x22? */
+ /* ##vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
- DPRINTK ("(for Picasso)\n");
- vga_wseq (regbase, CL_SEQR1F, 0x22); /*
##vorher 22 MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xd0); /* ## vorher
d0 avoid FIFO underruns..? */
+ DPRINTK("(for Picasso)\n");
+ /* ##vorher 22 MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* ## vorher d0 avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xd0);
break;
case BT_SPECTRUM:
- DPRINTK ("(for Spectrum)\n");
-/* ### ueberall 0x22? */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /*
##vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0?
avoid FIFO underruns..? */
+ DPRINTK("(for Spectrum)\n");
+ /* ### ueberall 0x22? */
+ /* ##vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* evtl d0? avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
case BT_LAGUNA:
- DPRINTK (" (for GD54xx)\n");
+ DPRINTK(" (for GD54xx)\n");
/* do nothing */
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- WGen (cinfo, VGA_PEL_MSK, 0x01); /* pixel mask:
pass-through for first plane */
+ /* pixel mask: pass-through for first plane */
+ WGen(cinfo, VGA_PEL_MSK, 0x01);
if (regs.multiplexing)
- WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024
*/
+ /* hidden dac reg: 1280x1024 */
+ WHDR(cinfo, 0x4a);
else
- WHDR (cinfo, 0); /* hidden dac: nothing */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06); /*
memory mode: odd/even, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01); /*
plane mask: only write to first plane */
+ /* hidden dac: nothing */
+ WHDR(cinfo, 0);
+ /* memory mode: odd/even, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
+ /* plane mask: only write to first plane */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
offset = var->xres_virtual / 16;
}
@@ -1259,7 +1282,7 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 8) {
- DPRINTK ("cirrusfb: preparing for 8 bit deep display\n")
;
+ DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
switch (cinfo->btype) {
case BT_SD64:
case BT_PICCOLO:
@@ -1268,75 +1291,89 @@ static int cirrusfb_set_par_foo (struct
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
- DPRINTK (" (for GD54xx)\n");
- vga_wseq (regbase, CL_SEQR7,
+ DPRINTK(" (for GD54xx)\n");
+ vga_wseq(regbase, CL_SEQR7,
regs.multiplexing ?
bi->sr07_8bpp_mux : bi->sr07_8bpp);
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) | 0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) | 0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR1F, 0x1d); /* MCLK
select */
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1d);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ###
vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ###
vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ###
vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO4:
#ifdef CONFIG_ZORRO
- vga_wseq (regbase, CL_SEQRF, 0xb8); /* ###
INCOMPLETE!! */
+ /* ### INCOMPLETE!! */
+ vga_wseq(regbase, CL_SEQRF, 0xb8);
#endif
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ DPRINTK(" (for GD543x)\n");
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
/* We already set SRF and SR1F */
break;
case BT_GD5480:
case BT_LAGUNA:
- DPRINTK (" (for GD54xx)\n");
+ DPRINTK(" (for GD54xx)\n");
/* do nothing */
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode
register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask:
pass-through all planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
if (regs.multiplexing)
- WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024
*/
+ /* hidden dac reg: 1280x1024 */
+ WHDR(cinfo, 0x4a);
else
- WHDR (cinfo, 0); /* hidden dac: nothing */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /*
memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /*
plane mask: enable writing to all 4 planes */
+ /* hidden dac: nothing */
+ WHDR(cinfo, 0);
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 8;
}
@@ -1347,72 +1384,84 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 16) {
- DPRINTK ("cirrusfb: preparing for 16 bit deep
display\n");
+ DPRINTK("cirrusfb: preparing for 16 bit deep display\n")
;
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR7, 0xf7); /* Extended
Sequencer Mode: 256c col. mode */
- vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK
select */
+ /* Extended Sequencer Mode: 256c col. mode */
+ vga_wseq(regbase, CL_SEQR7, 0xf7);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1e);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR7, 0x87);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x87);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR7, 0x27);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x27);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR7, 0x87);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x87);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO4:
- vga_wseq (regbase, CL_SEQR7, 0x27);
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+ vga_wseq(regbase, CL_SEQR7, 0x27);
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
+ DPRINTK(" (for GD543x)\n");
if (regs.HorizRes >= 1024)
- vga_wseq (regbase, CL_SEQR7, 0xa7);
+ vga_wseq(regbase, CL_SEQR7, 0xa7);
else
- vga_wseq (regbase, CL_SEQR7, 0xa3);
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ vga_wseq(regbase, CL_SEQR7, 0xa3);
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
break;
case BT_GD5480:
- DPRINTK (" (for GD5480)\n");
- vga_wseq (regbase, CL_SEQR7, 0x17);
+ DPRINTK(" (for GD5480)\n");
+ vga_wseq(regbase, CL_SEQR7, 0x17);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "CIRRUSFB: unknown Board\n");
+ printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode
register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask:
pass-through all planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
#ifdef CONFIG_PCI
- WHDR (cinfo, 0xc0); /* Copy Xbh */
+ WHDR(cinfo, 0xc0); /* Copy Xbh */
#elif defined(CONFIG_ZORRO)
/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined
both */
- WHDR (cinfo, 0xa0); /* hidden dac reg: nothing
special */
+ WHDR(cinfo, 0xa0); /* hidden dac reg: nothing
special */
#endif
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /*
memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /*
plane mask: enable writing to all 4 planes */
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 4;
}
@@ -1423,64 +1472,77 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 32) {
- DPRINTK ("cirrusfb: preparing for 24/32 bit deep
display\n");
+ DPRINTK("cirrusfb: preparing for 24/32 bit deep
display\n");
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR7, 0xf9); /* Extended
Sequencer Mode: 256c col. mode */
- vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK
select */
+ /* Extended Sequencer Mode: 256c col. mode */
+ vga_wseq(regbase, CL_SEQR7, 0xf9);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1e);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR7, 0x85);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x85);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR7, 0x25);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x25);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR7, 0x85);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast
Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK
select */
+ vga_wseq(regbase, CL_SEQR7, 0x85);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO4:
- vga_wseq (regbase, CL_SEQR7, 0x25);
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+ vga_wseq(regbase, CL_SEQR7, 0x25);
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
- vga_wseq (regbase, CL_SEQR7, 0xa9);
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ DPRINTK(" (for GD543x)\n");
+ vga_wseq(regbase, CL_SEQR7, 0xa9);
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
break;
case BT_GD5480:
- DPRINTK (" (for GD5480)\n");
- vga_wseq (regbase, CL_SEQR7, 0x19);
+ DPRINTK(" (for GD5480)\n");
+ vga_wseq(regbase, CL_SEQR7, 0x19);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode
register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask:
pass-through all planes */
- WHDR (cinfo, 0xc5); /* hidden dac reg: 8-8-8 mode
(24 or 32) */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /*
memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /*
plane mask: enable writing to all 4 planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
+ /* hidden dac reg: 8-8-8 mode (24 or 32) */
+ WHDR(cinfo, 0xc5);
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 4;
}
@@ -1490,48 +1552,67 @@ static int cirrusfb_set_par_foo (struct
*
*/
- else {
- printk (KERN_ERR "cirrusfb: What's this?? requested
color depth == %d.\n",
+ else
+ printk(KERN_ERR "cirrusfb: What's this?? "
+ " requested color depth == %d.\n",
var->bits_per_pixel);
- }
- vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
tmp = 0x22;
if (offset & 0x100)
tmp |= 0x10; /* offset overflow bit */
- vga_wcrt (regbase, CL_CRT1B, tmp); /* screen start addr
#16-18, fastpagemode cycles */
+ /* screen start addr #16-18, fastpagemode cycles */
+ vga_wcrt(regbase, CL_CRT1B, tmp);
if (cinfo->btype == BT_SD64 ||
cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE ||
cinfo->btype == BT_GD5480)
- vga_wcrt (regbase, CL_CRT1D, 0x00); /* screen start
address bit 19 */
+ /* screen start address bit 19 */
+ vga_wcrt(regbase, CL_CRT1D, 0x00);
- vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0); /* text
cursor location high */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0); /* text
cursor location low */
- vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0); /* underline
row scanline = at very bottom */
-
- vga_wattr (regbase, VGA_ATC_MODE, 1); /* controller
mode */
- vga_wattr (regbase, VGA_ATC_OVERSCAN, 0); /*
overscan (border) color */
- vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15); /* color
plane enable */
- vga_wattr (regbase, CL_AR33, 0); /* pixel panning */
- vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0); /* color
select */
+ /* text cursor location high */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
+ /* text cursor location low */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
+ /* underline row scanline = at very bottom */
+ vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
+
+ /* controller mode */
+ vga_wattr(regbase, VGA_ATC_MODE, 1);
+ /* overscan (border) color */
+ vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
+ /* color plane enable */
+ vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
+ /* pixel panning */
+ vga_wattr(regbase, CL_AR33, 0);
+ /* color select */
+ vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
/* [ EGS: SetOffset(); ] */
/* From SetOffset(): Turn on VideoEnable bit in Attribute
controller */
- AttrOn (cinfo);
+ AttrOn(cinfo);
- vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0); /* set/reset
register */
- vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0); /*
set/reset enable */
- vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0); /* color
compare */
- vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0); /* data
rotate */
- vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0); /* read map
select */
- vga_wgfx (regbase, VGA_GFX_MISC, 1); /* miscellaneous
register */
- vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15); /* color
don't care */
- vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255); /* bit mask
*/
+ /* set/reset register */
+ vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
+ /* set/reset enable */
+ vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
+ /* color compare */
+ vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
+ /* data rotate */
+ vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
+ /* read map select */
+ vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
+ /* miscellaneous register */
+ vga_wgfx(regbase, VGA_GFX_MISC, 1);
+ /* color don't care */
+ vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
+ /* bit mask */
+ vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
- vga_wseq (regbase, CL_SEQR12, 0x0); /* graphics cursor
attributes: nothing special */
+ /* graphics cursor attributes: nothing special */
+ vga_wseq(regbase, CL_SEQR12, 0x0);
/* finally, turn on everything - turn off "FullBandwidth"
bit */
/* also, set "DotClock%2" bit where requested */
@@ -1542,8 +1623,8 @@ static int cirrusfb_set_par_foo (struct
tmp |= 0x08;
*/
- vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp);
- DPRINTK ("CL_SEQR1: %d\n", tmp);
+ vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
+ DPRINTK("CL_SEQR1: %d\n", tmp);
cinfo->currentmode = regs;
info->fix.type = regs.type;
@@ -1551,27 +1632,27 @@ static int cirrusfb_set_par_foo (struct
info->fix.line_length = regs.line_length;
/* pan to requested offset */
- cirrusfb_pan_display (var, info);
+ cirrusfb_pan_display(var, info);
#ifdef CIRRUSFB_DEBUG
- cirrusfb_dump ();
+ cirrusfb_dump();
#endif
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return 0;
}
/* for some reason incomprehensible to me, cirrusfb requires
that you write
* the registers twice for the settings to take..grr. -dte */
-static int cirrusfb_set_par (struct fb_info *info)
+static int cirrusfb_set_par(struct fb_info *info)
{
- cirrusfb_set_par_foo (info);
- return cirrusfb_set_par_foo (info);
+ cirrusfb_set_par_foo(info);
+ return cirrusfb_set_par_foo(info);
}
-static int cirrusfb_setcolreg (unsigned regno, unsigned red,
unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info)
+static int cirrusfb_setcolreg(unsigned regno, unsigned red,
unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
@@ -1584,23 +1665,23 @@ static int cirrusfb_setcolreg (unsigned
green >>= (16 - info->var.green.length);
blue >>= (16 - info->var.blue.length);
- if (regno>=16)
+ if (regno >= 16)
return 1;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
switch (info->var.bits_per_pixel) {
- case 8:
- cinfo->pseudo_palette[regno] = v;
- break;
- case 16:
- cinfo->pseudo_palette[regno] = v;
- break;
- case 24:
- case 32:
- cinfo->pseudo_palette[regno] = v;
- break;
+ case 8:
+ cinfo->pseudo_palette[regno] = v;
+ break;
+ case 16:
+ cinfo->pseudo_palette[regno] = v;
+ break;
+ case 24:
+ case 32:
+ cinfo->pseudo_palette[regno] = v;
+ break;
}
return 0;
}
@@ -1609,9 +1690,8 @@ static int cirrusfb_setcolreg (unsigned
cinfo->palette[regno].green = green;
cinfo->palette[regno].blue = blue;
- if (info->var.bits_per_pixel == 8) {
- WClut (cinfo, regno, red >> 10, green >> 10, blue >>
10);
- }
+ if (info->var.bits_per_pixel == 8)
+ WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
return 0;
@@ -1622,8 +1702,8 @@ static int cirrusfb_setcolreg (unsigned
performs display panning - provided hardware permits this
*****************************************************************
*********/
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
- struct fb_info *info)
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
{
int xoffset = 0;
int yoffset = 0;
@@ -1631,8 +1711,8 @@ static int cirrusfb_pan_display (struct
unsigned char tmp = 0, tmp2 = 0, xpix;
struct cirrusfb_info *cinfo = info->par;
- DPRINTK ("ENTER\n");
- DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset,
var->yoffset);
+ DPRINTK("ENTER\n");
+ DPRINTK("virtual offset: (%d,%d)\n", var->xoffset,
var->yoffset);
/* no range checks for xoffset and yoffset, */
/* as fb_pan_display has already done this */
@@ -1655,11 +1735,13 @@ static int cirrusfb_pan_display (struct
xpix = (unsigned char) ((xoffset % 4) * 2);
}
- cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the
BLT's are done */
+ cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the
BLT's are done */
/* lower 8 + 8 bits of screen start address */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned
char) (base & 0xff));
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned
char) (base >> 8));
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
+ (unsigned char) (base & 0xff));
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
+ (unsigned char) (base >> 8));
/* construct bits 16, 17 and 18 of screen start address */
if (base & 0x10000)
@@ -1669,50 +1751,53 @@ static int cirrusfb_pan_display (struct
if (base & 0x40000)
tmp |= 0x08;
- tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
/* 0xf2 is %11110010, exclude tmp bits */
- vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2);
+ /* 0xf2 is %11110010, exclude tmp bits */
+ tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
+ vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
/* construct bit 19 of screen start address */
if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
tmp2 = 0;
if (base & 0x80000)
tmp2 = 0x80;
- vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2);
+ vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
}
- /* write pixel panning value to AR33; this does not quite
work in 8bpp */
- /* ### Piccolo..? Will this work? */
+ /* write pixel panning value to AR33; this does not quite
work in 8bpp
+ *
+ * ### Piccolo..? Will this work?
+ */
if (info->var.bits_per_pixel == 1)
- vga_wattr (cinfo->regbase, CL_AR33, xpix);
+ vga_wattr(cinfo->regbase, CL_AR33, xpix);
- cirrusfb_WaitBLT (cinfo->regbase);
+ cirrusfb_WaitBLT(cinfo->regbase);
- DPRINTK ("EXIT\n");
- return (0);
+ DPRINTK("EXIT\n");
+ return 0;
}
-
-static int cirrusfb_blank (int blank_mode, struct fb_info *info)
+static int cirrusfb_blank(int blank_mode, struct fb_info *info)
{
/*
- * Blank the screen if blank_mode != 0, else unblank. If
blank == NULL
- * then the caller blanks by setting the CLUT (Color Look Up
Table) to all
- * black. Return 0 if blanking succeeded, != 0 if
un-/blanking failed due
- * to e.g. a video mode which doesn't support it. Implements
VESA suspend
- * and powerdown modes on hardware that supports disabling
hsync/vsync:
- * blank_mode == 2: suspend vsync
- * blank_mode == 3: suspend hsync
- * blank_mode == 4: powerdown
+ * Blank the screen if blank_mode != 0, else unblank. If
blank == NULL
+ * then the caller blanks by setting the CLUT (Color Look Up
Table)
+ * to all black. Return 0 if blanking succeeded, != 0 if
un-/blanking
+ * failed due to e.g. a video mode which doesn't support it.
+ * Implements VESA suspend and powerdown modes on hardware
that
+ * supports disabling hsync/vsync:
+ * blank_mode == 2: suspend vsync
+ * blank_mode == 3: suspend hsync
+ * blank_mode == 4: powerdown
*/
unsigned char val;
struct cirrusfb_info *cinfo = info->par;
int current_mode = cinfo->blank_mode;
- DPRINTK ("ENTER, blank mode = %d\n", blank_mode);
+ DPRINTK("ENTER, blank mode = %d\n", blank_mode);
if (info->state != FBINFO_STATE_RUNNING ||
current_mode == blank_mode) {
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
return 0;
}
@@ -1720,17 +1805,19 @@ static int cirrusfb_blank (int blank_mod
if (current_mode == FB_BLANK_NORMAL ||
current_mode == FB_BLANK_UNBLANK) {
/* unblank the screen */
- val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val &
0xdf); /* clear "FullBandwidth" bit */
+ val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
+ /* clear "FullBandwidth" bit */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf)
;
/* and undo VESA suspend trickery */
- vga_wgfx (cinfo->regbase, CL_GRE, 0x00);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
}
/* set new */
- if(blank_mode > FB_BLANK_NORMAL) {
+ if (blank_mode > FB_BLANK_NORMAL) {
/* blank the screen */
- val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val |
0x20); /* set "FullBandwidth" bit */
+ val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
+ /* set "FullBandwidth" bit */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20)
;
}
switch (blank_mode) {
@@ -1738,21 +1825,21 @@ static int cirrusfb_blank (int blank_mod
case FB_BLANK_NORMAL:
break;
case FB_BLANK_VSYNC_SUSPEND:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x04);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
break;
case FB_BLANK_HSYNC_SUSPEND:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x02);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
break;
case FB_BLANK_POWERDOWN:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x06);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
break;
default:
- DPRINTK ("EXIT, returning 1\n");
+ DPRINTK("EXIT, returning 1\n");
return 1;
}
cinfo->blank_mode = blank_mode;
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
/* Let fbcon do a soft blank for us */
return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
@@ -1761,45 +1848,50 @@ static int cirrusfb_blank (int blank_mod
/****************************************************************
************/
/**** BEGIN Internal Routines
***********************************************/
-static void init_vgachip (struct cirrusfb_info *cinfo)
+static void init_vgachip(struct cirrusfb_info *cinfo)
{
const struct cirrusfb_board_info_rec *bi;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
bi = &cirrusfb_board_info[cinfo->btype];
/* reset board globally */
switch (cinfo->btype) {
case BT_PICCOLO:
- WSFR (cinfo, 0x01);
- udelay (500);
- WSFR (cinfo, 0x51);
- udelay (500);
+ WSFR(cinfo, 0x01);
+ udelay(500);
+ WSFR(cinfo, 0x51);
+ udelay(500);
break;
case BT_PICASSO:
- WSFR2 (cinfo, 0xff);
- udelay (500);
+ WSFR2(cinfo, 0xff);
+ udelay(500);
break;
case BT_SD64:
case BT_SPECTRUM:
- WSFR (cinfo, 0x1f);
- udelay (500);
- WSFR (cinfo, 0x4f);
- udelay (500);
+ WSFR(cinfo, 0x1f);
+ udelay(500);
+ WSFR(cinfo, 0x4f);
+ udelay(500);
break;
case BT_PICASSO4:
- vga_wcrt (cinfo->regbase, CL_CRT51, 0x00); /*
disable flickerfixer */
- mdelay (100);
- vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from
Klaus' NetBSD driver: */
- vga_wgfx (cinfo->regbase, CL_GR33, 0x00); /* put
blitter into 542x compat */
- vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* mode */
+ /* disable flickerfixer */
+ vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
+ mdelay(100);
+ /* from Klaus' NetBSD driver: */
+ vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
+ /* put blitter into 542x compat */
+ vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
+ /* mode */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
break;
case BT_GD5480:
- vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from
Klaus' NetBSD driver: */
+ /* from Klaus' NetBSD driver: */
+ vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
break;
case BT_ALPINE:
@@ -1807,153 +1899,207 @@ static void init_vgachip (struct
cirrusf
break;
default:
- printk (KERN_ERR "cirrusfb: Warning: Unknown board
type\n");
+ printk(KERN_ERR "cirrusfb: Warning: Unknown board
type\n");
break;
}
- assert (cinfo->size > 0); /* make sure RAM size set by this
point */
+ assert(cinfo->size > 0); /* make sure RAM size set by this
point */
/* the P4 is not fully initialized here; I rely on it
having been */
/* inited under AmigaOS already, which seems to work just
fine */
- /* (Klaus advised to do it this way)
*/
+ /* (Klaus advised to do it this way) */
if (cinfo->btype != BT_PICASSO4) {
- WGen (cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
- WGen (cinfo, CL_POS102, 0x01);
- WGen (cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
+ WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
+ WGen(cinfo, CL_POS102, 0x01);
+ WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
if (cinfo->btype != BT_SD64)
- WGen (cinfo, CL_VSSM2, 0x01);
+ WGen(cinfo, CL_VSSM2, 0x01);
- vga_wseq (cinfo->regbase, CL_SEQR0, 0x03); /* reset
sequencer logic */
+ /* reset sequencer logic */
+ vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
/* FullBandwidth (video off) and 8/9 dot clock */
- WGen (cinfo, VGA_MIS_W, 0xc1); /* polarity (-/-),
disable access to display memory, VGA_CRTC_START_HI base address:
color */
+ /* FullBandwidth (video off) and 8/9 dot clock */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
+ /* polarity (-/-), disable access to display memory,
+ * VGA_CRTC_START_HI base address: color
+ */
+ WGen(cinfo, VGA_MIS_W, 0xc1);
-/* vga_wgfx (cinfo->regbase, CL_GRA, 0xce); "magic
cookie" - doesn't make any sense to me.. */
- vga_wseq (cinfo->regbase, CL_SEQR6, 0x12); /* unlock
all extension registers */
+ /* "magic cookie" - doesn't make any sense to me.. */
+/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
+ /* unlock all extension registers */
+ vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
- vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* reset
blitter */
+ /* reset blitter */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
switch (cinfo->btype) {
case BT_GD5480:
- vga_wseq (cinfo->regbase, CL_SEQRF, 0x98);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
break;
case BT_ALPINE:
break;
case BT_SD64:
- vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
break;
default:
- vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f);
- vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0);
+ vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
break;
}
}
- vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
/* plane mask: nothing */
- vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
/* character map select: doesn't even matter in gx mode */
- vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
/* memory mode: chain-4, no odd/even, ext. memory */
+ /* plane mask: nothing */
+ vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
+ /* character map select: doesn't even matter in gx mode */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
+ /* memory mode: chain-4, no odd/even, ext. memory */
+ vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
/* controller-internal base address of video memory */
if (bi->init_sr07)
- vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07);
+ vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
- /* vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM
control: shouldn't be necessary to write to this at all.. */
+ /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
+ /* EEPROM control: shouldn't be necessary to write to this
at all.. */
- vga_wseq (cinfo->regbase, CL_SEQR10, 0x00); /*
graphics cursor X position (incomplete; position gives rem. 3
bits */
- vga_wseq (cinfo->regbase, CL_SEQR11, 0x00); /*
graphics cursor Y position (..."... ) */
- vga_wseq (cinfo->regbase, CL_SEQR12, 0x00); /*
graphics cursor attributes */
- vga_wseq (cinfo->regbase, CL_SEQR13, 0x00); /*
graphics cursor pattern address */
+ /* graphics cursor X position (incomplete; position gives
rem. 3 bits */
+ vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
+ /* graphics cursor Y position (..."... ) */
+ vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
+ /* graphics cursor attributes */
+ vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
+ /* graphics cursor pattern address */
+ vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
/* writing these on a P4 might give problems.. */
if (cinfo->btype != BT_PICASSO4) {
- vga_wseq (cinfo->regbase, CL_SEQR17, 0x00); /*
configuration readback and ext. color */
- vga_wseq (cinfo->regbase, CL_SEQR18, 0x02); /*
signature generator */
+ /* configuration readback and ext. color */
+ vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
+ /* signature generator */
+ vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
}
/* MCLK select etc. */
if (bi->init_sr1f)
- vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
- vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
/* Screen A preset row scan: none */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
/* Text cursor start: disable text cursor */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
/* Text cursor end: - */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00); /*
Screen start address high: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00); /*
Screen start address low: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /*
text cursor location high: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /*
text cursor location low: 0 */
-
- vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); /*
Underline Row scanline: - */
- vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode
control: timing enable, byte mode, no compat modes */
- vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
/* Line Compare: not needed */
+ /* Screen A preset row scan: none */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
+ /* Text cursor start: disable text cursor */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
+ /* Text cursor end: - */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
+ /* Screen start address high: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
+ /* Screen start address low: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
+ /* text cursor location high: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
+ /* text cursor location low: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
+
+ /* Underline Row scanline: - */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
+ /* mode control: timing enable, byte mode, no compat modes
*/
+ vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
+ /* Line Compare: not needed */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
/* ### add 0x40 for text modes with > 30 MHz pixclock */
- vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02); /* ext.
display controls: ext.adr. wrap */
+ /* ext. display controls: ext.adr. wrap */
+ vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
- vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /*
Set/Reset registes: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /*
Set/Reset enable: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
/* Color Compare: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
/* Data Rotate: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /*
Read Map Select: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00); /* Mode:
conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
- vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01); /*
Miscellaneous: memory map base address, graphics mode */
- vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
/* Color Don't care: involve all planes */
- vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); /*
Bit Mask: no mask at all */
+ /* Set/Reset registes: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
+ /* Set/Reset enable: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
+ /* Color Compare: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
+ /* Data Rotate: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
+ /* Read Map Select: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
+ /* Mode: conf. for 16/4/2 color mode, no odd/even,
read/write mode 0 */
+ vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
+ /* Miscellaneous: memory map base address, graphics mode */
+ vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
+ /* Color Don't care: involve all planes */
+ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
+ /* Bit Mask: no mask at all */
+ vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
if (cinfo->btype == BT_ALPINE)
- vga_wgfx (cinfo->regbase, CL_GRB, 0x20); /* (5434
can't have bit 3 set for bitblt) */
+ /* (5434 can't have bit 3 set for bitblt) */
+ vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
else
- vga_wgfx (cinfo->regbase, CL_GRB, 0x28); /* Graphics
controller mode extensions: finer granularity, 8byte data latches
*/
+ /* Graphics controller mode extensions: finer granularity,
+ * 8byte data latches
+ */
+ vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
- vga_wgfx (cinfo->regbase, CL_GRC, 0xff); /* Color Key
compare: - */
- vga_wgfx (cinfo->regbase, CL_GRD, 0x00); /* Color Key
compare mask: - */
- vga_wgfx (cinfo->regbase, CL_GRE, 0x00); /*
Miscellaneous control: - */
- /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//*
Background color byte 1: - */
-/* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
-
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00); /*
Attribute Controller palette registers: "identity mapping" */
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
-
- vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /*
Attribute Controller mode: graphics mode */
- vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /*
Overscan color reg.: reg. 0 */
- vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
/* Color Plane enable: Enable all 4 planes */
-/* ### vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel
Panning: - */
- vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
/* Color Select: - */
+ vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key
compare: - */
+ vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key
compare mask: - */
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /*
Miscellaneous control: - */
+ /* Background color byte 1: - */
+ /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
+ /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
+
+ /* Attribute Controller palette registers: "identity
mapping" */
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
+
+ /* Attribute Controller mode: graphics mode */
+ vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
+ /* Overscan color reg.: reg. 0 */
+ vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
+ /* Color Plane enable: Enable all 4 planes */
+ vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
+/* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel
Panning: - */
+ /* Color Select: - */
+ vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask
*/
+ WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask
*/
if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
- WGen (cinfo, VGA_MIS_W, 0xc3); /* polarity (-/-),
enable display mem, VGA_CRTC_START_HI i/o base = color */
+ /* polarity (-/-), enable display mem,
+ * VGA_CRTC_START_HI i/o base = color
+ */
+ WGen(cinfo, VGA_MIS_W, 0xc3);
- vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* BLT
Start/status: Blitter reset */
- vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* - " -
: "end-of-reset" */
+ /* BLT Start/status: Blitter reset */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
+ /* - " - : "end-of-reset" */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
/* misc... */
- WHDR (cinfo, 0); /* Hidden DAC register: - */
+ WHDR(cinfo, 0); /* Hidden DAC register: - */
- printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of
DRAM memory\n", cinfo->size);
- DPRINTK ("EXIT\n");
+ printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of
DRAM memory\n",
+ cinfo->size);
+ DPRINTK("EXIT\n");
return;
}
-static void switch_monitor (struct cirrusfb_info *cinfo, int on)
+static void switch_monitor(struct cirrusfb_info *cinfo, int on)
{
#ifdef CONFIG_ZORRO /* only works on Zorro boards */
static int IsOn = 0; /* XXX not ok for multiple boards
*/
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (cinfo->btype == BT_PICASSO4)
return; /* nothing to switch */
@@ -1963,44 +2109,43 @@ static void switch_monitor (struct cirru
return; /* nothing to switch */
if (cinfo->btype == BT_PICASSO) {
if ((on && !IsOn) || (!on && IsOn))
- WSFR (cinfo, 0xff);
+ WSFR(cinfo, 0xff);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return;
}
if (on) {
switch (cinfo->btype) {
case BT_SD64:
- WSFR (cinfo, cinfo->SFR | 0x21);
+ WSFR(cinfo, cinfo->SFR | 0x21);
break;
case BT_PICCOLO:
- WSFR (cinfo, cinfo->SFR | 0x28);
+ WSFR(cinfo, cinfo->SFR | 0x28);
break;
case BT_SPECTRUM:
- WSFR (cinfo, 0x6f);
+ WSFR(cinfo, 0x6f);
break;
default: /* do nothing */ break;
}
} else {
switch (cinfo->btype) {
case BT_SD64:
- WSFR (cinfo, cinfo->SFR & 0xde);
+ WSFR(cinfo, cinfo->SFR & 0xde);
break;
case BT_PICCOLO:
- WSFR (cinfo, cinfo->SFR & 0xd7);
+ WSFR(cinfo, cinfo->SFR & 0xd7);
break;
case BT_SPECTRUM:
- WSFR (cinfo, 0x4f);
+ WSFR(cinfo, 0x4f);
break;
default: /* do nothing */ break;
}
}
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
#endif /* CONFIG_ZORRO */
}
-
/******************************************/
/* Linux 2.6-style accelerated functions */
/******************************************/
@@ -2012,15 +2157,17 @@ static void cirrusfb_prim_fillrect(struc
u32 color = (cinfo->info->fix.visual ==
FB_VISUAL_TRUECOLOR) ?
cinfo->pseudo_palette[region->color] : region->color;
- if(cinfo->info->var.bits_per_pixel == 1) {
- cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.
bits_per_pixel,
+ if (cinfo->info->var.bits_per_pixel == 1) {
+ cirrusfb_RectFill(cinfo->regbase,
+ cinfo->info->var.bits_per_pixel,
region->dx / 8, region->dy,
region->width / 8, region->height,
color,
cinfo->currentmode.line_length);
} else {
- m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
- cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.
bits_per_pixel,
+ m = (cinfo->info->var.bits_per_pixel + 7) / 8;
+ cirrusfb_RectFill(cinfo->regbase,
+ cinfo->info->var.bits_per_pixel,
region->dx * m, region->dy,
region->width * m, region->height,
color,
@@ -2029,7 +2176,8 @@ static void cirrusfb_prim_fillrect(struc
return;
}
-static void cirrusfb_fillrect (struct fb_info *info, const
struct fb_fillrect *region)
+static void cirrusfb_fillrect(struct fb_info *info,
+ const struct fb_fillrect *region)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_fillrect modded;
@@ -2047,12 +2195,14 @@ static void cirrusfb_fillrect (struct fb
memcpy(&modded, region, sizeof(struct fb_fillrect));
- if(!modded.width || !modded.height ||
+ if (!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
- if(modded.dx + modded.width > vxres) modded.width = vxres
- modded.dx;
- if(modded.dy + modded.height > vyres) modded.height = vyres
- modded.dy;
+ if (modded.dx + modded.width > vxres)
+ modded.width = vxres - modded.dx;
+ if (modded.dy + modded.height > vyres)
+ modded.height = vyres - modded.dy;
cirrusfb_prim_fillrect(cinfo, &modded);
}
@@ -2061,14 +2211,14 @@ static void cirrusfb_prim_copyarea(struc
const struct fb_copyarea *area)
{
int m; /* bytes per pixel */
- if(cinfo->info->var.bits_per_pixel == 1) {
+ if (cinfo->info->var.bits_per_pixel == 1) {
cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.
bits_per_pixel,
area->sx / 8, area->sy,
area->dx / 8, area->dy,
area->width / 8, area->height,
cinfo->currentmode.line_length);
} else {
- m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
+ m = (cinfo->info->var.bits_per_pixel + 7) / 8;
cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.
bits_per_pixel,
area->sx * m, area->sy,
area->dx * m, area->dy,
@@ -2078,8 +2228,8 @@ static void cirrusfb_prim_copyarea(struc
return;
}
-
-static void cirrusfb_copyarea(struct fb_info *info, const struct
fb_copyarea *area)
+static void cirrusfb_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_copyarea modded;
@@ -2101,89 +2251,99 @@ static void cirrusfb_copyarea(struct fb_
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
- if(!modded.width || !modded.height ||
+ if (!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
- if(modded.sx + modded.width > vxres) modded.width = vxres
- modded.sx;
- if(modded.dx + modded.width > vxres) modded.width = vxres
- modded.dx;
- if(modded.sy + modded.height > vyres) modded.height = vyres
- modded.sy;
- if(modded.dy + modded.height > vyres) modded.height = vyres
- modded.dy;
+ if (modded.sx + modded.width > vxres)
+ modded.width = vxres - modded.sx;
+ if (modded.dx + modded.width > vxres)
+ modded.width = vxres - modded.dx;
+ if (modded.sy + modded.height > vyres)
+ modded.height = vyres - modded.sy;
+ if (modded.dy + modded.height > vyres)
+ modded.height = vyres - modded.dy;
cirrusfb_prim_copyarea(cinfo, &modded);
}
-static void cirrusfb_imageblit(struct fb_info *info, const
struct fb_image *image)
+static void cirrusfb_imageblit(struct fb_info *info,
+ const struct fb_image *image)
{
struct cirrusfb_info *cinfo = info->par;
- cirrusfb_WaitBLT(cinfo->regbase);
+ cirrusfb_WaitBLT(cinfo->regbase);
cfb_imageblit(info, image);
}
-
#ifdef CONFIG_PPC_PREP
#define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
#define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
-static void get_prep_addrs (unsigned long *display, unsigned
long *registers)
+static void get_prep_addrs(unsigned long *display, unsigned long
*registers)
{
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
*display = PREP_VIDEO_BASE;
*registers = (unsigned long) PREP_IO_BASE;
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
#endif /* CONFIG_PPC_PREP */
-
#ifdef CONFIG_PCI
-static int release_io_ports = 0;
+static int release_io_ports;
/* Pulled the logic from XFree86 Cirrus driver to get the memory
size,
* based on the DRAM bandwidth bit and DRAM bank switching bit.
This
* works with 1MB, 2MB and 4MB configurations (which the
Motorola boards
* seem to have. */
-static unsigned int cirrusfb_get_memsize (u8 __iomem *regbase)
+static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
{
unsigned long mem;
unsigned char SRF;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- SRF = vga_rseq (regbase, CL_SEQRF);
+ SRF = vga_rseq(regbase, CL_SEQRF);
switch ((SRF & 0x18)) {
- case 0x08: mem = 512 * 1024; break;
- case 0x10: mem = 1024 * 1024; break;
- /* 64-bit DRAM data bus width; assume 2MB. Also
indicates 2MB memory
- * on the 5430. */
- case 0x18: mem = 2048 * 1024; break;
- default: printk ("CLgenfb: Unknown memory size!\n");
+ case 0x08:
+ mem = 512 * 1024;
+ break;
+ case 0x10:
+ mem = 1024 * 1024;
+ break;
+ /* 64-bit DRAM data bus width; assume 2MB. Also indicates
2MB memory
+ * on the 5430.
+ */
+ case 0x18:
+ mem = 2048 * 1024;
+ break;
+ default:
+ printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
mem = 1024 * 1024;
}
- if (SRF & 0x80) {
- /* If DRAM bank switching is enabled, there must be
twice as much
- * memory installed. (4MB on the 5434) */
+ if (SRF & 0x80)
+ /* If DRAM bank switching is enabled, there must be twice
as much
+ * memory installed. (4MB on the 5434)
+ */
mem *= 2;
- }
+
/* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return mem;
}
-
-
-static void get_pci_addrs (const struct pci_dev *pdev,
- unsigned long *display, unsigned long *registers)
+static void get_pci_addrs(const struct pci_dev *pdev,
+ unsigned long *display, unsigned long *registers)
{
- assert (pdev != NULL);
- assert (display != NULL);
- assert (registers != NULL);
+ assert(pdev != NULL);
+ assert(display != NULL);
+ assert(registers != NULL);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
*display = 0;
*registers = 0;
@@ -2198,13 +2358,12 @@ static void get_pci_addrs (const struct
*registers = pci_resource_start(pdev, 1);
}
- assert (*display != 0);
+ assert(*display != 0);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
-static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
+static void cirrusfb_pci_unmap(struct cirrusfb_info *cinfo)
{
struct pci_dev *pdev = cinfo->pdev;
@@ -2219,19 +2378,18 @@ static void cirrusfb_pci_unmap (struct c
}
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
-static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info
*cinfo)
+static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info
*cinfo)
{
zorro_release_device(cinfo->zdev);
if (cinfo->btype == BT_PICASSO4) {
cinfo->regbase -= 0x600000;
- iounmap ((void *)cinfo->regbase);
- iounmap ((void *)cinfo->fbmem);
+ iounmap((void *)cinfo->regbase);
+ iounmap((void *)cinfo->fbmem);
} else {
if (zorro_resource_start(cinfo->zdev) > 0x01000000)
- iounmap ((void *)cinfo->fbmem);
+ iounmap((void *)cinfo->fbmem);
}
framebuffer_release(cinfo->info);
}
@@ -2267,7 +2425,8 @@ static int cirrusfb_set_fbinfo(struct ci
/* monochrome: only 1 memory plane */
/* 8 bit and above: Use whole memory area */
info->fix.smem_start = cinfo->fbmem_phys;
- info->fix.smem_len = (var->bits_per_pixel == 1) ?
cinfo->size / 4 : cinfo->size;
+ info->fix.smem_len =
+ (var->bits_per_pixel == 1) ? cinfo->size / 4 :
cinfo->size;
info->fix.type = cinfo->currentmode.type;
info->fix.type_aux = 0;
info->fix.visual = cinfo->currentmode.visual;
@@ -2292,17 +2451,18 @@ static int cirrusfb_register(struct cirr
int err;
cirrusfb_board_t btype;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based
graphic boards, v" CIRRUSFB_VERSION "\n");
+ printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
+ "graphic boards, v" CIRRUSFB_VERSION "\n");
info = cinfo->info;
btype = cinfo->btype;
/* sanity checks */
- assert (btype != BT_NONE);
+ assert(btype != BT_NONE);
- DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n",
cinfo->fbmem);
+ DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n",
cinfo->fbmem);
/* Make pretend we've set the var so our structures are in
a "good" */
/* state, even though we haven't written the mode to the hw
yet... */
@@ -2321,11 +2481,12 @@ static int cirrusfb_register(struct cirr
err = register_framebuffer(info);
if (err < 0) {
- printk (KERN_ERR "cirrusfb: could not register fb
device; err = %d!\n", err);
+ printk(KERN_ERR "cirrusfb: could not register "
+ "fb device; err = %d!\n", err);
goto err_dealloc_cmap;
}
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
return 0;
err_dealloc_cmap:
@@ -2335,24 +2496,23 @@ err_unmap_cirrusfb:
return err;
}
-static void __devexit cirrusfb_cleanup (struct fb_info *info)
+static void __devexit cirrusfb_cleanup(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- switch_monitor (cinfo, 0);
+ switch_monitor(cinfo, 0);
- unregister_framebuffer (info);
- fb_dealloc_cmap (&info->cmap);
- printk ("Framebuffer unregistered\n");
+ unregister_framebuffer(info);
+ fb_dealloc_cmap(&info->cmap);
+ printk("Framebuffer unregistered\n");
cinfo->unmap(cinfo);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
#ifdef CONFIG_PCI
-static int cirrusfb_pci_register (struct pci_dev *pdev,
+static int cirrusfb_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct cirrusfb_info *cinfo;
@@ -2379,31 +2539,34 @@ static int cirrusfb_pci_register (struct
cinfo->pdev = pdev;
cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
- DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype
set to %d\n",
+ DPRINTK(" Found PCI device, base address 0 is 0x%lx, btype
set to %d\n",
pdev->resource[0].start, btype);
- DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].
start);
+ DPRINTK(" base address 1 is 0x%lx\n", pdev->resource[1].
start);
- if(isPReP) {
- pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0,
0x00000000);
+ if (isPReP) {
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0,
0x00000000);
#ifdef CONFIG_PPC_PREP
- get_prep_addrs (&board_addr, &cinfo->fbregs_phys);
+ get_prep_addrs(&board_addr, &cinfo->fbregs_phys);
#endif
- /* PReP dies if we ioremap the IO registers, but it
works w/out... */
+ /* PReP dies if we ioremap the IO registers, but it works
w/out... */
cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
} else {
- DPRINTK ("Attempt to get PCI info for Cirrus Graphics
Card\n");
- get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys);
- cinfo->regbase = NULL; /* FIXME: this forces VGA.
alternatives? */
+ DPRINTK("Attempt to get PCI info for Cirrus Graphics
Card\n");
+ get_pci_addrs(pdev, &board_addr, &cinfo->fbregs_phys);
+ /* FIXME: this forces VGA. alternatives? */
+ cinfo->regbase = NULL;
}
- DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n",
board_addr, cinfo->fbregs_phys);
+ DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
+ board_addr, cinfo->fbregs_phys);
board_size = (btype == BT_GD5480) ?
- 32 * MB_ : cirrusfb_get_memsize (cinfo->regbase);
+ 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
ret = pci_request_regions(pdev, "cirrusfb");
- if (ret <0) {
- printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx,
abort\n",
+ if (ret < 0) {
+ printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx,
"
+ "abort\n",
board_addr);
goto err_release_fb;
}
@@ -2429,8 +2592,9 @@ static int cirrusfb_pci_register (struct
cinfo->size = board_size;
cinfo->unmap = cirrusfb_pci_unmap;
- printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_,
board_addr);
- printk ("Cirrus Logic chipset on PCI bus\n");
+ printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
+ cinfo->size / KB_, board_addr);
+ printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
pci_set_drvdata(pdev, info);
ret = cirrusfb_register(cinfo);
@@ -2453,14 +2617,14 @@ err_out:
return ret;
}
-static void __devexit cirrusfb_pci_unregister (struct pci_dev
*pdev)
+static void __devexit cirrusfb_pci_unregister(struct pci_dev
*pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- cirrusfb_cleanup (info);
+ cirrusfb_cleanup(info);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
static struct pci_driver cirrusfb_pci_driver = {
@@ -2477,7 +2641,6 @@ static struct pci_driver cirrusfb_pci_dr
};
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
static int cirrusfb_zorro_register(struct zorro_dev *z,
const struct zorro_device_id *ent)
@@ -2498,7 +2661,7 @@ static int cirrusfb_zorro_register(struc
info = framebuffer_alloc(sizeof(struct cirrusfb_info),
&z->dev);
if (!info) {
- printk (KERN_ERR "cirrusfb: could not allocate
memory\n");
+ printk(KERN_ERR "cirrusfb: could not allocate memory\n")
;
ret = -ENOMEM;
goto err_out;
}
@@ -2507,9 +2670,9 @@ static int cirrusfb_zorro_register(struc
cinfo->info = info;
cinfo->btype = btype;
- assert (z > 0);
- assert (z2 >= 0);
- assert (btype != BT_NONE);
+ assert(z > 0);
+ assert(z2 >= 0);
+ assert(btype != BT_NONE);
cinfo->zdev = z;
board_addr = zorro_resource_start(z);
@@ -2517,55 +2680,59 @@ static int cirrusfb_zorro_register(struc
cinfo->size = size;
if (!zorro_request_device(z, "cirrusfb")) {
- printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx,
abort\n",
+ printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx,
"
+ "abort\n",
board_addr);
ret = -EBUSY;
goto err_release_fb;
}
- printk (" RAM (%lu MB) at $%lx, ", board_size / MB_,
board_addr);
+ printk(" RAM (%lu MB) at $%lx, ", board_size / MB_,
board_addr);
ret = -EIO;
if (btype == BT_PICASSO4) {
- printk (" REG at $%lx\n", board_addr + 0x600000);
+ printk(KERN_INFO " REG at $%lx\n", board_addr +
0x600000);
/* To be precise, for the P4 this is not the */
/* begin of the board, but the begin of RAM. */
/* for P4, map in its address space in 2 chunks (###
TEST! ) */
/* (note the ugly hardcoded 16M number) */
- cinfo->regbase = ioremap (board_addr, 16777216);
+ cinfo->regbase = ioremap(board_addr, 16777216);
if (!cinfo->regbase)
goto err_release_region;
- DPRINTK ("cirrusfb: Virtual address for board set to: $%
p\n", cinfo->regbase);
+ DPRINTK("cirrusfb: Virtual address for board set to: $%
p\n",
+ cinfo->regbase);
cinfo->regbase += 0x600000;
cinfo->fbregs_phys = board_addr + 0x600000;
cinfo->fbmem_phys = board_addr + 16777216;
- cinfo->fbmem = ioremap (cinfo->fbmem_phys, 16777216);
+ cinfo->fbmem = ioremap(cinfo->fbmem_phys, 16777216);
if (!cinfo->fbmem)
goto err_unmap_regbase;
} else {
- printk (" REG at $%lx\n", (unsigned long) z2->resource.
start);
+ printk(KERN_INFO " REG at $%lx\n",
+ (unsigned long) z2->resource.start);
cinfo->fbmem_phys = board_addr;
if (board_addr > 0x01000000)
- cinfo->fbmem = ioremap (board_addr, board_size);
+ cinfo->fbmem = ioremap(board_addr, board_size);
else
- cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr);
+ cinfo->fbmem = (caddr_t) ZTWO_VADDR(board_addr);
if (!cinfo->fbmem)
goto err_release_region;
/* set address for REG area of board */
- cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.
start);
+ cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.
start);
cinfo->fbregs_phys = z2->resource.start;
- DPRINTK ("cirrusfb: Virtual address for board set to: $%
p\n", cinfo->regbase);
+ DPRINTK("cirrusfb: Virtual address for board set to: $%
p\n",
+ cinfo->regbase);
}
cinfo->unmap = cirrusfb_zorro_unmap;
- printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
+ printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
zorro_set_drvdata(z, info);
ret = cirrusfb_register(cinfo);
@@ -2592,11 +2759,11 @@ err_out:
void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
{
struct fb_info *info = zorro_get_drvdata(z);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- cirrusfb_cleanup (info);
+ cirrusfb_cleanup(info);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
static struct zorro_driver cirrusfb_zorro_driver = {
@@ -2628,26 +2795,24 @@ static int __init cirrusfb_init(void)
return error;
}
-
-
#ifndef MODULE
static int __init cirrusfb_setup(char *options) {
char *this_opt, s[32];
int i;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (!options || !*options)
return 0;
- while ((this_opt = strsep (&options, ",")) != NULL) {
+ while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
for (i = 0; i < NUM_TOTAL_MODES; i++) {
- sprintf (s, "mode:%s", cirrusfb_predefined[i].name);
- if (strcmp (this_opt, s) == 0)
+ sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
+ if (strcmp(this_opt, s) == 0)
cirrusfb_def_mode = i;
}
if (!strcmp(this_opt, "noaccel"))
@@ -2657,7 +2822,6 @@ static int __init cirrusfb_setup(char *o
}
#endif
-
/*
* Modularization
*/
@@ -2666,7 +2830,7 @@ MODULE_AUTHOR("Copyright 1999,2000 Jeff
MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic
chips");
MODULE_LICENSE("GPL");
-static void __exit cirrusfb_exit (void)
+static void __exit cirrusfb_exit(void)
{
#ifdef CONFIG_PCI
pci_unregister_driver(&cirrusfb_pci_driver);
@@ -2682,66 +2846,67 @@ module_init(cirrusfb_init);
module_exit(cirrusfb_exit);
#endif
-
/****************************************************************
******/
/* about the following functions - I have used the same names
for the */
/* functions as Markus Wild did in his Retina driver for NetBSD
as */
/* they just made sense for this purpose. Apart from that, I
wrote */
-/* these functions myself.
*/
+/* these functions myself. */
/****************************************************************
******/
/*** WGen() - write into one of the external/general registers
***/
-static void WGen (const struct cirrusfb_info *cinfo,
+static void WGen(const struct cirrusfb_info *cinfo,
int regnum, unsigned char val)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
-/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D
|| regnum == CL_VSSM2) */
+/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+ regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
- vga_w (cinfo->regbase, regofs + regnum, val);
+ vga_w(cinfo->regbase, regofs + regnum, val);
}
/*** RGen() - read out one of the external/general registers
***/
-static unsigned char RGen (const struct cirrusfb_info *cinfo,
int regnum)
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int
regnum)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
-/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D
|| regnum == CL_VSSM2) */
+/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+ regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
- return vga_r (cinfo->regbase, regofs + regnum);
+ return vga_r(cinfo->regbase, regofs + regnum);
}
/*** AttrOn() - turn on VideoEnable for Attribute controller
***/
-static void AttrOn (const struct cirrusfb_info *cinfo)
+static void AttrOn(const struct cirrusfb_info *cinfo)
{
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) {
+ if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
/* if we're just in "write value" mode, write back the
*/
/* same value as before to not modify anything */
- vga_w (cinfo->regbase, VGA_ATT_IW,
- vga_r (cinfo->regbase, VGA_ATT_R));
+ vga_w(cinfo->regbase, VGA_ATT_IW,
+ vga_r(cinfo->regbase, VGA_ATT_R));
}
/* turn on video bit */
-/* vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */
- vga_w (cinfo->regbase, VGA_ATT_IW, 0x33);
+/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
+ vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
/* dummy write on Reg0 to be on "write index" mode next
time */
- vga_w (cinfo->regbase, VGA_ATT_IW, 0x00);
+ vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
/*** WHDR() - write into the Hidden DAC register ***/
@@ -2750,119 +2915,115 @@ static void AttrOn (const struct
cirrusf
* registers of their functional group) here is a specialized
routine for
* accessing the HDR
*/
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned
char val)
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned
char val)
{
unsigned char dummy;
if (cinfo->btype == BT_PICASSO) {
/* Klaus' hint for correct access to HDR on some boards
*/
/* first write 0 to pixel mask (3c6) */
- WGen (cinfo, VGA_PEL_MSK, 0x00);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, 0x00);
+ udelay(200);
/* next read dummy from pixel address (3c8) */
- dummy = RGen (cinfo, VGA_PEL_IW);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_IW);
+ udelay(200);
}
/* now do the usual stuff to access the HDR */
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
- WGen (cinfo, VGA_PEL_MSK, val);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, val);
+ udelay(200);
if (cinfo->btype == BT_PICASSO) {
/* now first reset HDR access counter */
- dummy = RGen (cinfo, VGA_PEL_IW);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_IW);
+ udelay(200);
/* and at the end, restore the mask value */
/* ## is this mask always 0xff? */
- WGen (cinfo, VGA_PEL_MSK, 0xff);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
+ udelay(200);
}
}
-
/*** WSFR() - write to the "special function register" (SFR)
***/
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char
val)
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
{
#ifdef CONFIG_ZORRO
- assert (cinfo->regbase != NULL);
+ assert(cinfo->regbase != NULL);
cinfo->SFR = val;
- z_writeb (val, cinfo->regbase + 0x8000);
+ z_writeb(val, cinfo->regbase + 0x8000);
#endif
}
/* The Picasso has a second register for switching the monitor
bit */
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char
val)
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char
val)
{
#ifdef CONFIG_ZORRO
/* writing an arbitrary value to this one causes the
monitor switcher */
/* to flip to Amiga display */
- assert (cinfo->regbase != NULL);
+ assert(cinfo->regbase != NULL);
cinfo->SFR = val;
- z_writeb (val, cinfo->regbase + 0x9000);
+ z_writeb(val, cinfo->regbase + 0x9000);
#endif
}
-
/*** WClut - set CLUT entry (range: 0..63) ***/
-static void WClut (struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char red,
+static void WClut(struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char red,
unsigned char green, unsigned char blue)
{
unsigned int data = VGA_PEL_D;
/* address write mode register is not translated.. */
- vga_w (cinfo->regbase, VGA_PEL_IW, regnum);
+ vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype ==
BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
/* but DAC data register IS, at least for Picasso II */
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
- vga_w (cinfo->regbase, data, red);
- vga_w (cinfo->regbase, data, green);
- vga_w (cinfo->regbase, data, blue);
+ vga_w(cinfo->regbase, data, red);
+ vga_w(cinfo->regbase, data, green);
+ vga_w(cinfo->regbase, data, blue);
} else {
- vga_w (cinfo->regbase, data, blue);
- vga_w (cinfo->regbase, data, green);
- vga_w (cinfo->regbase, data, red);
+ vga_w(cinfo->regbase, data, blue);
+ vga_w(cinfo->regbase, data, green);
+ vga_w(cinfo->regbase, data, red);
}
}
-
#if 0
/*** RClut - read CLUT entry (range 0..63) ***/
-static void RClut (struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char *red,
+static void RClut(struct cirrusfb_info *cinfo, unsigned char
regnum, unsigned char *red,
unsigned char *green, unsigned char *blue)
{
unsigned int data = VGA_PEL_D;
- vga_w (cinfo->regbase, VGA_PEL_IR, regnum);
+ vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype ==
BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
- *red = vga_r (cinfo->regbase, data);
- *green = vga_r (cinfo->regbase, data);
- *blue = vga_r (cinfo->regbase, data);
+ *red = vga_r(cinfo->regbase, data);
+ *green = vga_r(cinfo->regbase, data);
+ *blue = vga_r(cinfo->regbase, data);
} else {
- *blue = vga_r (cinfo->regbase, data);
- *green = vga_r (cinfo->regbase, data);
- *red = vga_r (cinfo->regbase, data);
+ *blue = vga_r(cinfo->regbase, data);
+ *green = vga_r(cinfo->regbase, data);
+ *red = vga_r(cinfo->regbase, data);
}
}
#endif
-
/****************************************************************
***
cirrusfb_WaitBLT()
@@ -2870,10 +3031,10 @@ static void RClut (struct cirrusfb_info
*****************************************************************
****/
/* FIXME: use interrupts instead */
-static void cirrusfb_WaitBLT (u8 __iomem *regbase)
+static void cirrusfb_WaitBLT(u8 __iomem *regbase)
{
/* now busy-wait until we're done */
- while (vga_rgfx (regbase, CL_GR31) & 0x08)
+ while (vga_rgfx(regbase, CL_GR31) & 0x08)
/* do nothing */ ;
}
@@ -2883,15 +3044,17 @@ static void cirrusfb_WaitBLT (u8 __iomem
perform accelerated "scrolling"
*****************************************************************
***/
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int
bits_per_pixel,
- u_short curx, u_short cury, u_short destx, u_short
desty,
- u_short width, u_short height, u_short
line_length)
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int
bits_per_pixel,
+ u_short curx, u_short cury,
+ u_short destx, u_short desty,
+ u_short width, u_short height,
+ u_short line_length)
{
u_short nwidth, nheight;
u_long nsrc, ndest;
u_char bltmode;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
nwidth = width - 1;
nheight = height - 1;
@@ -2911,9 +3074,13 @@ static void cirrusfb_BitBLT (u8 __iomem
nsrc = (cury * line_length) + curx;
ndest = (desty * line_length) + destx;
} else {
- /* this means start addresses are at the end, counting
backwards */
- nsrc = cury * line_length + curx + nheight * line_length
+ nwidth;
- ndest = desty * line_length + destx + nheight *
line_length + nwidth;
+ /* this means start addresses are at the end,
+ * counting backwards
+ */
+ nsrc = cury * line_length + curx +
+ nheight * line_length + nwidth;
+ ndest = desty * line_length + destx +
+ nheight * line_length + nwidth;
}
/*
@@ -2929,52 +3096,65 @@ static void cirrusfb_BitBLT (u8 __iomem
start/stop
*/
- cirrusfb_WaitBLT(regbase);
+ cirrusfb_WaitBLT(regbase);
/* pitch: set to line_length */
- vga_wgfx (regbase, CL_GR24, line_length & 0xff); /*
dest pitch low */
- vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /*
dest pitch hi */
- vga_wgfx (regbase, CL_GR26, line_length & 0xff); /*
source pitch low */
- vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /*
source pitch hi */
+ /* dest pitch low */
+ vga_wgfx(regbase, CL_GR24, line_length & 0xff);
+ /* dest pitch hi */
+ vga_wgfx(regbase, CL_GR25, line_length >> 8);
+ /* source pitch low */
+ vga_wgfx(regbase, CL_GR26, line_length & 0xff);
+ /* source pitch hi */
+ vga_wgfx(regbase, CL_GR27, line_length >> 8);
/* BLT width: actual number of pixels - 1 */
- vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT
width low */
- vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT
width hi */
+ /* BLT width low */
+ vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
+ /* BLT width hi */
+ vga_wgfx(regbase, CL_GR21, nwidth >> 8);
/* BLT height: actual number of lines -1 */
- vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT
height low */
- vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT
width hi */
+ /* BLT height low */
+ vga_wgfx(regbase, CL_GR22, nheight & 0xff);
+ /* BLT width hi */
+ vga_wgfx(regbase, CL_GR23, nheight >> 8);
/* BLT destination */
- vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff));
/* BLT dest low */
- vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /*
BLT dest mid */
- vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /*
BLT dest hi */
+ /* BLT dest low */
+ vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
+ /* BLT dest mid */
+ vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
+ /* BLT dest hi */
+ vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT source */
- vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /*
BLT src low */
- vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8));
/* BLT src mid */
- vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16)); /*
BLT src hi */
+ /* BLT src low */
+ vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
+ /* BLT src mid */
+ vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
+ /* BLT src hi */
+ vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
/* BLT mode */
- vga_wgfx (regbase, CL_GR30, bltmode); /* BLT mode */
+ vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
/* BLT ROP: SrcCopy */
- vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
+ vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
- vga_wgfx (regbase, CL_GR31, 0x02); /* BLT
Start/status */
+ vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status
*/
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/****************************************************************
***
cirrusfb_RectFill()
perform accelerated rectangle fill
*****************************************************************
***/
-static void cirrusfb_RectFill (u8 __iomem *regbase, int
bits_per_pixel,
+static void cirrusfb_RectFill(u8 __iomem *regbase, int
bits_per_pixel,
u_short x, u_short y, u_short width, u_short height,
u_char color, u_short line_length)
{
@@ -2982,93 +3162,95 @@ static void cirrusfb_RectFill (u8 __iome
u_long ndest;
u_char op;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
nwidth = width - 1;
nheight = height - 1;
ndest = (y * line_length) + x;
- cirrusfb_WaitBLT(regbase);
+ cirrusfb_WaitBLT(regbase);
/* pitch: set to line_length */
- vga_wgfx (regbase, CL_GR24, line_length & 0xff); /*
dest pitch low */
- vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /*
dest pitch hi */
- vga_wgfx (regbase, CL_GR26, line_length & 0xff); /*
source pitch low */
- vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /*
source pitch hi */
+ vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest
pitch low */
+ vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest
pitch hi */
+ vga_wgfx(regbase, CL_GR26, line_length & 0xff); /*
source pitch low */
+ vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source
pitch hi */
/* BLT width: actual number of pixels - 1 */
- vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT
width low */
- vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT
width hi */
+ vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width
low */
+ vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width
hi */
/* BLT height: actual number of lines -1 */
- vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT
height low */
- vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT
width hi */
+ vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT
height low */
+ vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width
hi */
/* BLT destination */
- vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff));
/* BLT dest low */
- vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /*
BLT dest mid */
- vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT dest hi */
+ /* BLT dest low */
+ vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
+ /* BLT dest mid */
+ vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
+ /* BLT dest hi */
+ vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT source: set to 0 (is a dummy here anyway) */
- vga_wgfx (regbase, CL_GR2C, 0x00); /* BLT src low */
- vga_wgfx (regbase, CL_GR2D, 0x00); /* BLT src mid */
- vga_wgfx (regbase, CL_GR2E, 0x00); /* BLT src hi */
+ vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
+ vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
+ vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
/* This is a ColorExpand Blt, using the */
/* same color for foreground and background */
- vga_wgfx (regbase, VGA_GFX_SR_VALUE, color); /*
foreground color */
- vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color); /*
background color */
+ vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /*
foreground color */
+ vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /*
background color */
op = 0xc0;
if (bits_per_pixel == 16) {
- vga_wgfx (regbase, CL_GR10, color); /* foreground
color */
- vga_wgfx (regbase, CL_GR11, color); /* background
color */
+ vga_wgfx(regbase, CL_GR10, color); /* foreground
color */
+ vga_wgfx(regbase, CL_GR11, color); /* background
color */
op = 0x50;
op = 0xd0;
} else if (bits_per_pixel == 32) {
- vga_wgfx (regbase, CL_GR10, color); /* foreground
color */
- vga_wgfx (regbase, CL_GR11, color); /* background
color */
- vga_wgfx (regbase, CL_GR12, color); /* foreground
color */
- vga_wgfx (regbase, CL_GR13, color); /* background
color */
- vga_wgfx (regbase, CL_GR14, 0); /* foreground color
*/
- vga_wgfx (regbase, CL_GR15, 0); /* background color
*/
+ vga_wgfx(regbase, CL_GR10, color); /* foreground
color */
+ vga_wgfx(regbase, CL_GR11, color); /* background
color */
+ vga_wgfx(regbase, CL_GR12, color); /* foreground
color */
+ vga_wgfx(regbase, CL_GR13, color); /* background
color */
+ vga_wgfx(regbase, CL_GR14, 0); /* foreground color
*/
+ vga_wgfx(regbase, CL_GR15, 0); /* background color
*/
op = 0x50;
op = 0xf0;
}
/* BLT mode: color expand, Enable 8x8 copy (faster?) */
- vga_wgfx (regbase, CL_GR30, op); /* BLT mode */
+ vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
/* BLT ROP: SrcCopy */
- vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
+ vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
- vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status
*/
+ vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status
*/
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/****************************************************************
**********
* bestclock() - determine closest possible clock lower(?) than
the
* desired pixel clock
*****************************************************************
*********/
-static void bestclock (long freq, long *best, long *nom,
+static void bestclock(long freq, long *best, long *nom,
long *den, long *div, long maxfreq)
{
long n, h, d, f;
- assert (best != NULL);
- assert (nom != NULL);
- assert (den != NULL);
- assert (div != NULL);
- assert (maxfreq > 0);
+ assert(best != NULL);
+ assert(nom != NULL);
+ assert(den != NULL);
+ assert(div != NULL);
+ assert(maxfreq > 0);
*nom = 0;
*den = 0;
*div = 0;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (freq < 8000)
freq = 8000;
@@ -3085,7 +3267,7 @@ static void bestclock (long freq, long *
if (d > 31)
d = (d / 2) * 2;
h = (14318 * n) / d;
- if (abs (h - freq) < abs (*best - freq)) {
+ if (abs(h - freq) < abs(*best - freq)) {
*best = h;
*nom = n;
if (d < 32) {
@@ -3102,7 +3284,7 @@ static void bestclock (long freq, long *
if (d > 31)
d = (d / 2) * 2;
h = (14318 * n) / d;
- if (abs (h - freq) < abs (*best - freq)) {
+ if (abs(h - freq) < abs(*best - freq)) {
*best = h;
*nom = n;
if (d < 32) {
@@ -3116,14 +3298,13 @@ static void bestclock (long freq, long *
}
}
- DPRINTK ("Best possible values for given frequency:\n");
- DPRINTK (" best: %ld kHz nom: %ld den: %ld div: %
ld\n",
- freq, *nom, *den, *div);
+ DPRINTK("Best possible values for given frequency:\n");
+ DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %
ld\n",
+ freq, *nom, *den, *div);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/*
-----------------------------------------------------------------
--------
*
* debugging functions
@@ -3145,21 +3326,20 @@ static void bestclock (long freq, long *
*/
static
-void cirrusfb_dbg_print_byte (const char *name, unsigned char
val)
+void cirrusfb_dbg_print_byte(const char *name, unsigned char
val)
{
- DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
- name, val,
- val & 0x80 ? '1' : '0',
- val & 0x40 ? '1' : '0',
- val & 0x20 ? '1' : '0',
- val & 0x10 ? '1' : '0',
- val & 0x08 ? '1' : '0',
- val & 0x04 ? '1' : '0',
- val & 0x02 ? '1' : '0',
- val & 0x01 ? '1' : '0');
+ DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
+ name, val,
+ val & 0x80 ? '1' : '0',
+ val & 0x40 ? '1' : '0',
+ val & 0x20 ? '1' : '0',
+ val & 0x10 ? '1' : '0',
+ val & 0x08 ? '1' : '0',
+ val & 0x04 ? '1' : '0',
+ val & 0x02 ? '1' : '0',
+ val & 0x01 ? '1' : '0');
}
-
/**
* cirrusfb_dbg_print_regs
* @base: If using newmmio, the newmmio base address, otherwise
%NULL
@@ -3172,25 +3352,26 @@ void cirrusfb_dbg_print_byte (const char
*/
static
-void cirrusfb_dbg_print_regs (caddr_t regbase,
cirrusfb_dbg_reg_class_t reg_class,...)
+void cirrusfb_dbg_print_regs(caddr_t regbase,
+ cirrusfb_dbg_reg_class_t reg_class, ...)
{
va_list list;
unsigned char val = 0;
unsigned reg;
char *name;
- va_start (list, reg_class);
+ va_start(list, reg_class);
- name = va_arg (list, char *);
+ name = va_arg(list, char *);
while (name != NULL) {
- reg = va_arg (list, int);
+ reg = va_arg(list, int);
switch (reg_class) {
case CRT:
- val = vga_rcrt (regbase, (unsigned char) reg);
+ val = vga_rcrt(regbase, (unsigned char) reg);
break;
case SEQ:
- val = vga_rseq (regbase, (unsigned char) reg);
+ val = vga_rseq(regbase, (unsigned char) reg);
break;
default:
/* should never occur */
@@ -3198,15 +3379,14 @@ void cirrusfb_dbg_print_regs (caddr_t re
break;
}
- cirrusfb_dbg_print_byte (name, val);
+ cirrusfb_dbg_print_byte(name, val);
- name = va_arg (list, char *);
+ name = va_arg(list, char *);
}
- va_end (list);
+ va_end(list);
}
-
/**
* cirrusfb_dump
* @cirrusfbinfo:
@@ -3214,13 +3394,11 @@ void cirrusfb_dbg_print_regs (caddr_t re
* DESCRIPTION:
*/
-static
-void cirrusfb_dump (void)
+static void cirrusfb_dump(void)
{
- cirrusfb_dbg_reg_dump (NULL);
+ cirrusfb_dbg_reg_dump(NULL);
}
-
/**
* cirrusfb_dbg_reg_dump
* @base: If using newmmio, the newmmio base address, otherwise
%NULL
@@ -3232,11 +3410,11 @@ void cirrusfb_dump (void)
*/
static
-void cirrusfb_dbg_reg_dump (caddr_t regbase)
+void cirrusfb_dbg_reg_dump(caddr_t regbase)
{
- DPRINTK ("CIRRUSFB VGA CRTC register dump:\n");
+ DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
- cirrusfb_dbg_print_regs (regbase, CRT,
+ cirrusfb_dbg_print_regs(regbase, CRT,
"CR00", 0x00,
"CR01", 0x01,
"CR02", 0x02,
@@ -3286,11 +3464,11 @@ void cirrusfb_dbg_reg_dump (caddr_t regb
"CR3F", 0x3F,
NULL);
- DPRINTK ("\n");
+ DPRINTK("\n");
- DPRINTK ("CIRRUSFB VGA SEQ register dump:\n");
+ DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
- cirrusfb_dbg_print_regs (regbase, SEQ,
+ cirrusfb_dbg_print_regs(regbase, SEQ,
"SR00", 0x00,
"SR01", 0x01,
"SR02", 0x02,
@@ -3319,7 +3497,7 @@ void cirrusfb_dbg_reg_dump (caddr_t regb
"SR1F", 0x1F,
NULL);
- DPRINTK ("\n");
+ DPRINTK("\n");
}
#endif /* CIRRUSFB_DEBUG */
----------------------------------------------------
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[-- Attachment #2: cirrus-cleanup.diff --]
[-- Type: application/octet-stream, Size: 115130 bytes --]
From: Krzysztof Helt <krzysztof.h1@wp.pl>
This patch fixes over 850 errors and warnings pointed
out by the checkpatch.pl script.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
---
I run the checkpatch.pl script on the whole drivers/video
directory. The most errors are in drivers which share code
with X11 (sis, nvidia). The cirrus driver had the most errors
as a non-X11 driver.
--- linux-2.6.23.old/drivers/video/cirrusfb.c 2007-07-09 01:32:16.000000000 +0200
+++ linux-2.6.23/drivers/video/cirrusfb.c 2007-08-16 19:43:03.000000000 +0200
@@ -59,7 +59,7 @@
#endif
#ifdef CONFIG_PPC_PREP
#include <asm/machdep.h>
-#define isPReP (machine_is(prep))
+#define isPReP(machine_is(prep))
#else
#define isPReP 0
#endif
@@ -67,7 +67,6 @@
#include "video/vga.h"
#include "video/cirrus.h"
-
/*****************************************************************
*
* debugging and utility macros
@@ -82,7 +81,8 @@
/* debug output */
#ifdef CIRRUSFB_DEBUG
-#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
+#define DPRINTK(fmt, args...) \
+ printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif
@@ -90,20 +90,19 @@
/* debugging assertions */
#ifndef CIRRUSFB_NDEBUG
#define assert(expr) \
- if(!(expr)) { \
- printk( "Assertion failed! %s,%s,%s,line=%d\n",\
- #expr,__FILE__,__FUNCTION__,__LINE__); \
- }
+ if (!(expr)) { \
+ printk("Assertion failed! %s,%s,%s,line=%d\n", \
+ #expr, __FILE__, __FUNCTION__, __LINE__); \
+ }
#else
#define assert(expr)
#endif
-#define MB_ (1024*1024)
+#define MB_ (1024 * 1024)
#define KB_ (1024)
#define MAX_NUM_BOARDS 7
-
/*****************************************************************
*
* chipset information
@@ -123,7 +122,6 @@ typedef enum {
BT_LAGUNA, /* GD546x */
} cirrusfb_board_t;
-
/*
* per-board-type information, used for enumerating and abstracting
* chip-specific information
@@ -139,7 +137,8 @@ static const struct cirrusfb_board_info_
/* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
bool init_sr07 : 1; /* init SR07 during init_vgachip() */
bool init_sr1f : 1; /* write SR1F during init_vgachip() */
- bool scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
+ /* construct bit 19 of screen start address */
+ bool scrn_start_bit19 : 1;
/* initial SR07 value, then for each mode */
unsigned char sr07;
@@ -261,30 +260,28 @@ static const struct cirrusfb_board_info_
}
};
-
#ifdef CONFIG_PCI
#define CHIP(id, btype) \
{ PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
static struct pci_device_id cirrusfb_pci_table[] = {
- CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is same id */
- CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ),
- CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso likely */
- CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is 5446 */
- CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */
- CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */
- CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/
+ CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
+ CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
+ CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
+ CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
#undef CHIP
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
static const struct zorro_device_id cirrusfb_zorro_table[] = {
{
@@ -294,7 +291,7 @@ static const struct zorro_device_id cirr
.id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
.driver_data = BT_PICCOLO,
}, {
- .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
+ .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
.driver_data = BT_PICASSO,
}, {
.id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
@@ -333,7 +330,6 @@ static const struct {
};
#endif /* CONFIG_ZORRO */
-
struct cirrusfb_regs {
__u32 line_length; /* in BYTES! */
__u32 visual;
@@ -364,17 +360,12 @@ struct cirrusfb_regs {
long VertBlankEnd;
};
-
-
#ifdef CIRRUSFB_DEBUG
typedef enum {
- CRT,
- SEQ
+ CRT,
+ SEQ
} cirrusfb_dbg_reg_class_t;
-#endif /* CIRRUSFB_DEBUG */
-
-
-
+#endif /* CIRRUSFB_DEBUG */
/* info about board */
struct cirrusfb_info {
@@ -405,9 +396,8 @@ struct cirrusfb_info {
void (*unmap)(struct cirrusfb_info *cinfo);
};
-
static unsigned cirrusfb_def_mode = 1;
-static int noaccel = 0;
+static int noaccel;
/*
* Predefined Video Modes
@@ -441,7 +431,7 @@ static const struct {
.lower_margin = 8,
.hsync_len = 96,
.vsync_len = 4,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
}
}, {
@@ -502,27 +492,29 @@ static const struct {
/****************************************************************************/
/**** BEGIN PROTOTYPES ******************************************************/
-
/*--- Interface used by the world ------------------------------------------*/
-static int cirrusfb_init (void);
+static int cirrusfb_init(void);
#ifndef MODULE
-static int cirrusfb_setup (char *options);
+static int cirrusfb_setup(char *options);
#endif
-static int cirrusfb_open (struct fb_info *info, int user);
-static int cirrusfb_release (struct fb_info *info, int user);
-static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info);
-static int cirrusfb_check_var (struct fb_var_screeninfo *var,
- struct fb_info *info);
-static int cirrusfb_set_par (struct fb_info *info);
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
- struct fb_info *info);
-static int cirrusfb_blank (int blank_mode, struct fb_info *info);
-static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region);
-static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
-static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image);
+static int cirrusfb_open(struct fb_info *info, int user);
+static int cirrusfb_release(struct fb_info *info, int user);
+static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info);
+static int cirrusfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+static int cirrusfb_set_par(struct fb_info *info);
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+static int cirrusfb_blank(int blank_mode, struct fb_info *info);
+static void cirrusfb_fillrect(struct fb_info *info,
+ const struct fb_fillrect *region);
+static void cirrusfb_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area);
+static void cirrusfb_imageblit(struct fb_info *info,
+ const struct fb_image *image);
/* function table of the above functions */
static struct fb_ops cirrusfb_ops = {
@@ -540,68 +532,68 @@ static struct fb_ops cirrusfb_ops = {
};
/*--- Hardware Specific Routines -------------------------------------------*/
-static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
+static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
struct cirrusfb_regs *regs,
const struct fb_info *info);
/*--- Internal routines ----------------------------------------------------*/
-static void init_vgachip (struct cirrusfb_info *cinfo);
-static void switch_monitor (struct cirrusfb_info *cinfo, int on);
-static void WGen (const struct cirrusfb_info *cinfo,
- int regnum, unsigned char val);
-static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum);
-static void AttrOn (const struct cirrusfb_info *cinfo);
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val);
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char val);
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val);
-static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
- unsigned char green,
- unsigned char blue);
+static void init_vgachip(struct cirrusfb_info *cinfo);
+static void switch_monitor(struct cirrusfb_info *cinfo, int on);
+static void WGen(const struct cirrusfb_info *cinfo,
+ int regnum, unsigned char val);
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
+static void AttrOn(const struct cirrusfb_info *cinfo);
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
+static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
+ unsigned char red, unsigned char green, unsigned char blue);
#if 0
-static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
- unsigned char *green,
- unsigned char *blue);
-#endif
-static void cirrusfb_WaitBLT (u8 __iomem *regbase);
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
- u_short curx, u_short cury,
- u_short destx, u_short desty,
- u_short width, u_short height,
- u_short line_length);
-static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
- u_short x, u_short y,
- u_short width, u_short height,
- u_char color, u_short line_length);
-
-static void bestclock (long freq, long *best,
- long *nom, long *den,
- long *div, long maxfreq);
+static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
+ unsigned char *red, unsigned char *green,
+ unsigned char *blue);
+#endif
+static void cirrusfb_WaitBLT(u8 __iomem *regbase);
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
+ u_short curx, u_short cury,
+ u_short destx, u_short desty,
+ u_short width, u_short height,
+ u_short line_length);
+static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
+ u_short x, u_short y,
+ u_short width, u_short height,
+ u_char color, u_short line_length);
+
+static void bestclock(long freq, long *best,
+ long *nom, long *den,
+ long *div, long maxfreq);
#ifdef CIRRUSFB_DEBUG
-static void cirrusfb_dump (void);
-static void cirrusfb_dbg_reg_dump (caddr_t regbase);
-static void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...);
-static void cirrusfb_dbg_print_byte (const char *name, unsigned char val);
+static void cirrusfb_dump(void);
+static void cirrusfb_dbg_reg_dump(caddr_t regbase);
+static void cirrusfb_dbg_print_regs(caddr_t regbase,
+ cirrusfb_dbg_reg_class_t reg_class, ...);
+static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
#endif /* CIRRUSFB_DEBUG */
/*** END PROTOTYPES ********************************************************/
/*****************************************************************************/
/*** BEGIN Interface Used by the World ***************************************/
-static int opencount = 0;
+static int opencount;
/*--- Open /dev/fbx ---------------------------------------------------------*/
-static int cirrusfb_open (struct fb_info *info, int user)
+static int cirrusfb_open(struct fb_info *info, int user)
{
if (opencount++ == 0)
- switch_monitor (info->par, 1);
+ switch_monitor(info->par, 1);
return 0;
}
/*--- Close /dev/fbx --------------------------------------------------------*/
-static int cirrusfb_release (struct fb_info *info, int user)
+static int cirrusfb_release(struct fb_info *info, int user)
{
if (--opencount == 0)
- switch_monitor (info->par, 0);
+ switch_monitor(info->par, 0);
return 0;
}
@@ -610,11 +602,11 @@ static int cirrusfb_release (struct fb_i
/**** BEGIN Hardware specific Routines **************************************/
/* Get a good MCLK value */
-static long cirrusfb_get_mclk (long freq, int bpp, long *div)
+static long cirrusfb_get_mclk(long freq, int bpp, long *div)
{
long mclk;
- assert (div != NULL);
+ assert(div != NULL);
/* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
* Assume a 64-bit data path for now. The formula is:
@@ -624,23 +616,23 @@ static long cirrusfb_get_mclk (long freq
mclk = (mclk * 12) / 10;
if (mclk < 50000)
mclk = 50000;
- DPRINTK ("Use MCLK of %ld kHz\n", mclk);
+ DPRINTK("Use MCLK of %ld kHz\n", mclk);
/* Calculate value for SR1F. Multiply by 2 so we can round up. */
mclk = ((mclk * 16) / 14318);
mclk = (mclk + 1) / 2;
- DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk);
+ DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
/* Determine if we should use MCLK instead of VCLK, and if so, what we
* should divide it by to get VCLK */
switch (freq) {
case 24751 ... 25249:
*div = 2;
- DPRINTK ("Using VCLK = MCLK/2\n");
+ DPRINTK("Using VCLK = MCLK/2\n");
break;
case 49501 ... 50499:
*div = 1;
- DPRINTK ("Using VCLK = MCLK\n");
+ DPRINTK("Using VCLK = MCLK\n");
break;
default:
*div = 0;
@@ -691,37 +683,42 @@ static int cirrusfb_check_var(struct fb_
den = 1;
break; /* 4 bytes per pixel */
default:
- printk ("cirrusfb: mode %dx%dx%d rejected...color depth not supported.\n",
+ printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
+ "color depth not supported.\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("EXIT - EINVAL error\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
if (var->xres * nom / den * var->yres > cinfo->size) {
- printk ("cirrusfb: mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
+ printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
+ "resolution too high to fit into video memory!\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("EXIT - EINVAL error\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
/* use highest possible virtual resolution */
if (var->xres_virtual == -1 &&
var->yres_virtual == -1) {
- printk ("cirrusfb: using maximum available virtual resolution\n");
+ printk(KERN_INFO
+ "cirrusfb: using maximum available virtual resolution\n");
for (i = 0; modes[i].xres != -1; i++) {
if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
break;
}
if (modes[i].xres == -1) {
- printk ("cirrusfb: could not find a virtual resolution that fits into video memory!!\n");
- DPRINTK ("EXIT - EINVAL error\n");
+ printk(KERN_ERR "cirrusfb: could not find a virtual "
+ "resolution that fits into video memory!!\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
var->xres_virtual = modes[i].xres;
var->yres_virtual = modes[i].yres;
- printk ("cirrusfb: virtual resolution set to maximum of %dx%d\n",
- var->xres_virtual, var->yres_virtual);
+ printk(KERN_INFO "cirrusfb: virtual resolution set to "
+ "maximum of %dx%d\n", var->xres_virtual,
+ var->yres_virtual);
}
if (var->xres_virtual < var->xres)
@@ -760,7 +757,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 16:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 2;
var->green.offset = -3;
var->blue.offset = 8;
@@ -775,7 +772,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 24:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 8;
var->green.offset = 16;
var->blue.offset = 24;
@@ -790,7 +787,7 @@ static int cirrusfb_check_var(struct fb_
break;
case 32:
- if(isPReP) {
+ if (isPReP) {
var->red.offset = 8;
var->green.offset = 16;
var->blue.offset = 24;
@@ -825,15 +822,16 @@ static int cirrusfb_check_var(struct fb_
yres = (yres + 1) / 2;
if (yres >= 1280) {
- printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)\n");
- DPRINTK ("EXIT - EINVAL error\n");
+ printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
+ "special treatment required! (TODO)\n");
+ DPRINTK("EXIT - EINVAL error\n");
return -EINVAL;
}
return 0;
}
-static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
+static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
struct cirrusfb_regs *regs,
const struct fb_info *info)
{
@@ -844,7 +842,7 @@ static int cirrusfb_decode_var (const st
int xres, hfront, hsync, hback;
int yres, vfront, vsync, vback;
- switch(var->bits_per_pixel) {
+ switch (var->bits_per_pixel) {
case 1:
regs->line_length = var->xres_virtual / 8;
regs->visual = FB_VISUAL_MONO10;
@@ -887,7 +885,7 @@ static int cirrusfb_decode_var (const st
/* convert from ps to kHz */
freq = 1000000000 / var->pixclock;
- DPRINTK ("desired pixclock: %ld kHz\n", freq);
+ DPRINTK("desired pixclock: %ld kHz\n", freq);
maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
regs->multiplexing = 0;
@@ -902,8 +900,9 @@ static int cirrusfb_decode_var (const st
break;
default:
- printk (KERN_WARNING "cirrusfb: ERROR: Frequency greater than maxclock (%ld kHz)\n", maxclock);
- DPRINTK ("EXIT - return -EINVAL\n");
+ printk(KERN_ERR "cirrusfb: Frequency greater "
+ "than maxclock (%ld kHz)\n", maxclock);
+ DPRINTK("EXIT - return -EINVAL\n");
return -EINVAL;
}
}
@@ -914,14 +913,16 @@ static int cirrusfb_decode_var (const st
case 16:
case 32:
if (regs->HorizRes <= 800)
- freq /= 2; /* Xbh has this type of clock for 32-bit */
+ /* Xbh has this type of clock for 32-bit */
+ freq /= 2;
break;
}
#endif
- bestclock (freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
- maxclock);
- regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel, ®s->divMCLK);
+ bestclock(freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
+ maxclock);
+ regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
+ ®s->divMCLK);
xres = var->xres;
hfront = var->right_margin;
@@ -948,7 +949,8 @@ static int cirrusfb_decode_var (const st
regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
regs->HorizDispEnd = xres / 8 - 1;
regs->HorizBlankStart = xres / 8;
- regs->HorizBlankEnd = regs->HorizTotal + 5; /* does not count with "-5" */
+ /* does not count with "-5" */
+ regs->HorizBlankEnd = regs->HorizTotal + 5;
regs->HorizSyncStart = (xres + hfront) / 8 + 1;
regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
@@ -976,23 +978,23 @@ static int cirrusfb_decode_var (const st
return 0;
}
-
-static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int div)
+static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
+ int div)
{
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
if (div == 2) {
/* VCLK = MCLK/2 */
- unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
- vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1);
- vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
+ unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
+ vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
} else if (div == 1) {
/* VCLK = MCLK */
- unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
- vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1);
- vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
+ unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
+ vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
} else {
- vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
}
}
@@ -1001,7 +1003,7 @@ static void cirrusfb_set_mclk (const str
actually writes the values for a new video mode into the hardware,
**************************************************************************/
-static int cirrusfb_set_par_foo (struct fb_info *info)
+static int cirrusfb_set_par_foo(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_var_screeninfo *var = &info->var;
@@ -1011,15 +1013,15 @@ static int cirrusfb_set_par_foo (struct
int offset = 0, err;
const struct cirrusfb_board_info_rec *bi;
- DPRINTK ("ENTER\n");
- DPRINTK ("Requested mode: %dx%dx%d\n",
+ DPRINTK("ENTER\n");
+ DPRINTK("Requested mode: %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
- DPRINTK ("pixclock: %d\n", var->pixclock);
+ DPRINTK("pixclock: %d\n", var->pixclock);
- init_vgachip (cinfo);
+ init_vgachip(cinfo);
err = cirrusfb_decode_var(var, ®s, info);
- if(err) {
+ if (err) {
/* should never happen */
DPRINTK("mode change aborted. invalid var.\n");
return -EINVAL;
@@ -1027,34 +1029,35 @@ static int cirrusfb_set_par_foo (struct
bi = &cirrusfb_board_info[cinfo->btype];
-
/* unlock register VGA_CRTC_H_TOTAL..CRT7 */
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
/* if debugging is enabled, all parameters get output before writing */
- DPRINTK ("CRT0: %ld\n", regs.HorizTotal);
- vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
+ DPRINTK("CRT0: %ld\n", regs.HorizTotal);
+ vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
- DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd);
- vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
+ DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
+ vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
- DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart);
- vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
+ DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
+ vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
- DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32); /* + 128: Compatible read */
- vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.HorizBlankEnd % 32));
+ /* + 128: Compatible read */
+ DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
+ vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
+ 128 + (regs.HorizBlankEnd % 32));
- DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart);
- vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
+ DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
+ vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
tmp = regs.HorizSyncEnd % 32;
if (regs.HorizBlankEnd & 32)
tmp += 128;
- DPRINTK ("CRT5: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp);
+ DPRINTK("CRT5: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
- DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
+ DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
tmp = 16; /* LineCompare bit #9 */
if (regs.VertTotal & 256)
@@ -1071,34 +1074,34 @@ static int cirrusfb_set_par_foo (struct
tmp |= 64;
if (regs.VertSyncStart & 512)
tmp |= 128;
- DPRINTK ("CRT7: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp);
+ DPRINTK("CRT7: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
tmp = 0x40; /* LineCompare bit #8 */
if (regs.VertBlankStart & 512)
tmp |= 0x20;
if (var->vmode & FB_VMODE_DOUBLE)
tmp |= 0x80;
- DPRINTK ("CRT9: %d\n", tmp);
- vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp);
+ DPRINTK("CRT9: %d\n", tmp);
+ vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
- DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.VertSyncStart & 0xff));
+ DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
- DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
- vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd % 16 + 64 + 32));
+ DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
+ vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
- DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd & 0xff));
+ DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
- DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.VertBlankStart & 0xff));
+ DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
- DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
- vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd & 0xff));
+ DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
- DPRINTK ("CRT18: 0xff\n");
- vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff);
+ DPRINTK("CRT18: 0xff\n");
+ vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
tmp = 0;
if (var->vmode & FB_VMODE_INTERLACED)
@@ -1112,57 +1115,63 @@ static int cirrusfb_set_par_foo (struct
if (regs.VertBlankEnd & 512)
tmp |= 128;
- DPRINTK ("CRT1a: %d\n", tmp);
- vga_wcrt (regbase, CL_CRT1A, tmp);
+ DPRINTK("CRT1a: %d\n", tmp);
+ vga_wcrt(regbase, CL_CRT1A, tmp);
/* set VCLK0 */
/* hardware RefClock: 14.31818 MHz */
/* formula: VClk = (OSC * N) / (D * (1+P)) */
/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
- vga_wseq (regbase, CL_SEQRB, regs.nom);
+ vga_wseq(regbase, CL_SEQRB, regs.nom);
tmp = regs.den << 1;
if (regs.div != 0)
tmp |= 1;
+ /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
if ((cinfo->btype == BT_SD64) ||
(cinfo->btype == BT_ALPINE) ||
(cinfo->btype == BT_GD5480))
- tmp |= 0x80; /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
+ tmp |= 0x80;
- DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp);
- vga_wseq (regbase, CL_SEQR1B, tmp);
+ DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
+ vga_wseq(regbase, CL_SEQR1B, tmp);
if (regs.VertRes >= 1024)
/* 1280x1024 */
- vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7);
+ vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
else
/* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
* address wrap, no compat. */
- vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3);
+ vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
-/* HAEH? vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20); * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
+/* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
+ * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
/* don't know if it would hurt to also program this if no interlaced */
/* mode is used, but I feel better this way.. :-) */
if (var->vmode & FB_VMODE_INTERLACED)
- vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
+ vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
else
- vga_wcrt (regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
+ vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
- vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0);
+ vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
/* adjust horizontal/vertical sync type (low/high) */
- tmp = 0x03; /* enable display memory & CRTC I/O address for color mode */
+ /* enable display memory & CRTC I/O address for color mode */
+ tmp = 0x03;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
tmp |= 0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
tmp |= 0x80;
- WGen (cinfo, VGA_MIS_W, tmp);
+ WGen(cinfo, VGA_MIS_W, tmp);
- vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0); /* Screen A Preset Row-Scan register */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0); /* text cursor on and start line */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31); /* text cursor end line */
+ /* Screen A Preset Row-Scan register */
+ vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
+ /* text cursor on and start line */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
+ /* text cursor end line */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
/******************************************************
*
@@ -1172,8 +1181,8 @@ static int cirrusfb_set_par_foo (struct
/* programming for different color depths */
if (var->bits_per_pixel == 1) {
- DPRINTK ("cirrusfb: preparing for 1 bit deep display\n");
- vga_wgfx (regbase, VGA_GFX_MODE, 0); /* mode register */
+ DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
+ vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
/* SR07 */
switch (cinfo->btype) {
@@ -1184,71 +1193,85 @@ static int cirrusfb_set_par_foo (struct
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
- DPRINTK (" (for GD54xx)\n");
- vga_wseq (regbase, CL_SEQR7,
+ DPRINTK(" (for GD54xx)\n");
+ vga_wseq(regbase, CL_SEQR7,
regs.multiplexing ?
bi->sr07_1bpp_mux : bi->sr07_1bpp);
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
/* Extended Sequencer Mode */
switch (cinfo->btype) {
case BT_SD64:
- /* setting the SEQRF on SD64 is not necessary (only during init) */
- DPRINTK ("(for SD64)\n");
- vga_wseq (regbase, CL_SEQR1F, 0x1a); /* MCLK select */
+ /* setting the SEQRF on SD64 is not necessary
+ * (only during init)
+ */
+ DPRINTK("(for SD64)\n");
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1a);
break;
case BT_PICCOLO:
- DPRINTK ("(for Piccolo)\n");
-/* ### ueberall 0x22? */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
+ DPRINTK("(for Piccolo)\n");
+ /* ### ueberall 0x22? */
+ /* ##vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
- DPRINTK ("(for Picasso)\n");
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 22 MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xd0); /* ## vorher d0 avoid FIFO underruns..? */
+ DPRINTK("(for Picasso)\n");
+ /* ##vorher 22 MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* ## vorher d0 avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xd0);
break;
case BT_SPECTRUM:
- DPRINTK ("(for Spectrum)\n");
-/* ### ueberall 0x22? */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ##vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* evtl d0? avoid FIFO underruns..? */
+ DPRINTK("(for Spectrum)\n");
+ /* ### ueberall 0x22? */
+ /* ##vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* evtl d0? avoid FIFO underruns..? */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
case BT_LAGUNA:
- DPRINTK (" (for GD54xx)\n");
+ DPRINTK(" (for GD54xx)\n");
/* do nothing */
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- WGen (cinfo, VGA_PEL_MSK, 0x01); /* pixel mask: pass-through for first plane */
+ /* pixel mask: pass-through for first plane */
+ WGen(cinfo, VGA_PEL_MSK, 0x01);
if (regs.multiplexing)
- WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
+ /* hidden dac reg: 1280x1024 */
+ WHDR(cinfo, 0x4a);
else
- WHDR (cinfo, 0); /* hidden dac: nothing */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06); /* memory mode: odd/even, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01); /* plane mask: only write to first plane */
+ /* hidden dac: nothing */
+ WHDR(cinfo, 0);
+ /* memory mode: odd/even, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
+ /* plane mask: only write to first plane */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
offset = var->xres_virtual / 16;
}
@@ -1259,7 +1282,7 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 8) {
- DPRINTK ("cirrusfb: preparing for 8 bit deep display\n");
+ DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
switch (cinfo->btype) {
case BT_SD64:
case BT_PICCOLO:
@@ -1268,75 +1291,89 @@ static int cirrusfb_set_par_foo (struct
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
- DPRINTK (" (for GD54xx)\n");
- vga_wseq (regbase, CL_SEQR7,
+ DPRINTK(" (for GD54xx)\n");
+ vga_wseq(regbase, CL_SEQR7,
regs.multiplexing ?
bi->sr07_8bpp_mux : bi->sr07_8bpp);
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) | 0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) | 0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR1F, 0x1d); /* MCLK select */
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1d);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* ### vorher 1c MCLK select */
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
+ /* ### vorher 1c MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO4:
#ifdef CONFIG_ZORRO
- vga_wseq (regbase, CL_SEQRF, 0xb8); /* ### INCOMPLETE!! */
+ /* ### INCOMPLETE!! */
+ vga_wseq(regbase, CL_SEQRF, 0xb8);
#endif
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ DPRINTK(" (for GD543x)\n");
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
/* We already set SRF and SR1F */
break;
case BT_GD5480:
case BT_LAGUNA:
- DPRINTK (" (for GD54xx)\n");
+ DPRINTK(" (for GD54xx)\n");
/* do nothing */
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
if (regs.multiplexing)
- WHDR (cinfo, 0x4a); /* hidden dac reg: 1280x1024 */
+ /* hidden dac reg: 1280x1024 */
+ WHDR(cinfo, 0x4a);
else
- WHDR (cinfo, 0); /* hidden dac: nothing */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
+ /* hidden dac: nothing */
+ WHDR(cinfo, 0);
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 8;
}
@@ -1347,72 +1384,84 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 16) {
- DPRINTK ("cirrusfb: preparing for 16 bit deep display\n");
+ DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR7, 0xf7); /* Extended Sequencer Mode: 256c col. mode */
- vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
+ /* Extended Sequencer Mode: 256c col. mode */
+ vga_wseq(regbase, CL_SEQR7, 0xf7);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1e);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR7, 0x87);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x87);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR7, 0x27);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x27);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR7, 0x87);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x87);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO4:
- vga_wseq (regbase, CL_SEQR7, 0x27);
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+ vga_wseq(regbase, CL_SEQR7, 0x27);
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
+ DPRINTK(" (for GD543x)\n");
if (regs.HorizRes >= 1024)
- vga_wseq (regbase, CL_SEQR7, 0xa7);
+ vga_wseq(regbase, CL_SEQR7, 0xa7);
else
- vga_wseq (regbase, CL_SEQR7, 0xa3);
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ vga_wseq(regbase, CL_SEQR7, 0xa3);
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
break;
case BT_GD5480:
- DPRINTK (" (for GD5480)\n");
- vga_wseq (regbase, CL_SEQR7, 0x17);
+ DPRINTK(" (for GD5480)\n");
+ vga_wseq(regbase, CL_SEQR7, 0x17);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "CIRRUSFB: unknown Board\n");
+ printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
#ifdef CONFIG_PCI
- WHDR (cinfo, 0xc0); /* Copy Xbh */
+ WHDR(cinfo, 0xc0); /* Copy Xbh */
#elif defined(CONFIG_ZORRO)
/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
- WHDR (cinfo, 0xa0); /* hidden dac reg: nothing special */
+ WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
#endif
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 4;
}
@@ -1423,64 +1472,77 @@ static int cirrusfb_set_par_foo (struct
*/
else if (var->bits_per_pixel == 32) {
- DPRINTK ("cirrusfb: preparing for 24/32 bit deep display\n");
+ DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
switch (cinfo->btype) {
case BT_SD64:
- vga_wseq (regbase, CL_SEQR7, 0xf9); /* Extended Sequencer Mode: 256c col. mode */
- vga_wseq (regbase, CL_SEQR1F, 0x1e); /* MCLK select */
+ /* Extended Sequencer Mode: 256c col. mode */
+ vga_wseq(regbase, CL_SEQR7, 0xf9);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x1e);
break;
case BT_PICCOLO:
- vga_wseq (regbase, CL_SEQR7, 0x85);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x85);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO:
- vga_wseq (regbase, CL_SEQR7, 0x25);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x25);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_SPECTRUM:
- vga_wseq (regbase, CL_SEQR7, 0x85);
- vga_wseq (regbase, CL_SEQRF, 0xb0); /* Fast Page-Mode writes */
- vga_wseq (regbase, CL_SEQR1F, 0x22); /* MCLK select */
+ vga_wseq(regbase, CL_SEQR7, 0x85);
+ /* Fast Page-Mode writes */
+ vga_wseq(regbase, CL_SEQRF, 0xb0);
+ /* MCLK select */
+ vga_wseq(regbase, CL_SEQR1F, 0x22);
break;
case BT_PICASSO4:
- vga_wseq (regbase, CL_SEQR7, 0x25);
-/* vga_wseq (regbase, CL_SEQR1F, 0x1c); */
+ vga_wseq(regbase, CL_SEQR7, 0x25);
+/* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
break;
case BT_ALPINE:
- DPRINTK (" (for GD543x)\n");
- vga_wseq (regbase, CL_SEQR7, 0xa9);
- cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+ DPRINTK(" (for GD543x)\n");
+ vga_wseq(regbase, CL_SEQR7, 0xa9);
+ cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
break;
case BT_GD5480:
- DPRINTK (" (for GD5480)\n");
- vga_wseq (regbase, CL_SEQR7, 0x19);
+ DPRINTK(" (for GD5480)\n");
+ vga_wseq(regbase, CL_SEQR7, 0x19);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
- DPRINTK (" (for GD546x)\n");
- vga_wseq (regbase, CL_SEQR7,
- vga_rseq (regbase, CL_SEQR7) & ~0x01);
+ DPRINTK(" (for GD546x)\n");
+ vga_wseq(regbase, CL_SEQR7,
+ vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
- printk (KERN_WARNING "cirrusfb: unknown Board\n");
+ printk(KERN_WARNING "cirrusfb: unknown Board\n");
break;
}
- vga_wgfx (regbase, VGA_GFX_MODE, 64); /* mode register: 256 color mode */
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* pixel mask: pass-through all planes */
- WHDR (cinfo, 0xc5); /* hidden dac reg: 8-8-8 mode (24 or 32) */
- vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a); /* memory mode: chain4, ext. memory */
- vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: enable writing to all 4 planes */
+ /* mode register: 256 color mode */
+ vga_wgfx(regbase, VGA_GFX_MODE, 64);
+ /* pixel mask: pass-through all planes */
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
+ /* hidden dac reg: 8-8-8 mode (24 or 32) */
+ WHDR(cinfo, 0xc5);
+ /* memory mode: chain4, ext. memory */
+ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
+ /* plane mask: enable writing to all 4 planes */
+ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
offset = var->xres_virtual / 4;
}
@@ -1490,48 +1552,67 @@ static int cirrusfb_set_par_foo (struct
*
*/
- else {
- printk (KERN_ERR "cirrusfb: What's this?? requested color depth == %d.\n",
+ else
+ printk(KERN_ERR "cirrusfb: What's this?? "
+ " requested color depth == %d.\n",
var->bits_per_pixel);
- }
- vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff);
+ vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
tmp = 0x22;
if (offset & 0x100)
tmp |= 0x10; /* offset overflow bit */
- vga_wcrt (regbase, CL_CRT1B, tmp); /* screen start addr #16-18, fastpagemode cycles */
+ /* screen start addr #16-18, fastpagemode cycles */
+ vga_wcrt(regbase, CL_CRT1B, tmp);
if (cinfo->btype == BT_SD64 ||
cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE ||
cinfo->btype == BT_GD5480)
- vga_wcrt (regbase, CL_CRT1D, 0x00); /* screen start address bit 19 */
+ /* screen start address bit 19 */
+ vga_wcrt(regbase, CL_CRT1D, 0x00);
- vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0); /* text cursor location high */
- vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0); /* text cursor location low */
- vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0); /* underline row scanline = at very bottom */
-
- vga_wattr (regbase, VGA_ATC_MODE, 1); /* controller mode */
- vga_wattr (regbase, VGA_ATC_OVERSCAN, 0); /* overscan (border) color */
- vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15); /* color plane enable */
- vga_wattr (regbase, CL_AR33, 0); /* pixel panning */
- vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0); /* color select */
+ /* text cursor location high */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
+ /* text cursor location low */
+ vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
+ /* underline row scanline = at very bottom */
+ vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
+
+ /* controller mode */
+ vga_wattr(regbase, VGA_ATC_MODE, 1);
+ /* overscan (border) color */
+ vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
+ /* color plane enable */
+ vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
+ /* pixel panning */
+ vga_wattr(regbase, CL_AR33, 0);
+ /* color select */
+ vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
/* [ EGS: SetOffset(); ] */
/* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
- AttrOn (cinfo);
+ AttrOn(cinfo);
- vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0); /* set/reset register */
- vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0); /* set/reset enable */
- vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0); /* color compare */
- vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0); /* data rotate */
- vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0); /* read map select */
- vga_wgfx (regbase, VGA_GFX_MISC, 1); /* miscellaneous register */
- vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15); /* color don't care */
- vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255); /* bit mask */
+ /* set/reset register */
+ vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
+ /* set/reset enable */
+ vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
+ /* color compare */
+ vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
+ /* data rotate */
+ vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
+ /* read map select */
+ vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
+ /* miscellaneous register */
+ vga_wgfx(regbase, VGA_GFX_MISC, 1);
+ /* color don't care */
+ vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
+ /* bit mask */
+ vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
- vga_wseq (regbase, CL_SEQR12, 0x0); /* graphics cursor attributes: nothing special */
+ /* graphics cursor attributes: nothing special */
+ vga_wseq(regbase, CL_SEQR12, 0x0);
/* finally, turn on everything - turn off "FullBandwidth" bit */
/* also, set "DotClock%2" bit where requested */
@@ -1542,8 +1623,8 @@ static int cirrusfb_set_par_foo (struct
tmp |= 0x08;
*/
- vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp);
- DPRINTK ("CL_SEQR1: %d\n", tmp);
+ vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
+ DPRINTK("CL_SEQR1: %d\n", tmp);
cinfo->currentmode = regs;
info->fix.type = regs.type;
@@ -1551,27 +1632,27 @@ static int cirrusfb_set_par_foo (struct
info->fix.line_length = regs.line_length;
/* pan to requested offset */
- cirrusfb_pan_display (var, info);
+ cirrusfb_pan_display(var, info);
#ifdef CIRRUSFB_DEBUG
- cirrusfb_dump ();
+ cirrusfb_dump();
#endif
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return 0;
}
/* for some reason incomprehensible to me, cirrusfb requires that you write
* the registers twice for the settings to take..grr. -dte */
-static int cirrusfb_set_par (struct fb_info *info)
+static int cirrusfb_set_par(struct fb_info *info)
{
- cirrusfb_set_par_foo (info);
- return cirrusfb_set_par_foo (info);
+ cirrusfb_set_par_foo(info);
+ return cirrusfb_set_par_foo(info);
}
-static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info)
+static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
@@ -1584,23 +1665,23 @@ static int cirrusfb_setcolreg (unsigned
green >>= (16 - info->var.green.length);
blue >>= (16 - info->var.blue.length);
- if (regno>=16)
+ if (regno >= 16)
return 1;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
switch (info->var.bits_per_pixel) {
- case 8:
- cinfo->pseudo_palette[regno] = v;
- break;
- case 16:
- cinfo->pseudo_palette[regno] = v;
- break;
- case 24:
- case 32:
- cinfo->pseudo_palette[regno] = v;
- break;
+ case 8:
+ cinfo->pseudo_palette[regno] = v;
+ break;
+ case 16:
+ cinfo->pseudo_palette[regno] = v;
+ break;
+ case 24:
+ case 32:
+ cinfo->pseudo_palette[regno] = v;
+ break;
}
return 0;
}
@@ -1609,9 +1690,8 @@ static int cirrusfb_setcolreg (unsigned
cinfo->palette[regno].green = green;
cinfo->palette[regno].blue = blue;
- if (info->var.bits_per_pixel == 8) {
- WClut (cinfo, regno, red >> 10, green >> 10, blue >> 10);
- }
+ if (info->var.bits_per_pixel == 8)
+ WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
return 0;
@@ -1622,8 +1702,8 @@ static int cirrusfb_setcolreg (unsigned
performs display panning - provided hardware permits this
**************************************************************************/
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
- struct fb_info *info)
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
{
int xoffset = 0;
int yoffset = 0;
@@ -1631,8 +1711,8 @@ static int cirrusfb_pan_display (struct
unsigned char tmp = 0, tmp2 = 0, xpix;
struct cirrusfb_info *cinfo = info->par;
- DPRINTK ("ENTER\n");
- DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
+ DPRINTK("ENTER\n");
+ DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
/* no range checks for xoffset and yoffset, */
/* as fb_pan_display has already done this */
@@ -1655,11 +1735,13 @@ static int cirrusfb_pan_display (struct
xpix = (unsigned char) ((xoffset % 4) * 2);
}
- cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
+ cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
/* lower 8 + 8 bits of screen start address */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned char) (base & 0xff));
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned char) (base >> 8));
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
+ (unsigned char) (base & 0xff));
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
+ (unsigned char) (base >> 8));
/* construct bits 16, 17 and 18 of screen start address */
if (base & 0x10000)
@@ -1669,50 +1751,53 @@ static int cirrusfb_pan_display (struct
if (base & 0x40000)
tmp |= 0x08;
- tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp; /* 0xf2 is %11110010, exclude tmp bits */
- vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2);
+ /* 0xf2 is %11110010, exclude tmp bits */
+ tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
+ vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
/* construct bit 19 of screen start address */
if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
tmp2 = 0;
if (base & 0x80000)
tmp2 = 0x80;
- vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2);
+ vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
}
- /* write pixel panning value to AR33; this does not quite work in 8bpp */
- /* ### Piccolo..? Will this work? */
+ /* write pixel panning value to AR33; this does not quite work in 8bpp
+ *
+ * ### Piccolo..? Will this work?
+ */
if (info->var.bits_per_pixel == 1)
- vga_wattr (cinfo->regbase, CL_AR33, xpix);
+ vga_wattr(cinfo->regbase, CL_AR33, xpix);
- cirrusfb_WaitBLT (cinfo->regbase);
+ cirrusfb_WaitBLT(cinfo->regbase);
- DPRINTK ("EXIT\n");
- return (0);
+ DPRINTK("EXIT\n");
+ return 0;
}
-
-static int cirrusfb_blank (int blank_mode, struct fb_info *info)
+static int cirrusfb_blank(int blank_mode, struct fb_info *info)
{
/*
- * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
- * then the caller blanks by setting the CLUT (Color Look Up Table) to all
- * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
- * to e.g. a video mode which doesn't support it. Implements VESA suspend
- * and powerdown modes on hardware that supports disabling hsync/vsync:
- * blank_mode == 2: suspend vsync
- * blank_mode == 3: suspend hsync
- * blank_mode == 4: powerdown
+ * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
+ * then the caller blanks by setting the CLUT (Color Look Up Table)
+ * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
+ * failed due to e.g. a video mode which doesn't support it.
+ * Implements VESA suspend and powerdown modes on hardware that
+ * supports disabling hsync/vsync:
+ * blank_mode == 2: suspend vsync
+ * blank_mode == 3: suspend hsync
+ * blank_mode == 4: powerdown
*/
unsigned char val;
struct cirrusfb_info *cinfo = info->par;
int current_mode = cinfo->blank_mode;
- DPRINTK ("ENTER, blank mode = %d\n", blank_mode);
+ DPRINTK("ENTER, blank mode = %d\n", blank_mode);
if (info->state != FBINFO_STATE_RUNNING ||
current_mode == blank_mode) {
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
return 0;
}
@@ -1720,17 +1805,19 @@ static int cirrusfb_blank (int blank_mod
if (current_mode == FB_BLANK_NORMAL ||
current_mode == FB_BLANK_UNBLANK) {
/* unblank the screen */
- val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf); /* clear "FullBandwidth" bit */
+ val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
+ /* clear "FullBandwidth" bit */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
/* and undo VESA suspend trickery */
- vga_wgfx (cinfo->regbase, CL_GRE, 0x00);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
}
/* set new */
- if(blank_mode > FB_BLANK_NORMAL) {
+ if (blank_mode > FB_BLANK_NORMAL) {
/* blank the screen */
- val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20); /* set "FullBandwidth" bit */
+ val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
+ /* set "FullBandwidth" bit */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
}
switch (blank_mode) {
@@ -1738,21 +1825,21 @@ static int cirrusfb_blank (int blank_mod
case FB_BLANK_NORMAL:
break;
case FB_BLANK_VSYNC_SUSPEND:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x04);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
break;
case FB_BLANK_HSYNC_SUSPEND:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x02);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
break;
case FB_BLANK_POWERDOWN:
- vga_wgfx (cinfo->regbase, CL_GRE, 0x06);
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
break;
default:
- DPRINTK ("EXIT, returning 1\n");
+ DPRINTK("EXIT, returning 1\n");
return 1;
}
cinfo->blank_mode = blank_mode;
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
/* Let fbcon do a soft blank for us */
return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
@@ -1761,45 +1848,50 @@ static int cirrusfb_blank (int blank_mod
/****************************************************************************/
/**** BEGIN Internal Routines ***********************************************/
-static void init_vgachip (struct cirrusfb_info *cinfo)
+static void init_vgachip(struct cirrusfb_info *cinfo)
{
const struct cirrusfb_board_info_rec *bi;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
bi = &cirrusfb_board_info[cinfo->btype];
/* reset board globally */
switch (cinfo->btype) {
case BT_PICCOLO:
- WSFR (cinfo, 0x01);
- udelay (500);
- WSFR (cinfo, 0x51);
- udelay (500);
+ WSFR(cinfo, 0x01);
+ udelay(500);
+ WSFR(cinfo, 0x51);
+ udelay(500);
break;
case BT_PICASSO:
- WSFR2 (cinfo, 0xff);
- udelay (500);
+ WSFR2(cinfo, 0xff);
+ udelay(500);
break;
case BT_SD64:
case BT_SPECTRUM:
- WSFR (cinfo, 0x1f);
- udelay (500);
- WSFR (cinfo, 0x4f);
- udelay (500);
+ WSFR(cinfo, 0x1f);
+ udelay(500);
+ WSFR(cinfo, 0x4f);
+ udelay(500);
break;
case BT_PICASSO4:
- vga_wcrt (cinfo->regbase, CL_CRT51, 0x00); /* disable flickerfixer */
- mdelay (100);
- vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
- vga_wgfx (cinfo->regbase, CL_GR33, 0x00); /* put blitter into 542x compat */
- vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* mode */
+ /* disable flickerfixer */
+ vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
+ mdelay(100);
+ /* from Klaus' NetBSD driver: */
+ vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
+ /* put blitter into 542x compat */
+ vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
+ /* mode */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
break;
case BT_GD5480:
- vga_wgfx (cinfo->regbase, CL_GR2F, 0x00); /* from Klaus' NetBSD driver: */
+ /* from Klaus' NetBSD driver: */
+ vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
break;
case BT_ALPINE:
@@ -1807,153 +1899,207 @@ static void init_vgachip (struct cirrusf
break;
default:
- printk (KERN_ERR "cirrusfb: Warning: Unknown board type\n");
+ printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
break;
}
- assert (cinfo->size > 0); /* make sure RAM size set by this point */
+ assert(cinfo->size > 0); /* make sure RAM size set by this point */
/* the P4 is not fully initialized here; I rely on it having been */
/* inited under AmigaOS already, which seems to work just fine */
- /* (Klaus advised to do it this way) */
+ /* (Klaus advised to do it this way) */
if (cinfo->btype != BT_PICASSO4) {
- WGen (cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
- WGen (cinfo, CL_POS102, 0x01);
- WGen (cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
+ WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
+ WGen(cinfo, CL_POS102, 0x01);
+ WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
if (cinfo->btype != BT_SD64)
- WGen (cinfo, CL_VSSM2, 0x01);
+ WGen(cinfo, CL_VSSM2, 0x01);
- vga_wseq (cinfo->regbase, CL_SEQR0, 0x03); /* reset sequencer logic */
+ /* reset sequencer logic */
+ vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
- vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); /* FullBandwidth (video off) and 8/9 dot clock */
- WGen (cinfo, VGA_MIS_W, 0xc1); /* polarity (-/-), disable access to display memory, VGA_CRTC_START_HI base address: color */
+ /* FullBandwidth (video off) and 8/9 dot clock */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
+ /* polarity (-/-), disable access to display memory,
+ * VGA_CRTC_START_HI base address: color
+ */
+ WGen(cinfo, VGA_MIS_W, 0xc1);
-/* vga_wgfx (cinfo->regbase, CL_GRA, 0xce); "magic cookie" - doesn't make any sense to me.. */
- vga_wseq (cinfo->regbase, CL_SEQR6, 0x12); /* unlock all extension registers */
+ /* "magic cookie" - doesn't make any sense to me.. */
+/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
+ /* unlock all extension registers */
+ vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
- vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* reset blitter */
+ /* reset blitter */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
switch (cinfo->btype) {
case BT_GD5480:
- vga_wseq (cinfo->regbase, CL_SEQRF, 0x98);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
break;
case BT_ALPINE:
break;
case BT_SD64:
- vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
break;
default:
- vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f);
- vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0);
+ vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
+ vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
break;
}
}
- vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* plane mask: nothing */
- vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); /* character map select: doesn't even matter in gx mode */
- vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e); /* memory mode: chain-4, no odd/even, ext. memory */
+ /* plane mask: nothing */
+ vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
+ /* character map select: doesn't even matter in gx mode */
+ vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
+ /* memory mode: chain-4, no odd/even, ext. memory */
+ vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
/* controller-internal base address of video memory */
if (bi->init_sr07)
- vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07);
+ vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
- /* vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM control: shouldn't be necessary to write to this at all.. */
+ /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
+ /* EEPROM control: shouldn't be necessary to write to this at all.. */
- vga_wseq (cinfo->regbase, CL_SEQR10, 0x00); /* graphics cursor X position (incomplete; position gives rem. 3 bits */
- vga_wseq (cinfo->regbase, CL_SEQR11, 0x00); /* graphics cursor Y position (..."... ) */
- vga_wseq (cinfo->regbase, CL_SEQR12, 0x00); /* graphics cursor attributes */
- vga_wseq (cinfo->regbase, CL_SEQR13, 0x00); /* graphics cursor pattern address */
+ /* graphics cursor X position (incomplete; position gives rem. 3 bits */
+ vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
+ /* graphics cursor Y position (..."... ) */
+ vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
+ /* graphics cursor attributes */
+ vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
+ /* graphics cursor pattern address */
+ vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
/* writing these on a P4 might give problems.. */
if (cinfo->btype != BT_PICASSO4) {
- vga_wseq (cinfo->regbase, CL_SEQR17, 0x00); /* configuration readback and ext. color */
- vga_wseq (cinfo->regbase, CL_SEQR18, 0x02); /* signature generator */
+ /* configuration readback and ext. color */
+ vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
+ /* signature generator */
+ vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
}
/* MCLK select etc. */
if (bi->init_sr1f)
- vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f);
+ vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
- vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); /* Screen A preset row scan: none */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor start: disable text cursor */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); /* Text cursor end: - */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00); /* Screen start address high: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00); /* Screen start address low: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /* text cursor location high: 0 */
- vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /* text cursor location low: 0 */
-
- vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); /* Underline Row scanline: - */
- vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode control: timing enable, byte mode, no compat modes */
- vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00); /* Line Compare: not needed */
+ /* Screen A preset row scan: none */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
+ /* Text cursor start: disable text cursor */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
+ /* Text cursor end: - */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
+ /* Screen start address high: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
+ /* Screen start address low: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
+ /* text cursor location high: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
+ /* text cursor location low: 0 */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
+
+ /* Underline Row scanline: - */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
+ /* mode control: timing enable, byte mode, no compat modes */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
+ /* Line Compare: not needed */
+ vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
/* ### add 0x40 for text modes with > 30 MHz pixclock */
- vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02); /* ext. display controls: ext.adr. wrap */
+ /* ext. display controls: ext.adr. wrap */
+ vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
- vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /* Set/Reset registes: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /* Set/Reset enable: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Color Compare: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); /* Data Rotate: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /* Read Map Select: - */
- vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00); /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
- vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01); /* Miscellaneous: memory map base address, graphics mode */
- vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); /* Color Don't care: involve all planes */
- vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); /* Bit Mask: no mask at all */
+ /* Set/Reset registes: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
+ /* Set/Reset enable: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
+ /* Color Compare: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
+ /* Data Rotate: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
+ /* Read Map Select: - */
+ vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
+ /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
+ vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
+ /* Miscellaneous: memory map base address, graphics mode */
+ vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
+ /* Color Don't care: involve all planes */
+ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
+ /* Bit Mask: no mask at all */
+ vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
if (cinfo->btype == BT_ALPINE)
- vga_wgfx (cinfo->regbase, CL_GRB, 0x20); /* (5434 can't have bit 3 set for bitblt) */
+ /* (5434 can't have bit 3 set for bitblt) */
+ vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
else
- vga_wgfx (cinfo->regbase, CL_GRB, 0x28); /* Graphics controller mode extensions: finer granularity, 8byte data latches */
+ /* Graphics controller mode extensions: finer granularity,
+ * 8byte data latches
+ */
+ vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
- vga_wgfx (cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
- vga_wgfx (cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
- vga_wgfx (cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
- /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//* Background color byte 1: - */
-/* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
-
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00); /* Attribute Controller palette registers: "identity mapping" */
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
- vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
-
- vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /* Attribute Controller mode: graphics mode */
- vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /* Overscan color reg.: reg. 0 */
- vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); /* Color Plane enable: Enable all 4 planes */
-/* ### vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
- vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); /* Color Select: - */
+ vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
+ vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
+ vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
+ /* Background color byte 1: - */
+ /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
+ /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
+
+ /* Attribute Controller palette registers: "identity mapping" */
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
+ vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
+
+ /* Attribute Controller mode: graphics mode */
+ vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
+ /* Overscan color reg.: reg. 0 */
+ vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
+ /* Color Plane enable: Enable all 4 planes */
+ vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
+/* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
+ /* Color Select: - */
+ vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
- WGen (cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
+ WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
- WGen (cinfo, VGA_MIS_W, 0xc3); /* polarity (-/-), enable display mem, VGA_CRTC_START_HI i/o base = color */
+ /* polarity (-/-), enable display mem,
+ * VGA_CRTC_START_HI i/o base = color
+ */
+ WGen(cinfo, VGA_MIS_W, 0xc3);
- vga_wgfx (cinfo->regbase, CL_GR31, 0x04); /* BLT Start/status: Blitter reset */
- vga_wgfx (cinfo->regbase, CL_GR31, 0x00); /* - " - : "end-of-reset" */
+ /* BLT Start/status: Blitter reset */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
+ /* - " - : "end-of-reset" */
+ vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
/* misc... */
- WHDR (cinfo, 0); /* Hidden DAC register: - */
+ WHDR(cinfo, 0); /* Hidden DAC register: - */
- printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n", cinfo->size);
- DPRINTK ("EXIT\n");
+ printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
+ cinfo->size);
+ DPRINTK("EXIT\n");
return;
}
-static void switch_monitor (struct cirrusfb_info *cinfo, int on)
+static void switch_monitor(struct cirrusfb_info *cinfo, int on)
{
#ifdef CONFIG_ZORRO /* only works on Zorro boards */
static int IsOn = 0; /* XXX not ok for multiple boards */
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (cinfo->btype == BT_PICASSO4)
return; /* nothing to switch */
@@ -1963,44 +2109,43 @@ static void switch_monitor (struct cirru
return; /* nothing to switch */
if (cinfo->btype == BT_PICASSO) {
if ((on && !IsOn) || (!on && IsOn))
- WSFR (cinfo, 0xff);
+ WSFR(cinfo, 0xff);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return;
}
if (on) {
switch (cinfo->btype) {
case BT_SD64:
- WSFR (cinfo, cinfo->SFR | 0x21);
+ WSFR(cinfo, cinfo->SFR | 0x21);
break;
case BT_PICCOLO:
- WSFR (cinfo, cinfo->SFR | 0x28);
+ WSFR(cinfo, cinfo->SFR | 0x28);
break;
case BT_SPECTRUM:
- WSFR (cinfo, 0x6f);
+ WSFR(cinfo, 0x6f);
break;
default: /* do nothing */ break;
}
} else {
switch (cinfo->btype) {
case BT_SD64:
- WSFR (cinfo, cinfo->SFR & 0xde);
+ WSFR(cinfo, cinfo->SFR & 0xde);
break;
case BT_PICCOLO:
- WSFR (cinfo, cinfo->SFR & 0xd7);
+ WSFR(cinfo, cinfo->SFR & 0xd7);
break;
case BT_SPECTRUM:
- WSFR (cinfo, 0x4f);
+ WSFR(cinfo, 0x4f);
break;
default: /* do nothing */ break;
}
}
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
#endif /* CONFIG_ZORRO */
}
-
/******************************************/
/* Linux 2.6-style accelerated functions */
/******************************************/
@@ -2012,15 +2157,17 @@ static void cirrusfb_prim_fillrect(struc
u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ?
cinfo->pseudo_palette[region->color] : region->color;
- if(cinfo->info->var.bits_per_pixel == 1) {
- cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
+ if (cinfo->info->var.bits_per_pixel == 1) {
+ cirrusfb_RectFill(cinfo->regbase,
+ cinfo->info->var.bits_per_pixel,
region->dx / 8, region->dy,
region->width / 8, region->height,
color,
cinfo->currentmode.line_length);
} else {
- m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
- cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
+ m = (cinfo->info->var.bits_per_pixel + 7) / 8;
+ cirrusfb_RectFill(cinfo->regbase,
+ cinfo->info->var.bits_per_pixel,
region->dx * m, region->dy,
region->width * m, region->height,
color,
@@ -2029,7 +2176,8 @@ static void cirrusfb_prim_fillrect(struc
return;
}
-static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region)
+static void cirrusfb_fillrect(struct fb_info *info,
+ const struct fb_fillrect *region)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_fillrect modded;
@@ -2047,12 +2195,14 @@ static void cirrusfb_fillrect (struct fb
memcpy(&modded, region, sizeof(struct fb_fillrect));
- if(!modded.width || !modded.height ||
+ if (!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
- if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
- if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
+ if (modded.dx + modded.width > vxres)
+ modded.width = vxres - modded.dx;
+ if (modded.dy + modded.height > vyres)
+ modded.height = vyres - modded.dy;
cirrusfb_prim_fillrect(cinfo, &modded);
}
@@ -2061,14 +2211,14 @@ static void cirrusfb_prim_copyarea(struc
const struct fb_copyarea *area)
{
int m; /* bytes per pixel */
- if(cinfo->info->var.bits_per_pixel == 1) {
+ if (cinfo->info->var.bits_per_pixel == 1) {
cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
area->sx / 8, area->sy,
area->dx / 8, area->dy,
area->width / 8, area->height,
cinfo->currentmode.line_length);
} else {
- m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
+ m = (cinfo->info->var.bits_per_pixel + 7) / 8;
cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
area->sx * m, area->sy,
area->dx * m, area->dy,
@@ -2078,8 +2228,8 @@ static void cirrusfb_prim_copyarea(struc
return;
}
-
-static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+static void cirrusfb_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_copyarea modded;
@@ -2101,89 +2251,99 @@ static void cirrusfb_copyarea(struct fb_
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
- if(!modded.width || !modded.height ||
+ if (!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
- if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
- if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
- if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
- if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
+ if (modded.sx + modded.width > vxres)
+ modded.width = vxres - modded.sx;
+ if (modded.dx + modded.width > vxres)
+ modded.width = vxres - modded.dx;
+ if (modded.sy + modded.height > vyres)
+ modded.height = vyres - modded.sy;
+ if (modded.dy + modded.height > vyres)
+ modded.height = vyres - modded.dy;
cirrusfb_prim_copyarea(cinfo, &modded);
}
-static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image)
+static void cirrusfb_imageblit(struct fb_info *info,
+ const struct fb_image *image)
{
struct cirrusfb_info *cinfo = info->par;
- cirrusfb_WaitBLT(cinfo->regbase);
+ cirrusfb_WaitBLT(cinfo->regbase);
cfb_imageblit(info, image);
}
-
#ifdef CONFIG_PPC_PREP
#define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
#define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
-static void get_prep_addrs (unsigned long *display, unsigned long *registers)
+static void get_prep_addrs(unsigned long *display, unsigned long *registers)
{
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
*display = PREP_VIDEO_BASE;
*registers = (unsigned long) PREP_IO_BASE;
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
#endif /* CONFIG_PPC_PREP */
-
#ifdef CONFIG_PCI
-static int release_io_ports = 0;
+static int release_io_ports;
/* Pulled the logic from XFree86 Cirrus driver to get the memory size,
* based on the DRAM bandwidth bit and DRAM bank switching bit. This
* works with 1MB, 2MB and 4MB configurations (which the Motorola boards
* seem to have. */
-static unsigned int cirrusfb_get_memsize (u8 __iomem *regbase)
+static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
{
unsigned long mem;
unsigned char SRF;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- SRF = vga_rseq (regbase, CL_SEQRF);
+ SRF = vga_rseq(regbase, CL_SEQRF);
switch ((SRF & 0x18)) {
- case 0x08: mem = 512 * 1024; break;
- case 0x10: mem = 1024 * 1024; break;
- /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
- * on the 5430. */
- case 0x18: mem = 2048 * 1024; break;
- default: printk ("CLgenfb: Unknown memory size!\n");
+ case 0x08:
+ mem = 512 * 1024;
+ break;
+ case 0x10:
+ mem = 1024 * 1024;
+ break;
+ /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
+ * on the 5430.
+ */
+ case 0x18:
+ mem = 2048 * 1024;
+ break;
+ default:
+ printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
mem = 1024 * 1024;
}
- if (SRF & 0x80) {
- /* If DRAM bank switching is enabled, there must be twice as much
- * memory installed. (4MB on the 5434) */
+ if (SRF & 0x80)
+ /* If DRAM bank switching is enabled, there must be twice as much
+ * memory installed. (4MB on the 5434)
+ */
mem *= 2;
- }
+
/* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
return mem;
}
-
-
-static void get_pci_addrs (const struct pci_dev *pdev,
- unsigned long *display, unsigned long *registers)
+static void get_pci_addrs(const struct pci_dev *pdev,
+ unsigned long *display, unsigned long *registers)
{
- assert (pdev != NULL);
- assert (display != NULL);
- assert (registers != NULL);
+ assert(pdev != NULL);
+ assert(display != NULL);
+ assert(registers != NULL);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
*display = 0;
*registers = 0;
@@ -2198,13 +2358,12 @@ static void get_pci_addrs (const struct
*registers = pci_resource_start(pdev, 1);
}
- assert (*display != 0);
+ assert(*display != 0);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
-static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
+static void cirrusfb_pci_unmap(struct cirrusfb_info *cinfo)
{
struct pci_dev *pdev = cinfo->pdev;
@@ -2219,19 +2378,18 @@ static void cirrusfb_pci_unmap (struct c
}
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
-static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info *cinfo)
+static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
{
zorro_release_device(cinfo->zdev);
if (cinfo->btype == BT_PICASSO4) {
cinfo->regbase -= 0x600000;
- iounmap ((void *)cinfo->regbase);
- iounmap ((void *)cinfo->fbmem);
+ iounmap((void *)cinfo->regbase);
+ iounmap((void *)cinfo->fbmem);
} else {
if (zorro_resource_start(cinfo->zdev) > 0x01000000)
- iounmap ((void *)cinfo->fbmem);
+ iounmap((void *)cinfo->fbmem);
}
framebuffer_release(cinfo->info);
}
@@ -2267,7 +2425,8 @@ static int cirrusfb_set_fbinfo(struct ci
/* monochrome: only 1 memory plane */
/* 8 bit and above: Use whole memory area */
info->fix.smem_start = cinfo->fbmem_phys;
- info->fix.smem_len = (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
+ info->fix.smem_len =
+ (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
info->fix.type = cinfo->currentmode.type;
info->fix.type_aux = 0;
info->fix.visual = cinfo->currentmode.visual;
@@ -2292,17 +2451,18 @@ static int cirrusfb_register(struct cirr
int err;
cirrusfb_board_t btype;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based graphic boards, v" CIRRUSFB_VERSION "\n");
+ printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
+ "graphic boards, v" CIRRUSFB_VERSION "\n");
info = cinfo->info;
btype = cinfo->btype;
/* sanity checks */
- assert (btype != BT_NONE);
+ assert(btype != BT_NONE);
- DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
+ DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
/* Make pretend we've set the var so our structures are in a "good" */
/* state, even though we haven't written the mode to the hw yet... */
@@ -2321,11 +2481,12 @@ static int cirrusfb_register(struct cirr
err = register_framebuffer(info);
if (err < 0) {
- printk (KERN_ERR "cirrusfb: could not register fb device; err = %d!\n", err);
+ printk(KERN_ERR "cirrusfb: could not register "
+ "fb device; err = %d!\n", err);
goto err_dealloc_cmap;
}
- DPRINTK ("EXIT, returning 0\n");
+ DPRINTK("EXIT, returning 0\n");
return 0;
err_dealloc_cmap:
@@ -2335,24 +2496,23 @@ err_unmap_cirrusfb:
return err;
}
-static void __devexit cirrusfb_cleanup (struct fb_info *info)
+static void __devexit cirrusfb_cleanup(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- switch_monitor (cinfo, 0);
+ switch_monitor(cinfo, 0);
- unregister_framebuffer (info);
- fb_dealloc_cmap (&info->cmap);
- printk ("Framebuffer unregistered\n");
+ unregister_framebuffer(info);
+ fb_dealloc_cmap(&info->cmap);
+ printk("Framebuffer unregistered\n");
cinfo->unmap(cinfo);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
#ifdef CONFIG_PCI
-static int cirrusfb_pci_register (struct pci_dev *pdev,
+static int cirrusfb_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct cirrusfb_info *cinfo;
@@ -2379,31 +2539,34 @@ static int cirrusfb_pci_register (struct
cinfo->pdev = pdev;
cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
- DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
+ DPRINTK(" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
pdev->resource[0].start, btype);
- DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].start);
+ DPRINTK(" base address 1 is 0x%lx\n", pdev->resource[1].start);
- if(isPReP) {
- pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0, 0x00000000);
+ if (isPReP) {
+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
#ifdef CONFIG_PPC_PREP
- get_prep_addrs (&board_addr, &cinfo->fbregs_phys);
+ get_prep_addrs(&board_addr, &cinfo->fbregs_phys);
#endif
- /* PReP dies if we ioremap the IO registers, but it works w/out... */
+ /* PReP dies if we ioremap the IO registers, but it works w/out... */
cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
} else {
- DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
- get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys);
- cinfo->regbase = NULL; /* FIXME: this forces VGA. alternatives? */
+ DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
+ get_pci_addrs(pdev, &board_addr, &cinfo->fbregs_phys);
+ /* FIXME: this forces VGA. alternatives? */
+ cinfo->regbase = NULL;
}
- DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, cinfo->fbregs_phys);
+ DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
+ board_addr, cinfo->fbregs_phys);
board_size = (btype == BT_GD5480) ?
- 32 * MB_ : cirrusfb_get_memsize (cinfo->regbase);
+ 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
ret = pci_request_regions(pdev, "cirrusfb");
- if (ret <0) {
- printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
+ if (ret < 0) {
+ printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
+ "abort\n",
board_addr);
goto err_release_fb;
}
@@ -2429,8 +2592,9 @@ static int cirrusfb_pci_register (struct
cinfo->size = board_size;
cinfo->unmap = cirrusfb_pci_unmap;
- printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_, board_addr);
- printk ("Cirrus Logic chipset on PCI bus\n");
+ printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
+ cinfo->size / KB_, board_addr);
+ printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
pci_set_drvdata(pdev, info);
ret = cirrusfb_register(cinfo);
@@ -2453,14 +2617,14 @@ err_out:
return ret;
}
-static void __devexit cirrusfb_pci_unregister (struct pci_dev *pdev)
+static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- cirrusfb_cleanup (info);
+ cirrusfb_cleanup(info);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
static struct pci_driver cirrusfb_pci_driver = {
@@ -2477,7 +2641,6 @@ static struct pci_driver cirrusfb_pci_dr
};
#endif /* CONFIG_PCI */
-
#ifdef CONFIG_ZORRO
static int cirrusfb_zorro_register(struct zorro_dev *z,
const struct zorro_device_id *ent)
@@ -2498,7 +2661,7 @@ static int cirrusfb_zorro_register(struc
info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
if (!info) {
- printk (KERN_ERR "cirrusfb: could not allocate memory\n");
+ printk(KERN_ERR "cirrusfb: could not allocate memory\n");
ret = -ENOMEM;
goto err_out;
}
@@ -2507,9 +2670,9 @@ static int cirrusfb_zorro_register(struc
cinfo->info = info;
cinfo->btype = btype;
- assert (z > 0);
- assert (z2 >= 0);
- assert (btype != BT_NONE);
+ assert(z > 0);
+ assert(z2 >= 0);
+ assert(btype != BT_NONE);
cinfo->zdev = z;
board_addr = zorro_resource_start(z);
@@ -2517,55 +2680,59 @@ static int cirrusfb_zorro_register(struc
cinfo->size = size;
if (!zorro_request_device(z, "cirrusfb")) {
- printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
+ printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
+ "abort\n",
board_addr);
ret = -EBUSY;
goto err_release_fb;
}
- printk (" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
+ printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
ret = -EIO;
if (btype == BT_PICASSO4) {
- printk (" REG at $%lx\n", board_addr + 0x600000);
+ printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
/* To be precise, for the P4 this is not the */
/* begin of the board, but the begin of RAM. */
/* for P4, map in its address space in 2 chunks (### TEST! ) */
/* (note the ugly hardcoded 16M number) */
- cinfo->regbase = ioremap (board_addr, 16777216);
+ cinfo->regbase = ioremap(board_addr, 16777216);
if (!cinfo->regbase)
goto err_release_region;
- DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
+ DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
+ cinfo->regbase);
cinfo->regbase += 0x600000;
cinfo->fbregs_phys = board_addr + 0x600000;
cinfo->fbmem_phys = board_addr + 16777216;
- cinfo->fbmem = ioremap (cinfo->fbmem_phys, 16777216);
+ cinfo->fbmem = ioremap(cinfo->fbmem_phys, 16777216);
if (!cinfo->fbmem)
goto err_unmap_regbase;
} else {
- printk (" REG at $%lx\n", (unsigned long) z2->resource.start);
+ printk(KERN_INFO " REG at $%lx\n",
+ (unsigned long) z2->resource.start);
cinfo->fbmem_phys = board_addr;
if (board_addr > 0x01000000)
- cinfo->fbmem = ioremap (board_addr, board_size);
+ cinfo->fbmem = ioremap(board_addr, board_size);
else
- cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr);
+ cinfo->fbmem = (caddr_t) ZTWO_VADDR(board_addr);
if (!cinfo->fbmem)
goto err_release_region;
/* set address for REG area of board */
- cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.start);
+ cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
cinfo->fbregs_phys = z2->resource.start;
- DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
+ DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
+ cinfo->regbase);
}
cinfo->unmap = cirrusfb_zorro_unmap;
- printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
+ printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
zorro_set_drvdata(z, info);
ret = cirrusfb_register(cinfo);
@@ -2592,11 +2759,11 @@ err_out:
void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
{
struct fb_info *info = zorro_get_drvdata(z);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- cirrusfb_cleanup (info);
+ cirrusfb_cleanup(info);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
static struct zorro_driver cirrusfb_zorro_driver = {
@@ -2628,26 +2795,24 @@ static int __init cirrusfb_init(void)
return error;
}
-
-
#ifndef MODULE
static int __init cirrusfb_setup(char *options) {
char *this_opt, s[32];
int i;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (!options || !*options)
return 0;
- while ((this_opt = strsep (&options, ",")) != NULL) {
+ while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
for (i = 0; i < NUM_TOTAL_MODES; i++) {
- sprintf (s, "mode:%s", cirrusfb_predefined[i].name);
- if (strcmp (this_opt, s) == 0)
+ sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
+ if (strcmp(this_opt, s) == 0)
cirrusfb_def_mode = i;
}
if (!strcmp(this_opt, "noaccel"))
@@ -2657,7 +2822,6 @@ static int __init cirrusfb_setup(char *o
}
#endif
-
/*
* Modularization
*/
@@ -2666,7 +2830,7 @@ MODULE_AUTHOR("Copyright 1999,2000 Jeff
MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
MODULE_LICENSE("GPL");
-static void __exit cirrusfb_exit (void)
+static void __exit cirrusfb_exit(void)
{
#ifdef CONFIG_PCI
pci_unregister_driver(&cirrusfb_pci_driver);
@@ -2682,66 +2846,67 @@ module_init(cirrusfb_init);
module_exit(cirrusfb_exit);
#endif
-
/**********************************************************************/
/* about the following functions - I have used the same names for the */
/* functions as Markus Wild did in his Retina driver for NetBSD as */
/* they just made sense for this purpose. Apart from that, I wrote */
-/* these functions myself. */
+/* these functions myself. */
/**********************************************************************/
/*** WGen() - write into one of the external/general registers ***/
-static void WGen (const struct cirrusfb_info *cinfo,
+static void WGen(const struct cirrusfb_info *cinfo,
int regnum, unsigned char val)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
-/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
+/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+ regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
- vga_w (cinfo->regbase, regofs + regnum, val);
+ vga_w(cinfo->regbase, regofs + regnum, val);
}
/*** RGen() - read out one of the external/general registers ***/
-static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum)
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
-/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
+/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+ regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
- return vga_r (cinfo->regbase, regofs + regnum);
+ return vga_r(cinfo->regbase, regofs + regnum);
}
/*** AttrOn() - turn on VideoEnable for Attribute controller ***/
-static void AttrOn (const struct cirrusfb_info *cinfo)
+static void AttrOn(const struct cirrusfb_info *cinfo)
{
- assert (cinfo != NULL);
+ assert(cinfo != NULL);
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
- if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) {
+ if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
/* if we're just in "write value" mode, write back the */
/* same value as before to not modify anything */
- vga_w (cinfo->regbase, VGA_ATT_IW,
- vga_r (cinfo->regbase, VGA_ATT_R));
+ vga_w(cinfo->regbase, VGA_ATT_IW,
+ vga_r(cinfo->regbase, VGA_ATT_R));
}
/* turn on video bit */
-/* vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */
- vga_w (cinfo->regbase, VGA_ATT_IW, 0x33);
+/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
+ vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
/* dummy write on Reg0 to be on "write index" mode next time */
- vga_w (cinfo->regbase, VGA_ATT_IW, 0x00);
+ vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
/*** WHDR() - write into the Hidden DAC register ***/
@@ -2750,119 +2915,115 @@ static void AttrOn (const struct cirrusf
* registers of their functional group) here is a specialized routine for
* accessing the HDR
*/
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val)
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
{
unsigned char dummy;
if (cinfo->btype == BT_PICASSO) {
/* Klaus' hint for correct access to HDR on some boards */
/* first write 0 to pixel mask (3c6) */
- WGen (cinfo, VGA_PEL_MSK, 0x00);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, 0x00);
+ udelay(200);
/* next read dummy from pixel address (3c8) */
- dummy = RGen (cinfo, VGA_PEL_IW);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_IW);
+ udelay(200);
}
/* now do the usual stuff to access the HDR */
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
- dummy = RGen (cinfo, VGA_PEL_MSK);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
+ dummy = RGen(cinfo, VGA_PEL_MSK);
+ udelay(200);
- WGen (cinfo, VGA_PEL_MSK, val);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, val);
+ udelay(200);
if (cinfo->btype == BT_PICASSO) {
/* now first reset HDR access counter */
- dummy = RGen (cinfo, VGA_PEL_IW);
- udelay (200);
+ dummy = RGen(cinfo, VGA_PEL_IW);
+ udelay(200);
/* and at the end, restore the mask value */
/* ## is this mask always 0xff? */
- WGen (cinfo, VGA_PEL_MSK, 0xff);
- udelay (200);
+ WGen(cinfo, VGA_PEL_MSK, 0xff);
+ udelay(200);
}
}
-
/*** WSFR() - write to the "special function register" (SFR) ***/
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char val)
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
{
#ifdef CONFIG_ZORRO
- assert (cinfo->regbase != NULL);
+ assert(cinfo->regbase != NULL);
cinfo->SFR = val;
- z_writeb (val, cinfo->regbase + 0x8000);
+ z_writeb(val, cinfo->regbase + 0x8000);
#endif
}
/* The Picasso has a second register for switching the monitor bit */
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val)
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
{
#ifdef CONFIG_ZORRO
/* writing an arbitrary value to this one causes the monitor switcher */
/* to flip to Amiga display */
- assert (cinfo->regbase != NULL);
+ assert(cinfo->regbase != NULL);
cinfo->SFR = val;
- z_writeb (val, cinfo->regbase + 0x9000);
+ z_writeb(val, cinfo->regbase + 0x9000);
#endif
}
-
/*** WClut - set CLUT entry (range: 0..63) ***/
-static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
+static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
unsigned char green, unsigned char blue)
{
unsigned int data = VGA_PEL_D;
/* address write mode register is not translated.. */
- vga_w (cinfo->regbase, VGA_PEL_IW, regnum);
+ vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
/* but DAC data register IS, at least for Picasso II */
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
- vga_w (cinfo->regbase, data, red);
- vga_w (cinfo->regbase, data, green);
- vga_w (cinfo->regbase, data, blue);
+ vga_w(cinfo->regbase, data, red);
+ vga_w(cinfo->regbase, data, green);
+ vga_w(cinfo->regbase, data, blue);
} else {
- vga_w (cinfo->regbase, data, blue);
- vga_w (cinfo->regbase, data, green);
- vga_w (cinfo->regbase, data, red);
+ vga_w(cinfo->regbase, data, blue);
+ vga_w(cinfo->regbase, data, green);
+ vga_w(cinfo->regbase, data, red);
}
}
-
#if 0
/*** RClut - read CLUT entry (range 0..63) ***/
-static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
+static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
unsigned char *green, unsigned char *blue)
{
unsigned int data = VGA_PEL_D;
- vga_w (cinfo->regbase, VGA_PEL_IR, regnum);
+ vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
- *red = vga_r (cinfo->regbase, data);
- *green = vga_r (cinfo->regbase, data);
- *blue = vga_r (cinfo->regbase, data);
+ *red = vga_r(cinfo->regbase, data);
+ *green = vga_r(cinfo->regbase, data);
+ *blue = vga_r(cinfo->regbase, data);
} else {
- *blue = vga_r (cinfo->regbase, data);
- *green = vga_r (cinfo->regbase, data);
- *red = vga_r (cinfo->regbase, data);
+ *blue = vga_r(cinfo->regbase, data);
+ *green = vga_r(cinfo->regbase, data);
+ *red = vga_r(cinfo->regbase, data);
}
}
#endif
-
/*******************************************************************
cirrusfb_WaitBLT()
@@ -2870,10 +3031,10 @@ static void RClut (struct cirrusfb_info
*********************************************************************/
/* FIXME: use interrupts instead */
-static void cirrusfb_WaitBLT (u8 __iomem *regbase)
+static void cirrusfb_WaitBLT(u8 __iomem *regbase)
{
/* now busy-wait until we're done */
- while (vga_rgfx (regbase, CL_GR31) & 0x08)
+ while (vga_rgfx(regbase, CL_GR31) & 0x08)
/* do nothing */ ;
}
@@ -2883,15 +3044,17 @@ static void cirrusfb_WaitBLT (u8 __iomem
perform accelerated "scrolling"
********************************************************************/
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
- u_short curx, u_short cury, u_short destx, u_short desty,
- u_short width, u_short height, u_short line_length)
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
+ u_short curx, u_short cury,
+ u_short destx, u_short desty,
+ u_short width, u_short height,
+ u_short line_length)
{
u_short nwidth, nheight;
u_long nsrc, ndest;
u_char bltmode;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
nwidth = width - 1;
nheight = height - 1;
@@ -2911,9 +3074,13 @@ static void cirrusfb_BitBLT (u8 __iomem
nsrc = (cury * line_length) + curx;
ndest = (desty * line_length) + destx;
} else {
- /* this means start addresses are at the end, counting backwards */
- nsrc = cury * line_length + curx + nheight * line_length + nwidth;
- ndest = desty * line_length + destx + nheight * line_length + nwidth;
+ /* this means start addresses are at the end,
+ * counting backwards
+ */
+ nsrc = cury * line_length + curx +
+ nheight * line_length + nwidth;
+ ndest = desty * line_length + destx +
+ nheight * line_length + nwidth;
}
/*
@@ -2929,52 +3096,65 @@ static void cirrusfb_BitBLT (u8 __iomem
start/stop
*/
- cirrusfb_WaitBLT(regbase);
+ cirrusfb_WaitBLT(regbase);
/* pitch: set to line_length */
- vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
- vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
- vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
- vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
+ /* dest pitch low */
+ vga_wgfx(regbase, CL_GR24, line_length & 0xff);
+ /* dest pitch hi */
+ vga_wgfx(regbase, CL_GR25, line_length >> 8);
+ /* source pitch low */
+ vga_wgfx(regbase, CL_GR26, line_length & 0xff);
+ /* source pitch hi */
+ vga_wgfx(regbase, CL_GR27, line_length >> 8);
/* BLT width: actual number of pixels - 1 */
- vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
- vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
+ /* BLT width low */
+ vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
+ /* BLT width hi */
+ vga_wgfx(regbase, CL_GR21, nwidth >> 8);
/* BLT height: actual number of lines -1 */
- vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
- vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
+ /* BLT height low */
+ vga_wgfx(regbase, CL_GR22, nheight & 0xff);
+ /* BLT width hi */
+ vga_wgfx(regbase, CL_GR23, nheight >> 8);
/* BLT destination */
- vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
- vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
- vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
+ /* BLT dest low */
+ vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
+ /* BLT dest mid */
+ vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
+ /* BLT dest hi */
+ vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT source */
- vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /* BLT src low */
- vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8)); /* BLT src mid */
- vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16)); /* BLT src hi */
+ /* BLT src low */
+ vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
+ /* BLT src mid */
+ vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
+ /* BLT src hi */
+ vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
/* BLT mode */
- vga_wgfx (regbase, CL_GR30, bltmode); /* BLT mode */
+ vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
/* BLT ROP: SrcCopy */
- vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
+ vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
- vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
+ vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/*******************************************************************
cirrusfb_RectFill()
perform accelerated rectangle fill
********************************************************************/
-static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
+static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
u_short x, u_short y, u_short width, u_short height,
u_char color, u_short line_length)
{
@@ -2982,93 +3162,95 @@ static void cirrusfb_RectFill (u8 __iome
u_long ndest;
u_char op;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
nwidth = width - 1;
nheight = height - 1;
ndest = (y * line_length) + x;
- cirrusfb_WaitBLT(regbase);
+ cirrusfb_WaitBLT(regbase);
/* pitch: set to line_length */
- vga_wgfx (regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
- vga_wgfx (regbase, CL_GR25, (line_length >> 8)); /* dest pitch hi */
- vga_wgfx (regbase, CL_GR26, line_length & 0xff); /* source pitch low */
- vga_wgfx (regbase, CL_GR27, (line_length >> 8)); /* source pitch hi */
+ vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
+ vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
+ vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
+ vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
/* BLT width: actual number of pixels - 1 */
- vga_wgfx (regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
- vga_wgfx (regbase, CL_GR21, (nwidth >> 8)); /* BLT width hi */
+ vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
+ vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
/* BLT height: actual number of lines -1 */
- vga_wgfx (regbase, CL_GR22, nheight & 0xff); /* BLT height low */
- vga_wgfx (regbase, CL_GR23, (nheight >> 8)); /* BLT width hi */
+ vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
+ vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
/* BLT destination */
- vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest low */
- vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest mid */
- vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16)); /* BLT dest hi */
+ /* BLT dest low */
+ vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
+ /* BLT dest mid */
+ vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
+ /* BLT dest hi */
+ vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT source: set to 0 (is a dummy here anyway) */
- vga_wgfx (regbase, CL_GR2C, 0x00); /* BLT src low */
- vga_wgfx (regbase, CL_GR2D, 0x00); /* BLT src mid */
- vga_wgfx (regbase, CL_GR2E, 0x00); /* BLT src hi */
+ vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
+ vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
+ vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
/* This is a ColorExpand Blt, using the */
/* same color for foreground and background */
- vga_wgfx (regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
- vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color); /* background color */
+ vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
+ vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
op = 0xc0;
if (bits_per_pixel == 16) {
- vga_wgfx (regbase, CL_GR10, color); /* foreground color */
- vga_wgfx (regbase, CL_GR11, color); /* background color */
+ vga_wgfx(regbase, CL_GR10, color); /* foreground color */
+ vga_wgfx(regbase, CL_GR11, color); /* background color */
op = 0x50;
op = 0xd0;
} else if (bits_per_pixel == 32) {
- vga_wgfx (regbase, CL_GR10, color); /* foreground color */
- vga_wgfx (regbase, CL_GR11, color); /* background color */
- vga_wgfx (regbase, CL_GR12, color); /* foreground color */
- vga_wgfx (regbase, CL_GR13, color); /* background color */
- vga_wgfx (regbase, CL_GR14, 0); /* foreground color */
- vga_wgfx (regbase, CL_GR15, 0); /* background color */
+ vga_wgfx(regbase, CL_GR10, color); /* foreground color */
+ vga_wgfx(regbase, CL_GR11, color); /* background color */
+ vga_wgfx(regbase, CL_GR12, color); /* foreground color */
+ vga_wgfx(regbase, CL_GR13, color); /* background color */
+ vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
+ vga_wgfx(regbase, CL_GR15, 0); /* background color */
op = 0x50;
op = 0xf0;
}
/* BLT mode: color expand, Enable 8x8 copy (faster?) */
- vga_wgfx (regbase, CL_GR30, op); /* BLT mode */
+ vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
/* BLT ROP: SrcCopy */
- vga_wgfx (regbase, CL_GR32, 0x0d); /* BLT ROP */
+ vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
- vga_wgfx (regbase, CL_GR31, 0x02); /* BLT Start/status */
+ vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/**************************************************************************
* bestclock() - determine closest possible clock lower(?) than the
* desired pixel clock
**************************************************************************/
-static void bestclock (long freq, long *best, long *nom,
+static void bestclock(long freq, long *best, long *nom,
long *den, long *div, long maxfreq)
{
long n, h, d, f;
- assert (best != NULL);
- assert (nom != NULL);
- assert (den != NULL);
- assert (div != NULL);
- assert (maxfreq > 0);
+ assert(best != NULL);
+ assert(nom != NULL);
+ assert(den != NULL);
+ assert(div != NULL);
+ assert(maxfreq > 0);
*nom = 0;
*den = 0;
*div = 0;
- DPRINTK ("ENTER\n");
+ DPRINTK("ENTER\n");
if (freq < 8000)
freq = 8000;
@@ -3085,7 +3267,7 @@ static void bestclock (long freq, long *
if (d > 31)
d = (d / 2) * 2;
h = (14318 * n) / d;
- if (abs (h - freq) < abs (*best - freq)) {
+ if (abs(h - freq) < abs(*best - freq)) {
*best = h;
*nom = n;
if (d < 32) {
@@ -3102,7 +3284,7 @@ static void bestclock (long freq, long *
if (d > 31)
d = (d / 2) * 2;
h = (14318 * n) / d;
- if (abs (h - freq) < abs (*best - freq)) {
+ if (abs(h - freq) < abs(*best - freq)) {
*best = h;
*nom = n;
if (d < 32) {
@@ -3116,14 +3298,13 @@ static void bestclock (long freq, long *
}
}
- DPRINTK ("Best possible values for given frequency:\n");
- DPRINTK (" best: %ld kHz nom: %ld den: %ld div: %ld\n",
- freq, *nom, *den, *div);
+ DPRINTK("Best possible values for given frequency:\n");
+ DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
+ freq, *nom, *den, *div);
- DPRINTK ("EXIT\n");
+ DPRINTK("EXIT\n");
}
-
/* -------------------------------------------------------------------------
*
* debugging functions
@@ -3145,21 +3326,20 @@ static void bestclock (long freq, long *
*/
static
-void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
+void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
{
- DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
- name, val,
- val & 0x80 ? '1' : '0',
- val & 0x40 ? '1' : '0',
- val & 0x20 ? '1' : '0',
- val & 0x10 ? '1' : '0',
- val & 0x08 ? '1' : '0',
- val & 0x04 ? '1' : '0',
- val & 0x02 ? '1' : '0',
- val & 0x01 ? '1' : '0');
+ DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
+ name, val,
+ val & 0x80 ? '1' : '0',
+ val & 0x40 ? '1' : '0',
+ val & 0x20 ? '1' : '0',
+ val & 0x10 ? '1' : '0',
+ val & 0x08 ? '1' : '0',
+ val & 0x04 ? '1' : '0',
+ val & 0x02 ? '1' : '0',
+ val & 0x01 ? '1' : '0');
}
-
/**
* cirrusfb_dbg_print_regs
* @base: If using newmmio, the newmmio base address, otherwise %NULL
@@ -3172,25 +3352,26 @@ void cirrusfb_dbg_print_byte (const char
*/
static
-void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...)
+void cirrusfb_dbg_print_regs(caddr_t regbase,
+ cirrusfb_dbg_reg_class_t reg_class, ...)
{
va_list list;
unsigned char val = 0;
unsigned reg;
char *name;
- va_start (list, reg_class);
+ va_start(list, reg_class);
- name = va_arg (list, char *);
+ name = va_arg(list, char *);
while (name != NULL) {
- reg = va_arg (list, int);
+ reg = va_arg(list, int);
switch (reg_class) {
case CRT:
- val = vga_rcrt (regbase, (unsigned char) reg);
+ val = vga_rcrt(regbase, (unsigned char) reg);
break;
case SEQ:
- val = vga_rseq (regbase, (unsigned char) reg);
+ val = vga_rseq(regbase, (unsigned char) reg);
break;
default:
/* should never occur */
@@ -3198,15 +3379,14 @@ void cirrusfb_dbg_print_regs (caddr_t re
break;
}
- cirrusfb_dbg_print_byte (name, val);
+ cirrusfb_dbg_print_byte(name, val);
- name = va_arg (list, char *);
+ name = va_arg(list, char *);
}
- va_end (list);
+ va_end(list);
}
-
/**
* cirrusfb_dump
* @cirrusfbinfo:
@@ -3214,13 +3394,11 @@ void cirrusfb_dbg_print_regs (caddr_t re
* DESCRIPTION:
*/
-static
-void cirrusfb_dump (void)
+static void cirrusfb_dump(void)
{
- cirrusfb_dbg_reg_dump (NULL);
+ cirrusfb_dbg_reg_dump(NULL);
}
-
/**
* cirrusfb_dbg_reg_dump
* @base: If using newmmio, the newmmio base address, otherwise %NULL
@@ -3232,11 +3410,11 @@ void cirrusfb_dump (void)
*/
static
-void cirrusfb_dbg_reg_dump (caddr_t regbase)
+void cirrusfb_dbg_reg_dump(caddr_t regbase)
{
- DPRINTK ("CIRRUSFB VGA CRTC register dump:\n");
+ DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
- cirrusfb_dbg_print_regs (regbase, CRT,
+ cirrusfb_dbg_print_regs(regbase, CRT,
"CR00", 0x00,
"CR01", 0x01,
"CR02", 0x02,
@@ -3286,11 +3464,11 @@ void cirrusfb_dbg_reg_dump (caddr_t regb
"CR3F", 0x3F,
NULL);
- DPRINTK ("\n");
+ DPRINTK("\n");
- DPRINTK ("CIRRUSFB VGA SEQ register dump:\n");
+ DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
- cirrusfb_dbg_print_regs (regbase, SEQ,
+ cirrusfb_dbg_print_regs(regbase, SEQ,
"SR00", 0x00,
"SR01", 0x01,
"SR02", 0x02,
@@ -3319,7 +3497,7 @@ void cirrusfb_dbg_reg_dump (caddr_t regb
"SR1F", 0x1F,
NULL);
- DPRINTK ("\n");
+ DPRINTK("\n");
}
#endif /* CIRRUSFB_DEBUG */
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next reply other threads:[~2007-08-17 16:47 UTC|newest]
Thread overview: 1298+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-08-17 16:47 Krzysztof Helt [this message]
-- strict thread matches above, loose matches on Subject: below --
2026-04-05 20:38 (No Subject) Dhaval Patel
2025-09-19 20:07 Daniel G. Chultaeiz
2025-02-12 14:07 blg666
2024-10-14 18:41 td9076922
2024-09-21 20:42 [PATCH] drivers/gpu: Switching Adreno x1-85 device check to family check John Schulz
2024-09-22 14:39 ` Dmitry Baryshkov
2024-09-24 15:54 ` (No Subject) John Schulz
2024-09-24 16:34 ` Rob Clark
2024-09-24 20:02 ` Dmitry Baryshkov
2024-06-14 18:16 Pratham Patel
2024-03-06 12:36 Emilis Kiškis
2024-02-08 3:34 Oliver Webb
2024-02-08 3:46 ` Lawrence Velázquez
2024-02-08 4:04 ` Oliver Webb
2024-02-08 4:09 ` Lawrence Velázquez
2023-10-11 6:29 martin
2023-05-13 8:12 [no subject] Beatrice Benson
2023-05-13 8:12 Beatrice Benson
2022-09-20 10:04 Marc Kleine-Budde
2022-09-21 7:07 ` (No Subject) john
2022-09-21 19:58 ` Marc Kleine-Budde
2022-09-23 7:37 ` john
2022-07-21 20:02 loggervicky69
2021-12-27 14:59 [PATCH v2 2/3] arm64: Support huge vmalloc mappings Kefeng Wang
2021-12-27 17:35 ` (No subject) William Kucharski
2021-12-27 17:35 ` William Kucharski
2021-12-27 17:35 ` William Kucharski
2021-12-28 1:36 ` Kefeng Wang
2021-12-28 1:36 ` Kefeng Wang
2021-12-28 1:36 ` Kefeng Wang
2021-08-08 20:46 (No Subject) Yadunandan Pillai
2021-06-22 16:20 Yassine Oudjana
2021-07-14 18:03 ` Rob Herring
2021-05-07 22:47 Nathan Ringo
2021-03-21 17:46 Caleb Connolly
2021-03-22 10:06 ` Dmitry Baryshkov
2020-05-19 9:57 [PATCH 8/8] mac80211: IBSS: send deauth when expiring inactive STAs linux-wireless
2020-05-22 18:18 ` (No Subject) hyperfekt
2020-05-19 9:29 (no subject) Vinod Koul
2020-02-26 11:57 Ville Syrjälä
2020-02-26 12:08 ` Linus Walleij
2020-02-26 14:34 ` Ville Syrjälä
2020-02-26 14:56 ` Linus Walleij
2020-02-26 15:08 ` Ville Syrjälä
2019-12-20 17:06 [alsa-devel] [PATCH v5 2/7] ASoC: tegra: Allow 24bit and 32bit samples Ben Dooks
2019-12-22 17:08 ` Dmitry Osipenko
2020-01-05 0:04 ` Ben Dooks
2020-01-05 1:48 ` Dmitry Osipenko
2020-01-05 10:53 ` Ben Dooks
2020-01-06 19:00 ` [alsa-devel] [Linux-kernel] " Ben Dooks
2020-01-07 1:39 ` Dmitry Osipenko
2020-01-23 19:38 ` Ben Dooks
2020-01-24 16:50 ` Jon Hunter
2020-01-27 19:20 ` Dmitry Osipenko
2020-01-28 12:13 ` Mark Brown
2020-01-28 17:42 ` Dmitry Osipenko
2020-01-28 18:19 ` Jon Hunter
2020-01-29 0:17 ` Dmitry Osipenko
2020-01-30 8:05 ` [alsa-devel] (no subject) Ben Dooks
2020-01-30 9:31 ` Clemens Ladisch
2020-01-30 9:39 ` [alsa-devel] " Ben Dooks
2020-01-30 14:58 ` Clemens Ladisch
2020-01-31 10:50 ` Ben Dooks
2020-01-31 11:03 ` Clemens Ladisch
2019-11-05 16:34 Rob Clark
2019-10-18 15:54 (No subject) Lesia Kay Rivera
2019-09-30 15:50 Stephen K Jolley
2019-08-08 0:03 (no subject) Giuliano Zannetti - ART S.p.A.
2019-07-22 20:35 Sam Ravnborg
2019-07-14 22:31 Андрей Бохонов
2019-06-13 5:54 Ralf Beck
2019-06-13 15:51 ` Pierre-Louis Bossart
2019-06-13 19:19 ` Jaroslav Kysela
[not found] <CABRndgyzXQaYpefcMEMt1ShbqVKaf9vLJOXaL2cgUZMik4=xxw@mail.gmail.com>
2019-06-13 4:06 ` Philippe Proulx
[not found] ` <CAB4xu_0h-q6En3_hDODbKuXd1=4_e0car73pP8Cf=LNWMKjh_g@mail.gmail.com>
2019-06-13 12:20 ` Zvi Vered
[not found] ` <CABRndgwEg3wYLbyfobjxdEKd8O1dAu+B+PwS-0A5gxURjKj_WA@mail.gmail.com>
2019-06-13 15:38 ` Jonathan Rajotte-Julien
[not found] ` <20190613153823.GC972@joraj-alpa>
2019-06-14 4:30 ` Zvi Vered
2019-06-13 3:17 Zvi Vered
2019-05-22 8:53 [No Subject] Gardner, Tim
2019-05-22 8:53 Gardner, Tim
2019-05-22 8:53 Gardner, Tim
2019-05-22 8:53 Gardner, Tim
2019-05-22 5:51 Gardner, Tim
2019-05-22 5:41 Gardner, Tim
2019-05-22 4:27 Gardner, Tim
2019-05-08 14:14 (No subject) B, Karthik
2019-04-28 8:52 (No Subject) rodomar705
2019-04-03 19:09 (No subject) Mahesh Radhakrishnan
2019-03-08 15:14 Marija Stojanovska
2019-02-05 21:52 [PATCH] wpa_supplicant: Changed systemd template units Richard Purdie
2019-02-07 14:48 ` (No subject) Joshua DeWeese
2019-01-29 16:11 Antonio Santagiuliana
2019-01-29 17:41 ` Scott Rifenbark
2018-11-19 17:26 (no subject) Razvan Cojocaru
2018-11-19 17:34 ` Razvan Cojocaru
2018-11-03 17:13 (No subject) Ankit Navik
2018-10-04 16:10 Satya Sampangi
2018-10-04 13:29 Angelo Dureghello
2018-10-04 13:55 ` Burton, Ross
2018-10-04 15:00 ` Andrea Adami
2018-10-04 15:08 ` Angelo Dureghello
2018-09-15 15:47 (no subject) Arnd Bergmann
2018-09-02 17:42 (No subject) nishant poorswani
2018-08-16 21:21 Eric Ruei
2018-08-02 8:44 Nathan Rossi
2018-07-25 8:25 Eyal Reizer
2018-07-24 20:55 Djordje Senicic
2018-07-23 12:28 William Delacre
2018-07-26 19:40 ` Mark Asselstine
2018-07-27 15:03 ` Mark Asselstine
2018-07-27 16:04 ` William Delacre
2018-07-27 16:16 ` Mark Asselstine
2018-07-27 16:25 ` William Delacre
2018-07-27 16:44 ` S. Lockwood-Childs
2018-07-27 16:42 ` William Delacre
2018-07-27 16:47 ` Mark Asselstine
2018-07-31 11:54 ` William Delacre
2018-07-31 14:30 ` Mark Asselstine
2018-07-31 18:46 ` S. Lockwood-Childs
2018-07-31 22:34 ` William Delacre
2018-07-06 14:42 (no subject) Christian König
2018-07-05 10:38 rosdi ablatiff
2018-06-06 8:05 (No subject) Parthiban Nallathambi
2018-05-22 6:52 Rahul jangra
2018-05-03 19:55 taborskikrzysztof
2018-04-25 10:51 jan vermaete
2018-04-25 17:33 ` Otavio Salvador
2018-04-26 17:17 ` jan vermaete
2018-04-26 17:44 ` Otavio Salvador
[not found] <913813716.1318110.1522099057513.ref@mail.yahoo.com>
2018-03-26 21:17 ` Ruica Cristina
2018-03-26 22:10 ` Richard Purdie
2018-03-27 3:13 ` Stephano Cetola
2018-01-24 12:00 (no subject) twischer
2017-11-27 16:20 (No subject) Volker Vogelhuber
2017-11-26 0:22 (No Subject) n1had5
2017-11-26 0:25 ` Jason A. Donenfeld
2017-11-26 0:30 ` Jonathon Fernyhough
2017-08-17 15:13 <no subject> Bharath Krishna
2017-08-16 15:13 (no subject) Barr. Richard Williams
2017-07-19 15:25 [PATCH 000/102] Convert drivers to explicit reset API Philipp Zabel
2017-07-20 20:32 ` (no subject) Heiko Stuebner
2017-07-20 20:36 ` Heiko Stuebner
2017-07-20 20:32 ` Heiko Stuebner
2017-06-19 14:57 (No subject) Мар'ян Пріцак
2017-06-19 19:01 ` Josef Holzmayr
2017-06-20 8:07 ` Tamtamis, Panagiotis
2017-06-20 14:07 ` Josef Holzmayr
2017-06-20 14:32 ` Tamtamis, Panagiotis
2017-06-20 14:55 ` Мар'ян Пріцак
2017-06-06 21:34 <no subject> Stephen Bates
2017-05-30 5:19 (No subject) Андрей Кононов
2017-05-30 19:02 ` Petter Mabäcker
2017-05-31 5:40 ` Андрей Кононов
2017-05-07 1:33 [PATCH] openssh: Atomically generate host keys Joshua Watt
2017-05-09 2:24 ` (No subject) Joshua Watt
2017-04-06 0:06 Andrej Rode
2017-03-10 9:49 Suneetha Lakshmi G
2017-03-09 10:32 (no subject) Felix Bruns
2017-02-21 14:58 anders
2017-02-17 7:35 (No subject) Paulo Neves
2017-02-09 11:53 (no subject) anders
2017-01-25 9:38 <no subject> Sirisha Guduru
2017-01-16 16:28 (no subject) Tony Whittam
2017-01-09 11:33 [PATCH v2 0/7] uapi: export all headers under uapi directories Arnd Bergmann
2017-01-13 10:46 ` [PATCH v3 0/8] " Nicolas Dichtel
2017-01-13 10:46 ` [PATCH v3 1/8] arm: put types.h in uapi Nicolas Dichtel
2017-01-13 15:36 ` (no subject) David Howells
2017-01-13 10:46 ` [PATCH v3 4/8] x86: stop exporting msr-index.h to userland Nicolas Dichtel
2017-01-13 15:43 ` (no subject) David Howells
2017-01-13 15:43 ` David Howells
2017-01-09 10:49 (No subject) Rohit Jindal
2016-11-30 12:32 (no subject) 胡瑞桓
2016-11-11 16:16 [PATCH i-g-t v5 1/4] lib: add igt_dummyload Daniel Vetter
2016-11-14 18:24 ` (no subject) Abdiel Janulgue
2016-10-27 5:26 <no subject> Bharath Krishna
2016-09-20 18:12 (no subject) xerofoify
2016-07-22 10:35 (No subject) Amarnath Valluri
2016-07-19 8:34 (no subject) Alex Gershgorin
[not found] ` <1DC01DCD0F70AE4284AE3A5E8C726E2240106236-6dhP19T7b9reAA7jXO2vED4kX+cae0hd@public.gmane.org>
2016-08-10 11:39 ` Jarkko Sakkinen
2016-07-12 12:27 (No subject) Julien CARBONNIER
2016-06-29 6:16 (no subject) Jason Gunthorpe
2016-06-28 10:54 Xieyingtai
2016-04-12 22:52 Nichole Neeley
2016-03-18 16:55 (No subject) Nagi Chitta Reddy
2016-03-19 2:19 ` Zhenhua Luo
2016-02-23 0:55 Joe MacDonald
2016-01-07 5:34 Baokang.Huang(黄宝亢)
[not found] <CABRndgzjgufnXE7_0Erp=B2P-5j3w4nZFhShn8V5oqGxd8PPaw@mail.gmail.com>
2015-11-27 4:28 ` (no subject) Philippe Proulx
2015-11-27 3:20 Zvi Vered
2015-07-30 22:16 (No subject) Edward Vidal
2015-07-14 15:24 Alvaro Martinez Tovar
2015-07-15 10:59 ` Felipe Tonello
2015-07-14 5:56 Alvaro Martinez Tovar
2015-08-13 17:40 ` Khem Raj
2015-06-30 10:50 (no subject) E.Richiardone
[not found] <1433789441-8295-1-git-send-email-david.s.gordon@intel.com>
2015-06-12 17:09 ` [PATCH v2] Resolve issues with ringbuffer space management Dave Gordon
2015-06-12 17:09 ` [PATCH 2/2] drm/i915: Rework order of operations in {__intel, logical}_ring_prepare() Dave Gordon
2015-06-12 20:25 ` (no subject) Dave Gordon
2015-06-17 11:04 ` Daniel Vetter
2015-06-17 12:41 ` Jani Nikula
2015-06-18 10:30 ` Dave Gordon
2015-06-10 5:30 (No subject) Sharath M.
2015-06-10 12:21 ` Daiane Angolini
[not found] <CAG4vvd49JfNUgN9p9vW0bQXoRkBjER74zVbTAg-CmtETZeDn2Q@mail.gmail.com>
2015-05-14 21:14 ` (no subject) Simon Marchi
[not found] ` <CAFXXi0kf0aWS7vS9m8HmdPoXR3RL=bjtaL_y+coR7T2npE=eWQ@mail.gmail.com>
2015-05-16 15:35 ` Alexandre Montplaisir
2015-05-14 19:33 Francis Rivest
2015-04-14 10:10 Mika Kahola
2015-03-08 19:00 (No subject) Rickard Bremer
2015-03-02 12:39 Raghavendra Kakarla
2015-01-09 12:32 Debasmita Lohar
2015-01-02 9:29 (no subject) arivumani
2014-12-15 20:23 (No subject) Fabrício Lélis
2014-12-08 19:36 (no subject) dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-12-08 19:36 dev-bounces-VfR2kkLFssw
2014-11-14 16:40 Angelo Dureghello
2014-11-14 14:23 (No subject) Otavio Salvador
2014-11-09 1:18 (no subject) saulery
2014-09-22 15:10 Cleveland Finance
2014-09-13 15:24 asd
[not found] ` <20140913182452.45609099-jrA/B3VWHiL2D7C+UIOg5A@public.gmane.org>
2014-09-13 15:32 ` Ilia Mirkin
[not found] ` <CAKb7UvgnwZAUq1GMcNJBmSyH3Me2=ooKhDOPrgAes6TCbHMBHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-09-13 15:39 ` Martin Peres
2014-08-15 12:56 arivumani
2014-08-07 12:34 (No subject) Modemtec Modemtec
2014-08-05 21:20 (no subject) James McCammond
2014-07-23 10:50 这是发件人姓名
2014-07-16 3:26 (No subject) Shan Hai
2014-07-11 14:54 Philip Balister
2014-07-12 4:55 ` Khem Raj
2014-07-02 6:50 Himanshu Pandey
2014-06-25 18:28 Anand Moon
2014-05-30 4:05 Kashyap Gada
2014-05-27 9:36 hari prasad
2014-05-27 9:55 ` zhenhua.luo
2014-05-27 12:46 ` Otavio Salvador
2014-05-27 12:50 ` Daiane.Angolini
2014-05-26 4:36 hari prasad
2014-05-22 15:46 hari prasad
2014-05-22 16:05 ` Otavio Salvador
2014-05-23 6:07 ` zhenhua.luo
2014-05-18 19:54 hari prasad
2014-05-19 9:46 ` zhenhua.luo
2014-05-19 10:17 ` hari prasad
2014-05-19 10:29 ` zhenhua.luo
2014-02-04 14:18 (no subject) Валентин Сайков
[not found] <CA+knAyLjni_imS1h=+==+Gqax9ZAQu0k5Wxi0ztjph_J=LZJWw@mail.gmail.com>
2014-01-22 2:30 ` Suchakrapani Datt Sharma
2014-01-22 13:39 ` Simon Marchi
[not found] ` <CAFXXi0=xW=2CKSgcJuRZCx3MzTE-_gtxEm+kM+cM1LFWcHu=Wg@mail.gmail.com>
2014-01-22 20:01 ` Mehran Khan
2014-01-21 23:34 Mehran Khan
2014-01-21 16:38 [PATCH] drm/i915: (VLV2) Fix the hotplug detection bits Todd Previte
2014-01-23 4:22 ` (no subject) Todd Previte
2013-12-30 2:29 Oravil Nair
2014-01-07 7:32 ` Daniel Vetter
2013-12-13 13:39 (No subject) Flanagan, Elizabeth
2013-11-19 17:43 Jacob Kroon
2013-11-19 18:30 ` Jacob Kroon
2013-10-19 17:23 Otavio Salvador
2013-10-08 14:19 João Henrique Freitas
2013-10-08 19:42 ` Denys Dmytriyenko
2013-10-01 14:24 "Kernel access of bad area" in kernel module Jack
2013-10-01 14:39 ` Anders Darander
2013-10-03 7:47 ` (No subject) Jack
2013-10-04 17:55 ` Anders Darander
2013-10-10 7:07 ` Jack
2013-09-11 4:54 arun kumar
2013-08-18 10:37 Andy Ng
2013-08-05 8:38 (no subject) Chih-Chung Chang
2013-07-31 15:07 (No subject) Joe MacDonald
2013-06-02 11:27 [No subject] Giovane
[not found] <CAEyVMbDjLwcDFrQ7y4UtGp7HOT1wi5MB2EWLGTuOdJCKDWsUew@mail.gmail.com>
2013-04-03 15:46 ` (no subject) Daniel Vetter
2013-03-19 7:57 (No subject) Florin Cristian Dan
2013-03-06 14:55 Tarek El-Sherbiny
2013-02-26 20:04 (no subject) pedro noticioso
2013-02-22 18:18 (No subject) Jeremy Stashluk
2013-02-12 0:14 Belisko Marek
2013-02-12 0:14 Belisko Marek
2013-02-12 7:37 ` Iorga, Cristian
2013-02-12 8:22 ` Andrei Gherzan
2013-01-23 15:12 Belal, Awais
2013-01-21 10:49 Mike Looijmans
2013-01-21 11:26 ` Richard Purdie
2013-01-18 23:13 Carrillodominguez Francisco Alberto-B35153
2013-01-18 23:23 ` Otavio Salvador
2013-01-18 23:24 ` Eric Bénard
2013-01-05 10:25 (no subject) mnccsm-b2MIaZL8fbqsTnJN9+BGXg
2012-12-08 3:21 艾祝
2012-12-06 9:49 (No subject) Lukas Bulwahn
2012-11-27 8:45 GOPIKRISHNAN S
2012-11-27 17:02 ` McClintock Matthew-B29882
2012-11-28 7:22 ` Luo Zhenhua-B19537
2012-11-29 5:56 ` GOPIKRISHNAN S
2012-11-29 7:17 ` Luo Zhenhua-B19537
2013-03-01 6:00 ` McClintock Matthew-B29882
2012-11-19 20:39 (no subject) Stefan Priebe
2012-11-12 0:48 (No subject) Ilya Dmitrichenko
2012-10-05 11:48 (no subject) ABN AMRO
2012-10-05 11:48 ` ABN AMRO
[not found] <s5hmx1526mg.wl%tiwai@suse.de>
2012-09-06 6:02 ` Markus Trippelsdorf
2012-09-06 6:33 ` (no subject) Daniel Mack
2012-09-06 6:48 ` Takashi Iwai
2012-08-17 12:36 xuluqxulu
2012-08-05 19:48 (No subject) Javier Martinez Canillas
2012-08-06 14:59 ` Richard Purdie
2012-07-19 20:00 (no subject) Olivier Galibert
2012-07-17 16:16 (No subject) Ross Burton
2012-07-03 21:08 Mikhail Boiko
2012-06-23 15:23 (no subject) sindu sindhu
2012-06-21 21:36 (No subject) Andreas Müller
2012-06-22 9:34 ` Henning Heinold
2012-05-31 18:00 (no subject) Muhammad Jamil
2012-05-07 20:13 sabah halif
2012-05-01 7:57 (No subject) Craig McQueen
2012-05-01 11:00 ` Radoslav Kolev
2012-04-12 0:55 (no subject) Rodrigo Vivi
2012-04-08 2:26 Muhammad Jamil
2012-04-05 6:44 Muhammad Jamil
2012-04-03 18:25 Muhammad Jamil
2012-04-03 12:42 Muhammad Jamil
2012-02-21 22:33 (No subject) Andrei Gherzan
2012-02-15 12:06 Hauser, Wolfgang (external)
2011-11-05 1:45 (no subject) Tarak Ranjan
2011-10-20 0:17 Mikulas Patocka
2011-10-09 22:40 Maxim Levitsky
2011-09-08 10:20 A S
2011-09-08 11:03 ` Clemens Ladisch
[not found] <4a795deb3789430487146a8425c1c337@DLEE74.ent.ti.com>
2011-08-27 4:38 ` (No subject) Joel A Fernandes
2011-08-27 7:11 ` Koen Kooi
2011-08-27 3:26 Joel A Fernandes
2011-08-27 7:07 ` Koen Kooi
2011-07-01 2:28 Fan, WenhuaX
2011-06-14 14:53 Bruce Ashfield, Bruce Ashfield
2011-06-04 10:10 (no subject) ©2011.Coca-Cola Great Britain
2011-06-04 9:32 ©2011.Coca-Cola Great Britain
2011-06-04 9:31
2011-06-04 9:31 ` ©2011.Coca-Cola Great Britain
2011-06-04 9:31 ©2011.Coca-Cola Great Britain
2011-06-04 9:31 ©2011.Coca-Cola Great Britain
2011-06-04 9:30
2011-06-04 9:30 ©2011.Coca-Cola Great Britain
2011-06-04 9:30 ©2011.Coca-Cola Great Britain
2011-06-04 9:21 ©2011.Coca-Cola Great Britain
2011-06-04 9:20 ©2011.Coca-Cola Great Britain
2011-05-27 19:12 Swastik Das
2011-05-25 18:38 ©2011.Coca-Cola Great Britain
2011-05-25 18:38 ©2011.Coca-Cola Great Britain
2011-05-25 18:38 ©2011.Coca-Cola Great Britain
2011-05-25 18:38 ©2011.Coca-Cola Great Britain
2011-05-25 18:36 ©2011.Coca-Cola Great Britain
2011-05-01 7:56 Dan Carpenter
2011-05-01 8:02 ` Dan Carpenter
2011-04-28 18:33 [PATCH 0/2] safer reclocking take 2 Martin Peres
[not found] ` <1304015622-5910-1-git-send-email-martin.peres-GANU6spQydw@public.gmane.org>
2011-04-30 0:17 ` (no subject) Martin Peres
2011-04-28 5:35 [PATCH 0/1] Resend:[Image-Creator]Make bitbake server type configurable (xmlrpc, none) Liping Ke
2011-04-28 5:35 ` (No subject) Liping Ke
2011-04-14 18:13 forcewake v4 (now with spinlock) Ben Widawsky
2011-04-14 18:13 ` (no subject) Ben Widawsky
2011-04-11 2:20 TONY KINGS
2011-04-11 2:18 TONY KINGS
2011-04-11 2:15 TONY KINGS
2011-04-11 2:08 TONY KINGS
2011-04-08 17:47 forcewake junk, RFC, RFT(test) Ben Widawsky
2011-04-09 20:26 ` forcewake junk, part2 Ben Widawsky
2011-04-09 20:26 ` (no subject) Ben Widawsky
2011-04-07 21:32 Jesse Barnes
2011-03-01 17:45 (No subject) Denis 'GNUtoo' Carikli
2011-03-01 18:25 ` Denis 'GNUtoo' Carikli
2011-03-01 14:02 (no subject) Javier Martin
2010-11-10 18:10 Russell Cattelan
2010-11-09 9:17 [PATCH] drm/i915/ringbuffer: set force wake bit before reading ring register Zou Nan hai
2010-11-09 9:17 ` Zou, Nanhai
2010-11-09 10:50 ` Chris Wilson
2010-11-10 0:36 ` Zou, Nanhai
2010-11-10 7:54 ` Chris Wilson
2010-11-10 18:47 ` Jesse Barnes
2010-11-17 22:52 ` (no subject) Thantry, Hariharan L
2010-10-16 23:39 RODNEY BINGHAM
2010-10-06 3:28 Mrs. Habiba Miller
2010-09-13 19:47 [PATCH 00/25] treewide-next: Use static const char arrays Joe Perches
2010-09-14 9:14 ` (no subject) David Howells
2010-09-14 9:14 ` David Howells
2010-09-08 7:25 asim khan
2010-09-02 11:58 lode leroy
2010-09-02 13:17 ` BVK Chaitanya
2010-09-02 13:18 ` BVK Chaitanya
2010-08-24 13:15 Runtime power management during system resume Raj Kumar
2010-08-24 14:30 ` Alan Stern
2010-08-24 15:17 ` Raj Kumar
2010-08-25 13:27 ` Raj Kumar
2010-08-26 13:40 ` Raj Kumar
2010-09-18 11:49 ` (no subject) Raj Kumar
2010-07-29 10:44 (No subject) Soumya R
2010-07-16 13:40 (no subject) Tom H
2010-07-01 10:19 (No subject) Soumya R
2010-07-01 19:04 ` Khem Raj
2010-07-02 2:50 ` Soumya R
2010-06-14 20:26 [PATCH 0/8] Fix gcc 4.6.0 set but not used warning messages Justin P. Mattock
2010-06-14 20:26 ` [PATCH 7/8]ieee1394/sdp2 Fix warning: variable 'unit_characteristics' set but not used Justin P. Mattock
2010-06-14 21:44 ` [PATCH] ieee1394: sbp2: remove unused code Stefan Richter
2010-06-14 22:35 ` Justin P. Mattock
2010-06-14 23:22 ` Stefan Richter
2010-06-15 0:08 ` (no subject) Stefan Richter
2010-06-12 11:46 (No subject) "Andreas Müller"
2010-06-10 5:56 Soumya R
2010-06-10 6:29 ` Frans Meulenbroeks
2010-06-08 8:22 Soumya R
2010-06-08 14:09 ` Khem Raj
2010-06-02 9:19 Soumya R
2010-06-02 15:41 ` Hodgson, Simon
2010-06-03 2:37 ` Soumya R
2010-06-03 5:10 ` Khem Raj
2010-06-03 8:24 ` Hodgson, Simon
2010-10-29 11:43 ` Nick Lee
2010-06-03 12:13 ` Soumya R
2010-06-03 12:59 ` Nicolas Ferre
2010-05-12 14:05 (no subject) carlopmart
2010-04-21 2:00 bgamari.foss
2010-04-13 14:38 Sascha Hauer
2010-03-01 14:46 (No subject) majo huber
2010-02-15 19:39 (no subject) "Alexander Jölly"
2010-02-20 11:06 ` Vladimir 'φ-coder/phcoder' Serbinenko
2010-01-23 10:54 (No subject) saleh usman
2010-01-20 19:47 (no subject) Ben Gamari
2010-01-21 0:04 ` Ben Dooks
2009-12-14 23:44 Mr Mou Xinsheng
2009-12-13 20:22 Darrell
2009-12-11 5:31 Mikulas Patocka
2009-11-17 15:34 Mike Snitzer
2009-11-11 15:38 Roger Cruz
2009-11-04 14:36 evgen
2009-10-28 23:23 Noah Watkins
2009-10-29 0:42 ` Sage Weil
2009-10-29 0:51 ` Noah Watkins
2009-10-29 0:55 ` Noah Watkins
2009-10-29 3:12 ` Sage Weil
2009-10-24 19:42 Vikram Dhillon
[not found] <87k4z79b9p.fsf_-_@twilight.int.mornfall.net>
2009-10-08 1:37 ` Dave Wysochanski
2009-10-03 5:02 debmail_5f63g
2009-09-22 11:46 Delusion's Master
2009-09-21 13:39 David Howells
2009-09-24 12:04 ` Robert Millan
2009-09-28 12:39 ` David Howells
2009-09-11 17:14 Hyundai
2009-09-07 16:43 the uknl
2009-08-24 19:35 MRS SANDRA WHITE
2009-08-23 17:49 INFO
2009-08-11 21:02 Chaithrika U S
2009-08-11 11:36 ` chaithrika
2009-08-03 13:18 (No subject) Gregory Machairidis
2009-08-03 10:14 (no subject) kell
2009-07-17 12:02 UK
2009-07-17 4:17 CG LOTTO
2009-07-13 23:56 Camelot Group.
2009-07-10 21:36 The UKNL
2009-07-09 7:20 UKNL
2009-07-09 2:20 UKNL
2009-07-02 14:23 The British
2009-06-30 1:16 Mrs Dianne Thompson
2009-06-30 1:16 Mrs Dianne Thompson
2009-06-29 19:56 Uknl
2009-06-25 17:09 Robert Randall
2009-06-23 16:08 UNL
2009-06-23 2:55 UKL-DEPT
2009-06-21 13:34 The Nat
2009-06-11 22:44 Rafael J. Wysocki
2009-06-11 21:48 Rafael J. Wysocki
2009-06-09 18:04 IL
2009-06-09 3:17 (No subject) Rolf Leggewie
2009-06-09 3:26 ` Rolf Leggewie
2009-06-09 3:29 ` Rolf Leggewie
2009-06-05 10:41 (no subject) Mike Brodbelt
2009-06-01 11:20 Mnl
2009-05-30 1:23 James Gardiner
2009-05-30 7:01 ` Takashi Iwai
2009-05-29 16:03 CG
2009-05-29 13:14 Camelot Uk
2009-05-29 11:53 Camelot Uk
2009-05-28 4:26 CL
2009-05-28 1:44 Cgnlwin
2009-05-26 18:10 Mnl
2009-05-26 11:35 Mnl
2009-05-25 23:57 Mnl
2009-05-25 18:02 IL
2009-05-23 18:14 Cgnlwin
2009-05-23 18:14 ` Cgnlwin
2009-05-23 13:28 Cgnlwin
2009-05-23 11:09 Mnl
2009-05-23 11:09 Mnl
2009-05-18 15:18 Mnl
2009-05-18 15:12 Mnl
2009-05-18 15:12 Mnl
2009-05-18 12:20 Mnl
2009-05-18 12:16 Mnl
2009-05-18 12:16 Mnl
2009-05-18 9:59 Mnl
2009-05-18 8:58 Mnl
2009-05-16 4:56 il
2009-05-15 14:29 il
2009-05-15 14:29 il
2009-05-09 1:50 IL
2009-03-27 6:56 xrun on sdp340 with small buffers Jarkko Nikula
2009-03-27 13:32 ` (no subject) Jarkko Nikula
2009-03-27 16:31 ` Mark Brown
2009-03-19 17:59 (No subject) Theodore A. Roth
2009-02-20 11:24 (no subject) Thomas Woerner
2008-12-08 21:03 Paul L
[not found] ` <856033f20812081303v12353110jf51704b81d2a760-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2008-12-09 11:20 ` Ryusuke Konishi
[not found] ` <20081209.202059.122418779.ryusuke-sG5X7nlA6pw@public.gmane.org>
2008-12-09 16:16 ` Paul L
[not found] ` <856033f20812090816l183c974dj9eed760b3deedb8c-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2008-12-10 2:31 ` Ryusuke Konishi
2008-11-24 13:09 Nitin Mahajan
2008-11-20 13:10 Nitin Mahajan
2008-11-18 8:18 Bryan Wu
2008-11-18 11:45 ` (no subject) Mark Brown
2008-11-18 7:52 Bryan Wu
2008-11-17 23:24 Fernando Moro
2008-11-11 2:43 Yang, Libin
2008-11-11 8:17 ` Takashi Iwai
2008-10-14 12:16 Philippe CARRIERE
2008-10-13 10:51 Philippe CARRIERE
2008-10-13 14:28 ` Takashi Iwai
2008-10-14 9:54 ` Karsten Wiese
2008-10-14 10:41 ` Philippe Carriere
2008-10-14 11:29 ` Karsten Wiese
2009-01-27 0:16 ` Karsten Wiese
2009-01-29 8:35 ` Philippe Carriere
2008-09-30 2:17 Peter Leckie
2008-07-28 15:01 Ben Dooks
2008-07-12 22:31 Kevin Phair
2008-07-09 20:44 Jesper Krogh
2008-05-15 4:15 林先生
2008-05-03 4:01 林先生
2008-04-23 18:50 Jim Carter
2008-04-23 20:04 ` Jeff Moyer
2008-04-24 3:10 ` Ian Kent
2008-04-21 18:21 George Shammas
2008-04-19 21:53 钟文辉
2008-04-14 9:01 钟文辉
2008-04-14 8:55 钟文辉
2008-04-14 8:49 钟文辉
2008-04-13 14:24 钟文辉
2008-04-13 14:13 钟文辉
2008-04-13 6:20 钟文辉
2008-04-13 5:42 钟文辉
2008-04-09 22:40 钟文辉
2008-04-09 22:32 钟文辉
2008-04-06 12:47 [PATCH] x86: remove superfluous initialisation in boot code Alexander van Heukelum
2008-04-07 7:46 ` Ingo Molnar
2008-04-07 9:13 ` Alexander van Heukelum
2008-04-07 10:00 ` (no subject) zhenwenxu
2008-04-04 23:46 Clint Moore
2008-04-03 22:53 badguy development
2008-04-03 8:47 郝舜
2008-04-03 8:56 ` Clemens Ladisch
2008-03-31 9:59 钟文辉
2008-03-23 21:10 钟文辉
2008-03-23 19:49 钟文辉
2008-03-10 14:36 (No subject) Lele
[not found] <EC2127EFF67248B9B1F7F34B45F74E55@Main>
[not found] ` <B84B1606A0264FA18CBE236F84E6CE96@Main>
2008-02-21 10:51 ` Ответы для Linux Format Serge A. Suchkov
2008-02-21 12:13 ` (no subject) Serge A. Suchkov
2008-02-01 18:14 veerasena reddy
2008-02-04 5:41 ` Ramgopal Kota
2008-01-22 0:00 Thiemo Seufer
2008-01-16 18:38 Jed Davidow
2008-01-12 13:45 Abhishek Gupta
2008-01-12 14:55 ` Steve Grubb
2008-01-04 14:00 Cristian
2008-01-03 8:33 Awad, Sinan (GE Healthcare)
2008-01-03 10:34 ` (no subject) Misbah khan
2007-12-18 4:09 Yu Fei
2007-12-04 17:29 余上
2007-11-25 2:10 Thomas Bogendoerfer
2007-11-11 13:08 (unknown) Michael Dressel
2007-11-11 15:22 ` (no subject) Johannes Schindelin
2007-11-08 15:36 Willis
2007-11-02 16:21 Bill Tangren
2007-11-01 20:27 张先生
2007-10-31 20:59 immanuel lily
2007-10-26 21:38 『晴れたらいいね』
2007-10-19 3:44 Neil Brown
2007-10-09 20:03 蔡先生
2007-10-09 19:28 蔡先生
2007-10-09 17:05 蔡先生
2007-10-09 15:29 蔡先生
2007-10-09 6:59 Donna Lackey
2007-10-08 18:35 蔡先生
2007-10-08 18:29 蔡先生
2007-10-08 18:16 蔡先生
2007-10-08 17:06 蔡先生
2007-10-06 23:59 蔡先生
2007-10-06 19:30 蔡先生
2007-10-06 15:33 蔡先生
2007-10-06 10:34 蔡先生
2007-10-06 10:03 蔡先生
2007-10-06 9:53 蔡先生
2007-10-05 16:24 Aline Edmonds
2007-10-02 15:49 蔡先生
2007-10-02 14:33 蔡先生
2007-10-02 5:55 蔡先生
2007-09-22 14:05 蔡先生
2007-09-13 3:08 Dong, Eddie
2007-09-07 22:19 Jim Cromie
2007-09-06 5:57 Krzysztof Helt
2007-09-06 13:14 ` Takashi Iwai
2007-08-21 19:54 Melgar
2007-08-21 19:43 Joeann Moyini
2007-08-21 16:23 CeDarlyn Pellikka
2007-08-21 14:43 Springs
2007-08-21 11:54 tahir Laanemets
2007-08-21 9:51 shirlee Taruc
2007-08-21 0:01 holley
2007-08-20 19:08 Gmagm sssssssssssa
2007-08-18 17:02 Henning, Arthur C. (CSL)
2007-08-18 10:00 Guzman
2007-08-18 9:54 aanidi-CYedFwHYa5iBl8o7nT1L3dBPR1lH4CV8
2007-08-13 13:48 Tony Lindgren
2007-08-13 13:58 ` Felipe Balbi
2007-08-12 19:59 Izik Eidus
[not found] ` <64F9B87B6B770947A9F8391472E032160CBECF40-yEcIvxbTEBqsx+V+t5oei8rau4O3wl8o3fe8/T/H7NteoWH0uzbU5w@public.gmane.org>
2007-08-12 21:37 ` Anthony Liguori
2007-08-13 8:10 ` Avi Kivity
2007-08-14 10:38 ` Carsten Otte
2007-08-10 7:30 Reza schutter
2007-08-10 7:16 grikxd
2007-08-09 17:27 Harlan Kellis
2007-08-08 20:15 采购成本降低技巧及供应商管理
2007-08-07 4:23 Jean
2007-08-06 13:45 Piotr Kandziora
2007-08-02 7:24 Piotr Kandziora
2007-08-02 15:45 ` Jeff Layton
2007-08-02 0:08 Mahoney O.Becky
2007-07-30 7:24 Trujillo
2007-07-29 23:52 Hooper
2007-07-29 15:40 Vivien Gilmore
2007-07-29 10:02 Neville
2007-07-29 0:46 Smartschan
2007-07-28 23:39 Hendrickson L. Maggie
2007-07-28 23:39 Watkins S. Valentine
2007-07-28 10:24 White
2007-07-27 16:05 Agatha C. Walter
2007-07-27 11:17 Stacy Lilly
2007-07-27 7:35 Blanchard R. Tim
2007-07-27 4:03 Frederick
2007-07-26 9:27 Olive Crosby
2007-07-26 0:16 Carlton
2007-07-25 14:36 Eldridge
2007-07-24 14:42 Dennis
2007-07-24 14:41 Bella
[not found] <FC1D1B23302A22499C60C967336B2AE00186B15C@pdsmsx411.ccr.corp.intel.com>
[not found] ` <FC1D1B23302A22499C60C967336B2AE00186B15C-wq7ZOvIWXbNpB2pF5aRoyrfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2007-07-24 13:40 ` Shaohua Li
2007-07-24 10:54 Walter
2007-07-23 15:08 Riley
2007-07-23 15:08 Santiago
2007-07-21 23:57 Mathilda S. Corbett
2007-07-21 8:25 Joachim B.Byrne
2007-07-21 5:45 Sandy Holloway
2007-07-20 19:48 Cohen Micky
2007-07-20 8:13 Dong, Eddie
2007-07-20 8:11 Dong, Eddie
2007-07-20 4:13 Palmer
2007-07-18 7:02 Persy
2007-07-18 7:02 Gwendolyn
2007-07-18 4:09 Glenn
2007-07-17 22:39 Mark Levedahl
2007-07-16 13:20 Marshall
2007-07-16 9:48 Riccardo Bini
2007-07-16 0:06 Hull N.Flossie
2007-07-14 14:24 Cummings
2007-06-20 9:00 sun lu
2007-06-08 7:53 Nicklas Bondesson
2007-06-07 17:05 [PATCH] locks: provide a file lease method enabling cluster-coherent leases J. Bruce Fields
2007-06-08 22:14 ` (no subject) J. Bruce Fields
2007-06-05 0:32 Xyber Blue
2007-05-24 14:03 Kirkwood, David A.
2007-05-09 7:01 ashok.shanmugam
2007-04-24 16:25 Fabio Olive Leite
2007-04-20 22:13 paul moore
2007-04-20 22:13 ` paul moore
2007-04-20 23:32 ` Steve Grubb
2007-04-21 0:24 ` paul moore
2007-04-21 0:24 ` paul moore
2007-04-23 13:46 ` Steve Grubb
2007-04-16 6:10 xfwolf
2007-04-11 13:13 Jojo Keiser
2007-04-08 10:40 Maung Nadir Ali
2007-03-15 19:42 Kirkwood, David A.
2007-03-15 21:15 ` Bill Tangren
2007-03-09 12:28 Sutton O. Javelin
2007-03-09 6:48 Empty V. Crock
2007-03-08 16:58 Giggler S. Defeatist
2007-03-08 0:13 Arjuna H. Settlement
2007-03-07 8:58 Cutlasses M. Greek
2007-03-07 2:38 Flickering E. Sharps
2007-03-06 19:35 Rational K. Haggard
2007-03-06 15:57 Redeeming T. Angus
2007-02-28 0:11 Orient K. Underpinnings
2007-02-27 8:42 Depreciates F. Sum
2007-02-27 4:07 Whispers F. Charlie
2007-02-20 1:21 Dr.Friedrick Conway
2007-02-17 11:14 Dr.Hank Miles
2007-02-17 1:20 Dr.Aaron Barrera
2007-02-15 19:58 Nautilus S. Womb
2007-02-15 11:54 ddup1
2007-02-13 22:04 Dear Sir Madam
2007-02-01 9:19 ddup1
2007-02-01 6:55 COM CYCL
2007-01-31 19:06 operators country
2007-01-30 19:51 Karsten Wiese
2007-01-31 9:22 ` Takashi Iwai
2007-01-26 7:29 orig
2007-01-25 20:50 Craig Van Tassle
2007-01-23 1:12 Establishes S. Adoption
2007-01-21 15:47 Maisie T. Deathblow
2007-01-12 3:00 Barracuda K. Bobbi
2007-01-10 10:53 Acid P. Hank
2007-01-10 3:03 Timezone D. Authenticity
2007-01-06 4:15 Lintel E. Late
2007-01-05 20:41 Princeton F. Aligns
2007-01-05 10:44 Wot V. Armband
[not found] <JAMB7R$1E04724C7A33DA4578A20ADF8AC469B0@libero.it>
2006-12-21 15:03 ` Clemens Ladisch
2006-12-19 9:20 Niyanth, Venkata
2006-12-19 17:24 ` Tony Lindgren
2006-12-16 14:17 tardo2002
2006-12-18 9:53 ` Clemens Ladisch
2006-12-04 7:01 miki
2006-11-26 3:25 Glenn K. Transporting
2006-11-24 22:41 Generality O. Lifeblood
2006-11-24 10:44 Proponent V. Stepbrother
2006-11-24 4:07 Scrounger D. Aboded
2006-11-24 1:17 Profanation R. Meandering
2006-11-23 18:13 Groins O. Animation
2006-11-22 1:27 Variance P. Whirled
2006-11-21 13:26 Tim Edwards
2006-11-21 10:44 Tim Edwards
2006-11-21 10:54 ` Bernd Petrovitsch
2006-11-21 9:25 Tim Edwards
2006-11-21 10:13 ` Bernd Petrovitsch
2006-11-20 8:18 Tamil E. Turnoffs
2006-11-15 10:46 Doctor
2006-11-13 14:19 Doctor
2006-11-12 10:26 Rectums C. Palate
2006-11-12 6:26 Antonio Sampayo
2006-10-31 19:37 Isabel Decker
2006-10-30 10:40 Doctor
2006-10-30 2:57 Kaleb D. Tuimala
2006-10-30 2:45 Doctor
2006-10-28 22:25 Garbs H. Pecan
2006-10-28 19:35 ATA YAZILIM A.Þ.
2006-10-27 14:44 Skelhorn.RJC
2006-10-20 16:55 (Was Re: [Alsa-user] Poorly supported HDA intel) Ricardo Cerqueira
2006-10-20 17:16 ` Ricardo Cerqueira
2006-10-24 19:08 ` (no subject) Thierry Vignaud
2006-10-19 3:24 misato
2006-10-19 1:28 Thomas Sandquist
2006-10-18 6:57 James Templeton
2006-10-09 23:13 albox
2006-10-07 12:41 yuki
2006-10-04 1:18 miyuki
[not found] <200609260011.28160.lucke@o2.pl>
2006-09-25 22:23 ` lucke
2006-09-16 12:15 yukihana
2006-09-16 9:11 Laurent CARON
2006-09-16 9:10 Laurent CARON
2006-09-14 11:02 Tim Kirk
2006-09-14 14:00 ` Dave Wysochanski
[not found] ` <20060914134154.GC6045@jam.ts>
2006-09-14 22:05 ` Darrick J. Wong
2006-09-15 19:36 ` ted creedon
2006-09-11 3:38 qinping
2006-09-11 2:58 yukaridayo
2006-08-10 7:19 richard
2006-08-03 8:25 Franck Bui-Huu
2006-07-26 10:47 Bernd Schubert
2006-07-26 11:43 ` Trond Myklebust
2006-07-12 16:07 gary douglas
2006-07-14 9:55 ` Rob Sterenborg
2006-07-08 22:27 潘思广
2006-07-06 12:21 Jochen Maes
2006-07-05 8:39 Petronenko Denis
2006-06-27 3:26 Paulo Cordeiro
2006-06-22 8:46 legwpjv
2006-06-17 12:56 cycrypxz
2006-06-15 5:07 icjoqtc
2006-06-10 5:03 Rita Bruce
2006-06-05 19:48 process starvation with 2.6 scheduler Kallol Biswas
2006-06-05 23:49 ` (no subject) Hack Sung Lee
2006-05-14 12:57 [No Subject] Arnulfo Titor
2006-05-05 1:37 (no subject) OcHe
2006-05-06 23:25 ` Eric Shattow
2006-05-10 17:26 ` Clemens Ladisch
2006-05-03 17:21 Kirkwood, David A
2006-05-03 17:31 ` Steve Grubb
2006-04-26 2:23 Nichole
2006-04-14 15:02 Javier Ruano
2006-04-14 15:28 ` Jan-Benedict Glaw
2006-04-15 5:47 ` Knut Petersen
2006-03-19 13:05 汇嘉宏
2006-03-14 14:27 Nick Dvoeglazov
2006-03-10 13:57 Selmeci, Tamas
2006-02-21 12:41 rasmit.ranjan
2006-02-14 14:02 Mark L. Wise
2006-01-24 6:59 Yu, Luming
2006-01-18 6:49 Ian Kent
2006-01-18 6:48 Ian Kent
2006-01-18 6:48 Ian Kent
2006-01-18 6:48 Ian Kent
2006-01-18 6:48 Ian Kent
2006-01-17 21:37 Jonas Lihnell
2006-01-17 21:41 ` Trond Myklebust
2006-01-17 22:18 ` Jonas Lihnell
2006-01-10 17:13 Nicolas Turro
2006-01-11 15:08 ` Amitabh Kant
2006-01-10 13:24 Daniel Mack
2006-01-10 17:07 ` Takashi Iwai
2006-01-10 19:12 ` Clemens Ladisch
2006-01-11 11:29 ` Daniel Mack
2006-01-07 4:16 Chaitanya Vinay Hazarey
2006-01-05 16:16 Pedro Venda
[not found] <20051227010004.D4C7568950@ozlabs.org>
2005-12-27 15:29 ` siman
2005-12-07 10:44 Ramani Karuppiah
2005-12-03 18:40 Otavio Salvador
2005-11-30 5:56 [GIT PATCH] USB patches for 2.6.15-rc3 Greg KH
2005-11-30 18:23 ` Linus Torvalds
2005-11-30 19:35 ` Greg KH
2005-12-01 4:10 ` (no subject) Glenn L Shurson
2005-11-18 16:05 Andi Kleen
2005-11-21 10:06 ` (no subject) Keir Fraser
2005-11-21 10:11 ` Russell King
2005-11-21 17:27 ` Andi Kleen
2005-11-14 21:58 Kyle Perkins
2005-11-02 1:02 Zhao Yu,SCNB R&D NNA(BJ)
2005-11-01 7:21 Zhao Yu,SCNB R&D NNA(BJ)
2005-11-01 12:17 ` Yoshinori K. Okuji
2005-10-31 11:11 Yasuyuki KOZAKAI
2005-11-01 17:47 ` Patrick McHardy
2005-10-20 16:05 Korolev, Alexey
2005-10-06 8:11 Amresh Kumar
2005-10-06 8:22 ` Vinod Chandran
2005-10-06 8:26 ` Rob Sterenborg
2005-10-04 12:24 Doug McLain
2005-10-03 1:00 Bob Brose
2005-10-03 7:07 ` Andreas Schwab
2005-09-27 13:53 ÏÄÓê
2005-09-27 16:07 ` Wolfgang Denk
2005-09-22 14:05 Heyman, Michael
2005-09-22 14:31 ` Henrik Nordstrom
2005-09-22 12:39 difference between syn and NEW Subramanian
2005-09-22 13:39 ` (no subject) Bernd Lippert
2005-09-21 18:35 Ryan Olejnik
2005-09-21 11:29 Heyman, Michael
2005-09-22 8:01 ` Henrik Nordstrom
2005-09-15 13:22 Konstantin Kletschke
2005-09-10 18:19 James Strickland
2005-08-30 13:21 Yasuyuki KOZAKAI
2005-08-24 22:15 netfilter
2005-08-24 22:40 ` Daniel Lopes
2005-08-25 11:55 ` Chris Notley
2005-07-29 7:22 Armil
2005-07-23 4:50 Mr.Derrick Tanner.
2005-07-18 12:06 murasfdg sjhfsd
[not found] <20050710124100.D643673691@tux.linux.ee>
2005-07-12 19:50 ` Kaupo Arulo
2005-07-10 12:40 樊亮
2005-07-05 12:13 Brent Clark
2005-07-03 2:47 Amit Sharma
2005-07-03 12:04 ` Artem B. Bityuckiy
2005-06-29 6:21 董晓凡
2005-06-29 16:22 ` evilninja
2005-06-27 12:25 FLAMENT David
2005-06-21 14:48 David L
2005-06-20 7:08 dierbro
2005-06-16 8:03 faton kurteshi
2005-06-13 11:38 colui77
2005-05-22 16:05 Pedro Henrique
2005-05-22 12:40 Timo Hallek
2005-05-21 3:08 bright true
2005-05-21 18:16 ` Jason Opperisano
2005-05-21 5:18 ` bright true
2005-05-21 19:31 ` Jason Opperisano
2005-05-21 18:01 ` bright true
2005-05-21 1:25 haf
2005-05-20 10:39 haf
2005-05-18 7:56 suzuki
2005-05-10 7:00 Mateusz
2005-04-26 4:20 Frederic Weisbecker
2005-04-18 16:31 Davide Rossetti
2005-04-15 22:34 David Richards
2005-04-12 19:38 Eric N. Johnson (ACD)
2005-04-12 21:13 ` Wolfgang Denk
2005-04-01 9:16 Mar. Ca. Gian Luca Zamboni
2005-03-29 4:46 Sumesh
2005-03-16 12:38 Eric
2005-03-16 13:22 ` Takashi Iwai
[not found] ` <1806.132.168.64.149.1110980407.squirrel@132.168.64.149>
2005-03-16 13:43 ` Takashi Iwai
[not found] ` <1908.132.168.64.149.1110981336.squirrel@132.168.64.149>
2005-03-16 13:59 ` Takashi Iwai
2005-03-10 2:03 Ray Bryant
2005-03-10 2:02 dpeng
2005-03-10 2:16 ` Patrick McHardy
2005-03-03 6:41 Pmishra
2005-03-03 13:43 ` Michael Tautschnig
2005-03-03 17:17 ` Daniel Lopes
2005-02-25 8:52 shahid shaikh
2005-02-16 19:01 Inglor
2005-02-16 4:08 Ethan Weinstein
2005-02-15 21:09 Varga Endre
2005-02-16 8:14 ` Jozsef Kadlecsik
2005-02-16 11:26 ` KOVACS Krisztian
2005-02-13 12:28 Support for Adder875 in Linux 2.4 Markus Westergren
2005-02-14 6:45 ` Yuli Barcohen
2005-02-14 19:44 ` Markus Westergren
2005-02-15 9:35 ` (no subject) Yuli Barcohen
2005-02-10 4:37 Michael Thompson
2005-02-10 4:42 ` Michael Thompson
2005-02-07 3:37 Dean Anderson
2005-02-07 5:24 ` Dean Anderson
2005-02-07 14:27 ` Samuel Jean
2005-02-08 0:10 ` Dean Anderson
2005-01-26 15:58 mohammad Mahbubur rahman
2005-01-26 16:26 ` Tobias DiPasquale
2005-01-24 18:46 Filip Moritz
2005-01-20 19:33 Ram Kumar
2004-12-29 9:01 Zacky Ho
2004-12-29 22:32 ` Jason Opperisano
2004-12-30 6:56 ` Zacky Ho
2004-12-28 11:42 Geoffrey Kendall
2004-12-28 8:31 Daniel L. Finch
2004-12-28 7:58 Sung S. Marshall
2004-12-25 23:11 Gil F. Phelps
2004-12-25 9:06 Juanita Britt
2004-12-23 8:33 Jake Link
2004-12-13 11:08 Steven
2004-12-13 0:46 Irma M. Harris
2004-12-04 7:02 Jamal Lambert
2004-12-03 7:12 Marsha Olson
2004-12-02 17:34 Vickie
2004-12-01 0:04 Mason Sinclair
2004-11-30 22:49 Lena M. Ochoa
2004-11-30 18:27 Janine Rowe
2004-11-30 5:35 Jill
2004-11-28 10:24 Tonia Castillo
2004-11-28 7:07 Sasha Peoples
2004-11-28 3:13 emx-ShkBkJ/ES20
2004-11-26 1:40 yopy-Hm3cg6mZ9cc
2004-11-25 13:09 skchoi-PufmhqLRAwUysxA8WJXlww
2004-11-25 11:29 刘小姐
2004-11-23 11:31 Andreas Grabner
2004-11-22 19:23 Ratin Kumar
2004-11-22 22:53 ` Kumar Gala
2004-11-16 13:48 Artem B. Bityuckiy
2004-11-16 13:55 ` David Woodhouse
2004-11-16 11:42 Artem B. Bityuckiy
2004-11-06 2:30 Julie
2004-10-27 12:09 Mirko Bonasorte
2004-10-26 16:28 Katherine S. Burris
2004-10-25 1:00 Matt
2004-10-23 13:28 Ashley
2004-10-22 13:42 Desmond Murdock
2004-10-21 3:11 Tiffany Bloom
2004-10-20 8:26 Rui Nuno Capela
2004-10-20 8:56 ` Jaroslav Kysela
2004-10-19 12:34 Oleg A. Arkhanglelsky
2004-10-14 19:23 Alyson Holley
2004-10-14 19:23 ` Alyson Holley
2004-10-14 19:23 Dane May
2004-10-14 19:23 ` Dane May
2004-10-12 13:11 news globelife
2004-10-09 13:36 Adolph Tipton
2004-10-09 3:55 Robert Ritter
2004-10-08 20:11 Francesca B. Mendoza
2004-10-05 18:20 そふとうぇあ
2004-10-05 8:15 Genaro P. Tapia
2004-09-24 4:39 Yen Tran
2004-09-21 14:57 rte news
2004-09-19 18:54 Michael Barry
2004-09-21 14:38 ` Aleksandar Milivojevic
2004-09-21 16:43 ` George Alexandru Dragoi
2004-09-21 17:27 ` Jason Opperisano
2004-09-21 17:55 ` George Alexandru Dragoi
2004-09-19 7:02 Jill
2004-09-13 22:08 Inez
2004-09-13 19:52 Melkor
2004-09-06 1:16 Julie
2004-09-04 9:12 Newbie
2004-09-04 15:40 ` Jose Maria Lopez
2004-09-03 6:14 Ben
2004-09-01 2:42 Anthony DiSante
2004-08-29 13:21 <no subject> Joachim Bremer
2004-08-29 12:36 Joachim Bremer
2004-08-29 12:42 ` Nick Piggin
[not found] <200408280740.i7S7eYd07083@sites1.grossepointe.com>
2004-08-29 0:39 ` (no subject) security
2004-08-16 1:09 A. Mani
2004-08-05 11:52 Ehrhardt René
2004-08-04 6:11 rudy BERRY
2004-07-21 13:56 Brent Clark
2004-07-05 5:45 Bo Henriksen
2004-07-01 16:45 IZEM Farid
2004-06-30 20:15 IZEM Farid
2004-06-30 22:16 ` Antony Stone
2004-06-30 17:58 Frederic Krueger
2004-06-30 13:33 IZEM Farid
2004-06-30 14:19 ` Antony Stone
2004-06-30 9:50 <no subject> Michael Tasche
2004-06-29 14:25 (no subject) Richard Gutery
2004-06-29 14:37 ` Antony Stone
2004-06-29 13:49 Richard Gutery
2004-06-29 14:05 ` Feizhou
2004-06-29 14:08 ` Antony Stone
2004-06-29 14:26 ` Antony Stone
2004-06-29 14:29 ` listuser
2004-06-29 14:37 ` Sven Schuster
2004-06-29 13:19 Richard Gutery
2004-06-29 13:30 ` Antony Stone
2004-06-23 4:59 Dharmendra T.
2004-06-07 9:37 "romio kasyanov"
2004-06-02 3:04 Zhu, Yi
2004-05-31 11:18 Ivan
2004-05-31 11:39 ` Markus Zeilinger
2004-05-31 11:53 ` Krishna Prasanth
2004-06-01 1:34 ` Mark E. Donaldson
2004-05-30 14:22 fil.tri@libero.it
[not found] ` <HYJ6LH$8F4FB33FB70F6F8E7D71D47BD17E0250-VGgt2q2+T+FeoWH0uzbU5w@public.gmane.org>
2004-06-01 9:21 ` Stefan Seyfried
2004-05-30 10:20 fil.tri@libero.it
2004-05-29 20:06 fil.tri@libero.it
2004-05-26 9:00 xuhaoz
2004-05-28 7:42 ` Antonino A. Daplas
2004-05-24 13:46 <no subject> Frank Pieczynski
2004-05-22 1:48 (no subject) xuhaoz
2004-05-19 2:32 Jotinha
2004-05-19 14:08 ` Marco Gerards
2004-04-30 8:32 zze-KHOURY Jad FTRD/DMI/CAE
2004-05-01 0:10 ` Mark E. Donaldson
2004-04-16 2:58 James
2004-04-16 13:00 ` Rob Sterenborg
2004-04-11 11:40 Bjorn Brox
2004-04-08 13:12 __ Radien__
2004-04-08 13:53 ` Antony Stone
2004-04-08 9:43 __ Radien__
2004-04-08 10:20 ` Antony Stone
2004-04-06 19:56 Brian Murphy
2004-03-18 1:08 True fsync() in Linux (on IDE) Peter Zaitsev
2004-03-18 6:47 ` Jens Axboe
2004-03-18 11:34 ` Matthias Andree
2004-03-18 11:58 ` (no subject) Daniel Czarnecki
2004-02-25 15:16 Joel Cant
2004-02-25 15:54 ` Redeeman
2004-02-21 12:46 Anthony de Almeida Lopes
2004-02-21 20:52 ` Tomasz Korycki
2004-02-21 21:26 ` Daniel Chemko
2004-02-21 22:49 ` Alexis
2004-02-22 3:23 ` c0ldbyte
2004-02-22 13:10 ` Anthony de Almeida Lopes
2004-02-19 13:19 rruegner
2004-02-14 16:13 scp
2004-02-14 23:36 ` Pablo Neira
[not found] <402A710F.9080908@surricani.cjb.net>
2004-02-11 18:20 ` Armen Kaleshian
2004-02-09 21:05 Alexandr Chernyy
2004-02-09 21:22 ` Matti Aarnio
2004-02-09 22:46 ` Alessandro Amici
2004-02-06 20:58 Pete Phillips
[not found] ` <200402062058.i16KwPA5028014-epL5dT2ynbxW7IvYoCtsgA@public.gmane.org>
2004-02-06 23:11 ` Bruno Ducrot
[not found] ` <20040206231124.GK13262-kk6yZipjEM5g9hUCZPvPmw@public.gmane.org>
2004-02-07 9:41 ` Pete Phillips
2004-01-17 19:31 Joni Sawyer
2004-02-22 1:20 ` Evelyn Carter
2004-03-09 0:34 ` Josie Feldman
2004-03-26 0:05 ` Rosemarie Crockett
2004-04-03 5:46 ` Forrest Lehman
2004-04-05 4:01 ` Dane Kirkland
2004-04-28 12:54 ` Neva Thompson
2004-05-02 22:21 ` Dawn Atwood
2004-05-13 13:58 ` Kenton Stringer
2004-11-08 2:58 ` Steven
2004-11-11 0:50 ` Julie
2004-11-11 8:31 ` Julie
2004-11-21 13:59 ` Matt
2004-12-06 0:34 ` Jill
2008-11-03 7:42 ` Jesse DeFer
2003-05-22 19:49 Curtis Lehman
2004-02-16 15:15 ` christophe.varoqui
2004-10-09 13:36 ` Emilia Greenberg
2004-12-04 11:58 ` pablarribas
2004-12-05 2:58 ` Kay Sievers
2005-04-05 18:58 ` craig
2005-04-05 20:23 ` Patrick Mansfield
2005-05-04 17:30 ` Layne Garrett Pedersen
2005-05-04 17:40 ` Kay Sievers
2005-05-06 13:27 ` Victor Riquelme Durán
2005-05-16 22:50 ` Kay Sievers
2005-06-02 11:52 ` Rajat Jain
2005-06-05 7:21 ` shubhrangam
2002-07-04 11:11 Fabrice MARIE
2005-09-22 10:25 ` Amin Azez
2005-09-22 10:28 ` Samuel Liddicott
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