[Xenomai-help] Event flag from ISR

[Xenomai-help] Event flag from ISR

[Patrick]

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Hi all,

 

I am using a RT event flag structure to start a task from an ISR.

The task waits on rt_event_wait and when the IRQ occurs the ISR executes
rt_event_signal (the ISR code only clears the flag and calls
rt_event_signal).

I'm using an oscilloscope to measure the length of the ISR and the first
occurrence lasts about 20us and all the next occurrences last about 4us.

 

My question is why the first ISR is so long?

 

For information I use xenomai 2.4 rc4 on ARM pxa270 machine with 2.6.20
kernel. 

 

Thanks in advance,

 

Patrick


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Re: [Xenomai-help] Event flag from ISR

[Gilles Chanteperdrix]

Patrick wrote:
 > Hi all,
 > 
 >  
 > 
 > I am using a RT event flag structure to start a task from an ISR.
 > 
 > The task waits on rt_event_wait and when the IRQ occurs the ISR executes
 > rt_event_signal (the ISR code only clears the flag and calls
 > rt_event_signal).
 > 
 > I'm using an oscilloscope to measure the length of the ISR and the first
 > occurrence lasts about 20us and all the next occurrences last about 4us.
 > 
 >  
 > 
 > My question is why the first ISR is so long?
 > 
 >  
 > 
 > For information I use xenomai 2.4 rc4 on ARM pxa270 machine with 2.6.20
 > kernel. 

Typical worst case interrupt latency on ARM is around 50 us, so 20 us is
not that long. What you are observing is probably a cache effect. In
this case, you should observe 20us after each user-space context switch
since on ARM, cache is flushed at each user-space context switch.


-- 


					    Gilles Chanteperdrix.

Re: [Xenomai-help] Event flag from ISR

[ROSSIER Daniel]

>-----Original Message-----
>From: xenomai-help-bounces@domain.hid
[mailto:xenomai-help-bounces@domain.hid]
>On Behalf Of Gilles Chanteperdrix
>Sent: jeudi 25 octobre 2007 19:48
>To: Patrick
>Cc: xenomai@xenomai.org
>Subject: Re: [Xenomai-help] Event flag from ISR
>
>Patrick wrote:
> > Hi all,
> >
> >
> >
> > I am using a RT event flag structure to start a task from an ISR.
> >
> > The task waits on rt_event_wait and when the IRQ occurs the ISR
>executes
> > rt_event_signal (the ISR code only clears the flag and calls
> > rt_event_signal).
> >
> > I'm using an oscilloscope to measure the length of the ISR and the
>first
> > occurrence lasts about 20us and all the next occurrences last about
>4us.
> >
> >
> >
> > My question is why the first ISR is so long?
> >
> >
> >
> > For information I use xenomai 2.4 rc4 on ARM pxa270 machine with
>2.6.20
> > kernel.
>
>Typical worst case interrupt latency on ARM is around 50 us, so 20 us
is
>not that long. What you are observing is probably a cache effect. In
>this case, you should observe 20us after each user-space context switch
>since on ARM, cache is flushed at each user-space context switch.

It could make sense to have a look at the L4-embedded microkernel which
uses the Fast Context Switch Extension (FCSE) of ARM
and to adapt the mm switch accordingly. But as far as I remember, this
could introduce some limitations to a process
size since all threads are sharing a same virtual address space
subdivided into smaller virtual regions.
Benchmarks with FCSE reported some significant improvements and I know
this technics is commonly used for virtualization layer on ARM.

>
>--
>
>
>					    Gilles Chanteperdrix.
>
>_______________________________________________
>Xenomai-help mailing list
>Xenomai-help@domain.hid
>https://mail.gna.org/listinfo/xenomai-help

Daniel

Re: [Xenomai-help] Event flag from ISR

[Jan Kiszka]

ROSSIER Daniel wrote:
>> -----Original Message-----
>> From: xenomai-help-bounces@domain.hid
> [mailto:xenomai-help-bounces@domain.hid]
>> On Behalf Of Gilles Chanteperdrix
>> Sent: jeudi 25 octobre 2007 19:48
>> To: Patrick
>> Cc: xenomai@xenomai.org
>> Subject: Re: [Xenomai-help] Event flag from ISR
>>
>> Patrick wrote:
>>> Hi all,
>>>
>>>
>>>
>>> I am using a RT event flag structure to start a task from an ISR.
>>>
>>> The task waits on rt_event_wait and when the IRQ occurs the ISR
>> executes
>>> rt_event_signal (the ISR code only clears the flag and calls
>>> rt_event_signal).
>>>
>>> I'm using an oscilloscope to measure the length of the ISR and the
>> first
>>> occurrence lasts about 20us and all the next occurrences last about
>> 4us.
>>>
>>>
>>> My question is why the first ISR is so long?
>>>
>>>
>>>
>>> For information I use xenomai 2.4 rc4 on ARM pxa270 machine with
>> 2.6.20
>>> kernel.
>> Typical worst case interrupt latency on ARM is around 50 us, so 20 us
> is
>> not that long. What you are observing is probably a cache effect. In
>> this case, you should observe 20us after each user-space context switch
>> since on ARM, cache is flushed at each user-space context switch.
> 
> It could make sense to have a look at the L4-embedded microkernel which
> uses the Fast Context Switch Extension (FCSE) of ARM
> and to adapt the mm switch accordingly. But as far as I remember, this
> could introduce some limitations to a process
> size since all threads are sharing a same virtual address space
> subdivided into smaller virtual regions.
> Benchmarks with FCSE reported some significant improvements and I know
> this technics is commonly used for virtualization layer on ARM.

There is already ongoing work toward FCSE for current Linux, which could
then be used by Xenomai as well, see linux-arm-kernel and xenomai-core
[1] archives. I guess anyone willing to join this effort is welcome.

Jan

[1] https://mail.gna.org/public/xenomai-core/2007-09/msg00059.html

-- 
Siemens AG, Corporate Technology, CT SE 2
Corporate Competence Center Embedded Linux

Re: [Xenomai-help] Event flag from ISR

[ROSSIER Daniel]

>-----Original Message-----
>From: Jan Kiszka [mailto:jan.kiszka@domain.hid]
>Sent: vendredi 26 octobre 2007 10:27
>To: ROSSIER Daniel
>Cc: Gilles Chanteperdrix; Patrick; xenomai@xenomai.org
>Subject: Re: [Xenomai-help] Event flag from ISR
>
>ROSSIER Daniel wrote:
>>> -----Original Message-----
>>> From: xenomai-help-bounces@domain.hid
>> [mailto:xenomai-help-bounces@domain.hid]
>>> On Behalf Of Gilles Chanteperdrix
>>> Sent: jeudi 25 octobre 2007 19:48
>>> To: Patrick
>>> Cc: xenomai@xenomai.org
>>> Subject: Re: [Xenomai-help] Event flag from ISR
>>>
>>> Patrick wrote:
>>>> Hi all,
>>>>
>>>>
>>>>
>>>> I am using a RT event flag structure to start a task from an ISR.
>>>>
>>>> The task waits on rt_event_wait and when the IRQ occurs the ISR
>>> executes
>>>> rt_event_signal (the ISR code only clears the flag and calls
>>>> rt_event_signal).
>>>>
>>>> I'm using an oscilloscope to measure the length of the ISR and the
>>> first
>>>> occurrence lasts about 20us and all the next occurrences last about
>>> 4us.
>>>>
>>>>
>>>> My question is why the first ISR is so long?
>>>>
>>>>
>>>>
>>>> For information I use xenomai 2.4 rc4 on ARM pxa270 machine with
>>> 2.6.20
>>>> kernel.
>>> Typical worst case interrupt latency on ARM is around 50 us, so 20
us
>> is
>>> not that long. What you are observing is probably a cache effect. In
>>> this case, you should observe 20us after each user-space context
>switch
>>> since on ARM, cache is flushed at each user-space context switch.
>>
>> It could make sense to have a look at the L4-embedded microkernel
>which
>> uses the Fast Context Switch Extension (FCSE) of ARM
>> and to adapt the mm switch accordingly. But as far as I remember,
this
>> could introduce some limitations to a process
>> size since all threads are sharing a same virtual address space
>> subdivided into smaller virtual regions.
>> Benchmarks with FCSE reported some significant improvements and I
know
>> this technics is commonly used for virtualization layer on ARM.
>
>There is already ongoing work toward FCSE for current Linux, which
could
>then be used by Xenomai as well, see linux-arm-kernel and xenomai-core
>[1] archives. I guess anyone willing to join this effort is welcome.
>

Thanks for the update Jan; great to see that there is some interest
(BTW, I realized that I mix 
the FCSE with DACR feature which allows to share an address space;
limitations of 32 MB process
address space is bound to DACR ;-)).
We will then see if we can put some efforts on this topic. We keep you
posted.

Daniel

Re: [Xenomai-help] Event flag from ISR

[Sebastian Smolorz]

ROSSIER Daniel wrote:
> >-----Original Message-----
> >From: Jan Kiszka [mailto:jan.kiszka@domain.hid]
> >Sent: vendredi 26 octobre 2007 10:27
> >There is already ongoing work toward FCSE for current Linux, which
>
> could
>
> >then be used by Xenomai as well, see linux-arm-kernel and xenomai-core
> >[1] archives. I guess anyone willing to join this effort is welcome.
>
> Thanks for the update Jan; great to see that there is some interest
> (BTW, I realized that I mix
> the FCSE with DACR feature which allows to share an address space;
> limitations of 32 MB process
> address space is bound to DACR ;-)).

No, this limitation is imposed by FCSE. You can use FCSE without domain access 
control which is for checking memory accesses.

-- 
Sebastian

Re: [Xenomai-help] Event flag from ISR

[Patrick]

Hi,

The 20us are just the ISR duration; the latency time is not included.

Thanks

Patrick

-----Message d'origine-----
De : Gilles Chanteperdrix [mailto:gilles.chanteperdrix@xenomai.org
Envoyé : jeudi, 25. octobre 2007 19:48
À : Patrick
Cc : xenomai@xenomai.org
Objet : Re: [Xenomai-help] Event flag from ISR

Patrick wrote:
 > Hi all,
 > 
 >  
 > 
 > I am using a RT event flag structure to start a task from an ISR.
 > 
 > The task waits on rt_event_wait and when the IRQ occurs the ISR executes
 > rt_event_signal (the ISR code only clears the flag and calls
 > rt_event_signal).
 > 
 > I'm using an oscilloscope to measure the length of the ISR and the first
 > occurrence lasts about 20us and all the next occurrences last about 4us.
 > 
 >  
 > 
 > My question is why the first ISR is so long?
 > 
 >  
 > 
 > For information I use xenomai 2.4 rc4 on ARM pxa270 machine with 2.6.20
 > kernel. 

Typical worst case interrupt latency on ARM is around 50 us, so 20 us is
not that long. What you are observing is probably a cache effect. In
this case, you should observe 20us after each user-space context switch
since on ARM, cache is flushed at each user-space context switch.


-- 


					    Gilles Chanteperdrix.