From: Tomasz Figa <tomasz.figa@gmail.com>
To: Vikas Sajjan <vikas.sajjan@linaro.org>
Cc: yadi.brar01@gmail.com, linux-samsung-soc@vger.kernel.org,
dianders@chromium.org, linux-arm-kernel@lists.infradead.org,
kgene.kim@samsung.com, mturquette@linaro.org,
thomas.abraham@linaro.org
Subject: Re: [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx
Date: Fri, 24 May 2013 23:55:03 +0200 [thread overview]
Message-ID: <4808417.0aThqqOIhP@flatron> (raw)
In-Reply-To: <1369391478-7665-2-git-send-email-vikas.sajjan@linaro.org>
Hi,
On Friday 24 of May 2013 16:01:14 Vikas Sajjan wrote:
> From: Yadwinder Singh Brar <yadi.brar@samsung.com>
>
> To factor out possible common code, this patch unifies the clk strutures
> used for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos4.c | 10 ++++---
> drivers/clk/samsung/clk-exynos5250.c | 14 ++++-----
> drivers/clk/samsung/clk-pll.c | 54
> ++++++++++++++++++---------------- drivers/clk/samsung/clk-pll.h
> | 4 +--
> 4 files changed, 44 insertions(+), 38 deletions(-)
>
Whether this patch really allows to factor out any significant amount of
common code is rather discussible, but generally looks fine.
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
WARNING: multiple messages have this Message-ID (diff)
From: tomasz.figa@gmail.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx
Date: Fri, 24 May 2013 23:55:03 +0200 [thread overview]
Message-ID: <4808417.0aThqqOIhP@flatron> (raw)
In-Reply-To: <1369391478-7665-2-git-send-email-vikas.sajjan@linaro.org>
Hi,
On Friday 24 of May 2013 16:01:14 Vikas Sajjan wrote:
> From: Yadwinder Singh Brar <yadi.brar@samsung.com>
>
> To factor out possible common code, this patch unifies the clk strutures
> used for PLL35xx & PLL36xx and usues clk->base instead of clk->con0.
>
> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos4.c | 10 ++++---
> drivers/clk/samsung/clk-exynos5250.c | 14 ++++-----
> drivers/clk/samsung/clk-pll.c | 54
> ++++++++++++++++++---------------- drivers/clk/samsung/clk-pll.h
> | 4 +--
> 4 files changed, 44 insertions(+), 38 deletions(-)
>
Whether this patch really allows to factor out any significant amount of
common code is rather discussible, but generally looks fine.
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Best regards,
Tomasz
next prev parent reply other threads:[~2013-05-24 21:55 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-24 10:31 [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
2013-05-24 10:31 ` [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
2013-05-24 21:55 ` Tomasz Figa [this message]
2013-05-24 21:55 ` Tomasz Figa
2013-05-24 10:31 ` [RESEND PATCH 2/5] clk: samsung: Add support to register rate_table " Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
2013-05-24 22:04 ` Tomasz Figa
2013-05-24 22:04 ` Tomasz Figa
2013-05-27 6:35 ` Yadwinder Singh Brar
2013-05-27 6:35 ` Yadwinder Singh Brar
2013-05-24 10:31 ` [RESEND PATCH 3/5] clk: samsung: Add set_rate() clk_ops for PLL35xx Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
2013-05-24 22:19 ` Tomasz Figa
2013-05-24 22:19 ` Tomasz Figa
2013-05-27 6:36 ` Yadwinder Singh Brar
2013-05-27 6:36 ` Yadwinder Singh Brar
2013-05-24 10:31 ` [RESEND PATCH 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
2013-05-24 22:20 ` Tomasz Figa
2013-05-24 22:20 ` Tomasz Figa
2013-05-24 10:31 ` [RESEND PATCH 5/5] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Vikas Sajjan
2013-05-24 10:31 ` Vikas Sajjan
-- strict thread matches above, loose matches on Subject: below --
2013-05-24 5:55 [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs Vikas Sajjan
2013-05-24 5:55 ` [RESEND PATCH 1/5] clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx Vikas Sajjan
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