[PATCH 1/2] [MIPS] add DECstation I/O ASIC clocksource

[PATCH 1/2] [MIPS] add DECstation I/O ASIC clocksource

[Yoichi Yuasa]

add DECstation I/O ASIC clocksource

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X /home/yuasa/Memo/dontdiff mips-queue-orig/arch/mips/Kconfig mips-queue/arch/mips/Kconfig
--- mips-queue-orig/arch/mips/Kconfig	2008-04-22 23:13:37.099040014 +0900
+++ mips-queue/arch/mips/Kconfig	2008-04-22 23:13:21.770166469 +0900
@@ -82,6 +82,7 @@ config MACH_DECSTATION
 	bool "DECstations"
 	select BOOT_ELF32
 	select CEVT_R4K
+	select CSRC_IOASIC
 	select CSRC_R4K
 	select CPU_DADDI_WORKAROUNDS if 64BIT
 	select CPU_R4000_WORKAROUNDS if 64BIT
@@ -783,6 +784,9 @@ config CEVT_TXX9
 config CSRC_BCM1480
 	bool
 
+config CSRC_IOASIC
+	bool
+
 config CSRC_R4K
 	bool
 
diff -pruN -X /home/yuasa/Memo/dontdiff mips-queue-orig/arch/mips/dec/time.c mips-queue/arch/mips/dec/time.c
--- mips-queue-orig/arch/mips/dec/time.c	2008-04-22 23:13:37.231047535 +0900
+++ mips-queue/arch/mips/dec/time.c	2008-04-22 23:13:21.770166469 +0900
@@ -165,7 +165,7 @@ void __init plat_time_init(void)
 
 	if (!cpu_has_counter && IOASIC)
 		/* For pre-R4k systems we use the I/O ASIC's counter.  */
-		clocksource_mips.read = dec_ioasic_hpt_read;
+		dec_ioasic_clocksource_init();
 
 	/* Set up the rate of periodic DS1287 interrupts.  */
 	CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
diff -pruN -X /home/yuasa/Memo/dontdiff mips-queue-orig/arch/mips/kernel/Makefile mips-queue/arch/mips/kernel/Makefile
--- mips-queue-orig/arch/mips/kernel/Makefile	2008-04-22 23:13:37.239047990 +0900
+++ mips-queue/arch/mips/kernel/Makefile	2008-04-22 23:13:21.774166698 +0900
@@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641
 obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
 obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
+obj-$(CONFIG_CSRC_IOASIC)	+= csrc-ioasic.o
 obj-$(CONFIG_CSRC_R4K)		+= csrc-r4k.o
 obj-$(CONFIG_CSRC_SB1250)	+= csrc-sb1250.o
 obj-$(CONFIG_SYNC_R4K)		+= sync-r4k.o
diff -pruN -X /home/yuasa/Memo/dontdiff mips-queue-orig/arch/mips/kernel/csrc-ioasic.c mips-queue/arch/mips/kernel/csrc-ioasic.c
--- mips-queue-orig/arch/mips/kernel/csrc-ioasic.c	1970-01-01 09:00:00.000000000 +0900
+++ mips-queue/arch/mips/kernel/csrc-ioasic.c	2008-04-22 23:13:21.774166698 +0900
@@ -0,0 +1,45 @@
+/*
+ *  DEC I/O ASIC's counter clocksource
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/clocksource.h>
+#include <linux/init.h>
+
+#include <asm/time.h>
+#include <asm/dec/ioasic.h>
+#include <asm/dec/ioasic_addrs.h>
+
+static cycle_t dec_ioasic_hpt_read(void)
+{
+	return ioasic_read(IO_REG_FCTR);
+}
+
+static struct clocksource clocksource_dec = {
+	.name		= "dec-ioasic",
+	.read		= dec_ioasic_hpt_read,
+	.mask		= CLOCKSOURCE_MASK(32),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __init dec_ioasic_clocksource_init(void)
+{
+	clocksource_dec.rating = 200;
+	clocksource_set_clock(&clocksource_dec, 25000000);
+
+	clocksource_register(&clocksource_dec);
+}
diff -pruN -X /home/yuasa/Memo/dontdiff mips-queue-orig/include/asm-mips/dec/ioasic.h mips-queue/include/asm-mips/dec/ioasic.h
--- mips-queue-orig/include/asm-mips/dec/ioasic.h	2008-04-22 23:13:58.672269400 +0900
+++ mips-queue/include/asm-mips/dec/ioasic.h	2008-04-22 23:13:21.774166698 +0900
@@ -33,4 +33,6 @@ static inline u32 ioasic_read(unsigned i
 
 extern void init_ioasic_irqs(int base);
 
+extern void dec_ioasic_clocksource_init(void);
+
 #endif /* __ASM_DEC_IOASIC_H */

[PATCH 2/2] [MIPS] add DECstation DS1287 clockevent

[Yoichi Yuasa]

add DECstation DS1287 clockevent

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig
--- linux-orig/arch/mips/Kconfig	2008-04-22 19:01:43.957134178 +0900
+++ linux/arch/mips/Kconfig	2008-04-22 18:03:05.427649422 +0900
@@ -81,6 +81,7 @@ config MIPS_COBALT
 config MACH_DECSTATION
 	bool "DECstations"
 	select BOOT_ELF32
+	select CEVT_DS1287
 	select CEVT_R4K
 	select CSRC_IOASIC
 	select CSRC_R4K
@@ -769,6 +770,9 @@ config BOOT_RAW
 config CEVT_BCM1480
 	bool
 
+config CEVT_DS1287
+	bool
+
 config CEVT_GT641XX
 	bool
 
diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/dec/time.c linux/arch/mips/dec/time.c
--- linux-orig/arch/mips/dec/time.c	2008-04-22 19:01:43.957134178 +0900
+++ linux/arch/mips/dec/time.c	2008-04-22 18:03:05.427649422 +0900
@@ -9,30 +9,16 @@
  *
  */
 #include <linux/bcd.h>
-#include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
 #include <linux/mc146818rtc.h>
-#include <linux/mm.h>
-#include <linux/module.h>
 #include <linux/param.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/time.h>
-#include <linux/types.h>
-
-#include <asm/bootinfo.h>
-#include <asm/cpu.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mipsregs.h>
-#include <asm/sections.h>
+
+#include <asm/cpu-features.h>
 #include <asm/time.h>
 
+#include <asm/dec/ds1287.h>
 #include <asm/dec/interrupts.h>
 #include <asm/dec/ioasic.h>
-#include <asm/dec/ioasic_addrs.h>
 #include <asm/dec/machtype.h>
 
 unsigned long read_persistent_clock(void)
@@ -139,42 +125,32 @@ int rtc_mips_set_mmss(unsigned long nowt
 	return retval;
 }
 
-static int dec_timer_state(void)
+void __init plat_time_init(void)
 {
-	return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
-}
+	u32 start, end;
+	int i = HZ / 10;
 
-static void dec_timer_ack(void)
-{
-	CMOS_READ(RTC_REG_C);			/* Ack the RTC interrupt.  */
-}
+	/* Set up the rate of periodic DS1287 interrupts. */
+	ds1287_set_base_clock(HZ);
 
-static cycle_t dec_ioasic_hpt_read(void)
-{
-	/*
-	 * The free-running counter is 32-bit which is good for about
-	 * 2 minutes, 50 seconds at possible count rates of up to 25MHz.
-	 */
-	return ioasic_read(IO_REG_FCTR);
-}
+	if (cpu_has_counter) {
+		while (!ds1287_timer_state())
+			;
 
+		start = read_c0_count();
 
-void __init plat_time_init(void)
-{
-	mips_timer_ack = dec_timer_ack;
+		while (i--)
+			while (!ds1287_timer_state())
+				;
+
+		end = read_c0_count();
 
-	if (!cpu_has_counter && IOASIC)
+		mips_hpt_frequency = (end - start) * 10;
+		printk(KERN_INFO "MIPS counter frequency %dHz\n",
+			mips_hpt_frequency);
+	} else if (IOASIC)
 		/* For pre-R4k systems we use the I/O ASIC's counter.  */
 		dec_ioasic_clocksource_init();
 
-	/* Set up the rate of periodic DS1287 interrupts.  */
-	CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
-}
-
-void __init plat_timer_setup(struct irqaction *irq)
-{
-	setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
-
-	/* Enable periodic DS1287 interrupts.  */
-	CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
+	ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
 }
diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/kernel/Makefile linux/arch/mips/kernel/Makefile
--- linux-orig/arch/mips/kernel/Makefile	2008-04-22 19:01:43.957134178 +0900
+++ linux/arch/mips/kernel/Makefile	2008-04-22 18:03:05.427649422 +0900
@@ -9,8 +9,9 @@ obj-y		+= cpu-probe.o branch.o entry.o g
 		   time.o topology.o traps.o unaligned.o
 
 obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
-obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
+obj-$(CONFIG_CEVT_DS1287)	+= cevt-ds1287.o
 obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641xx.o
+obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
 obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
 obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
 obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/kernel/cevt-ds1287.c linux/arch/mips/kernel/cevt-ds1287.c
--- linux-orig/arch/mips/kernel/cevt-ds1287.c	1970-01-01 09:00:00.000000000 +0900
+++ linux/arch/mips/kernel/cevt-ds1287.c	2008-04-22 18:03:05.455637018 +0900
@@ -0,0 +1,132 @@
+/*
+ *  DS1287 clockevent driver
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mc146818rtc.h>
+
+#include <asm/time.h>
+
+#include <irq.h>
+
+int ds1287_timer_state(void)
+{
+	return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
+}
+
+int ds1287_set_base_clock(unsigned int hz)
+{
+	u8 rate;
+
+	switch (hz) {
+	case 128:
+		rate = 0x9;
+		break;
+	case 256:
+		rate = 0x8;
+		break;
+	case 1024:
+		rate = 0x6;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
+
+	return 0;
+}
+
+static int ds1287_set_next_event(unsigned long delta,
+				 struct clock_event_device *evt)
+{
+	return -EINVAL;
+}
+
+static void ds1287_set_mode(enum clock_event_mode mode,
+			    struct clock_event_device *evt)
+{
+	unsigned long flags;
+	u8 val;
+
+	spin_lock_irqsave(&rtc_lock, flags);
+
+	val = CMOS_READ(RTC_REG_B);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		val |= RTC_PIE;
+		break;
+	default:
+		val &= ~RTC_PIE;
+		break;
+	}
+
+	CMOS_WRITE(val, RTC_REG_B);
+
+	spin_unlock_irqrestore(&rtc_lock, flags);
+}
+
+static void ds1287_event_handler(struct clock_event_device *dev)
+{
+}
+
+static struct clock_event_device ds1287_clockevent = {
+	.name		= "ds1287",
+	.features	= CLOCK_EVT_FEAT_PERIODIC,
+	.cpumask	= CPU_MASK_CPU0,
+	.set_next_event	= ds1287_set_next_event,
+	.set_mode	= ds1287_set_mode,
+	.event_handler	= ds1287_event_handler,
+};
+
+static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *cd = &ds1287_clockevent;
+
+	/* Ack the RTC interrupt. */
+	CMOS_READ(RTC_REG_C);
+
+	cd->event_handler(cd);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ds1287_irqaction = {
+	.handler	= ds1287_interrupt,
+	.flags		= IRQF_DISABLED | IRQF_PERCPU,
+	.name		= "ds1287",
+};
+
+int __init ds1287_clockevent_init(int irq)
+{
+	struct clock_event_device *cd;
+
+	cd = &ds1287_clockevent;
+	cd->rating = 100;
+	cd->irq = irq;
+	clockevent_set_clock(cd, 32768);
+	cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
+	cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
+
+	clockevents_register_device(&ds1287_clockevent);
+
+	return setup_irq(irq, &ds1287_irqaction);
+}
diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/include/asm-mips/dec/ds1287.h linux/include/asm-mips/dec/ds1287.h
--- linux-orig/include/asm-mips/dec/ds1287.h	1970-01-01 09:00:00.000000000 +0900
+++ linux/include/asm-mips/dec/ds1287.h	2008-04-22 18:03:05.455637018 +0900
@@ -0,0 +1,27 @@
+/*
+ *  DS1287 timer functions.
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __ASM_DEC_DS1287_H
+#define __ASM_DEC_DS1287_H
+
+extern int ds1287_timer_state(void);
+extern void ds1287_set_base_clock(unsigned int clock);
+extern int ds1287_clockevent_init(int irq);
+
+#endif

Re: [PATCH 1/2] [MIPS] add DECstation I/O ASIC clocksource

[Maciej W. Rozycki]

On Wed, 23 Apr 2008, Yoichi Yuasa wrote:

> add DECstation I/O ASIC clocksource

 Thanks, I will have a look into it; reasonably soon I hope -- I'm
updating my tree right now.  I am quite surprised you care about this 
platform too.

> +void __init dec_ioasic_clocksource_init(void)
> +{
> +	clocksource_dec.rating = 200;
> +	clocksource_set_clock(&clocksource_dec, 25000000);
> +
> +	clocksource_register(&clocksource_dec);
> +}

 This is not true for all systems -- the clock rate is based on the
TURBOchannel clock and it varies across systems.  And some have no counter
in the I/O ASIC at all (it has been added in a later revision of the 
chip), which the old code handled albeit not in the prettiest way (by 
chance actually, as originally I did know of the older revision).

  Maciej

Re: [PATCH 1/2] [MIPS] add DECstation I/O ASIC clocksource

[Yoichi Yuasa]

Hi Maciej,

On Wed, 23 Apr 2008 01:46:16 +0100 (BST)
"Maciej W. Rozycki" <macro@linux-mips.org> wrote:

> On Wed, 23 Apr 2008, Yoichi Yuasa wrote:
> 
> > add DECstation I/O ASIC clocksource
> 
>  Thanks, I will have a look into it; reasonably soon I hope -- I'm
> updating my tree right now.  I am quite surprised you care about this 
> platform too.

I'm interested in the little endian systems ;)
 
> > +void __init dec_ioasic_clocksource_init(void)
> > +{
> > +	clocksource_dec.rating = 200;
> > +	clocksource_set_clock(&clocksource_dec, 25000000);
> > +
> > +	clocksource_register(&clocksource_dec);
> > +}
> 
>  This is not true for all systems -- the clock rate is based on the
> TURBOchannel clock and it varies across systems.  And some have no counter
> in the I/O ASIC at all (it has been added in a later revision of the 
> chip), which the old code handled albeit not in the prettiest way (by 
> chance actually, as originally I did know of the older revision).

Hmm, we should measure the clock rate.
OK, I'll update dec-ioasic clocksource.

Yoichi

Re: [PATCH 2/2] [MIPS] add DECstation DS1287 clockevent

[Atsushi Nemoto]

On Wed, 23 Apr 2008 08:52:45 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> add DECstation DS1287 clockevent
> 
> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
...
> --- linux-orig/arch/mips/kernel/Makefile	2008-04-22 19:01:43.957134178 +0900
> +++ linux/arch/mips/kernel/Makefile	2008-04-22 18:03:05.427649422 +0900
> @@ -9,8 +9,9 @@ obj-y		+= cpu-probe.o branch.o entry.o g
>  		   time.o topology.o traps.o unaligned.o
>  
>  obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
> -obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
> +obj-$(CONFIG_CEVT_DS1287)	+= cevt-ds1287.o
>  obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641xx.o
> +obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
>  obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
>  obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
>  obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o

Why CONFIG_CEVT_R4K line was moved?  The order is important?

> --- linux-orig/arch/mips/kernel/cevt-ds1287.c	1970-01-01 09:00:00.000000000 +0900
> +++ linux/arch/mips/kernel/cevt-ds1287.c	2008-04-22 18:03:05.455637018 +0900
...
> +static void ds1287_set_mode(enum clock_event_mode mode,
> +			    struct clock_event_device *evt)
> +{
> +	unsigned long flags;
> +	u8 val;
> +
> +	spin_lock_irqsave(&rtc_lock, flags);

You do not have to use irqsave here, while set_mode is always called
with interrupts disabled.  And for rtc_lock ... I don't know if this
code could be used on SMP :-)

> --- linux-orig/include/asm-mips/dec/ds1287.h	1970-01-01 09:00:00.000000000 +0900
> +++ linux/include/asm-mips/dec/ds1287.h	2008-04-22 18:03:05.455637018 +0900
> @@ -0,0 +1,27 @@
...

I suppose CEVT_DS1287 is not DEC specific one.  If so,
include/asm-mips/ would be better place.

---
Atsushi Nemoto

Re: [PATCH 2/2] [MIPS] add DECstation DS1287 clockevent

[Yoichi Yuasa]

Hi,

On Wed, 23 Apr 2008 11:55:28 +0900 (JST)
Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:

> On Wed, 23 Apr 2008 08:52:45 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> > add DECstation DS1287 clockevent
> > 
> > Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
> ...
> > --- linux-orig/arch/mips/kernel/Makefile	2008-04-22 19:01:43.957134178 +0900
> > +++ linux/arch/mips/kernel/Makefile	2008-04-22 18:03:05.427649422 +0900
> > @@ -9,8 +9,9 @@ obj-y		+= cpu-probe.o branch.o entry.o g
> >  		   time.o topology.o traps.o unaligned.o
> >  
> >  obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
> > -obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
> > +obj-$(CONFIG_CEVT_DS1287)	+= cevt-ds1287.o
> >  obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641xx.o
> > +obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
> >  obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
> >  obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
> >  obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
> 
> Why CONFIG_CEVT_R4K line was moved?  The order is important?

Just sorted.
It's not important.

> 
> > --- linux-orig/arch/mips/kernel/cevt-ds1287.c	1970-01-01 09:00:00.000000000 +0900
> > +++ linux/arch/mips/kernel/cevt-ds1287.c	2008-04-22 18:03:05.455637018 +0900
> ...
> > +static void ds1287_set_mode(enum clock_event_mode mode,
> > +			    struct clock_event_device *evt)
> > +{
> > +	unsigned long flags;
> > +	u8 val;
> > +
> > +	spin_lock_irqsave(&rtc_lock, flags);
> 
> You do not have to use irqsave here, while set_mode is always called
> with interrupts disabled.  And for rtc_lock ... I don't know if this
> code could be used on SMP :-)
> 
> > --- linux-orig/include/asm-mips/dec/ds1287.h	1970-01-01 09:00:00.000000000 +0900
> > +++ linux/include/asm-mips/dec/ds1287.h	2008-04-22 18:03:05.455637018 +0900
> > @@ -0,0 +1,27 @@
> ...
> 
> I suppose CEVT_DS1287 is not DEC specific one.  If so,
> include/asm-mips/ would be better place.

Thank you for your comment.
I'll update this patch.

Yoichi

Re: [PATCH 2/2] [MIPS] add DECstation DS1287 clockevent

[Dmitri Vorobiev]

Atsushi Nemoto пишет:
> On Wed, 23 Apr 2008 08:52:45 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
>> add DECstation DS1287 clockevent
>>
>> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
> ...
>> --- linux-orig/arch/mips/kernel/Makefile	2008-04-22 19:01:43.957134178 +0900
>> +++ linux/arch/mips/kernel/Makefile	2008-04-22 18:03:05.427649422 +0900
>> @@ -9,8 +9,9 @@ obj-y		+= cpu-probe.o branch.o entry.o g
>>  		   time.o topology.o traps.o unaligned.o
>>  
>>  obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
>> -obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
>> +obj-$(CONFIG_CEVT_DS1287)	+= cevt-ds1287.o
>>  obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641xx.o
>> +obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
>>  obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
>>  obj-$(CONFIG_CEVT_TXX9)		+= cevt-txx9.o
>>  obj-$(CONFIG_CSRC_BCM1480)	+= csrc-bcm1480.o
> 
> Why CONFIG_CEVT_R4K line was moved?  The order is important?
> 
>> --- linux-orig/arch/mips/kernel/cevt-ds1287.c	1970-01-01 09:00:00.000000000 +0900
>> +++ linux/arch/mips/kernel/cevt-ds1287.c	2008-04-22 18:03:05.455637018 +0900
> ...
>> +static void ds1287_set_mode(enum clock_event_mode mode,
>> +			    struct clock_event_device *evt)
>> +{
>> +	unsigned long flags;
>> +	u8 val;
>> +
>> +	spin_lock_irqsave(&rtc_lock, flags);
> 
> You do not have to use irqsave here, while set_mode is always called
> with interrupts disabled.  And for rtc_lock ... I don't know if this
> code could be used on SMP :-)
> 

After I had saved a DECstation 5000/200 from a junkyard a few years
ago (very neat hardware, actually), I did some research on this brand.
AFAICT, all MIPS-based DECstation models were UP.

Dmitri

Re: [PATCH 2/2] [MIPS] add DECstation DS1287 clockevent

[Maciej W. Rozycki]

On Wed, 23 Apr 2008, Dmitri Vorobiev wrote:

> After I had saved a DECstation 5000/200 from a junkyard a few years
> ago (very neat hardware, actually), I did some research on this brand.
> AFAICT, all MIPS-based DECstation models were UP.

 As were all the TURBOchannel Alpha machines which may eventually reuse 
many bits of code.  That does not mean code should not be written in a 
clean and portable way and all the associated atomic operations and 
spinlock types will be optimised away when built for UP.

 BTW, DEC actually used to manufacture a MIPS-based line of SMP computers.  
It was called DECsystem 5800 and supported up to four CPU boards.  
Similarly to the DECsystem 5400 and 5500 computers the design was based
around an existing VAX cabinet with the CPU cards using MIPS R3000
processors rather than VAX ones.

 As a curiosity the systems included a low-end VAX processor as well, as a
service unit for the purpose of console diagnostics and system bootstrap.  
The main CPU would be kept frozen until an OS was loaded at which point
the MIPS unit would get unlocked and start executing while the service
procesor would get halted.  AFAIK, the operation was controlled by some
external register and was atomic, never allowing the two processors to run
simultaneously.  Conceptually it was similar to how the original
VAX-11/780 and its console operated.

 We will probably never support any of these systems as getting these
pieces of hardware is problematic and then you need to use a lorry to move
them around.  Support for SMP operation of the 5800 would be particularly
tricky, because, as we all know too well, ;) the R3000 did not support
atomic operations and bus lock logic for atomic RMW cycles was provided by
the chipset.  All the relevant bits of code would have to be modified to
make use of it.  I am told NetBSD folks have had some success with one of
the machines; the 5500, I think.

 These DECsystem computers were designed by a different group to one which
did all the DECstations (WSE).  The same group also designed a small box
called DECsystem 5100 which was also similar to a VAX computer.  We have
some initial support for this machine implemented and if I got my hands on
an actual piece of hardware, I might consider getting it into a better
state.  Chances are our code as it is would crash on this system
immediately ;) -- otherwise the only supported peripheral might be the
serial port.

  Maciej