* [PATCH 01/37] Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 02/37] Add Cavium OCTEON files to arch/mips/include/asm/mach-cavium-octeon ddaney
` (35 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 92701 bytes --]
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/cavium-octeon/Kconfig | 85 +++++
arch/mips/cavium-octeon/Makefile | 21 ++
arch/mips/cavium-octeon/console.c | 34 ++
arch/mips/cavium-octeon/dma-octeon.c | 324 +++++++++++++++++++
arch/mips/cavium-octeon/flash_setup.c | 76 +++++
arch/mips/cavium-octeon/hal.c | 496 +++++++++++++++++++++++++++++
arch/mips/cavium-octeon/hal.h | 197 ++++++++++++
arch/mips/cavium-octeon/i8259.c | 180 +++++++++++
arch/mips/cavium-octeon/irq.c | 61 ++++
arch/mips/cavium-octeon/octeon-memcpy.S | 521 +++++++++++++++++++++++++++++++
arch/mips/cavium-octeon/serial.c | 187 +++++++++++
arch/mips/cavium-octeon/setup.c | 387 +++++++++++++++++++++++
arch/mips/cavium-octeon/smp.c | 231 ++++++++++++++
arch/mips/cavium-octeon/userio.c | 156 +++++++++
14 files changed, 2956 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/cavium-octeon/Kconfig
create mode 100644 arch/mips/cavium-octeon/Makefile
create mode 100644 arch/mips/cavium-octeon/console.c
create mode 100644 arch/mips/cavium-octeon/dma-octeon.c
create mode 100644 arch/mips/cavium-octeon/flash_setup.c
create mode 100644 arch/mips/cavium-octeon/hal.c
create mode 100644 arch/mips/cavium-octeon/hal.h
create mode 100644 arch/mips/cavium-octeon/i8259.c
create mode 100644 arch/mips/cavium-octeon/irq.c
create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S
create mode 100644 arch/mips/cavium-octeon/serial.c
create mode 100644 arch/mips/cavium-octeon/setup.c
create mode 100644 arch/mips/cavium-octeon/smp.c
create mode 100644 arch/mips/cavium-octeon/userio.c
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
new file mode 100644
index 0000000..094c17e
--- /dev/null
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -0,0 +1,85 @@
+config CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ bool "Enable Octeon specific options"
+ depends on CPU_CAVIUM_OCTEON
+ default "y"
+
+config CAVIUM_OCTEON_2ND_KERNEL
+ bool "Build the kernel to be used as a 2nd kernel on the same chip"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ default "n"
+ help
+ This option configures this kernel to be linked at a different
+ address and use the 2nd uart for output. This allows a kernel built
+ with this option to be run at the same time as one built without this
+ option.
+
+config CAVIUM_OCTEON_HW_FIX_UNALIGNED
+ bool "Enable hardware fixups of unaligned loads and stores"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ default "y"
+ help
+ Configure the Octeon hardware to automatically fix unaligned loads
+ and stores. Normally unaligned accesses are fixed using a kernel
+ exception handler. This option enables the hardware automatic fixups,
+ which requires only an extra 3 cycles. Disable this option if you
+ are running code that relies on address exceptions on unaligned
+ accesses.
+
+config CAVIUM_OCTEON_CVMSEG_SIZE
+ int "Number of L1 cache lines reserved for CVMSEG memory"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ range 0 54
+ default 1
+ help
+ CVMSEG LM is a segment that accesses portions of the dcache as a
+ local memory; the larger CVMSEG is, the smaller the cache is.
+ This selects the size of CVMSEG LM, which is in cache blocks. The
+ legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
+ between zero and 6192 bytes).
+
+config CAVIUM_OCTEON_LOCK_L2
+ bool "Lock often used kernel code in the L2"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ default "y"
+ help
+ Enable locking parts of the kernel into the L2 cache.
+
+config CAVIUM_OCTEON_LOCK_L2_TLB
+ bool "Lock the TLB handler in L2"
+ depends on CAVIUM_OCTEON_LOCK_L2
+ default "y"
+ help
+ Lock the low level TLB fast path into L2.
+
+config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
+ bool "Lock the exception handler in L2"
+ depends on CAVIUM_OCTEON_LOCK_L2
+ default "y"
+ help
+ Lock the low level exception handler into L2.
+
+config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
+ bool "Lock the interrupt handler in L2"
+ depends on CAVIUM_OCTEON_LOCK_L2
+ default "y"
+ help
+ Lock the low level interrupt handler into L2.
+
+config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
+ bool "Lock the 2nd level interrupt handler in L2"
+ depends on CAVIUM_OCTEON_LOCK_L2
+ default "y"
+ help
+ Lock the 2nd level interrupt handler in L2.
+
+config CAVIUM_OCTEON_LOCK_L2_MEMCPY
+ bool "Lock memcpy() in L2"
+ depends on CAVIUM_OCTEON_LOCK_L2
+ default "y"
+ help
+ Lock the kernel's implementation of memcpy() into L2.
+
+config ARCH_SPARSEMEM_ENABLE
+ def_bool y
+ select SPARSEMEM_STATIC
+ depends on CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
new file mode 100644
index 0000000..43d5a98
--- /dev/null
+++ b/arch/mips/cavium-octeon/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for the Cavium Octeon specific kernel interface routines
+# under Linux.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License. See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2005-2007 Cavium Networks
+#
+
+OCTEON_ROOT = $(srctree)/arch/mips/cavium-octeon
+EXTRA_CFLAGS += -I$(OCTEON_ROOT)/executive/config \
+ -I$(OCTEON_ROOT)/executive
+
+obj-y := setup.o serial.o irq.o hal.o
+obj-y += dma-octeon.o userio.o flash_setup.o
+obj-y += octeon-memcpy.o
+obj-y += console.o
+
+obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/cavium-octeon/console.c b/arch/mips/cavium-octeon/console.c
new file mode 100644
index 0000000..492a190
--- /dev/null
+++ b/arch/mips/cavium-octeon/console.c
@@ -0,0 +1,34 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Putting things on the screen/serial line using YAMONs facilities.
+ */
+#include "hal.h"
+
+int prom_putchar(char c)
+{
+ uint64_t lsrval;
+
+ /* Spin until there is room */
+ do {
+ lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
+ } while ((lsrval & 0x20) == 0);
+
+ /* Write the byte */
+ cvmx_write_csr(CVMX_MIO_UARTX_THR(0), c);
+ return 1;
+}
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
new file mode 100644
index 0000000..e74f59c
--- /dev/null
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -0,0 +1,324 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
+ * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
+ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
+ * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
+ * IP32 changes by Ilya.
+ * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
+ * the kernels original.
+ */
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+
+#include <linux/cache.h>
+#include <linux/io.h>
+
+#include <dma-coherence.h>
+
+#include "hal.h"
+#ifdef CONFIG_PCI
+#include "pci-common.h"
+#endif
+
+#define BAR2_PCI_ADDRESS 0x8000000000ul
+
+struct bar1_index_state {
+ int16_t ref_count; /* Number of PCI mappings using this index */
+ int16_t address_bits; /* Upper bits of physical address. This is
+ shifted 22 bits */
+};
+
+#ifdef CONFIG_PCI
+static DEFINE_SPINLOCK(bar1_lock);
+static struct bar1_index_state bar1_state[32] = { {0, 0}, };
+#endif
+
+dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
+{
+#ifndef CONFIG_PCI
+ /* Without PCI/PCIe this function can be called for Octeon internal
+ devices such as USB. These devices all support 64bit addressing */
+ return virt_to_phys(ptr);
+#else
+ unsigned long flags;
+ uint64_t dma_mask;
+ int64_t start_index;
+ dma_addr_t result = -1;
+ uint64_t physical = virt_to_phys(ptr);
+ int64_t index;
+
+ /* Use the DMA masks to determine the allowed memory region. For us it
+ doesn't limit the actual memory, just the address visible over PCI.
+ Devices with limits need to use lower indexed Bar1 entries. */
+ if (dev) {
+ dma_mask = dev->coherent_dma_mask;
+ if (dev->dma_mask)
+ dma_mask = *dev->dma_mask;
+ } else
+ dma_mask = 0xfffffffful;
+
+ /* Platform devices, such as the internal USB, skip all translation and
+ use Octeon physical addresses directly */
+ if (dev->bus == &platform_bus_type)
+ return physical;
+
+ switch (octeon_dma_bar_type) {
+ case OCTEON_DMA_BAR_TYPE_PCIE:
+ if (unlikely(physical < (16ul << 10)))
+ panic("dma_map_single: Not allowed to map first 16KB."
+ " It interferes with BAR0 special area\n");
+ else if ((physical + size >= (256ul << 20)) &&
+ (physical < (512ul << 20)))
+ panic("dma_map_single: Not allowed to map bootbus\n");
+ else if ((physical + size >= 0x400000000ull) &&
+ physical < 0x410000000ull)
+ panic("dma_map_single: "
+ "Attempt to map illegal memory address 0x%lx\n",
+ physical);
+ else if (physical >= 0x420000000ull)
+ panic("dma_map_single: "
+ "Attempt to map illegal memory address 0x%lx\n",
+ physical);
+ else if ((physical + size >=
+ (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
+ && physical < (4ull<<30))
+ pr_warning("dma_map_single: Warning: "
+ "Mapping memory address that might "
+ "conflict with devices 0x%lx-0x%lx\n",
+ physical, physical+size-1);
+ /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
+ if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
+ result = physical - 0x400000000ull;
+ else
+ result = physical;
+ if (((result+size-1) & dma_mask) != result+size-1)
+ panic("dma_map_single: Attempt to map address "
+ "0x%lx-0x%lx, which can't be accessed according "
+ "to the dma mask 0x%lx\n",
+ physical, physical+size-1, dma_mask);
+ goto done;
+
+ case OCTEON_DMA_BAR_TYPE_BIG:
+#ifdef CONFIG_64BIT
+ /* If the device supports 64bit addressing, then use BAR2 */
+ if (dma_mask > BAR2_PCI_ADDRESS) {
+ result = physical + BAR2_PCI_ADDRESS;
+ goto done;
+ }
+#endif
+ if (unlikely(physical < (4ul << 10))) {
+ panic("dma_map_single: Not allowed to map first 4KB. "
+ "It interferes with BAR0 special area\n");
+ } else if (physical < (256ul << 20)) {
+ if (unlikely(physical + size > (256ul << 20)))
+ panic("dma_map_single: Requested memory spans "
+ "Bar0 0:256MB and bootbus\n");
+ result = physical;
+ goto done;
+ } else if (unlikely(physical < (512ul << 20))) {
+ panic("dma_map_single: Not allowed to map bootbus\n");
+ } else if (physical < (2ul << 30)) {
+ if (unlikely(physical + size > (2ul << 30)))
+ panic("dma_map_single: Requested memory spans "
+ "Bar0 512MB:2GB and BAR1\n");
+ result = physical;
+ goto done;
+ } else if (physical < (2ul << 30) + (128 << 20)) {
+ /* Fall through */
+ } else if (physical <
+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
+ if (unlikely
+ (physical + size >
+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
+ panic("dma_map_single: Requested memory "
+ "extends past Bar1 (4GB-%luMB)\n",
+ OCTEON_PCI_BAR1_HOLE_SIZE);
+ result = physical;
+ goto done;
+ } else if ((physical >= 0x410000000ull) &&
+ (physical < 0x420000000ull)) {
+ if (unlikely(physical + size > 0x420000000ull))
+ panic("dma_map_single: Requested memory spans "
+ "non existant memory\n");
+ /* BAR0 fixed mapping 256MB:512MB ->
+ * 16GB+256MB:16GB+512MB */
+ result = physical - 0x400000000ull;
+ goto done;
+ } else {
+ /* Continued below switch statement */
+ }
+ break;
+
+ case OCTEON_DMA_BAR_TYPE_SMALL:
+#ifdef CONFIG_64BIT
+ /* If the device supports 64bit addressing, then use BAR2 */
+ if (dma_mask > BAR2_PCI_ADDRESS) {
+ result = physical + BAR2_PCI_ADDRESS;
+ goto done;
+ }
+#endif
+ /* Continued below switch statement */
+ break;
+
+ default:
+ panic("dma_map_single: Invalid octeon_dma_bar_type\n");
+ }
+
+ /* Don't allow mapping to span multiple Bar entries. The hardware guys
+ won't guarantee that DMA across boards work */
+ if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
+ panic("dma_map_single: "
+ "Requested memory spans more than one Bar1 entry\n");
+
+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+ start_index = 31;
+ else if (unlikely(dma_mask < (1ul << 27)))
+ start_index = (dma_mask >> 22);
+ else
+ start_index = 31;
+
+ /* Only one processor can access the Bar register at once */
+ spin_lock_irqsave(&bar1_lock, flags);
+
+ /* Look through Bar1 for existing mapping that will work */
+ for (index = start_index; index >= 0; index--) {
+ if ((bar1_state[index].address_bits == physical >> 22) &&
+ (bar1_state[index].ref_count)) {
+ /* An existing mapping will work, use it */
+ bar1_state[index].ref_count++;
+ if (unlikely(bar1_state[index].ref_count < 0))
+ panic("dma_map_single: "
+ "Bar1[%d] reference count overflowed\n",
+ (int) index);
+ result = (index << 22) | (physical & ((1 << 22) - 1));
+ /* Large BAR1 is offset at 2GB */
+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+ result += 2ul << 30;
+ goto done_unlock;
+ }
+ }
+
+ /* No existing mappings, look for a free entry */
+ for (index = start_index; index >= 0; index--) {
+ if (unlikely(bar1_state[index].ref_count == 0)) {
+ cvmx_pci_bar1_indexx_t bar1_index;
+ /* We have a free entry, use it */
+ bar1_state[index].ref_count = 1;
+ bar1_state[index].address_bits = physical >> 22;
+ bar1_index.u32 = 0;
+ /* Address bits[35:22] sent to L2C */
+ bar1_index.s.addr_idx = physical >> 22;
+ /* Don't put PCI accesses in L2. */
+ bar1_index.s.ca = 1;
+ /* Endian Swap Mode */
+ bar1_index.s.end_swp = 1;
+ /* Set '1' when the selected address range is valid. */
+ bar1_index.s.addr_v = 1;
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+ bar1_index.u32);
+ /* An existing mapping will work, use it */
+ result = (index << 22) | (physical & ((1 << 22) - 1));
+ /* Large BAR1 is offset at 2GB */
+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+ result += 2ul << 30;
+ goto done_unlock;
+ }
+ }
+
+ pr_err("dma_map_single: "
+ "Can't find empty BAR1 index for physical mapping 0x%llx\n",
+ (unsigned long long) physical);
+
+ done_unlock:
+ spin_unlock_irqrestore(&bar1_lock, flags);
+ done:
+ pr_debug("dma_map_single 0x%lx->0x%lx\n", physical, result);
+ return result;
+#endif
+}
+
+void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+{
+#ifndef CONFIG_PCI
+ /* Without PCI/PCIe this function can be called for Octeon internal
+ * devices such as USB. These devices all support 64bit addressing */
+ return;
+#else
+ unsigned long flags;
+ uint64_t index;
+
+ /* Platform devices, such as the internal USB, skip all translation and
+ use Octeon physical addresses directly */
+ if (dev->bus == &platform_bus_type)
+ return;
+
+ switch (octeon_dma_bar_type) {
+ case OCTEON_DMA_BAR_TYPE_PCIE:
+ /* Nothing to do, all mappings are static */
+ goto done;
+
+ case OCTEON_DMA_BAR_TYPE_BIG:
+#ifdef CONFIG_64BIT
+ /* Nothing to do for addresses using BAR2 */
+ if (dma_addr >= BAR2_PCI_ADDRESS)
+ goto done;
+#endif
+ if (unlikely(dma_addr < (4ul << 10)))
+ panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
+ dma_addr);
+ else if (dma_addr < (2ul << 30))
+ /* Nothing to do for addresses using BAR0 */
+ goto done;
+ else if (dma_addr < (2ul << 30) + (128ul << 20))
+ /* Need to unmap, fall through */
+ index = (dma_addr - (2ul << 30)) >> 22;
+ else if (dma_addr <
+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
+ goto done; /* Nothing to do for the rest of BAR1 */
+ else
+ panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
+ dma_addr);
+ /* Continued below switch statement */
+ break;
+
+ case OCTEON_DMA_BAR_TYPE_SMALL:
+#ifdef CONFIG_64BIT
+ /* Nothing to do for addresses using BAR2 */
+ if (dma_addr >= BAR2_PCI_ADDRESS)
+ goto done;
+#endif
+ index = dma_addr >> 22;
+ /* Continued below switch statement */
+ break;
+
+ default:
+ panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+ }
+
+ if (unlikely(index > 31))
+ panic("dma_unmap_single: "
+ "Attempt to unmap an invalid address (0x%llx)\n",
+ (unsigned long long) dma_addr);
+
+ spin_lock_irqsave(&bar1_lock, flags);
+ bar1_state[index].ref_count--;
+ if (bar1_state[index].ref_count == 0)
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+ else if (unlikely(bar1_state[index].ref_count < 0))
+ panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
+ (int) index);
+ spin_unlock_irqrestore(&bar1_lock, flags);
+ done:
+ pr_debug("dma_unmap_single 0x%lx\n", dma_addr);
+ return;
+#endif
+}
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
new file mode 100644
index 0000000..f66edb2
--- /dev/null
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -0,0 +1,76 @@
+/*
+ * Octeon Bootbus flash setup
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include "hal.h"
+
+static struct map_info flash_map;
+static struct mtd_info *mymtd;
+#ifdef CONFIG_MTD_PARTITIONS
+static int nr_parts;
+static struct mtd_partition *parts;
+static const char *part_probe_types[] = {
+ "cmdlinepart",
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ "RedBoot",
+#endif
+ NULL
+};
+#endif
+
+/**
+ * Module/ driver initialization.
+ *
+ * @return Zero on success
+ */
+static int __init flash_init(void)
+{
+ /* Read the bootbus region 0 setup to determine where the base of flash
+ is set for */
+ cvmx_mio_boot_reg_cfgx_t region_cfg;
+ region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFG0);
+ if (region_cfg.s.en) {
+ /* The bootloader always takes the flash and sets its address
+ so the entire flash fits below 0x1fc00000. This way the
+ flash aliases to 0x1fc00000 for booting. Software can access
+ the full flash at the true address, while core boot can
+ access 4MB */
+ flash_map.name = "phys_mapped_flash"; /* Use this name so old
+ part lines work */
+ flash_map.phys = region_cfg.s.base << 16;
+ flash_map.size = 0x1fc00000 - flash_map.phys;
+ flash_map.bankwidth = 1;
+ flash_map.virt = ioremap(flash_map.phys, flash_map.size);
+ pr_notice("Bootbus flash: Setting flash for %luMB flash at 0x%08lx\n", flash_map.size >> 20, flash_map.phys);
+ simple_map_init(&flash_map);
+ mymtd = do_map_probe("cfi_probe", &flash_map);
+ if (mymtd) {
+ mymtd->owner = THIS_MODULE;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ nr_parts =
+ parse_mtd_partitions(mymtd, part_probe_types,
+ &parts, 0);
+ if (nr_parts > 0)
+ add_mtd_partitions(mymtd, parts, nr_parts);
+ else
+ add_mtd_device(mymtd);
+#else
+ add_mtd_device(mymtd);
+#endif
+ } else
+ pr_err("Failed to register MTD device for flash\n");
+ }
+ return 0;
+}
+
+late_initcall(flash_init);
diff --git a/arch/mips/cavium-octeon/hal.c b/arch/mips/cavium-octeon/hal.c
new file mode 100644
index 0000000..baff76f
--- /dev/null
+++ b/arch/mips/cavium-octeon/hal.c
@@ -0,0 +1,496 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 - 2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#include <asm/time.h>
+
+#include <octeon-app-init.h>
+
+#ifndef CONFIG_CAVIUM_RESERVE32
+#define CONFIG_CAVIUM_RESERVE32 0
+#endif
+
+#include "hal.h"
+
+#include "cvmx-bootmem.h"
+#include "cvmx-bootinfo.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-l2c.h"
+
+extern void add_wired_entry(unsigned long entrylo0,
+ unsigned long entrylo1,
+ unsigned long entryhi,
+ unsigned long pagemask);
+extern asmlinkage void handle_int(void);
+extern asmlinkage void plat_irq_dispatch(void);
+
+/* Set to non-zero, so it is not in .bss section and is not zeroed */
+volatile octeon_boot_descriptor_t *octeon_boot_desc_ptr = (void *) 0xEADBEEFULL;
+cvmx_bootinfo_t *octeon_bootinfo;
+
+/* This must not be static since inline functions access it */
+spinlock_t octeon_led_lock;
+
+#if CONFIG_CAVIUM_RESERVE32
+uint64_t octeon_reserve32_memory;
+#endif
+
+
+/**
+ * Write to the LCD display connected to the bootbus. This display
+ * exists on most Cavium evaluation boards. If it doesn't exist, then
+ * this function doesn't do anything.
+ *
+ * @param s String to write
+ */
+void octeon_write_lcd(const char *s)
+{
+ if (octeon_bootinfo->led_display_base_addr) {
+ volatile char *lcd_address =
+ cvmx_phys_to_ptr(octeon_bootinfo->
+ led_display_base_addr);
+ int i;
+ for (i = 0; i < 8; i++) {
+ if (*s)
+ lcd_address[i] = *s++;
+ else
+ lcd_address[i] = ' ';
+ }
+ }
+}
+
+
+/**
+ * Check the hardware BIST results for a CPU
+ */
+void octeon_check_cpu_bist(void)
+{
+ const int coreid = cvmx_get_core_num();
+ unsigned long long mask;
+ unsigned long long bist_val;
+
+ /* Check BIST results for COP0 registers */
+ mask = 0x1f00000000ull;
+ bist_val = __read_64bit_c0_register($27, 0);
+ if (bist_val & mask)
+ pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
+ coreid, bist_val);
+
+ bist_val = __read_64bit_c0_register($27, 1);
+ if (bist_val & 1)
+ pr_err("Core%d L1 Dcache parity error: "
+ "CacheErr(dcache) = 0x%llx\n",
+ coreid, bist_val);
+
+ mask = 0xfc00000000000000ull;
+ bist_val = __read_64bit_c0_register($11, 7);
+ if (bist_val & mask)
+ pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
+ coreid, bist_val);
+
+ __write_64bit_c0_register($27, 1, 0);
+}
+
+
+/**
+ * Return non zero if we are currently running in the Octeon simulator
+ *
+ * @return
+ */
+int octeon_is_simulation(void)
+{
+ return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
+}
+
+
+/**
+ * Return true if Octeon is in PCI Host mode. This means
+ * Linux can control the PCI bus.
+ *
+ * @return Non zero if Octeon in host mode
+ */
+int octeon_is_pci_host(void)
+{
+#ifdef CONFIG_PCI
+ return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
+#else
+ return 0;
+#endif
+}
+
+
+/**
+ * This function returns if the USB clock uses 12/24/48MHz 3.3V
+ * reference clock at the USB_REF_CLK pin. Result is non zero
+ * if it does, If it uses 12MHz crystal as clock source at USB_XO
+ * and USB_XI, then the return value is zero. This function will
+ * need update for new boards.
+ *
+ * @return True is USB is using a reference clock
+ */
+int octeon_usb_is_ref_clk(void)
+{
+ switch (octeon_bootinfo->board_type) {
+ case CVMX_BOARD_TYPE_BBGW_REF:
+ return 0;
+ }
+ return 1;
+}
+
+
+/**
+ * Get the clock rate of Octeon
+ *
+ * @return Clock rate in HZ
+ */
+uint64_t octeon_get_clock_rate(void)
+{
+ if (octeon_is_simulation())
+ octeon_bootinfo->eclock_hz = 6000000;
+ return octeon_bootinfo->eclock_hz;
+}
+
+
+/**
+ * Return the board name as a constant string
+ *
+ * @return board name
+ */
+const char *octeon_board_type_string(void)
+{
+ static char name[80];
+ sprintf(name, "%s (%s)",
+ cvmx_board_type_to_string(octeon_bootinfo->board_type),
+ octeon_model_get_string(read_c0_prid()));
+ return name;
+}
+
+
+/**
+ * Return the interrupt line for the i8259 in the southbridge
+ *
+ * @return
+ */
+int octeon_get_southbridge_interrupt(void)
+{
+ switch (octeon_bootinfo->board_type) {
+ case CVMX_BOARD_TYPE_EBH3000:
+ return 47; /* PCI INDD */
+ case CVMX_BOARD_TYPE_NAC38:
+ return 39; /* GPIO 15 */
+ default:
+ return 0; /* No southbridge */
+ }
+}
+
+
+/**
+ * Get the coremask Linux was booted on.
+ *
+ * @return Core mask
+ */
+int octeon_get_boot_coremask(void)
+{
+ return octeon_boot_desc_ptr->core_mask;
+}
+
+
+/**
+ * Return the number of arguments we got from the bootloader
+ *
+ * @return argc
+ */
+int octeon_get_boot_num_arguments(void)
+{
+ return octeon_boot_desc_ptr->argc;
+}
+
+
+/**
+ * Return the console uart passed by the bootloader
+ *
+ * @return uart (0 or 1)
+ */
+int octeon_get_boot_uart(void)
+{
+#if OCTEON_APP_INIT_H_VERSION >= 1 /* The UART1 flag is new */
+ return !!(octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1);
+#else
+ return 0;
+#endif
+}
+
+/**
+ * Return the debug flag passed by the bootloader
+ *
+ * @return debug flag (0 or 1)
+ */
+int octeon_get_boot_debug_flag(void)
+{
+ return !!(octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_DEBUG);
+}
+
+/**
+ * Get an argument from the bootloader
+ *
+ * @param arg argument to get
+ * @return argument
+ */
+const char *octeon_get_boot_argument(int arg)
+{
+ return cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[arg]);
+}
+
+
+/**
+ * Called very early in the initial C code to initialize the Octeon
+ * HAL layer.
+ */
+void octeon_hal_init(void)
+{
+ cvmx_sysinfo_t *sysinfo;
+
+ /* Make sure we got the boot descriptor block */
+ if ((octeon_boot_desc_ptr == (void *) 0xEADBEEFULL))
+ panic("Boot descriptor block wasn't passed properly\n");
+
+ octeon_bootinfo =
+ cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
+ cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
+
+ spin_lock_init(&octeon_led_lock);
+ /* Only enable the LED controller if we're running on a CN38XX, CN58XX,
+ or CN56XX. The CN30XX and CN31XX don't have an LED controller */
+ if (!octeon_is_simulation() &&
+ octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
+ cvmx_write_csr(CVMX_LED_EN, 0);
+ cvmx_write_csr(CVMX_LED_PRT, 0);
+ cvmx_write_csr(CVMX_LED_DBG, 0);
+ cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
+ cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
+ cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
+ cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
+ cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
+ cvmx_write_csr(CVMX_LED_EN, 1);
+ }
+#if CONFIG_CAVIUM_RESERVE32
+ {
+ int64_t addr = -1;
+ /* We need to temporarily allocate all memory in the reserve32
+ region. This makes sure the kernel doesn't allocate this
+ memory when it is getting memory from the bootloader. Later,
+ after the memory allocations are complete, the reserve32
+ will be freed */
+#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
+ if (CONFIG_CAVIUM_RESERVE32 & 0x1ff)
+ pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. This is required if CAVIUM_RESERVE32_USE_WIRED_TLB is set\n");
+ else
+ addr = cvmx_bootmem_phy_named_block_alloc
+ (CONFIG_CAVIUM_RESERVE32 << 20, 0, 0, 512 << 20,
+ "CAVIUM_RESERVE32", 0);
+#else
+ /* Allocate memory for RESERVED32 aligned on 2MB boundary. This
+ is in case we later use hugetlb entries with it */
+ addr = cvmx_bootmem_phy_named_block_alloc
+ (CONFIG_CAVIUM_RESERVE32 << 20, 0, 0, 2 << 20,
+ "CAVIUM_RESERVE32", 0);
+#endif
+ if (addr < 0)
+ pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
+ else
+ octeon_reserve32_memory = addr;
+
+ }
+#endif
+
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
+ if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
+ pr_info("Skipping L2 locking due to reduced L2 cache size\n");
+ } else {
+ uint32_t ebase = read_c0_ebase() & 0x3ffff000;
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
+ cvmx_l2c_lock_mem_region(ebase, 0x100); /* TLB refill */
+#endif
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
+ cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); /* General
+ exception */
+#endif
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
+ cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); /* Interrupt
+ handler */
+#endif
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
+ cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
+ cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
+#endif
+#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
+ cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
+#endif
+ }
+#endif
+
+ sysinfo = cvmx_sysinfo_get();
+ memset(sysinfo, 0, sizeof(*sysinfo));
+ sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
+ sysinfo->phy_mem_desc_ptr =
+ cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
+ sysinfo->core_mask = octeon_bootinfo->core_mask;
+ sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
+ sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
+ sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
+ sysinfo->board_type = octeon_bootinfo->board_type;
+ sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
+ sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
+ memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
+ sizeof(sysinfo->mac_addr_base));
+ sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
+ memcpy(sysinfo->board_serial_number,
+ octeon_bootinfo->board_serial_number,
+ sizeof(sysinfo->board_serial_number));
+ sysinfo->compact_flash_common_base_addr =
+ octeon_bootinfo->compact_flash_common_base_addr;
+ sysinfo->compact_flash_attribute_base_addr =
+ octeon_bootinfo->compact_flash_attribute_base_addr;
+ sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
+ sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
+ sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
+}
+
+
+#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
+/**
+ * Called on every core to setup the wired tlb entry needed
+ * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set.
+ *
+ * @param unused
+ */
+static void octeon_hal_setup_per_cpu_reserved32(void *unused)
+{
+ /* The config has selected to wire the reserve32 memory for all
+ userspace applications. We need to put a wired TLB entry in for each
+ 512MB of reserve32 memory. We only handle double 256MB pages here,
+ so reserve32 must be multiple of 512MB */
+ uint32_t size = CONFIG_CAVIUM_RESERVE32;
+ uint32_t entrylo0 =
+ 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6);
+ uint32_t entrylo1 = entrylo0 + (256 << 14);
+ uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20));
+ while (size >= 512) {
+ /*
+ pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n",
+ smp_processor_id(), entryhi);
+ */
+ add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M);
+ entrylo0 += 512 << 14;
+ entrylo1 += 512 << 14;
+ entryhi += 512 << 20;
+ size -= 512;
+ }
+}
+#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */
+
+/**
+ * Called to release the named block which was used to made sure
+ * that nobody used the memory for something else during
+ * init. Now we'll free it so userspace apps can use this
+ * memory region with bootmem_alloc.
+ *
+ * This function is called only once from prom_free_prom_memory().
+ */
+void octeon_hal_setup_reserved32(void)
+{
+#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
+ on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1);
+#endif
+}
+
+
+/**
+ * Poweroff the Octeon board if possible.
+ */
+void octeon_poweroff(void)
+{
+ switch (octeon_bootinfo->board_type) {
+ case CVMX_BOARD_TYPE_NAO38:
+ /* Driving a 1 to GPIO 12 shuts off this board */
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
+ cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
+ break;
+ default:
+ octeon_write_lcd("PowerOff");
+ break;
+ }
+}
+
+
+/**
+ * Enable access to Octeon's COP2 crypto hardware for kernel use.
+ * Wrap any crypto operations in calls to
+ * octeon_crypto_enable/disable in order to make sure the state of
+ * COP2 isn't corrupted if userspace is also performing hardware
+ * crypto operations. Allocate the state parameter on the stack.
+ *
+ * @param state State structure to store current COP2 state in
+ *
+ * @return Flags to be passed to octeon_crypto_disable()
+ */
+unsigned long octeon_crypto_enable(struct octeon_cop2_state *state)
+{
+ extern void octeon_cop2_save(struct octeon_cop2_state *);
+ int status;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ status = read_c0_status();
+ write_c0_status(status | ST0_CU2);
+ if (KSTK_STATUS(current) & ST0_CU2) {
+ octeon_cop2_save(&(current->thread.cp2));
+ KSTK_STATUS(current) &= ~ST0_CU2;
+ status &= ~ST0_CU2;
+ } else if (status & ST0_CU2)
+ octeon_cop2_save(state);
+ local_irq_restore(flags);
+ return status & ST0_CU2;
+}
+EXPORT_SYMBOL(octeon_crypto_enable);
+
+
+/**
+ * Disable access to Octeon's COP2 crypto hardware in the kernel.
+ * This must be called after an octeon_crypto_enable() before any
+ * context switch or return to userspace.
+ *
+ * @param state COP2 state to restore
+ * @param flags Return value from octeon_crypto_enable()
+ */
+void octeon_crypto_disable(struct octeon_cop2_state *state, unsigned long crypto_flags)
+{
+ extern void octeon_cop2_restore(struct octeon_cop2_state *);
+ unsigned long flags;
+
+ local_irq_save(flags);
+ if (crypto_flags & ST0_CU2)
+ octeon_cop2_restore(state);
+ else
+ write_c0_status(read_c0_status() & ~ST0_CU2);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(octeon_crypto_disable);
+
+
+
+/* Misc exports */
+EXPORT_SYMBOL(octeon_is_simulation);
+EXPORT_SYMBOL(octeon_bootinfo);
+#if CONFIG_CAVIUM_RESERVE32
+EXPORT_SYMBOL(octeon_reserve32_memory);
+#endif
+
+EXPORT_SYMBOL(octeon_get_clock_rate);
diff --git a/arch/mips/cavium-octeon/hal.h b/arch/mips/cavium-octeon/hal.h
new file mode 100644
index 0000000..afa0759
--- /dev/null
+++ b/arch/mips/cavium-octeon/hal.h
@@ -0,0 +1,197 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#ifndef __CAVIUM_OCTEON_HAL_H
+#define __CAVIUM_OCTEON_HAL_H
+
+#include "octeon-hal-read-write.h"
+
+#ifndef __BYTE_ORDER
+# error "__BYTE_ORDER not set"
+#endif
+#ifndef __BIG_ENDIAN
+# error "__BIG_ENDIAN not set"
+#endif
+
+extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
+ uint64_t alignment,
+ uint64_t min_addr,
+ uint64_t max_addr,
+ int do_locking);
+extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
+ int do_locking);
+extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
+ uint64_t min_addr, uint64_t max_addr,
+ int do_locking);
+extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+ char *name);
+extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr, uint64_t align,
+ char *name);
+extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+ char *name);
+extern int octeon_bootmem_free_named(char *name);
+extern void octeon_bootmem_lock(void);
+extern void octeon_bootmem_unlock(void);
+
+extern int octeon_is_simulation(void);
+extern int octeon_is_pci_host(void);
+extern int octeon_usb_is_ref_clk(void);
+extern uint64_t octeon_get_clock_rate(void);
+extern const char *octeon_board_type_string(void);
+extern const char *octeon_get_pci_interrupts(void);
+extern int octeon_get_southbridge_interrupt(void);
+extern int octeon_get_boot_coremask(void);
+extern int octeon_get_boot_num_arguments(void);
+extern const char *octeon_get_boot_argument(int arg);
+extern void octeon_hal_setup_reserved32(void);
+struct octeon_cop2_state;
+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
+extern void octeon_crypto_disable(struct octeon_cop2_state *state,
+ unsigned long flags);
+
+typedef union {
+ uint64_t u64;
+ struct {
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t tlbbist:1;
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t l1cbist:1;
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t l1dbist:1;
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t dcmbist:1;
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t ptgbist:1;
+ /* RO 1 = BIST fail, 0 = BIST pass */
+ uint64_t wbfbist:1;
+ /* Reserved */
+ uint64_t reserved:22;
+ /* R/W If set, marked write-buffer entries time out
+ * the same as as other entries; if clear, marked
+ * write-buffer entries use the maximum timeout. */
+ uint64_t dismarkwblongto:1;
+ /* R/W If set, a merged store does not clear the
+ * write-buffer entry timeout state. */
+ uint64_t dismrgclrwbto:1;
+ /* R/W Two bits that are the MSBs of the resultant
+ * CVMSEG LM word location for an IOBDMA. The other 8
+ * bits come from the SCRADDR field of the IOBDMA. */
+ uint64_t iobdmascrmsb:2;
+ /* R/W If set, SYNCWS and SYNCS only order marked
+ * stores; if clear, SYNCWS and SYNCS only order
+ * unmarked stores. SYNCWSMARKED has no effect when
+ * DISSYNCWS is set. */
+ uint64_t syncwsmarked:1;
+ /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
+ * SYNC. */
+ uint64_t dissyncws:1;
+ /* R/W If set, no stall happens on write buffer
+ * full. */
+ uint64_t diswbfst:1;
+ /* R/W If set (and SX set), supervisor-level
+ * loads/stores can use XKPHYS addresses with
+ * VA<48>==0 */
+ uint64_t xkmemenas:1;
+ /* R/W If set (and UX set), user-level loads/stores
+ * can use XKPHYS addresses with VA<48>==0 */
+ uint64_t xkmemenau:1;
+ /* R/W If set (and SX set), supervisor-level
+ * loads/stores can use XKPHYS addresses with
+ * VA<48>==1 */
+ uint64_t xkioenas:1;
+ /* R/W If set (and UX set), user-level loads/stores
+ * can use XKPHYS addresses with VA<48>==1 */
+ uint64_t xkioenau:1;
+ /* R/W If set, all stores act as SYNCW (NOMERGE must
+ * be set when this is set) RW, reset to 0. */
+ uint64_t allsyncw:1;
+ /* R/W If set, no stores merge, and all stores reach
+ * the coherent bus in order. */
+ uint64_t nomerge:1;
+ /* R/W Selects the bit in the counter used for DID
+ * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
+ * 214. Actual time-out is between 1� and 2� this
+ * interval. For example, with DIDTTO=3, expiration
+ * interval is between 16K and 32K. */
+ uint64_t didtto:2;
+ /* R/W If set, the (mem) CSR clock never turns off. */
+ uint64_t csrckalwys:1;
+ /* R/W If set, mclk never turns off. */
+ uint64_t mclkalwys:1;
+ /* R/W Selects the bit in the counter used for write
+ * buffer flush time-outs (WBFLT+11) is the bit
+ * position in an internal counter used to determine
+ * expiration. The write buffer expires between 1� and
+ * 2� this interval. For example, with WBFLT = 0, a
+ * write buffer expires between 2K and 4K cycles after
+ * the write buffer entry is allocated. */
+ uint64_t wbfltime:3;
+ /* R/W If set, do not put Istream in the L2 cache. */
+ uint64_t istrnol2:1;
+ /* R/W The write buffer threshold. */
+ uint64_t wbthresh:4;
+ /* Reserved */
+ uint64_t reserved2:2;
+ /* R/W If set, CVMSEG is available for loads/stores in
+ * kernel/debug mode. */
+ uint64_t cvmsegenak:1;
+ /* R/W If set, CVMSEG is available for loads/stores in
+ * supervisor mode. */
+ uint64_t cvmsegenas:1;
+ /* R/W If set, CVMSEG is available for loads/stores in
+ * user mode. */
+ uint64_t cvmsegenau:1;
+ /* R/W Size of local memory in cache blocks, 54 (6912
+ * bytes) is max legal value. */
+ uint64_t lmemsz:6;
+ } s;
+} octeon_cvmemctl_t;
+
+static inline void octeon_led_write(int bank, uint32_t data)
+{
+ cvmx_write_csr(CVMX_LED_UDD_DATX(bank), data);
+}
+
+static inline uint32_t octeon_led_read(int bank)
+{
+ return cvmx_read_csr(CVMX_LED_UDD_DATX(bank));
+}
+
+static inline void octeon_led_set(int bank, int bit)
+{
+ cvmx_write_csr(CVMX_LED_UDD_DAT_SETX(bank), 1 << bit);
+}
+
+static inline void octeon_led_clear(int bank, int bit)
+{
+ cvmx_write_csr(CVMX_LED_UDD_DAT_CLRX(bank), 1 << bit);
+}
+
+static inline unsigned long octeon_get_cycles(void)
+{
+ unsigned long result;
+ asm volatile ("rdhwr %0,$31\n\t"
+#ifndef CONFIG_64BIT
+ "sll %0,0"
+#endif
+ : "=r" (result));
+ return result;
+}
+
+extern void octeon_write_lcd(const char *s);
+extern void octeon_check_cpu_bist(void);
+extern void octeon_hal_init(void);
+extern int octeon_get_boot_uart(void);
+extern int octeon_get_boot_debug_flag(void);
+extern void octeon_poweroff(void);
+
+struct uart_port;
+extern unsigned int octeon_serial_in(struct uart_port *, int);
+extern void octeon_serial_out(struct uart_port *, int, int);
+
+#endif
diff --git a/arch/mips/cavium-octeon/i8259.c b/arch/mips/cavium-octeon/i8259.c
new file mode 100644
index 0000000..bfa8ade
--- /dev/null
+++ b/arch/mips/cavium-octeon/i8259.c
@@ -0,0 +1,180 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006-2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include "hal.h"
+
+#define SLAVE (0xa0 - 0x20)
+
+/* Initialization Command Word 1 (ICW1 address 0x20 or 0xa0) */
+/* 7:5 Interrupt Vector Addresses for MCS-80/85 Mode. */
+#define ICW1_ADDRESS 0x20
+#define ICW1 0x10 /* 4 Must be set to 1 for ICW1 */
+#define ICW1_LEVEL_TRIG (1<<3) /* 3 1 Level Triggered Interrupts, 0 Edge
+ Triggered Interrupts */
+#define ICW1_INTERVAL4 (1<<2) /* 2 1 Call Address Interval of 4, 0 Call
+ Address Interval of 8 */
+#define ICW1_SINGLE_PIC (1<<1) /* 1 1 Single PIC, 0 Cascaded PICs */
+#define ICW1_NEED_ICW4 (1<<0) /* 0 1 Will be Sending ICW4,
+ 0 Don't need ICW4 */
+
+/* Initialization Command Word 2 (ICW2 address 0x21 or 0xa1) */
+#define ICW2_ADDRESS 0x21
+/* Bit 8086/8080 Mode MCS 80/85 Mode 7 I7 A15 6 I6 A14 5 I5 A13 4 I4 A12 3 I3
+ A11 2 - A10 1 - A9 0 - A8 */
+
+/* Initialization Command Word 3 (ICW3 address 0x21 or 0xa1) For the master,
+ this is a bitfield saying which line is hooked to a slave. For a slave, this
+ is the slave's ID, the line it is hooked to */
+#define ICW3_ADDRESS 0x21
+
+/* Initialization Command Word 4 (ICW4 address 0x21 or 0xa1) */
+/* Bits 7-5 are reserved */
+#define ICW4_ADDRESS 0x21
+#define ICW4_FULLY_NESTED (1<<4) /* 4 1 Special Fully Nested Mode, 0 Not
+ Special Fully Nested Mode */
+#define ICW4_BUFFERED (3<<2) /* 3 1 Buffered Mode, 0 Unbuffered */
+#define ICW4_MASTER (2<<2) /* 2 1 Master, 0 Slave */
+#define ICW4_AUTO_EOI (1<<1) /* 1 1 Auto EOI, 0 Normal EOI */
+#define ICW4_8086 (1<<0) /* 0 1 8086/8080 Mode, 0 MCS-80/85 */
+
+/* Operation Control Word 1 (OCW1 address 0x21 or 0xa1) This is a bitmask for
+ each interrupt */
+#define OCW1_ADDRESS 0x21
+
+/* Operation Control Word 2 (OCW2 address 0x20 or 0xa0) */
+#define OCW2_ADDRESS 0x20
+#define OCW2 0x00 /* Bits 4:3 must be zero */
+#define OCW2_ROTATE_AUTO_EOI_CLEAR (0<<5) /* 7:5 000 Rotate in Auto EOI
+ Mode (Clear) */
+#define OCW2_NON_SPECIFIC_EOI (1<<5) /* 001 Non Specific EOI */
+#define OCW2_NOP (2<<5) /* 010 NOP */
+#define OCW2_SPECIFIC_EOI (3<<5) /* 011 Specific EOI */
+#define OCW2_ROTATE_AUTO_EOI_SET (4<<5) /* 100 Rotate in Auto EOI Mode
+ (Set) */
+#define OCW2_ROTATE_NON_SPECIFIC_EOI (5<<5) /* 101 Rotate on Non-Specific
+ EOI */
+#define OCW2_SET_PRIORITY (6<<5) /* 110 Set Priority Command
+ (Use Bits 2:0) */
+#define OCW2_ROTATE_SPECIFIC_EOI (7<<5) /* 111 Rotate on Specific EOI
+ (Use Bits 2:0) */
+
+/* Operation Control Word 3 (OCW3 address 0x20 or 0xa0) */
+/* Bit 7 Must be set to 0 */
+#define OCW3_ADDRESS 0x20
+#define OCW3 0x08 /* 4:3 Must be set to 01 */
+#define OCW3_RESET_SPECIAL_MASK (2<<5) /* 6:5 00 Reserved, 01 Reserved, 10
+ Reset Special Mask */
+#define OCW3_SET_SPECIAL_MASK (3<<5) /* 11 Set Special Mask */
+#define OCW3_POLL (1<<2) /* 2 1 Poll Command,
+ 0 No Poll Command */
+#define OCW3_READ_IRR (2<<0) /* 1:0 00 Reserved, 01 Reserved, 10
+ Next Read Returns Interrupt Request
+ Register */
+#define OCW3_READ_ISR (3<<0) /* 11 Next Read Returns In-Service
+ Register */
+
+
+static irqreturn_t octeon_i8259_interrupt(int cpl, void *dev_id)
+{
+ u8 master_isr;
+ u8 slave_isr;
+
+ outb(OCW3 | OCW3_POLL, OCW3_ADDRESS);
+ master_isr = inb(OCW3_ADDRESS);
+ if (master_isr & 0x80) { /* Top bit is set if the master
+ requested the interrupt */
+ if ((master_isr & 0x7) == 2) {
+ outb(OCW3 | OCW3_POLL, OCW3_ADDRESS + SLAVE);
+ slave_isr = inb(OCW3_ADDRESS + SLAVE);
+ if (slave_isr & 0x80) { /* Top bit is set if the slave
+ requested the interrupt */
+ int irq = (slave_isr & 7) + OCTEON_IRQ_I8259S0;
+ pr_debug("8259: Interrupt %d from slave\n",
+ irq);
+ if (irq_desc[irq].action)
+ do_IRQ(irq);
+
+ /* Ack the slave */
+ outb(OCW2 | OCW2_SPECIFIC_EOI | (slave_isr & 7),
+ OCW2_ADDRESS + SLAVE);
+ } else
+ pr_err("8259: Spurious interrupt from "
+ "master for slave\n");
+ } else {
+ int irq = (master_isr & 7) + OCTEON_IRQ_I8259M0;
+ /*
+ pr_debug("8259: Interrupt %d from master\n", irq);
+ */
+ if (irq_desc[irq].action)
+ do_IRQ(irq);
+ }
+
+ /* Ack the master */
+ outb(OCW2 | OCW2_SPECIFIC_EOI | (master_isr & 7), OCW2_ADDRESS);
+
+ return IRQ_HANDLED;
+ } else {
+ pr_err("8259: Spurious interrupt from master\n");
+ return IRQ_NONE;
+ }
+}
+
+void octeon_i8259_setup(int irq_line)
+{
+ /* Setup the Master 8259 */
+ /* Begin the init sequence */
+ outb(ICW1 | ICW1_NEED_ICW4, ICW1_ADDRESS);
+ /* Master base address is zero, interrupts 0-7 */
+ outb(0, ICW2_ADDRESS);
+ /* Slave is connected to line 2 */
+ outb(1 << 2, ICW3_ADDRESS);
+ /* Set the mode to buffered with edge triggering */
+ outb(ICW4_FULLY_NESTED | ICW4_MASTER | ICW4_BUFFERED | ICW4_8086,
+ ICW4_ADDRESS);
+ /* Read ISR */
+ outb(OCW3 | OCW3_READ_ISR, OCW3_ADDRESS);
+
+ /* Setup the Slave 8259 */
+ /* Begin the init sequence */
+ outb(ICW1 | ICW1_NEED_ICW4, ICW1_ADDRESS + SLAVE);
+ /* Slave base address is 8, interrupts 8-15 */
+ outb(8, ICW2_ADDRESS + SLAVE);
+ /* Slave is connected to line 2 */
+ outb(2, ICW3_ADDRESS + SLAVE);
+ /* Set the mode to buffered with edge triggering */
+ outb(ICW4_BUFFERED | ICW4_8086, ICW4_ADDRESS + SLAVE);
+ /* Read ISR */
+ outb(OCW3 | OCW3_READ_ISR, OCW3_ADDRESS + SLAVE);
+
+ /* Set interrupt mask to disable all interrupts */
+ outb(0xfb, OCW1_ADDRESS);
+ outb(0xff, OCW1_ADDRESS + SLAVE);
+
+ /* Setup the GPIO pin if the interrupt is hooked to it */
+ if ((irq_line >= 24) && (irq_line <= 39)) {
+ pr_notice("8259: Setting GPIO %d for the interrupt\n",
+ irq_line - 24);
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq_line - 24), 0x114);
+ if (request_irq(irq_line, octeon_i8259_interrupt, IRQF_SHARED,
+ "8259", octeon_i8259_interrupt)) {
+ panic("8259: Could not request_irq(%d)\n", irq_line);
+ }
+ } else if ((irq_line >= 44) && (irq_line <= 47)) {
+ pr_notice("8259: Using PCI INT-%c\n", irq_line - 44 + 'A');
+ if (request_irq(irq_line, octeon_i8259_interrupt, IRQF_SHARED,
+ "8259", octeon_i8259_interrupt)) {
+ panic("8259: Could not request_irq(%d)\n", irq_line);
+ }
+ } else {
+ panic("8259: Don't know how to setup the interrupt IRQ %d\n",
+ irq_line);
+ }
+}
diff --git a/arch/mips/cavium-octeon/irq.c b/arch/mips/cavium-octeon/irq.c
new file mode 100644
index 0000000..0e1f5e1
--- /dev/null
+++ b/arch/mips/cavium-octeon/irq.c
@@ -0,0 +1,61 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#include "linux/irq.h"
+#include "linux/hardirq.h"
+#include "linux/kernel_stat.h"
+#include "hal.h"
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ const unsigned long core_id = cvmx_get_core_num();
+ const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
+ const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
+ const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
+ const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
+ unsigned long cop0_cause;
+ unsigned long cop0_status;
+ uint64_t ciu_en;
+ uint64_t ciu_sum;
+
+ while (1) {
+ cop0_cause = read_c0_cause();
+ cop0_status = read_c0_status();
+ cop0_cause &= cop0_status;
+ cop0_cause &= ST0_IM;
+
+ if (unlikely(cop0_cause & STATUSF_IP2)) {
+ asm volatile ("ld %[sum], 0(%[sum_address])\n"
+ "ld %[en], 0(%[en_address])\n" :
+ [sum] "=r"(ciu_sum),
+ [en] "=r"(ciu_en) :
+ [sum_address] "r"(ciu_sum0_address),
+ [en_address] "r"(ciu_en0_address));
+ ciu_sum &= ciu_en;
+ if (likely(ciu_sum))
+ do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
+ else
+ spurious_interrupt();
+ } else if (unlikely(cop0_cause & STATUSF_IP3)) {
+ asm volatile ("ld %[sum], 0(%[sum_address])\n"
+ "ld %[en], 0(%[en_address])\n" :
+ [sum] "=r"(ciu_sum),
+ [en] "=r"(ciu_en) :
+ [sum_address] "r"(ciu_sum1_address),
+ [en_address] "r"(ciu_en1_address));
+ ciu_sum &= ciu_en;
+ if (likely(ciu_sum))
+ do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
+ else
+ spurious_interrupt();
+ } else if (likely(cop0_cause)) {
+ do_IRQ(fls(cop0_cause) - 9);
+ } else {
+ break;
+ }
+ }
+}
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
new file mode 100644
index 0000000..88e0cdd
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -0,0 +1,521 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Unified implementation of memcpy, memmove and the __copy_user backend.
+ *
+ * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Broadcom, Inc.
+ * memcpy/copy_user author: Mark Vandevoorde
+ *
+ * Mnemonic names for arguments to memcpy/__copy_user
+ */
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+
+#define dst a0
+#define src a1
+#define len a2
+
+/*
+ * Spec
+ *
+ * memcpy copies len bytes from src to dst and sets v0 to dst.
+ * It assumes that
+ * - src and dst don't overlap
+ * - src is readable
+ * - dst is writable
+ * memcpy uses the standard calling convention
+ *
+ * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
+ * the number of uncopied bytes due to an exception caused by a read or write.
+ * __copy_user assumes that src and dst don't overlap, and that the call is
+ * implementing one of the following:
+ * copy_to_user
+ * - src is readable (no exceptions when reading src)
+ * copy_from_user
+ * - dst is writable (no exceptions when writing dst)
+ * __copy_user uses a non-standard calling convention; see
+ * arch/mips/include/asm/uaccess.h
+ *
+ * When an exception happens on a load, the handler must
+ # ensure that all of the destination buffer is overwritten to prevent
+ * leaking information to user mode programs.
+ */
+
+/*
+ * Implementation
+ */
+
+/*
+ * The exception handler for loads requires that:
+ * 1- AT contain the address of the byte just past the end of the source
+ * of the copy,
+ * 2- src_entry <= src < AT, and
+ * 3- (dst - src) == (dst_entry - src_entry),
+ * The _entry suffix denotes values when __copy_user was called.
+ *
+ * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
+ * (2) is met by incrementing src by the number of bytes copied
+ * (3) is met by not doing loads between a pair of increments of dst and src
+ *
+ * The exception handlers for stores adjust len (if necessary) and return.
+ * These handlers do not need to overwrite any data.
+ *
+ * For __rmemcpy and memmove an exception is always a kernel bug, therefore
+ * they're not protected.
+ */
+
+#define EXC(inst_reg,addr,handler) \
+9: inst_reg, addr; \
+ .section __ex_table,"a"; \
+ PTR 9b, handler; \
+ .previous
+
+/*
+ * Only on the 64-bit kernel we can made use of 64-bit registers.
+ */
+#ifdef CONFIG_64BIT
+#define USE_DOUBLE
+#endif
+
+#ifdef USE_DOUBLE
+
+#define LOAD ld
+#define LOADL ldl
+#define LOADR ldr
+#define STOREL sdl
+#define STORER sdr
+#define STORE sd
+#define ADD daddu
+#define SUB dsubu
+#define SRL dsrl
+#define SRA dsra
+#define SLL dsll
+#define SLLV dsllv
+#define SRLV dsrlv
+#define NBYTES 8
+#define LOG_NBYTES 3
+
+/*
+ * As we are sharing code base with the mips32 tree (which use the o32 ABI
+ * register definitions). We need to redefine the register definitions from
+ * the n64 ABI register naming to the o32 ABI register naming.
+ */
+#undef t0
+#undef t1
+#undef t2
+#undef t3
+#define t0 $8
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
+
+#else
+
+#define LOAD lw
+#define LOADL lwl
+#define LOADR lwr
+#define STOREL swl
+#define STORER swr
+#define STORE sw
+#define ADD addu
+#define SUB subu
+#define SRL srl
+#define SLL sll
+#define SRA sra
+#define SLLV sllv
+#define SRLV srlv
+#define NBYTES 4
+#define LOG_NBYTES 2
+
+#endif /* USE_DOUBLE */
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define LDFIRST LOADR
+#define LDREST LOADL
+#define STFIRST STORER
+#define STREST STOREL
+#define SHIFT_DISCARD SLLV
+#else
+#define LDFIRST LOADL
+#define LDREST LOADR
+#define STFIRST STOREL
+#define STREST STORER
+#define SHIFT_DISCARD SRLV
+#endif
+
+#define FIRST(unit) ((unit)*NBYTES)
+#define REST(unit) (FIRST(unit)+NBYTES-1)
+#define UNIT(unit) FIRST(unit)
+
+#define ADDRMASK (NBYTES-1)
+
+ .text
+ .set noreorder
+ .set noat
+
+/*
+ * A combined memcpy/__copy_user
+ * __copy_user sets len to 0 for success; else to an upper bound of
+ * the number of uncopied bytes.
+ * memcpy sets v0 to dst.
+ */
+ .align 5
+LEAF(memcpy) /* a0=dst a1=src a2=len */
+ move v0, dst /* return value */
+__memcpy:
+FEXPORT(__copy_user)
+ /*
+ * Note: dst & src may be unaligned, len may be 0
+ * Temps
+ */
+ #
+ # Octeon doesn't care if the destination is unaligned. The hardware
+ # can fix it faster than we can special case the assembly.
+ #
+ pref 0, 0(src)
+ sltu t0, len, NBYTES # Check if < 1 word
+ bnez t0, copy_bytes_checklen
+ and t0, src, ADDRMASK # Check if src unaligned
+ bnez t0, src_unaligned
+ sltu t0, len, 4*NBYTES # Check if < 4 words
+ bnez t0, less_than_4units
+ sltu t0, len, 8*NBYTES # Check if < 8 words
+ bnez t0, less_than_8units
+ sltu t0, len, 16*NBYTES # Check if < 16 words
+ bnez t0, cleanup_both_aligned
+ sltu t0, len, 128+1 # Check if len < 129
+ bnez t0, 1f # Skip prefetch if len is too short
+ sltu t0, len, 256+1 # Check if len < 257
+ bnez t0, 1f # Skip prefetch if len is too short
+ pref 0, 128(src) # We must not prefetch invalid addresses
+ #
+ # This is where we loop if there is more than 128 bytes left
+2: pref 0, 256(src) # We must not prefetch invalid addresses
+ #
+ # This is where we loop if we can't prefetch anymore
+1:
+EXC( LOAD t0, UNIT(0)(src), l_exc)
+EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
+ SUB len, len, 16*NBYTES
+EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
+EXC( STORE t1, UNIT(1)(dst), s_exc_p15u)
+EXC( STORE t2, UNIT(2)(dst), s_exc_p14u)
+EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
+EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
+EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
+EXC( STORE t0, UNIT(4)(dst), s_exc_p12u)
+EXC( STORE t1, UNIT(5)(dst), s_exc_p11u)
+EXC( STORE t2, UNIT(6)(dst), s_exc_p10u)
+ ADD src, src, 16*NBYTES
+EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
+ ADD dst, dst, 16*NBYTES
+EXC( LOAD t0, UNIT(-8)(src), l_exc_copy)
+EXC( LOAD t1, UNIT(-7)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(-6)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
+EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
+EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u)
+EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
+EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
+EXC( LOAD t0, UNIT(-4)(src), l_exc_copy)
+EXC( LOAD t1, UNIT(-3)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(-2)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
+EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
+EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u)
+EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u)
+EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u)
+ sltu t0, len, 256+1 # See if we can prefetch more
+ beqz t0, 2b
+ sltu t0, len, 128 # See if we can loop more time
+ beqz t0, 1b
+ nop
+ #
+ # Jump here if there are less than 16*NBYTES left.
+ #
+cleanup_both_aligned:
+ beqz len, done
+ sltu t0, len, 8*NBYTES
+ bnez t0, less_than_8units
+ nop
+EXC( LOAD t0, UNIT(0)(src), l_exc)
+EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
+ SUB len, len, 8*NBYTES
+EXC( STORE t0, UNIT(0)(dst), s_exc_p8u)
+EXC( STORE t1, UNIT(1)(dst), s_exc_p7u)
+EXC( STORE t2, UNIT(2)(dst), s_exc_p6u)
+EXC( STORE t3, UNIT(3)(dst), s_exc_p5u)
+EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
+EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
+EXC( STORE t0, UNIT(4)(dst), s_exc_p4u)
+EXC( STORE t1, UNIT(5)(dst), s_exc_p3u)
+EXC( STORE t2, UNIT(6)(dst), s_exc_p2u)
+EXC( STORE t3, UNIT(7)(dst), s_exc_p1u)
+ ADD src, src, 8*NBYTES
+ beqz len, done
+ ADD dst, dst, 8*NBYTES
+ #
+ # Jump here if there are less than 8*NBYTES left.
+ #
+less_than_8units:
+ sltu t0, len, 4*NBYTES
+ bnez t0, less_than_4units
+ nop
+EXC( LOAD t0, UNIT(0)(src), l_exc)
+EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
+EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
+EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
+ SUB len, len, 4*NBYTES
+EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
+EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
+EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
+EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
+ ADD src, src, 4*NBYTES
+ beqz len, done
+ ADD dst, dst, 4*NBYTES
+ #
+ # Jump here if there are less than 4*NBYTES left. This means
+ # we may need to copy up to 3 NBYTES words.
+ #
+less_than_4units:
+ sltu t0, len, 1*NBYTES
+ bnez t0, copy_bytes_checklen
+ nop
+ #
+ # 1) Copy NBYTES, then check length again
+ #
+EXC( LOAD t0, 0(src), l_exc)
+ SUB len, len, NBYTES
+ sltu t1, len, 8
+EXC( STORE t0, 0(dst), s_exc_p1u)
+ ADD src, src, NBYTES
+ bnez t1, copy_bytes_checklen
+ ADD dst, dst, NBYTES
+ #
+ # 2) Copy NBYTES, then check length again
+ #
+EXC( LOAD t0, 0(src), l_exc)
+ SUB len, len, NBYTES
+ sltu t1, len, 8
+EXC( STORE t0, 0(dst), s_exc_p1u)
+ ADD src, src, NBYTES
+ bnez t1, copy_bytes_checklen
+ ADD dst, dst, NBYTES
+ #
+ # 3) Copy NBYTES, then check length again
+ #
+EXC( LOAD t0, 0(src), l_exc)
+ SUB len, len, NBYTES
+ ADD src, src, NBYTES
+ ADD dst, dst, NBYTES
+ b copy_bytes_checklen
+EXC( STORE t0, -8(dst), s_exc_p1u)
+
+src_unaligned:
+#define rem t8
+ SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
+ beqz t0, cleanup_src_unaligned
+ and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
+1:
+/*
+ * Avoid consecutive LD*'s to the same register since some mips
+ * implementations can't issue them in the same cycle.
+ * It's OK to load FIRST(N+1) before REST(N) because the two addresses
+ * are to the same unit (unless src is aligned, but it's not).
+ */
+EXC( LDFIRST t0, FIRST(0)(src), l_exc)
+EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
+ SUB len, len, 4*NBYTES
+EXC( LDREST t0, REST(0)(src), l_exc_copy)
+EXC( LDREST t1, REST(1)(src), l_exc_copy)
+EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
+EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
+EXC( LDREST t2, REST(2)(src), l_exc_copy)
+EXC( LDREST t3, REST(3)(src), l_exc_copy)
+ ADD src, src, 4*NBYTES
+EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
+EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
+EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
+EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
+ bne len, rem, 1b
+ ADD dst, dst, 4*NBYTES
+
+cleanup_src_unaligned:
+ beqz len, done
+ and rem, len, NBYTES-1 # rem = len % NBYTES
+ beq rem, len, copy_bytes
+ nop
+1:
+EXC( LDFIRST t0, FIRST(0)(src), l_exc)
+EXC( LDREST t0, REST(0)(src), l_exc_copy)
+ SUB len, len, NBYTES
+EXC( STORE t0, 0(dst), s_exc_p1u)
+ ADD src, src, NBYTES
+ bne len, rem, 1b
+ ADD dst, dst, NBYTES
+
+copy_bytes_checklen:
+ beqz len, done
+ nop
+copy_bytes:
+ /* 0 < len < NBYTES */
+#define COPY_BYTE(N) \
+EXC( lb t0, N(src), l_exc); \
+ SUB len, len, 1; \
+ beqz len, done; \
+EXC( sb t0, N(dst), s_exc_p1)
+
+ COPY_BYTE(0)
+ COPY_BYTE(1)
+#ifdef USE_DOUBLE
+ COPY_BYTE(2)
+ COPY_BYTE(3)
+ COPY_BYTE(4)
+ COPY_BYTE(5)
+#endif
+EXC( lb t0, NBYTES-2(src), l_exc)
+ SUB len, len, 1
+ jr ra
+EXC( sb t0, NBYTES-2(dst), s_exc_p1)
+done:
+ jr ra
+ nop
+ END(memcpy)
+
+l_exc_copy:
+ /*
+ * Copy bytes from src until faulting load address (or until a
+ * lb faults)
+ *
+ * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
+ * may be more than a byte beyond the last address.
+ * Hence, the lb below may get an exception.
+ *
+ * Assumes src < THREAD_BUADDR($28)
+ */
+ LOAD t0, TI_TASK($28)
+ nop
+ LOAD t0, THREAD_BUADDR(t0)
+1:
+EXC( lb t1, 0(src), l_exc)
+ ADD src, src, 1
+ sb t1, 0(dst) # can't fault -- we're copy_from_user
+ bne src, t0, 1b
+ ADD dst, dst, 1
+l_exc:
+ LOAD t0, TI_TASK($28)
+ nop
+ LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
+ nop
+ SUB len, AT, t0 # len number of uncopied bytes
+ /*
+ * Here's where we rely on src and dst being incremented in tandem,
+ * See (3) above.
+ * dst += (fault addr - src) to put dst at first byte to clear
+ */
+ ADD dst, t0 # compute start address in a1
+ SUB dst, src
+ /*
+ * Clear len bytes starting at dst. Can't call __bzero because it
+ * might modify len. An inefficient loop for these rare times...
+ */
+ beqz len, done
+ SUB src, len, 1
+1: sb zero, 0(dst)
+ ADD dst, dst, 1
+ bnez src, 1b
+ SUB src, src, 1
+ jr ra
+ nop
+
+
+#define SEXC(n) \
+s_exc_p ## n ## u: \
+ jr ra; \
+ ADD len, len, n*NBYTES
+
+SEXC(16)
+SEXC(15)
+SEXC(14)
+SEXC(13)
+SEXC(12)
+SEXC(11)
+SEXC(10)
+SEXC(9)
+SEXC(8)
+SEXC(7)
+SEXC(6)
+SEXC(5)
+SEXC(4)
+SEXC(3)
+SEXC(2)
+SEXC(1)
+
+s_exc_p1:
+ jr ra
+ ADD len, len, 1
+s_exc:
+ jr ra
+ nop
+
+ .align 5
+LEAF(memmove)
+ ADD t0, a0, a2
+ ADD t1, a1, a2
+ sltu t0, a1, t0 # dst + len <= src -> memcpy
+ sltu t1, a0, t1 # dst >= src + len -> memcpy
+ and t0, t1
+ beqz t0, __memcpy
+ move v0, a0 /* return value */
+ beqz a2, r_out
+ END(memmove)
+
+ /* fall through to __rmemcpy */
+LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
+ sltu t0, a1, a0
+ beqz t0, r_end_bytes_up # src >= dst
+ nop
+ ADD a0, a2 # dst = dst + len
+ ADD a1, a2 # src = src + len
+
+r_end_bytes:
+ lb t0, -1(a1)
+ SUB a2, a2, 0x1
+ sb t0, -1(a0)
+ SUB a1, a1, 0x1
+ bnez a2, r_end_bytes
+ SUB a0, a0, 0x1
+
+r_out:
+ jr ra
+ move a2, zero
+
+r_end_bytes_up:
+ lb t0, (a1)
+ SUB a2, a2, 0x1
+ sb t0, (a0)
+ ADD a1, a1, 0x1
+ bnez a2, r_end_bytes_up
+ ADD a0, a0, 0x1
+
+ jr ra
+ move a2, zero
+ END(__rmemcpy)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
new file mode 100644
index 0000000..077b66c
--- /dev/null
+++ b/arch/mips/cavium-octeon/serial.c
@@ -0,0 +1,187 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#include <linux/console.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+#include <linux/tty.h>
+
+#include <asm/time.h>
+
+#include "hal.h"
+
+#ifdef CONFIG_GDB_CONSOLE
+#define DEBUG_UART 0
+#else
+#define DEBUG_UART 1
+#endif
+
+#ifdef CONFIG_KGDB
+
+char getDebugChar(void)
+{
+ unsigned long lsrval;
+
+ octeon_write_lcd("kgdb");
+
+ /* Spin until data is available */
+ do {
+ lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(DEBUG_UART));
+ } while ((lsrval & 0x1) == 0);
+
+ octeon_write_lcd("");
+
+ /* Read and return the data */
+ return cvmx_read_csr(CVMX_MIO_UARTX_RBR(DEBUG_UART));
+}
+
+void putDebugChar(char ch)
+{
+ unsigned long lsrval;
+
+ /* Spin until there is room */
+ do {
+ lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(DEBUG_UART));
+ } while ((lsrval & 0x20) == 0);
+
+ /* Write the byte */
+ cvmx_write_csr(CVMX_MIO_UARTX_THR(DEBUG_UART), ch);
+}
+
+#endif
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_CAVIUM_GDB)
+
+static irqreturn_t interruptDebugChar(int cpl, void *dev_id)
+{
+ unsigned long lsrval;
+ lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(1));
+ if (lsrval & 1) {
+#ifdef CONFIG_KGDB
+ struct pt_regs *regs = get_irq_regs();
+
+ putDebugChar(getDebugChar());
+ set_async_breakpoint(®s->cp0_epc);
+#else
+ unsigned long tmp;
+ /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set
+ the MCD0 to be not masked by this core so we know the signal
+ is received by someone */
+ octeon_write_lcd("brk");
+ asm volatile ("dmfc0 %0, $22\n"
+ "ori %0, %0, 0x10\n"
+ "dmtc0 %0, $22\n" : "=r" (tmp));
+ octeon_write_lcd("");
+#endif
+ return IRQ_HANDLED;
+ }
+ return IRQ_NONE;
+}
+
+#endif
+
+unsigned int octeon_serial_in(struct uart_port *up, int offset)
+{
+ return cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
+}
+
+void octeon_serial_out(struct uart_port *up, int offset, int value)
+{
+ /*
+ * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
+ * working.
+ */
+ if (offset == UART_LCR)
+ value &= 0x9f;
+ cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
+}
+
+static int octeon_serial_init(void)
+{
+ struct uart_port octeon_port;
+ int enable_uart0;
+ int enable_uart1;
+ int enable_uart2;
+
+#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+ /* If we are configured to run as the second of two kernels, disable
+ uart0 and enable uart1. Uart0 is owned by the first kernel */
+ enable_uart0 = 0;
+ enable_uart1 = 1;
+#else
+ /* We are configured for the first kernel. We'll enable uart0 if the
+ bootloader told us to use 0, otherwise will enable uart 1 */
+ enable_uart0 = (octeon_get_boot_uart() == 0);
+ enable_uart1 = (octeon_get_boot_uart() == 1);
+ /* Uncomment the following line if you'd like uart1 to be enable as
+ well as uart 0 when the bootloader tells us to use uart0 */
+ /*
+ enable_uart1 = 1;
+ */
+#endif
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_CAVIUM_GDB)
+ /* As a special case disable uart1 if KGDB is in use */
+ enable_uart1 = 0;
+#endif
+
+ /* Right now CN52XX is the only chip with a third uart */
+ enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+ /* These fields are common to all Octeon UARTs */
+ memset(&octeon_port, 0, sizeof(octeon_port));
+ octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ octeon_port.type = PORT_OCTEON;
+ octeon_port.iotype = UPIO_MEM;
+ octeon_port.regshift = 3; /* I/O addresses are every 8 bytes */
+ octeon_port.uartclk = mips_hpt_frequency;
+ octeon_port.fifosize = 64;
+ octeon_port.serial_in_fn = octeon_serial_in;
+ octeon_port.serial_out_fn = octeon_serial_out;
+
+ /* Add a ttyS device for hardware uart 0 */
+ if (enable_uart0) {
+ octeon_port.membase = (void *) CVMX_MIO_UARTX_RBR(0);
+ octeon_port.mapbase =
+ CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
+ /* Only CN38XXp{1,2} has errata with uart interrupt */
+ if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ octeon_port.irq = OCTEON_IRQ_UART0;
+ serial8250_register_port(&octeon_port);
+ }
+
+ /* Add a ttyS device for hardware uart 1 */
+ if (enable_uart1) {
+ octeon_port.membase = (void *) CVMX_MIO_UARTX_RBR(1);
+ octeon_port.mapbase =
+ CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
+ /* Only CN38XXp{1,2} has errata with uart interrupt */
+ if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ octeon_port.irq = OCTEON_IRQ_UART1;
+ serial8250_register_port(&octeon_port);
+ }
+
+ /* Add a ttyS device for hardware uart 2 */
+ if (enable_uart2) {
+ octeon_port.membase = (void *) CVMX_MIO_UART2_RBR;
+ octeon_port.mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
+ octeon_port.irq = OCTEON_IRQ_UART2;
+ serial8250_register_port(&octeon_port);
+ }
+#if defined(CONFIG_KGDB) || defined(CONFIG_CAVIUM_GDB)
+ request_irq(OCTEON_IRQ_UART0 + DEBUG_UART, interruptDebugChar,
+ IRQF_SHARED, "KGDB", interruptDebugChar);
+
+ /* Enable uart1 interrupts for debugger Control-C processing */
+ cvmx_write_csr(CVMX_MIO_UARTX_IER(DEBUG_UART),
+ cvmx_read_csr(CVMX_MIO_UARTX_IER(DEBUG_UART)) | 1);
+#endif
+ return 0;
+}
+
+late_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
new file mode 100644
index 0000000..342f672
--- /dev/null
+++ b/arch/mips/cavium-octeon/setup.c
@@ -0,0 +1,387 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ * Copyright (C) 2008 Wind River Systems
+ */
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/serial.h>
+#include <linux/types.h>
+#include <linux/string.h> /* for memset */
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/time.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/string.h>
+
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/smp-ops.h>
+#include <asm/system.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/bootinfo.h>
+#include <asm/sections.h>
+#include <asm/time.h>
+#include "hal.h"
+#include "cvmx-l2c.h"
+#include "cvmx-bootmem.h"
+
+#ifdef CONFIG_CAVIUM_DECODE_RSL
+extern void cvmx_interrupt_rsl_decode(void);
+extern int __cvmx_interrupt_ecc_report_single_bit_errors;
+extern void cvmx_interrupt_rsl_enable(void);
+#endif
+
+extern struct plat_smp_ops octeon_smp_ops;
+extern void octeon_user_io_init(void);
+#ifdef CONFIG_PCI
+extern void pci_console_init(const char *arg);
+#endif
+extern void putDebugChar(char ch);
+
+#ifdef CONFIG_CAVIUM_OCTEON_BOOTBUS_COMPACT_FLASH
+extern void ebt3000_cf_enable_dma(void);
+#endif
+
+#ifdef CONFIG_CAVIUM_RESERVE32
+extern uint64_t octeon_reserve32_memory;
+#endif
+static unsigned long long MAX_MEMORY = 512ull << 20;
+
+/**
+ * Reboot Octeon
+ *
+ * @param command Command to pass to the bootloader. Currently ignored.
+ */
+static void octeon_restart(char *command)
+{
+ /* Disable all watchdogs before soft reset. They don't get cleared */
+#ifdef CONFIG_SMP
+ int cpu;
+ for (cpu = 0; cpu < NR_CPUS; cpu++)
+ if (cpu_online(cpu))
+ cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
+#else
+ cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
+#endif
+
+ mb();
+ while (1)
+ cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
+}
+
+
+/**
+ * Permanently stop a core.
+ *
+ * @param arg
+ */
+static void octeon_kill_core(void *arg)
+{
+ mb();
+ if (octeon_is_simulation()) {
+ /* The simulator needs the watchdog to stop for dead cores */
+ cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
+ /* A break instruction causes the simulator stop a core */
+ asm volatile ("sync\nbreak");
+ }
+}
+
+
+/**
+ * Halt the system
+ */
+static void octeon_halt(void)
+{
+ smp_call_function(octeon_kill_core, NULL, 0);
+ octeon_poweroff();
+ octeon_kill_core(NULL);
+}
+
+
+/**
+ * Platform time init specifics.
+ * @return
+ */
+void __init plat_time_init(void)
+{
+ /* Nothing special here, but we are required to have one */
+}
+
+
+/**
+ * Handle all the error condition interrupts that might occur.
+ *
+ * @param cpl
+ * @param dev_id
+ * @return
+ */
+#ifdef CONFIG_CAVIUM_DECODE_RSL
+static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
+{
+ cvmx_interrupt_rsl_decode();
+ return IRQ_HANDLED;
+}
+#endif
+
+/**
+ * Return a string representing the system type
+ *
+ * @return
+ */
+const char *get_system_type(void)
+{
+ return octeon_board_type_string();
+}
+
+
+/**
+ * Early entry point for arch setup
+ */
+void __init prom_init(void)
+{
+ const int coreid = cvmx_get_core_num();
+ int i;
+ int argc;
+ struct uart_port octeon_port;
+ int octeon_uart;
+
+ octeon_hal_init();
+ octeon_check_cpu_bist();
+#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+ octeon_uart = 1;
+#else
+ octeon_uart = octeon_get_boot_uart();
+#endif
+
+ /* Disable All CIU Interrupts. The ones we need will be
+ * enabled later. Read the SUM register so we know the write
+ * completed. */
+ cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
+ cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
+
+#ifdef CONFIG_SMP
+ octeon_write_lcd("LinuxSMP");
+#else
+ octeon_write_lcd("Linux");
+#endif
+
+#ifdef CONFIG_CAVIUM_GDB
+ /* When debugging the linux kernel, force the cores to enter
+ * the debug exception handler to break in. */
+ if (octeon_get_boot_debug_flag()) {
+ cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
+ cvmx_read_csr(CVMX_CIU_DINT);
+ }
+#endif
+
+ /* BIST should always be enabled when doing a soft reset. L2
+ * Cache locking for instance is not cleared unless BIST is
+ * enabled. Unfortunately due to a chip errata G-200 for
+ * Cn38XX and CN31XX, BIST msut be disabled on these parts */
+ if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
+ OCTEON_IS_MODEL(OCTEON_CN31XX))
+ cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
+ else
+ cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
+
+ /* Default to 64MB in the simulator to speed things up */
+ if (octeon_is_simulation())
+ MAX_MEMORY = 64ull << 20;
+
+ arcs_cmdline[0] = 0;
+ argc = octeon_get_boot_num_arguments();
+ for (i = 0; i < argc; i++) {
+ const char *arg = octeon_get_boot_argument(i);
+ if ((strncmp(arg, "MEM=", 4) == 0) ||
+ (strncmp(arg, "mem=", 4) == 0)) {
+ sscanf(arg + 4, "%llu", &MAX_MEMORY);
+ MAX_MEMORY <<= 20;
+ if (MAX_MEMORY == 0)
+ MAX_MEMORY = 32ull << 30;
+ } else if (strcmp(arg, "ecc_verbose") == 0) {
+#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
+ __cvmx_interrupt_ecc_report_single_bit_errors = 1;
+ pr_notice("Reporting of single bit ECC errors is "
+ "turned on\n");
+#endif
+ } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
+ sizeof(arcs_cmdline) - 1) {
+ strcat(arcs_cmdline, " ");
+ strcat(arcs_cmdline, arg);
+ }
+ }
+#ifdef CONFIG_CAVIUM_OCTEON_BOOTBUS_COMPACT_FLASH
+ if (strstr(arcs_cmdline, "use_cf_dma"))
+ ebt3000_cf_enable_dma();
+#endif
+
+#ifdef CONFIG_PCI
+ if (strstr(arcs_cmdline, "console=pci"))
+ pci_console_init(strstr(arcs_cmdline, "console=pci") + 8);
+#endif
+
+ if (strstr(arcs_cmdline, "console=") == NULL) {
+#ifdef CONFIG_GDB_CONSOLE
+ strcat(arcs_cmdline, " console=gdb");
+#else
+#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+ strcat(arcs_cmdline, " console=ttyS0,115200");
+#else
+ if (octeon_uart == 1)
+ strcat(arcs_cmdline, " console=ttyS1,115200");
+ else
+ strcat(arcs_cmdline, " console=ttyS0,115200");
+#endif
+#endif
+ }
+
+ if (octeon_is_simulation()) {
+ /* The simulator uses a mtdram device pre filled with the
+ filesystem. Also specify the calibration delay to avoid
+ calculating it every time */
+ strcat(arcs_cmdline, " rw root=1f00"
+ " lpj=60176 slram=root,0x40000000,+1073741824");
+ }
+
+ mips_hpt_frequency = octeon_get_clock_rate();
+
+ _machine_restart = octeon_restart;
+ _machine_halt = octeon_halt;
+
+ memset(&octeon_port, 0, sizeof(octeon_port));
+ /* For early_serial_setup we don't set the port type or
+ * UPF_FIXED_TYPE. */
+ octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ;
+ octeon_port.iotype = UPIO_MEM;
+ /* I/O addresses are every 8 bytes */
+ octeon_port.regshift = 3;
+ /* Clock rate of the chip */
+ octeon_port.uartclk = mips_hpt_frequency;
+ octeon_port.fifosize = 64;
+ octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart);
+ octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase);
+ octeon_port.serial_in_fn = octeon_serial_in;
+ octeon_port.serial_out_fn = octeon_serial_out;
+#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+ octeon_port.line = 0;
+#else
+ octeon_port.line = octeon_uart;
+#endif
+ /* Only CN38XXp{1,2} has errata with uart interrupt */
+ if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ octeon_port.irq = 42 + octeon_uart;
+ early_serial_setup(&octeon_port);
+
+ octeon_user_io_init();
+ register_smp_ops(&octeon_smp_ops);
+
+#ifdef CONFIG_KGDB
+ {
+ const char *s = "\r\nConnect GDB to this port\r\n";
+ while (*s)
+ putDebugChar(*s++);
+ }
+#endif
+}
+
+
+
+void __init plat_mem_setup(void)
+{
+ uint64_t mem_alloc_size;
+ uint64_t total;
+ int64_t memory;
+
+ total = 0;
+
+ /* First add the init memory we will be returning. */
+ memory = __pa_symbol(&__init_begin) & PAGE_MASK;
+ mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
+ if (mem_alloc_size > 0) {
+ add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+ total += mem_alloc_size;
+ }
+
+ /* The Mips memory init uses the first memory location for some memory
+ vectors. When SPARSEMEM is in use, it doesn't verify that the size
+ is big enough for the final vectors. Making the smallest chuck 4MB
+ seems to be enough to consistantly work. This needs to be debugged
+ more */
+ mem_alloc_size = 4 << 20;
+ if (mem_alloc_size > MAX_MEMORY)
+ mem_alloc_size = MAX_MEMORY;
+
+ /* When allocating memory, we want incrementing addresses from
+ bootmem_alloc so the code in add_memory_region can merge regions
+ next to each other */
+ cvmx_bootmem_lock();
+ while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
+ && (total < MAX_MEMORY)) {
+#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
+ memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
+ __pa_symbol(&__init_end), -1,
+ 0x100000,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#elif defined(CONFIG_HIGHMEM)
+ memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
+ 0x100000,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#else
+ memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
+ 0x100000,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+#endif
+ if (memory >= 0) {
+ /* This function automatically merges address regions
+ next to each other if they are received in
+ incrementing order */
+ add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+ total += mem_alloc_size;
+ } else
+ break;
+ }
+ cvmx_bootmem_unlock();
+
+#ifdef CONFIG_CAVIUM_RESERVE32
+ /* Now that we've allocated the kernel memory it is safe to free the
+ reserved region. We free it here so that builtin drivers can
+ use the memory */
+ if (octeon_reserve32_memory)
+ cvmx_bootmem_free_named("CAVIUM_RESERVE32");
+#endif /* CONFIG_CAVIUM_RESERVE32 */
+
+ if (total == 0)
+ panic("Unable to allocate memory from cvmx_bootmem_phy_alloc\n");
+}
+
+
+void prom_free_prom_memory(void)
+{
+#ifdef CONFIG_CAVIUM_DECODE_RSL
+ cvmx_interrupt_rsl_enable();
+
+ /* Add an interrupt handler for general failures. */
+ if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
+ "RML/RSL", octeon_rlm_interrupt)) {
+ panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
+ }
+#endif
+
+ /* This call is here so that it is performed after any TLB
+ initializations. It needs to be after these in case the
+ CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
+ octeon_hal_setup_reserved32();
+}
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
new file mode 100644
index 0000000..37820f2
--- /dev/null
+++ b/arch/mips/cavium-octeon/smp.c
@@ -0,0 +1,231 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+
+#include <asm/mmu_context.h>
+#include <asm/system.h>
+#include <asm/time.h>
+
+#include "hal.h"
+
+extern void octeon_user_io_init(void);
+
+volatile unsigned long octeon_processor_boot = 0xff;
+volatile unsigned long octeon_processor_cycle;
+volatile unsigned long octeon_processor_sp;
+volatile unsigned long octeon_processor_gp;
+
+
+static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
+{
+ const int coreid = cvmx_get_core_num();
+ uint64_t action;
+
+ /* Load the mailbox register to figure out what we're supposed to do */
+ action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
+
+ /* Clear the mailbox to clear the interrupt */
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
+
+ if (action & SMP_CALL_FUNCTION)
+ smp_call_function_interrupt();
+
+ /* Check if we've been told to flush the icache */
+ if (action & SMP_ICACHE_FLUSH)
+ asm volatile ("synci 0($0)\n");
+ return IRQ_HANDLED;
+}
+
+
+/**
+ * Cause the function described by call_data to be executed on the passed
+ * cpu. When the function has finished, increment the finished field of
+ * call_data.
+ *
+ * @param cpu
+ * @param action
+ */
+static void octeon_send_ipi_single(int cpu, unsigned int action)
+{
+ int coreid = cpu_logical_map(cpu);
+ /*
+ pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
+ coreid, action);
+ */
+ cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
+}
+
+static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
+{
+ unsigned int i;
+
+ for_each_cpu_mask(i, mask)
+ octeon_send_ipi_single(i, action);
+}
+
+/**
+ * Detect available CPUs, populate phys_cpu_present_map
+ */
+static void octeon_smp_setup(void)
+{
+ const int coreid = cvmx_get_core_num();
+ int cpus;
+ int id;
+
+ int core_mask = octeon_get_boot_coremask();
+
+ cpus_clear(phys_cpu_present_map);
+ __cpu_number_map[coreid] = 0;
+ __cpu_logical_map[0] = coreid;
+ cpu_set(0, phys_cpu_present_map);
+
+ cpus = 1;
+ for (id = 0; id < 16; id++) {
+ if ((id != coreid) && (core_mask & (1 << id))) {
+ cpu_set(cpus, phys_cpu_present_map);
+ __cpu_number_map[id] = cpus;
+ __cpu_logical_map[cpus] = id;
+ cpus++;
+ }
+ }
+}
+
+
+/**
+ * Firmware CPU startup hook
+ *
+ * @param cpu
+ * @param idle
+ */
+static void octeon_boot_secondary(int cpu, struct task_struct *idle)
+{
+ int count;
+
+ pr_info("SMP: Booting CPU%02d (CoreId %2d)...", cpu,
+ cpu_logical_map(cpu));
+
+ octeon_processor_sp = __KSTK_TOS(idle);
+ octeon_processor_gp = (unsigned long)(task_thread_info(idle));
+ /* Use sync so all ops are done. This makes the cycle counter
+ * propagate in a more bounded amount of time */
+ __sync();
+ octeon_processor_cycle = octeon_get_cycles();
+ octeon_processor_boot = cpu_logical_map(cpu);
+ mb();
+
+ count = 10000;
+ while (octeon_processor_sp && count) {
+ /* Waiting for processor to get the SP and GP */
+ udelay(1);
+ count--;
+ }
+ if (count == 0)
+ pr_err("Secondary boot timeout\n");
+}
+
+
+/**
+ * After we've done initial boot, this function is called to allow the
+ * board code to clean up state, if needed
+ */
+static void octeon_init_secondary(void)
+{
+ const int coreid = cvmx_get_core_num();
+ cvmx_ciu_intx0_t interrupt_enable;
+
+ octeon_check_cpu_bist();
+
+ /*
+ pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
+ */
+ /* Enable Mailbox interrupts to this core. These are the only
+ interrupts allowed on line 3 */
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
+ interrupt_enable.u64 = 0;
+ interrupt_enable.s.mbox = 0x3;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
+ /* Enable core interrupt processing for 2,3 and 7 */
+ set_c0_status(0x8c01);
+}
+
+
+/**
+ * Callout to firmware before smp_init
+ *
+ * @param max_cpus
+ */
+void octeon_prepare_cpus(unsigned int max_cpus)
+{
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
+ if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED,
+ "mailbox0", mailbox_interrupt)) {
+ panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
+ }
+ if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED,
+ "mailbox1", mailbox_interrupt)) {
+ panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
+ }
+}
+
+
+/**
+ * Last chance for the board code to finish SMP initialization before
+ * the CPU is "online".
+ */
+static void octeon_smp_finish(void)
+{
+#ifdef CONFIG_CAVIUM_GDB
+ unsigned long tmp;
+ /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
+ to be not masked by this core so we know the signal is received by
+ someone */
+ asm volatile ("dmfc0 %0, $22\n"
+ "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
+#endif
+
+ octeon_user_io_init();
+
+ /* to generate the first CPU timer interrupt */
+ write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+}
+
+
+/**
+ * Hook for after all CPUs are online
+ */
+static void octeon_cpus_done(void)
+{
+#ifdef CONFIG_CAVIUM_GDB
+ unsigned long tmp;
+ /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
+ to be not masked by this core so we know the signal is received by
+ someone */
+ asm volatile ("dmfc0 %0, $22\n"
+ "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
+#endif
+}
+
+struct plat_smp_ops octeon_smp_ops = {
+ .send_ipi_single = octeon_send_ipi_single,
+ .send_ipi_mask = octeon_send_ipi_mask,
+ .init_secondary = octeon_init_secondary,
+ .smp_finish = octeon_smp_finish,
+ .cpus_done = octeon_cpus_done,
+ .boot_secondary = octeon_boot_secondary,
+ .smp_setup = octeon_smp_setup,
+ .prepare_cpus = octeon_prepare_cpus,
+};
diff --git a/arch/mips/cavium-octeon/userio.c b/arch/mips/cavium-octeon/userio.c
new file mode 100644
index 0000000..9577464
--- /dev/null
+++ b/arch/mips/cavium-octeon/userio.c
@@ -0,0 +1,156 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/types.h>
+#include <linux/string.h> /* for memset */
+#include <linux/console.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/time.h>
+#include <linux/serial_core.h>
+#include <linux/reboot.h>
+#include <linux/io.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/bootinfo.h>
+
+#include "hal.h"
+
+
+/**
+ *
+ * @return
+ */
+void octeon_user_io_init(void)
+{
+ octeon_cvmemctl_t cvmmemctl;
+ cvmx_iob_fau_timeout_t fau_timeout;
+ cvmx_pow_nw_tim_t nm_tim;
+ uint64_t cvmctl;
+
+ /* Get the current settings for CP0_CVMMEMCTL_REG */
+ cvmmemctl.u64 = __read_64bit_c0_register($11, 7);
+ /* R/W If set, marked write-buffer entries time out the same
+ * as as other entries; if clear, marked write-buffer entries
+ * use the maximum timeout. */
+ cvmmemctl.s.dismarkwblongto = 1;
+ /* R/W If set, a merged store does not clear the write-buffer
+ * entry timeout state. */
+ cvmmemctl.s.dismrgclrwbto = 0;
+ /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
+ * word location for an IOBDMA. The other 8 bits come from the
+ * SCRADDR field of the IOBDMA. */
+ cvmmemctl.s.iobdmascrmsb = 0;
+ /* R/W If set, SYNCWS and SYNCS only order marked stores; if
+ * clear, SYNCWS and SYNCS only order unmarked
+ * stores. SYNCWSMARKED has no effect when DISSYNCWS is
+ * set. */
+ cvmmemctl.s.syncwsmarked = 0;
+ /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
+ cvmmemctl.s.dissyncws = 0;
+ /* R/W If set, no stall happens on write buffer full. */
+ if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ cvmmemctl.s.diswbfst = 1;
+ else
+ cvmmemctl.s.diswbfst = 0;
+ /* R/W If set (and SX set), supervisor-level loads/stores can
+ * use XKPHYS addresses with <48>==0 */
+ cvmmemctl.s.xkmemenas = 0;
+
+ /* R/W If set (and UX set), user-level loads/stores can use
+ * XKPHYS addresses with VA<48>==0 */
+ cvmmemctl.s.xkmemenau = 0;
+
+ /* R/W If set (and SX set), supervisor-level loads/stores can
+ * use XKPHYS addresses with VA<48>==1 */
+ cvmmemctl.s.xkioenas = 0;
+
+ /* R/W If set (and UX set), user-level loads/stores can use
+ * XKPHYS addresses with VA<48>==1 */
+ cvmmemctl.s.xkioenau = 0;
+
+ /* R/W If set, all stores act as SYNCW (NOMERGE must be set
+ * when this is set) RW, reset to 0. */
+ cvmmemctl.s.allsyncw = 0;
+
+ /* R/W If set, no stores merge, and all stores reach the
+ * coherent bus in order. */
+ cvmmemctl.s.nomerge = 0;
+ /* R/W Selects the bit in the counter used for DID time-outs 0
+ * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
+ * between 1� and 2� this interval. For example, with
+ * DIDTTO=3, expiration interval is between 16K and 32K. */
+ cvmmemctl.s.didtto = 0;
+ /* R/W If set, the (mem) CSR clock never turns off. */
+ cvmmemctl.s.csrckalwys = 0;
+ /* R/W If set, mclk never turns off. */
+ cvmmemctl.s.mclkalwys = 0;
+ /* R/W Selects the bit in the counter used for write buffer
+ * flush time-outs (WBFLT+11) is the bit position in an
+ * internal counter used to determine expiration. The write
+ * buffer expires between 1� and 2� this interval. For
+ * example, with WBFLT = 0, a write buffer expires between 2K
+ * and 4K cycles after the write buffer entry is allocated. */
+ cvmmemctl.s.wbfltime = 0;
+ /* R/W If set, do not put Istream in the L2 cache. */
+ cvmmemctl.s.istrnol2 = 0;
+ /* R/W The write buffer threshold. */
+ cvmmemctl.s.wbthresh = 10;
+ /* R/W If set, CVMSEG is available for loads/stores in
+ * kernel/debug mode. */
+#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
+ cvmmemctl.s.cvmsegenak = 1;
+#else
+ cvmmemctl.s.cvmsegenak = 0;
+#endif
+ /* R/W If set, CVMSEG is available for loads/stores in
+ * supervisor mode. */
+ cvmmemctl.s.cvmsegenas = 0;
+ /* R/W If set, CVMSEG is available for loads/stores in user
+ * mode. */
+ cvmmemctl.s.cvmsegenau = 0;
+ /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
+ * is max legal value. */
+ cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
+
+
+ if (smp_processor_id() == 0)
+ pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
+ CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
+ CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+
+ __write_64bit_c0_register($11, 7, cvmmemctl.u64);
+
+ /* Move the performance counter interrupts to IRQ 6 */
+ cvmctl = __read_64bit_c0_register($9, 7);
+ cvmctl &= ~(7 << 7);
+ cvmctl |= 6 << 7;
+ __write_64bit_c0_register($9, 7, cvmctl);
+
+ /* Set a default for the hardware timeouts */
+ fau_timeout.u64 = 0;
+ fau_timeout.s.tout_val = 0xfff;
+ /* Disable tagwait FAU timeout */
+ fau_timeout.s.tout_enb = 0;
+ cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
+
+ nm_tim.u64 = 0;
+ /* 4096 cycles */
+ nm_tim.s.nw_tim = 3;
+ cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
+
+ write_c0_cacheerr(0);
+ write_c0_derraddr1(0);
+}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 02/37] Add Cavium OCTEON files to arch/mips/include/asm/mach-cavium-octeon
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
2008-10-24 0:56 ` [PATCH 01/37] Add Cavium OCTEON processor support files to arch/mips/cavium-octeon ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 03/37] Add Cavium OCTEON processor support files to arch/mips/kernel ddaney
` (34 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 63 +++++
.../include/asm/mach-cavium-octeon/dma-coherence.h | 64 +++++
arch/mips/include/asm/mach-cavium-octeon/irq.h | 253 ++++++++++++++++++++
.../asm/mach-cavium-octeon/kernel-entry-init.h | 140 +++++++++++
.../asm/mach-cavium-octeon/octeon-hal-read-write.h | 38 +++
.../include/asm/mach-cavium-octeon/perf_counters.h | 24 ++
arch/mips/include/asm/mach-cavium-octeon/war.h | 26 ++
7 files changed, 608 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/octeon-hal-read-write.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/perf_counters.h
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 0000000..2b85565
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Cavium Networks
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/types.h>
+#include <asm/mipsregs.h>
+
+/*
+ * Cavium Octeons are MIPS64v2 processors
+ */
+#define cpu_dcache_line_size() 128
+#define cpu_icache_line_size() 128
+
+#ifdef CONFIG_SMP
+#define cpu_has_llsc 1
+#else
+/* Disable LL/SC on non SMP systems. It is faster to disable interrupts for
+ atomic access than a LL/SC */
+#define cpu_has_llsc 0
+#endif
+#define cpu_has_prefetch 1
+#define cpu_has_dc_aliases 0
+#define cpu_has_fpu 0
+#define cpu_has_64bits 1
+#define cpu_has_octeon_cache 1
+#define cpu_has_4k_cache 0
+#define cpu_has_saa octeon_has_saa()
+#define cpu_has_mips64r2 1
+#define cpu_has_counter 1
+#define ARCH_HAS_READ_CURRENT_TIMER 1
+#define ARCH_HAS_IRQ_PER_CPU 1
+#define ARCH_HAS_SPINLOCK_PREFETCH 1
+#define spin_lock_prefetch(x) prefetch(x)
+#define PREFETCH_STRIDE 128
+
+static inline int read_current_timer(unsigned long *result)
+{
+ asm volatile ("rdhwr %0,$31\n"
+#ifndef CONFIG_64BIT
+ "sll %0, 0\n"
+#endif
+ : "=r" (*result));
+ return 0;
+}
+
+static inline int octeon_has_saa(void)
+{
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ int id;
+ asm volatile ("mfc0 %0, $15,0" : "=r" (id));
+ return id >= 0x000d0300;
+#else
+ return 0;
+#endif
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
new file mode 100644
index 0000000..f30fce9
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
+ *
+ *
+ * Similar to mach-generic/dma-coherence.h except
+ * plat_device_is_coherent hard coded to return 1.
+ *
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
+#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
+
+struct device;
+
+dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
+void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+ size_t size)
+{
+ return octeon_map_dma_mem(dev, addr, size);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
+{
+ return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+ return dma_addr;
+}
+
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+{
+ octeon_unmap_dma_mem(dev, dma_addr);
+}
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ mb();
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+ return 1;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return dma_addr == -1;
+}
+
+#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 0000000..3dc0e0b
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,253 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#ifndef __OCTEON_IRQ_H__
+#define __OCTEON_IRQ_H__
+
+#define NR_IRQS OCTEON_IRQ_LAST
+#define MIPS_CPU_IRQ_BASE 0
+
+/* 0 - 7 represent the 8 MIPS standard interrupt sources */
+#define OCTEON_IRQ_SW0 0
+#define OCTEON_IRQ_SW1 1
+#define OCTEON_IRQ_CIU0 2
+#define OCTEON_IRQ_CIU1 3
+#define OCTEON_IRQ_CIU4 4
+#define OCTEON_IRQ_5 5
+#define OCTEON_IRQ_PERF 6
+#define OCTEON_IRQ_TIMER 7
+/* 8 - 71 represent the sources in CIU_INTX_EN0 */
+#define OCTEON_IRQ_WORKQ0 8
+#define OCTEON_IRQ_WORKQ1 9
+#define OCTEON_IRQ_WORKQ2 10
+#define OCTEON_IRQ_WORKQ3 11
+#define OCTEON_IRQ_WORKQ4 12
+#define OCTEON_IRQ_WORKQ5 13
+#define OCTEON_IRQ_WORKQ6 14
+#define OCTEON_IRQ_WORKQ7 15
+#define OCTEON_IRQ_WORKQ8 16
+#define OCTEON_IRQ_WORKQ9 17
+#define OCTEON_IRQ_WORKQ10 18
+#define OCTEON_IRQ_WORKQ11 19
+#define OCTEON_IRQ_WORKQ12 20
+#define OCTEON_IRQ_WORKQ13 21
+#define OCTEON_IRQ_WORKQ14 22
+#define OCTEON_IRQ_WORKQ15 23
+#define OCTEON_IRQ_GPIO0 24
+#define OCTEON_IRQ_GPIO1 25
+#define OCTEON_IRQ_GPIO2 26
+#define OCTEON_IRQ_GPIO3 27
+#define OCTEON_IRQ_GPIO4 28
+#define OCTEON_IRQ_GPIO5 29
+#define OCTEON_IRQ_GPIO6 30
+#define OCTEON_IRQ_GPIO7 31
+#define OCTEON_IRQ_GPIO8 32
+#define OCTEON_IRQ_GPIO9 33
+#define OCTEON_IRQ_GPIO10 34
+#define OCTEON_IRQ_GPIO11 35
+#define OCTEON_IRQ_GPIO12 36
+#define OCTEON_IRQ_GPIO13 37
+#define OCTEON_IRQ_GPIO14 38
+#define OCTEON_IRQ_GPIO15 39
+#define OCTEON_IRQ_MBOX0 40
+#define OCTEON_IRQ_MBOX1 41
+#define OCTEON_IRQ_UART0 42
+#define OCTEON_IRQ_UART1 43
+#define OCTEON_IRQ_PCI_INT0 44
+#define OCTEON_IRQ_PCI_INT1 45
+#define OCTEON_IRQ_PCI_INT2 46
+#define OCTEON_IRQ_PCI_INT3 47
+#define OCTEON_IRQ_PCI_MSI0 48
+#define OCTEON_IRQ_PCI_MSI1 49
+#define OCTEON_IRQ_PCI_MSI2 50
+#define OCTEON_IRQ_PCI_MSI3 51
+#define OCTEON_IRQ_RESERVED52 52 /* Summary of CIU_INT_SUM1 */
+#define OCTEON_IRQ_TWSI 53
+#define OCTEON_IRQ_RML 54
+#define OCTEON_IRQ_TRACE 55
+#define OCTEON_IRQ_GMX_DRP0 56
+#define OCTEON_IRQ_GMX_DRP1 57
+#define OCTEON_IRQ_IPD_DRP 58
+#define OCTEON_IRQ_KEY_ZERO 59
+#define OCTEON_IRQ_TIMER0 60
+#define OCTEON_IRQ_TIMER1 61
+#define OCTEON_IRQ_TIMER2 62
+#define OCTEON_IRQ_TIMER3 63
+#define OCTEON_IRQ_USB0 64
+#define OCTEON_IRQ_PCM 65
+#define OCTEON_IRQ_MPI 66
+#define OCTEON_IRQ_TWSI2 67
+#define OCTEON_IRQ_POWIQ 68
+#define OCTEON_IRQ_IPDPPTHR 69
+#define OCTEON_IRQ_MII0 70
+#define OCTEON_IRQ_BOOTDMA 71
+/* 72 - 135 represent the sources in CIU_INTX_EN1 */
+#define OCTEON_IRQ_WDOG0 72
+#define OCTEON_IRQ_WDOG1 73
+#define OCTEON_IRQ_WDOG2 74
+#define OCTEON_IRQ_WDOG3 75
+#define OCTEON_IRQ_WDOG4 76
+#define OCTEON_IRQ_WDOG5 77
+#define OCTEON_IRQ_WDOG6 78
+#define OCTEON_IRQ_WDOG7 79
+#define OCTEON_IRQ_WDOG8 80
+#define OCTEON_IRQ_WDOG9 81
+#define OCTEON_IRQ_WDOG10 82
+#define OCTEON_IRQ_WDOG11 83
+#define OCTEON_IRQ_WDOG12 84
+#define OCTEON_IRQ_WDOG13 85
+#define OCTEON_IRQ_WDOG14 86
+#define OCTEON_IRQ_WDOG15 87
+#define OCTEON_IRQ_UART2 88
+#define OCTEON_IRQ_USB1 89
+#define OCTEON_IRQ_MII1 90
+#define OCTEON_IRQ_RESERVED91 91
+#define OCTEON_IRQ_RESERVED92 92
+#define OCTEON_IRQ_RESERVED93 93
+#define OCTEON_IRQ_RESERVED94 94
+#define OCTEON_IRQ_RESERVED95 95
+#define OCTEON_IRQ_RESERVED96 96
+#define OCTEON_IRQ_RESERVED97 97
+#define OCTEON_IRQ_RESERVED98 98
+#define OCTEON_IRQ_RESERVED99 99
+#define OCTEON_IRQ_RESERVED100 100
+#define OCTEON_IRQ_RESERVED101 101
+#define OCTEON_IRQ_RESERVED102 102
+#define OCTEON_IRQ_RESERVED103 103
+#define OCTEON_IRQ_RESERVED104 104
+#define OCTEON_IRQ_RESERVED105 105
+#define OCTEON_IRQ_RESERVED106 106
+#define OCTEON_IRQ_RESERVED107 107
+#define OCTEON_IRQ_RESERVED108 108
+#define OCTEON_IRQ_RESERVED109 109
+#define OCTEON_IRQ_RESERVED110 110
+#define OCTEON_IRQ_RESERVED111 111
+#define OCTEON_IRQ_RESERVED112 112
+#define OCTEON_IRQ_RESERVED113 113
+#define OCTEON_IRQ_RESERVED114 114
+#define OCTEON_IRQ_RESERVED115 115
+#define OCTEON_IRQ_RESERVED116 116
+#define OCTEON_IRQ_RESERVED117 117
+#define OCTEON_IRQ_RESERVED118 118
+#define OCTEON_IRQ_RESERVED119 119
+#define OCTEON_IRQ_RESERVED120 120
+#define OCTEON_IRQ_RESERVED121 121
+#define OCTEON_IRQ_RESERVED122 122
+#define OCTEON_IRQ_RESERVED123 123
+#define OCTEON_IRQ_RESERVED124 124
+#define OCTEON_IRQ_RESERVED125 125
+#define OCTEON_IRQ_RESERVED126 126
+#define OCTEON_IRQ_RESERVED127 127
+#define OCTEON_IRQ_RESERVED128 128
+#define OCTEON_IRQ_RESERVED129 129
+#define OCTEON_IRQ_RESERVED130 130
+#define OCTEON_IRQ_RESERVED131 131
+#define OCTEON_IRQ_RESERVED132 132
+#define OCTEON_IRQ_RESERVED133 133
+#define OCTEON_IRQ_RESERVED134 134
+#define OCTEON_IRQ_RESERVED135 135
+/* 136 - 143 are reserved to align the i8259 in a multiple of 16. This
+ alignment is necessary since old style ISA interrupts hanging off the i8259
+ have internal alignment assumptions */
+#define OCTEON_IRQ_RESERVED136 136
+#define OCTEON_IRQ_RESERVED137 137
+#define OCTEON_IRQ_RESERVED138 138
+#define OCTEON_IRQ_RESERVED139 139
+#define OCTEON_IRQ_RESERVED140 140
+#define OCTEON_IRQ_RESERVED141 141
+#define OCTEON_IRQ_RESERVED142 142
+#define OCTEON_IRQ_RESERVED143 143
+/* 144 - 151 represent the i8259 master */
+#define OCTEON_IRQ_I8259M0 144
+#define OCTEON_IRQ_I8259M1 145
+#define OCTEON_IRQ_I8259M2 146
+#define OCTEON_IRQ_I8259M3 147
+#define OCTEON_IRQ_I8259M4 148
+#define OCTEON_IRQ_I8259M5 149
+#define OCTEON_IRQ_I8259M6 150
+#define OCTEON_IRQ_I8259M7 151
+/* 152 - 159 represent the i8259 slave */
+#define OCTEON_IRQ_I8259S0 152
+#define OCTEON_IRQ_I8259S1 153
+#define OCTEON_IRQ_I8259S2 154
+#define OCTEON_IRQ_I8259S3 155
+#define OCTEON_IRQ_I8259S4 156
+#define OCTEON_IRQ_I8259S5 157
+#define OCTEON_IRQ_I8259S6 158
+#define OCTEON_IRQ_I8259S7 159
+#ifdef CONFIG_PCI_MSI
+/* 160 - 223 represent the MSI interrupts 0-63 */
+#define OCTEON_IRQ_MSI_BIT0 160
+#define OCTEON_IRQ_MSI_BIT1 161
+#define OCTEON_IRQ_MSI_BIT2 162
+#define OCTEON_IRQ_MSI_BIT3 163
+#define OCTEON_IRQ_MSI_BIT4 164
+#define OCTEON_IRQ_MSI_BIT5 165
+#define OCTEON_IRQ_MSI_BIT6 166
+#define OCTEON_IRQ_MSI_BIT7 167
+#define OCTEON_IRQ_MSI_BIT8 168
+#define OCTEON_IRQ_MSI_BIT9 169
+#define OCTEON_IRQ_MSI_BIT10 170
+#define OCTEON_IRQ_MSI_BIT11 171
+#define OCTEON_IRQ_MSI_BIT12 172
+#define OCTEON_IRQ_MSI_BIT13 173
+#define OCTEON_IRQ_MSI_BIT14 174
+#define OCTEON_IRQ_MSI_BIT15 175
+#define OCTEON_IRQ_MSI_BIT16 176
+#define OCTEON_IRQ_MSI_BIT17 177
+#define OCTEON_IRQ_MSI_BIT18 178
+#define OCTEON_IRQ_MSI_BIT19 179
+#define OCTEON_IRQ_MSI_BIT20 180
+#define OCTEON_IRQ_MSI_BIT21 181
+#define OCTEON_IRQ_MSI_BIT22 182
+#define OCTEON_IRQ_MSI_BIT23 183
+#define OCTEON_IRQ_MSI_BIT24 184
+#define OCTEON_IRQ_MSI_BIT25 185
+#define OCTEON_IRQ_MSI_BIT26 186
+#define OCTEON_IRQ_MSI_BIT27 187
+#define OCTEON_IRQ_MSI_BIT28 188
+#define OCTEON_IRQ_MSI_BIT29 189
+#define OCTEON_IRQ_MSI_BIT30 190
+#define OCTEON_IRQ_MSI_BIT31 191
+#define OCTEON_IRQ_MSI_BIT32 192
+#define OCTEON_IRQ_MSI_BIT33 193
+#define OCTEON_IRQ_MSI_BIT34 194
+#define OCTEON_IRQ_MSI_BIT35 195
+#define OCTEON_IRQ_MSI_BIT36 196
+#define OCTEON_IRQ_MSI_BIT37 197
+#define OCTEON_IRQ_MSI_BIT38 198
+#define OCTEON_IRQ_MSI_BIT39 199
+#define OCTEON_IRQ_MSI_BIT40 200
+#define OCTEON_IRQ_MSI_BIT41 201
+#define OCTEON_IRQ_MSI_BIT42 202
+#define OCTEON_IRQ_MSI_BIT43 203
+#define OCTEON_IRQ_MSI_BIT44 204
+#define OCTEON_IRQ_MSI_BIT45 205
+#define OCTEON_IRQ_MSI_BIT46 206
+#define OCTEON_IRQ_MSI_BIT47 207
+#define OCTEON_IRQ_MSI_BIT48 208
+#define OCTEON_IRQ_MSI_BIT49 209
+#define OCTEON_IRQ_MSI_BIT50 210
+#define OCTEON_IRQ_MSI_BIT51 211
+#define OCTEON_IRQ_MSI_BIT52 212
+#define OCTEON_IRQ_MSI_BIT53 213
+#define OCTEON_IRQ_MSI_BIT54 214
+#define OCTEON_IRQ_MSI_BIT55 215
+#define OCTEON_IRQ_MSI_BIT56 216
+#define OCTEON_IRQ_MSI_BIT57 217
+#define OCTEON_IRQ_MSI_BIT58 218
+#define OCTEON_IRQ_MSI_BIT59 219
+#define OCTEON_IRQ_MSI_BIT60 220
+#define OCTEON_IRQ_MSI_BIT61 221
+#define OCTEON_IRQ_MSI_BIT62 222
+#define OCTEON_IRQ_MSI_BIT63 223
+#define OCTEON_IRQ_LAST 224
+#else
+#define OCTEON_IRQ_LAST 160
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 0000000..5851dbd
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,140 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2008 Cavium Networks, Inc
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+
+
+#define CP0_CYCLE_COUNTER $9,6
+#define CP0_CVMCTL_REG $9,7
+#define CP0_CVMMEMCTL_REG $11,7
+#define CP0_PRID_REG $15,0
+#define CP0_PRID_OCTEON_PASS1 0x000d0000
+#define CP0_PRID_OCTEON_CN30XX 0x000d0200
+
+.macro kernel_entry_setup
+ # Registers set by bootloader:
+ # (only 32 bits set by bootloader, all addresses are physical
+ # addresses, and need to have the appropriate memory region set
+ # by the kernel
+ # a0 = argc
+ # a1 = argv (kseg0 compat addr )
+ # a2 = 1 if init core, zero otherwise
+ # a3 = address of boot descriptor block
+ .set push
+ .set arch=octeon
+ # Read the cavium mem control register
+ dmfc0 v0, CP0_CVMMEMCTL_REG
+ # Clear the lower 6 bits, the CVMSEG size
+ dins v0, $0, 0, 6
+ ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+ dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
+ dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
+#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
+ # Disable unaligned load/store support but leave HW fixup enabled
+ or v0, v0, 0x5001
+ xor v0, v0, 0x1001
+#else
+ # Disable unaligned load/store and HW fixup support
+ or v0, v0, 0x5001
+ xor v0, v0, 0x5001
+#endif
+ # Read the processor ID register
+ mfc0 v1, CP0_PRID_REG
+ # Disable instruction prefetching (Octeon Pass1 errata)
+ or v0, v0, 0x2000
+ # Skip reenable of prefetching for Octeon Pass1
+ beq v1, CP0_PRID_OCTEON_PASS1,skip
+ nop
+ # Reenable instruction prefetching, not on Pass1
+ xor v0, v0, 0x2000
+ # Strip off pass number off of processor id
+ srl v1, 8
+ sll v1, 8
+ # CN30XX needs some extra stuff turned off for better performance
+ bne v1, CP0_PRID_OCTEON_CN30XX,skip
+ nop
+ # CN30XX Use random Icache replacement
+ or v0, v0, 0x400
+ # CN30XX Disable instruction prefetching
+ or v0, v0, 0x2000
+skip:
+ # Write the cavium control register
+ dmtc0 v0, CP0_CVMCTL_REG
+ sync
+ # Flush dcache after config change
+ cache 9, 0($0)
+ # Store the boot descriptor pointer
+ PTR_LA t2, octeon_boot_desc_ptr
+ LONG_S a3, (t2)
+ # Get my core id
+ rdhwr v0, $0
+ # Jump the master to kernel_entry
+ bne a2, zero, octeon_main_processor
+ nop
+
+#ifdef CONFIG_SMP
+
+ #
+ # All cores other than the master need to wait here for SMP bootstrap
+ # to begin
+ #
+
+ # This is the variable where the next core to boot os stored
+ PTR_LA t0, octeon_processor_boot
+octeon_spin_wait_boot:
+ # Get the core id of the next to be booted
+ LONG_L t1, (t0)
+ # Keep looping if it isn't me
+ bne t1, v0, octeon_spin_wait_boot
+ nop
+ # Synchronize the cycle counters
+ PTR_LA t0, octeon_processor_cycle
+ LONG_L t0, (t0)
+ # Aproximately how many cycles we will be off
+ LONG_ADDU t0, 122
+ MTC0 t0, CP0_CYCLE_COUNTER
+ # Get my GP from the global variable
+ PTR_LA t0, octeon_processor_gp
+ LONG_L gp, (t0)
+ # Get my SP from the global variable
+ PTR_LA t0, octeon_processor_sp
+ LONG_L sp, (t0)
+ # Set the SP global variable to zero so the master knows we've started
+ LONG_S zero, (t0)
+#ifdef __OCTEON__
+ syncw
+ syncw
+#else
+ sync
+#endif
+ # Jump to the normal Linux SMP entry point
+ j smp_bootstrap
+ nop
+#else /* CONFIG_SMP */
+
+ #
+ # Someone tried to boot SMP with a non SMP kernel. All extra cores
+ # will halt here.
+ #
+octeon_wait_forever:
+ wait
+ b octeon_wait_forever
+ nop
+
+#endif /* CONFIG_SMP */
+octeon_main_processor:
+ .set pop
+.endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+ .macro smp_slave_setup
+ .endm
+
+#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/octeon-hal-read-write.h b/arch/mips/include/asm/mach-cavium-octeon/octeon-hal-read-write.h
new file mode 100644
index 0000000..8c1dfc8
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/octeon-hal-read-write.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#ifndef __CAVIUM_OCTEON_HAL_READ_WRITE_H__
+#define __CAVIUM_OCTEON_HAL_READ_WRITE_H__
+
+#include "cvmx.h"
+
+
+/**
+ * Write a 32bit value to the Octeon NPI register space
+ *
+ * @param address Address to write to
+ * @param val Value to write
+ */
+static inline void octeon_npi_write32(uint64_t address, uint32_t val)
+{
+ cvmx_write64_uint32(address ^ 4, val);
+ cvmx_read64_uint32(address ^ 4);
+}
+
+
+/**
+ * Read a 32bit value from the Octeon NPI register space
+ *
+ * @param address Address to read
+ * @return The result
+ */
+static inline uint32_t octeon_npi_read32(uint64_t address)
+{
+ return cvmx_read64_uint32(address ^ 4);
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/perf_counters.h b/arch/mips/include/asm/mach-cavium-octeon/perf_counters.h
new file mode 100644
index 0000000..f52a511
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/perf_counters.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Cavium Networks
+ */
+
+/**
+ * The IOCTL numbers supported on /proc/octeon_perf
+ */
+#define PROC_PERF_IOCTL_SETUP_COUNTER0 _IOW(0x81, 0, int)
+#define PROC_PERF_IOCTL_SETUP_COUNTER1 _IOW(0x81, 1, int)
+#define PROC_PERF_IOCTL_SETUP_L2COUNTER0 _IOW(0x81, 2, int)
+#define PROC_PERF_IOCTL_SETUP_L2COUNTER1 _IOW(0x81, 3, int)
+#define PROC_PERF_IOCTL_SETUP_L2COUNTER2 _IOW(0x81, 4, int)
+#define PROC_PERF_IOCTL_SETUP_L2COUNTER3 _IOW(0x81, 5, int)
+#define PROC_PERF_IOCTL_READ_COUNTER0 _IOR(0x81, 6, long long)
+#define PROC_PERF_IOCTL_READ_COUNTER1 _IOR(0x81, 7, long long)
+#define PROC_PERF_IOCTL_READ_L2COUNTER0 _IOR(0x81, 8, long long)
+#define PROC_PERF_IOCTL_READ_L2COUNTER1 _IOR(0x81, 9, long long)
+#define PROC_PERF_IOCTL_READ_L2COUNTER2 _IOR(0x81, 10, long long)
+#define PROC_PERF_IOCTL_READ_L2COUNTER3 _IOR(0x81, 11, long long)
+
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
new file mode 100644
index 0000000..c4712d7
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
+ */
+#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 03/37] Add Cavium OCTEON processor support files to arch/mips/kernel.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
2008-10-24 0:56 ` [PATCH 01/37] Add Cavium OCTEON processor support files to arch/mips/cavium-octeon ddaney
2008-10-24 0:56 ` [PATCH 02/37] Add Cavium OCTEON files to arch/mips/include/asm/mach-cavium-octeon ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 04/37] Add Cavium OCTEON processor support files to arch/mips/mm ddaney
` (33 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/irq-octeon.c | 464 ++++++++++++++++++++++++++++++++++
arch/mips/kernel/octeon_switch.S | 506 ++++++++++++++++++++++++++++++++++++++
2 files changed, 970 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/kernel/irq-octeon.c
create mode 100644 arch/mips/kernel/octeon_switch.S
diff --git a/arch/mips/kernel/irq-octeon.c b/arch/mips/kernel/irq-octeon.c
new file mode 100644
index 0000000..738f3c6
--- /dev/null
+++ b/arch/mips/kernel/irq-octeon.c
@@ -0,0 +1,464 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2007 Cavium Networks
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include "../cavium-octeon/hal.h"
+
+DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
+DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
+DEFINE_SPINLOCK(octeon_irq_msi_lock);
+
+static void octeon_irq_core_ack(unsigned int irq)
+{
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ clear_c0_status(0x100 << irq);
+ /* The two user interrupts must be cleared manually */
+ if (irq < 2)
+ clear_c0_cause(0x100 << irq);
+}
+
+static void octeon_irq_core_eoi(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ /* If an IRQ is being processed while we are disabling it the handler
+ will attempt to unmask the interrupt after it has been disabled */
+ if (desc->status & IRQ_DISABLED)
+ return;
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ set_c0_status(0x100 << irq);
+}
+
+static void octeon_irq_core_enable(unsigned int irq)
+{
+ /* We need to disable interrupts to make sure our updates are atomic */
+ unsigned long flags;
+ local_irq_save(flags);
+ set_c0_status(0x100 << irq);
+ local_irq_restore(flags);
+}
+
+static void octeon_irq_core_disable_local(unsigned int irq)
+{
+ /* We need to disable interrupts to make sure our updates are atomic */
+ unsigned long flags;
+ local_irq_save(flags);
+ clear_c0_status(0x100 << irq);
+ local_irq_restore(flags);
+}
+
+static void octeon_irq_core_disable(unsigned int irq)
+{
+#ifdef CONFIG_SMP
+ on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
+ (void *) (long) irq, 1);
+#else
+ octeon_irq_core_disable_local(irq);
+#endif
+}
+
+struct irq_chip octeon_irq_chip_core = {
+ .name = "Core",
+ .enable = octeon_irq_core_enable,
+ .disable = octeon_irq_core_disable,
+ .ack = octeon_irq_core_ack,
+ .eoi = octeon_irq_core_eoi,
+};
+
+
+static void octeon_irq_ciu0_ack(unsigned int irq)
+{
+ /* In order to avoid any locking accessing the CIU, we acknowledge CIU
+ interrupts by disabling all of them. This way we can use a per core
+ register and avoid any out of core locking requirements. This has
+ the side affect that CIU interrupts can't be processed recursively */
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ clear_c0_status(0x100 << 2);
+}
+
+static void octeon_irq_ciu0_eoi(unsigned int irq)
+{
+ /* Enable all CIU interrupts again */
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ set_c0_status(0x100 << 2);
+}
+
+static void octeon_irq_ciu0_enable(unsigned int irq)
+{
+ int coreid = cvmx_get_core_num();
+ unsigned long flags;
+ uint64_t en0;
+ int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
+
+ /* A read lock is used here to make sure only one core is ever updating
+ the CIU enable bits at a time. During an enable the cores don't
+ interfere with each other. During a disable the write lock stops any
+ enables that might cause a problem */
+ read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
+ en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ en0 |= 1ull << bit;
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
+}
+
+static void octeon_irq_ciu0_disable(unsigned int irq)
+{
+ int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
+ unsigned long flags;
+ uint64_t en0;
+#ifdef CONFIG_SMP
+ int cpu;
+ write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
+ if (cpu_present(cpu)) {
+ int coreid = cpu_logical_map(cpu);
+ en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ en0 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+ }
+ }
+ /* We need to do a read after the last update to make sure all of them
+ are done */
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
+ write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
+#else
+ int coreid = cvmx_get_core_num();
+ local_irq_save(flags);
+ en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ en0 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ local_irq_restore(flags);
+#endif
+}
+
+#ifdef CONFIG_SMP
+static void octeon_irq_ciu0_set_affinity(unsigned int irq, cpumask_t dest)
+{
+ int cpu;
+ int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
+
+ write_lock(&octeon_irq_ciu0_rwlock);
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
+ if (cpu_present(cpu)) {
+ int coreid = cpu_logical_map(cpu);
+ uint64_t en0 =
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+ if (cpu_isset(cpu, dest))
+ en0 |= 1ull << bit;
+ else
+ en0 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+ }
+ }
+ /* We need to do a read after the last update to make sure all of them
+ are done */
+ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
+ write_unlock(&octeon_irq_ciu0_rwlock);
+}
+#endif
+
+struct irq_chip octeon_irq_chip_ciu0 = {
+ .name = "CIU0",
+ .enable = octeon_irq_ciu0_enable,
+ .disable = octeon_irq_ciu0_disable,
+ .ack = octeon_irq_ciu0_ack,
+ .eoi = octeon_irq_ciu0_eoi,
+#ifdef CONFIG_SMP
+ .set_affinity = octeon_irq_ciu0_set_affinity,
+#endif
+};
+
+
+static void octeon_irq_ciu1_ack(unsigned int irq)
+{
+ /* In order to avoid any locking accessing the CIU, we acknowledge CIU
+ interrupts by disabling all of them. This way we can use a per core
+ register and avoid any out of core locking requirements. This has
+ the side affect that CIU interrupts can't be processed recursively */
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ clear_c0_status(0x100 << 3);
+}
+
+static void octeon_irq_ciu1_eoi(unsigned int irq)
+{
+ /* Enable all CIU interrupts again */
+ /* We don't need to disable IRQs to make these atomic since they are
+ already disabled earlier in the low level interrupt code */
+ set_c0_status(0x100 << 3);
+}
+
+static void octeon_irq_ciu1_enable(unsigned int irq)
+{
+ int coreid = cvmx_get_core_num();
+ unsigned long flags;
+ uint64_t en1;
+ int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+
+ /* A read lock is used here to make sure only one core is ever updating
+ the CIU enable bits at a time. During an enable the cores don't
+ interfere with each other. During a disable the write lock stops any
+ enables that might cause a problem */
+ read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
+ en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ en1 |= 1ull << bit;
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
+}
+
+static void octeon_irq_ciu1_disable(unsigned int irq)
+{
+ int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+ unsigned long flags;
+ uint64_t en1;
+#ifdef CONFIG_SMP
+ int cpu;
+ write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
+ if (cpu_present(cpu)) {
+ int coreid = cpu_logical_map(cpu);
+ en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ en1 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+ }
+ }
+ /* We need to do a read after the last update to make sure all of them
+ are done */
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
+ write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
+#else
+ int coreid = cvmx_get_core_num();
+ local_irq_save(flags);
+ en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ en1 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+ local_irq_restore(flags);
+#endif
+}
+
+#ifdef CONFIG_SMP
+static void octeon_irq_ciu1_set_affinity(unsigned int irq, cpumask_t dest)
+{
+ int cpu;
+ int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
+
+ write_lock(&octeon_irq_ciu1_rwlock);
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
+ if (cpu_present(cpu)) {
+ int coreid = cpu_logical_map(cpu);
+ uint64_t en1 =
+ cvmx_read_csr(CVMX_CIU_INTX_EN1
+ (coreid * 2 + 1));
+ if (cpu_isset(cpu, dest))
+ en1 |= 1ull << bit;
+ else
+ en1 &= ~(1ull << bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+ }
+ }
+ /* We need to do a read after the last update to make sure all of them
+ are done */
+ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
+ write_unlock(&octeon_irq_ciu1_rwlock);
+}
+#endif
+
+struct irq_chip octeon_irq_chip_ciu1 = {
+ .name = "CIU1",
+ .enable = octeon_irq_ciu1_enable,
+ .disable = octeon_irq_ciu1_disable,
+ .ack = octeon_irq_ciu1_ack,
+ .eoi = octeon_irq_ciu1_eoi,
+#ifdef CONFIG_SMP
+ .set_affinity = octeon_irq_ciu1_set_affinity,
+#endif
+};
+
+
+static void octeon_irq_i8289_master_unmask(unsigned int irq)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ outb(inb(0x21) & ~(1 << (irq - OCTEON_IRQ_I8259M0)), 0x21);
+ local_irq_restore(flags);
+}
+
+static void octeon_irq_i8289_master_mask(unsigned int irq)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ outb(inb(0x21) | (1 << (irq - OCTEON_IRQ_I8259M0)), 0x21);
+ local_irq_restore(flags);
+}
+
+struct irq_chip octeon_irq_chip_i8259_master = {
+ .name = "i8259M",
+ .mask = octeon_irq_i8289_master_mask,
+ .mask_ack = octeon_irq_i8289_master_mask,
+ .unmask = octeon_irq_i8289_master_unmask,
+ .eoi = octeon_irq_i8289_master_unmask,
+};
+
+
+static void octeon_irq_i8289_slave_unmask(unsigned int irq)
+{
+ outb(inb(0xa1) & ~(1 << (irq - OCTEON_IRQ_I8259S0)), 0xa1);
+}
+
+static void octeon_irq_i8289_slave_mask(unsigned int irq)
+{
+ outb(inb(0xa1) | (1 << (irq - OCTEON_IRQ_I8259S0)), 0xa1);
+}
+
+struct irq_chip octeon_irq_chip_i8259_slave = {
+ .name = "i8259S",
+ .mask = octeon_irq_i8289_slave_mask,
+ .mask_ack = octeon_irq_i8289_slave_mask,
+ .unmask = octeon_irq_i8289_slave_unmask,
+ .eoi = octeon_irq_i8289_slave_unmask,
+};
+
+#ifdef CONFIG_PCI_MSI
+
+static void octeon_irq_msi_ack(unsigned int irq)
+{
+ if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ /* These chips have PCI */
+ cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
+ 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
+ } else {
+ /* These chips have PCIe. Thankfully the ACK doesn't need any
+ locking */
+ cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
+ 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
+ }
+}
+
+static void octeon_irq_msi_eoi(unsigned int irq)
+{
+ /* Nothing needed */
+}
+
+static void octeon_irq_msi_enable(unsigned int irq)
+{
+ if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ /* Octeon PCI doesn't have the ability to mask/unmask MSI
+ interrupts individually. Instead of masking/unmasking them
+ in groups of 16, we simple assume MSI devices are well
+ behaved. MSI interrupts are always enable and the ACK is
+ assumed to be enough */
+ } else {
+ /* These chips have PCIe. Note that we only support the first
+ 64 MSI interrupts. Unfortunately all the MSI enables are in
+ the same register. We use MSI0's lock to control access to
+ them all. */
+ uint64_t en;
+ unsigned long flags;
+ spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+ en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
+ en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
+ cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
+ cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
+ spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+ }
+}
+
+static void octeon_irq_msi_disable(unsigned int irq)
+{
+ if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ /* See comment in enable */
+ } else {
+ /* These chips have PCIe. Note that we only support the first
+ 64 MSI interrupts. Unfortunately all the MSI enables are in
+ the same register. We use MSI0's lock to control access to
+ them all. */
+ uint64_t en;
+ unsigned long flags;
+ spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+ en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
+ en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
+ cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
+ cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
+ spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+ }
+}
+
+struct irq_chip octeon_irq_chip_msi = {
+ .name = "MSI",
+ .enable = octeon_irq_msi_enable,
+ .disable = octeon_irq_msi_disable,
+ .ack = octeon_irq_msi_ack,
+ .eoi = octeon_irq_msi_eoi,
+};
+#endif
+
+void __init arch_init_irq(void)
+{
+ int irq;
+
+ if (NR_IRQS < OCTEON_IRQ_LAST)
+ pr_err("octeon_irq_init: NR_IRQS is set too low\n");
+
+ /* 0-7 Mips internal */
+ for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
+ handle_percpu_irq);
+ }
+
+ /* 8-71 CIU_INT_SUM0 */
+ for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
+ handle_percpu_irq);
+ }
+
+ /* 72-135 CIU_INT_SUM1 */
+ for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED135; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
+ handle_percpu_irq);
+ }
+
+ /* 136 - 143 are reserved to align the i8259 in a multiple of 16. This
+ alignment is necessary since old style ISA interrupts hanging off
+ the i8259 have internal alignment assumptions */
+
+ /* 144-151 i8259 master controller */
+ for (irq = OCTEON_IRQ_I8259M0; irq <= OCTEON_IRQ_I8259M7; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_i8259_master,
+ handle_level_irq);
+ }
+
+ /* 152-159 i8259 slave controller */
+ for (irq = OCTEON_IRQ_I8259S0; irq <= OCTEON_IRQ_I8259S7; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_i8259_slave,
+ handle_level_irq);
+ }
+
+#ifdef CONFIG_PCI_MSI
+ /* 160-223 PCI/PCIe MSI interrupts */
+ for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
+ set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
+ handle_percpu_irq);
+ }
+#endif
+
+ set_c0_status(0x300 << 2);
+}
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
new file mode 100644
index 0000000..d523896
--- /dev/null
+++ b/arch/mips/kernel/octeon_switch.S
@@ -0,0 +1,506 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1994, 1995, 1996, by Andreas Busse
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ * written by Carsten Langgaard, carstenl@mips.com
+ */
+#include <asm/asm.h>
+#include <asm/cachectl.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+#include <asm/pgtable-bits.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/thread_info.h>
+
+#include <asm/asmmacro.h>
+
+/*
+ * Offset to the current process status flags, the first 32 bytes of the
+ * stack are not used.
+ */
+#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
+
+/*
+ * task_struct *resume(task_struct *prev, task_struct *next,
+ * struct thread_info *next_ti)
+ */
+ .align 7
+ LEAF(resume)
+ .set arch=octeon
+#ifndef CONFIG_CPU_HAS_LLSC
+ sw zero, ll_bit
+#endif
+ mfc0 t1, CP0_STATUS
+ LONG_S t1, THREAD_STATUS(a0)
+ cpu_save_nonscratch a0
+ LONG_S ra, THREAD_REG31(a0)
+
+ /* check if we need to save COP2 registers */
+ PTR_L t2, TASK_THREAD_INFO(a0)
+ LONG_L t0, ST_OFF(t2)
+ bbit0 t0, 30, 1f
+
+ /* Disable COP2 in the stored process state */
+ li t1, ST0_CU2
+ xor t0, t1
+ LONG_S t0, ST_OFF(t2)
+
+ /* Enable COP2 so we can save it */
+ mfc0 t0, CP0_STATUS
+ or t0, t1
+ mtc0 t0, CP0_STATUS
+
+ /* Save COP2 */
+ daddu a0, THREAD_CP2
+ jal octeon_cop2_save
+ dsubu a0, THREAD_CP2
+
+ /* Disable COP2 now that we are done */
+ mfc0 t0, CP0_STATUS
+ li t1, ST0_CU2
+ xor t0, t1
+ mtc0 t0, CP0_STATUS
+
+1:
+#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
+ /* Check if we need to store CVMSEG state */
+ mfc0 t0, $11,7 /* CvmMemCtl */
+ bbit0 t0, 6, 3f /* Is user access enabled? */
+
+ /* Store the CVMSEG state */
+ /* Extract the size of CVMSEG */
+ andi t0, 0x3f
+ /* Multiply * (cache line size/sizeof(long)/2) */
+ sll t0, 7-LONGLOG-1
+ li t1, -32768 /* Base address of CVMSEG */
+ LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
+ synciobdma
+2:
+ .set noreorder
+ LONG_L t8, 0(t1) /* Load from CVMSEG */
+ subu t0, 1 /* Decrement loop var */
+ LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
+ LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
+ LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
+ LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
+ bnez t0, 2b /* Loop until we've copied it all */
+ LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
+ .set reorder
+
+ /* Disable access to CVMSEG */
+ mfc0 t0, $11,7 /* CvmMemCtl */
+ xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
+ mtc0 t0, $11,7 /* CvmMemCtl */
+#endif
+3:
+ /*
+ * The order of restoring the registers takes care of the race
+ * updating $28, $29 and kernelsp without disabling ints.
+ */
+ move $28, a2
+ cpu_restore_nonscratch a1
+
+#if (_THREAD_SIZE - 32) < 0x8000
+ PTR_ADDIU t0, $28, _THREAD_SIZE - 32
+#else
+ PTR_LI t0, _THREAD_SIZE - 32
+ PTR_ADDU t0, $28
+#endif
+ set_saved_sp t0, t1, t2
+
+ mfc0 t1, CP0_STATUS /* Do we really need this? */
+ li a3, 0xff01
+ and t1, a3
+ LONG_L a2, THREAD_STATUS(a1)
+ nor a3, $0, a3
+ and a2, a3
+ or a2, t1
+ mtc0 a2, CP0_STATUS
+ move v0, a0
+ jr ra
+ END(resume)
+
+/*
+ * void octeon_cop2_save(struct octeon_cop2_state *a0)
+ */
+ .align 7
+ LEAF(octeon_cop2_save)
+
+ dmfc0 t9, $9,7 /* CvmCtl register. */
+
+ /* Save the COP2 CRC state */
+ dmfc2 t0, 0x0201
+ dmfc2 t1, 0x0202
+ dmfc2 t2, 0x0200
+ sd t0, OCTEON_CP2_CRC_IV(a0)
+ sd t1, OCTEON_CP2_CRC_LENGTH(a0)
+ sd t2, OCTEON_CP2_CRC_POLY(a0)
+ /* Skip next instructions if CvmCtl[NODFA_CP2] set */
+ bbit1 t9, 28, 1f
+
+ /* Save the LLM state */
+ dmfc2 t0, 0x0402
+ dmfc2 t1, 0x040A
+ sd t0, OCTEON_CP2_LLM_DAT(a0)
+ sd t1, OCTEON_CP2_LLM_DAT+8(a0)
+
+1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
+
+ /* Save the COP2 crypto state */
+ /* this part is mostly common to both pass 1 and later revisions */
+ dmfc2 t0, 0x0084
+ dmfc2 t1, 0x0080
+ dmfc2 t2, 0x0081
+ dmfc2 t3, 0x0082
+ sd t0, OCTEON_CP2_3DES_IV(a0)
+ dmfc2 t0, 0x0088
+ sd t1, OCTEON_CP2_3DES_KEY(a0)
+ dmfc2 t1, 0x0111 /* only necessary for pass 1 */
+ sd t2, OCTEON_CP2_3DES_KEY+8(a0)
+ dmfc2 t2, 0x0102
+ sd t3, OCTEON_CP2_3DES_KEY+16(a0)
+ dmfc2 t3, 0x0103
+ sd t0, OCTEON_CP2_3DES_RESULT(a0)
+ dmfc2 t0, 0x0104
+ sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
+ dmfc2 t1, 0x0105
+ sd t2, OCTEON_CP2_AES_IV(a0)
+ dmfc2 t2, 0x0106
+ sd t3, OCTEON_CP2_AES_IV+8(a0)
+ dmfc2 t3, 0x0107
+ sd t0, OCTEON_CP2_AES_KEY(a0)
+ dmfc2 t0, 0x0110
+ sd t1, OCTEON_CP2_AES_KEY+8(a0)
+ dmfc2 t1, 0x0100
+ sd t2, OCTEON_CP2_AES_KEY+16(a0)
+ dmfc2 t2, 0x0101
+ sd t3, OCTEON_CP2_AES_KEY+24(a0)
+ mfc0 t3, $15,0 /* Get the processor ID register */
+ sd t0, OCTEON_CP2_AES_KEYLEN(a0)
+ li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
+ sd t1, OCTEON_CP2_AES_RESULT(a0)
+ sd t2, OCTEON_CP2_AES_RESULT+8(a0)
+ /* Skip to the Pass1 version of the remainder of the COP2 state */
+ beq t3, t0, 2f
+
+ /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
+ dmfc2 t1, 0x0240
+ dmfc2 t2, 0x0241
+ dmfc2 t3, 0x0242
+ dmfc2 t0, 0x0243
+ sd t1, OCTEON_CP2_HSH_DATW(a0)
+ dmfc2 t1, 0x0244
+ sd t2, OCTEON_CP2_HSH_DATW+8(a0)
+ dmfc2 t2, 0x0245
+ sd t3, OCTEON_CP2_HSH_DATW+16(a0)
+ dmfc2 t3, 0x0246
+ sd t0, OCTEON_CP2_HSH_DATW+24(a0)
+ dmfc2 t0, 0x0247
+ sd t1, OCTEON_CP2_HSH_DATW+32(a0)
+ dmfc2 t1, 0x0248
+ sd t2, OCTEON_CP2_HSH_DATW+40(a0)
+ dmfc2 t2, 0x0249
+ sd t3, OCTEON_CP2_HSH_DATW+48(a0)
+ dmfc2 t3, 0x024A
+ sd t0, OCTEON_CP2_HSH_DATW+56(a0)
+ dmfc2 t0, 0x024B
+ sd t1, OCTEON_CP2_HSH_DATW+64(a0)
+ dmfc2 t1, 0x024C
+ sd t2, OCTEON_CP2_HSH_DATW+72(a0)
+ dmfc2 t2, 0x024D
+ sd t3, OCTEON_CP2_HSH_DATW+80(a0)
+ dmfc2 t3, 0x024E
+ sd t0, OCTEON_CP2_HSH_DATW+88(a0)
+ dmfc2 t0, 0x0250
+ sd t1, OCTEON_CP2_HSH_DATW+96(a0)
+ dmfc2 t1, 0x0251
+ sd t2, OCTEON_CP2_HSH_DATW+104(a0)
+ dmfc2 t2, 0x0252
+ sd t3, OCTEON_CP2_HSH_DATW+112(a0)
+ dmfc2 t3, 0x0253
+ sd t0, OCTEON_CP2_HSH_IVW(a0)
+ dmfc2 t0, 0x0254
+ sd t1, OCTEON_CP2_HSH_IVW+8(a0)
+ dmfc2 t1, 0x0255
+ sd t2, OCTEON_CP2_HSH_IVW+16(a0)
+ dmfc2 t2, 0x0256
+ sd t3, OCTEON_CP2_HSH_IVW+24(a0)
+ dmfc2 t3, 0x0257
+ sd t0, OCTEON_CP2_HSH_IVW+32(a0)
+ dmfc2 t0, 0x0258
+ sd t1, OCTEON_CP2_HSH_IVW+40(a0)
+ dmfc2 t1, 0x0259
+ sd t2, OCTEON_CP2_HSH_IVW+48(a0)
+ dmfc2 t2, 0x025E
+ sd t3, OCTEON_CP2_HSH_IVW+56(a0)
+ dmfc2 t3, 0x025A
+ sd t0, OCTEON_CP2_GFM_MULT(a0)
+ dmfc2 t0, 0x025B
+ sd t1, OCTEON_CP2_GFM_MULT+8(a0)
+ sd t2, OCTEON_CP2_GFM_POLY(a0)
+ sd t3, OCTEON_CP2_GFM_RESULT(a0)
+ sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
+ jr ra
+
+2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
+ dmfc2 t3, 0x0040
+ dmfc2 t0, 0x0041
+ dmfc2 t1, 0x0042
+ dmfc2 t2, 0x0043
+ sd t3, OCTEON_CP2_HSH_DATW(a0)
+ dmfc2 t3, 0x0044
+ sd t0, OCTEON_CP2_HSH_DATW+8(a0)
+ dmfc2 t0, 0x0045
+ sd t1, OCTEON_CP2_HSH_DATW+16(a0)
+ dmfc2 t1, 0x0046
+ sd t2, OCTEON_CP2_HSH_DATW+24(a0)
+ dmfc2 t2, 0x0048
+ sd t3, OCTEON_CP2_HSH_DATW+32(a0)
+ dmfc2 t3, 0x0049
+ sd t0, OCTEON_CP2_HSH_DATW+40(a0)
+ dmfc2 t0, 0x004A
+ sd t1, OCTEON_CP2_HSH_DATW+48(a0)
+ sd t2, OCTEON_CP2_HSH_IVW(a0)
+ sd t3, OCTEON_CP2_HSH_IVW+8(a0)
+ sd t0, OCTEON_CP2_HSH_IVW+16(a0)
+
+3: /* pass 1 or CvmCtl[NOCRYPTO] set */
+ jr ra
+ END(octeon_cop2_save)
+
+/*
+ * void octeon_cop2_restore(struct octeon_cop2_state *a0)
+ */
+ .align 7
+ .set push
+ .set noreorder
+ LEAF(octeon_cop2_restore)
+ /* First cache line was prefetched before the call */
+ pref 4, 128(a0)
+ dmfc0 t9, $9,7 /* CvmCtl register. */
+
+ pref 4, 256(a0)
+ ld t0, OCTEON_CP2_CRC_IV(a0)
+ pref 4, 384(a0)
+ ld t1, OCTEON_CP2_CRC_LENGTH(a0)
+ ld t2, OCTEON_CP2_CRC_POLY(a0)
+
+ /* Restore the COP2 CRC state */
+ dmtc2 t0, 0x0201
+ dmtc2 t1, 0x1202
+ bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
+ dmtc2 t2, 0x4200
+
+ /* Restore the LLM state */
+ ld t0, OCTEON_CP2_LLM_DAT(a0)
+ ld t1, OCTEON_CP2_LLM_DAT+8(a0)
+ dmtc2 t0, 0x0402
+ dmtc2 t1, 0x040A
+
+2:
+ bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
+ nop
+
+ /* Restore the COP2 crypto state common to pass 1 and pass 2 */
+ ld t0, OCTEON_CP2_3DES_IV(a0)
+ ld t1, OCTEON_CP2_3DES_KEY(a0)
+ ld t2, OCTEON_CP2_3DES_KEY+8(a0)
+ dmtc2 t0, 0x0084
+ ld t0, OCTEON_CP2_3DES_KEY+16(a0)
+ dmtc2 t1, 0x0080
+ ld t1, OCTEON_CP2_3DES_RESULT(a0)
+ dmtc2 t2, 0x0081
+ ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
+ dmtc2 t0, 0x0082
+ ld t0, OCTEON_CP2_AES_IV(a0)
+ dmtc2 t1, 0x0098
+ ld t1, OCTEON_CP2_AES_IV+8(a0)
+ dmtc2 t2, 0x010A /* only really needed for pass 1 */
+ ld t2, OCTEON_CP2_AES_KEY(a0)
+ dmtc2 t0, 0x0102
+ ld t0, OCTEON_CP2_AES_KEY+8(a0)
+ dmtc2 t1, 0x0103
+ ld t1, OCTEON_CP2_AES_KEY+16(a0)
+ dmtc2 t2, 0x0104
+ ld t2, OCTEON_CP2_AES_KEY+24(a0)
+ dmtc2 t0, 0x0105
+ ld t0, OCTEON_CP2_AES_KEYLEN(a0)
+ dmtc2 t1, 0x0106
+ ld t1, OCTEON_CP2_AES_RESULT(a0)
+ dmtc2 t2, 0x0107
+ ld t2, OCTEON_CP2_AES_RESULT+8(a0)
+ mfc0 t3, $15,0 /* Get the processor ID register */
+ dmtc2 t0, 0x0110
+ li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
+ dmtc2 t1, 0x0100
+ bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
+ dmtc2 t2, 0x0101
+
+ /* this code is specific for pass 1 */
+ ld t0, OCTEON_CP2_HSH_DATW(a0)
+ ld t1, OCTEON_CP2_HSH_DATW+8(a0)
+ ld t2, OCTEON_CP2_HSH_DATW+16(a0)
+ dmtc2 t0, 0x0040
+ ld t0, OCTEON_CP2_HSH_DATW+24(a0)
+ dmtc2 t1, 0x0041
+ ld t1, OCTEON_CP2_HSH_DATW+32(a0)
+ dmtc2 t2, 0x0042
+ ld t2, OCTEON_CP2_HSH_DATW+40(a0)
+ dmtc2 t0, 0x0043
+ ld t0, OCTEON_CP2_HSH_DATW+48(a0)
+ dmtc2 t1, 0x0044
+ ld t1, OCTEON_CP2_HSH_IVW(a0)
+ dmtc2 t2, 0x0045
+ ld t2, OCTEON_CP2_HSH_IVW+8(a0)
+ dmtc2 t0, 0x0046
+ ld t0, OCTEON_CP2_HSH_IVW+16(a0)
+ dmtc2 t1, 0x0048
+ dmtc2 t2, 0x0049
+ b done_restore /* unconditional branch */
+ dmtc2 t0, 0x004A
+
+3: /* this is post-pass1 code */
+ ld t2, OCTEON_CP2_HSH_DATW(a0)
+ ld t0, OCTEON_CP2_HSH_DATW+8(a0)
+ ld t1, OCTEON_CP2_HSH_DATW+16(a0)
+ dmtc2 t2, 0x0240
+ ld t2, OCTEON_CP2_HSH_DATW+24(a0)
+ dmtc2 t0, 0x0241
+ ld t0, OCTEON_CP2_HSH_DATW+32(a0)
+ dmtc2 t1, 0x0242
+ ld t1, OCTEON_CP2_HSH_DATW+40(a0)
+ dmtc2 t2, 0x0243
+ ld t2, OCTEON_CP2_HSH_DATW+48(a0)
+ dmtc2 t0, 0x0244
+ ld t0, OCTEON_CP2_HSH_DATW+56(a0)
+ dmtc2 t1, 0x0245
+ ld t1, OCTEON_CP2_HSH_DATW+64(a0)
+ dmtc2 t2, 0x0246
+ ld t2, OCTEON_CP2_HSH_DATW+72(a0)
+ dmtc2 t0, 0x0247
+ ld t0, OCTEON_CP2_HSH_DATW+80(a0)
+ dmtc2 t1, 0x0248
+ ld t1, OCTEON_CP2_HSH_DATW+88(a0)
+ dmtc2 t2, 0x0249
+ ld t2, OCTEON_CP2_HSH_DATW+96(a0)
+ dmtc2 t0, 0x024A
+ ld t0, OCTEON_CP2_HSH_DATW+104(a0)
+ dmtc2 t1, 0x024B
+ ld t1, OCTEON_CP2_HSH_DATW+112(a0)
+ dmtc2 t2, 0x024C
+ ld t2, OCTEON_CP2_HSH_IVW(a0)
+ dmtc2 t0, 0x024D
+ ld t0, OCTEON_CP2_HSH_IVW+8(a0)
+ dmtc2 t1, 0x024E
+ ld t1, OCTEON_CP2_HSH_IVW+16(a0)
+ dmtc2 t2, 0x0250
+ ld t2, OCTEON_CP2_HSH_IVW+24(a0)
+ dmtc2 t0, 0x0251
+ ld t0, OCTEON_CP2_HSH_IVW+32(a0)
+ dmtc2 t1, 0x0252
+ ld t1, OCTEON_CP2_HSH_IVW+40(a0)
+ dmtc2 t2, 0x0253
+ ld t2, OCTEON_CP2_HSH_IVW+48(a0)
+ dmtc2 t0, 0x0254
+ ld t0, OCTEON_CP2_HSH_IVW+56(a0)
+ dmtc2 t1, 0x0255
+ ld t1, OCTEON_CP2_GFM_MULT(a0)
+ dmtc2 t2, 0x0256
+ ld t2, OCTEON_CP2_GFM_MULT+8(a0)
+ dmtc2 t0, 0x0257
+ ld t0, OCTEON_CP2_GFM_POLY(a0)
+ dmtc2 t1, 0x0258
+ ld t1, OCTEON_CP2_GFM_RESULT(a0)
+ dmtc2 t2, 0x0259
+ ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
+ dmtc2 t0, 0x025E
+ dmtc2 t1, 0x025A
+ dmtc2 t2, 0x025B
+
+done_restore:
+ jr ra
+ nop
+ END(octeon_cop2_restore)
+ .set pop
+
+/*
+ * void octeon_mult_save()
+ * sp is assumed to point to a struct pt_regs
+ *
+ * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
+ * safely modify k0 and k1.
+ */
+ .align 7
+ .set push
+ .set noreorder
+ LEAF(octeon_mult_save)
+ dmfc0 k0, $9,7 /* CvmCtl register. */
+ bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
+ nop
+
+ /* Save the multiplier state */
+ v3mulu k0, $0, $0
+ v3mulu k1, $0, $0
+ sd k0, PT_MTP(sp) /* PT_MTP has P0 */
+ v3mulu k0, $0, $0
+ sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
+ ori k1, $0, 1
+ v3mulu k1, k1, $0
+ sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
+ v3mulu k0, $0, $0
+ sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
+ v3mulu k1, $0, $0
+ sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
+ jr ra
+ sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
+
+1: /* Resume here if CvmCtl[NOMUL] */
+ jr ra
+ END(octeon_mult_save)
+ .set pop
+
+/*
+ * void octeon_mult_restore()
+ * sp is assumed to point to a struct pt_regs
+ *
+ * NOTE: This is called in RESTORE_SOME in stackframe.h.
+ */
+ .align 7
+ .set push
+ .set noreorder
+ LEAF(octeon_mult_restore)
+ dmfc0 k1, $9,7 /* CvmCtl register. */
+ ld v0, PT_MPL(sp) /* MPL0 */
+ ld v1, PT_MPL+8(sp) /* MPL1 */
+ ld k0, PT_MPL+16(sp) /* MPL2 */
+ bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
+ /* Normally falls through, so no time wasted here */
+ nop
+
+ /* Restore the multiplier state */
+ ld k1, PT_MTP+16(sp) /* P2 */
+ MTM0 v0 /* MPL0 */
+ ld v0, PT_MTP+8(sp) /* P1 */
+ MTM1 v1 /* MPL1 */
+ ld v1, PT_MTP(sp) /* P0 */
+ MTM2 k0 /* MPL2 */
+ MTP2 k1 /* P2 */
+ MTP1 v0 /* P1 */
+ jr ra
+ MTP0 v1 /* P0 */
+
+1: /* Resume here if CvmCtl[NOMUL] */
+ jr ra
+ nop
+ END(octeon_mult_restore)
+ .set pop
+
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 04/37] Add Cavium OCTEON processor support files to arch/mips/mm.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (2 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 03/37] Add Cavium OCTEON processor support files to arch/mips/kernel ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 05/37] Add Cavium OCTEON processor support files to and arch/mips/cavium-octeon/executive ddaney
` (32 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/mm/c-octeon.c | 309 +++++++++++++++++++++++++++++++++++++++++++++++
arch/mips/mm/cex-oct.S | 70 +++++++++++
2 files changed, 379 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/mm/c-octeon.c
create mode 100644 arch/mips/mm/cex-oct.S
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
new file mode 100644
index 0000000..6c96c1a
--- /dev/null
+++ b/arch/mips/mm/c-octeon.c
@@ -0,0 +1,309 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/bitops.h>
+#include <linux/cpu.h>
+#include <linux/io.h>
+
+#include <asm/bcache.h>
+#include <asm/bootinfo.h>
+#include <asm/cacheops.h>
+#include <asm/cpu-features.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/r4kcache.h>
+#include <asm/system.h>
+#include <asm/mmu_context.h>
+#include <asm/war.h>
+#include "../cavium-octeon/hal.h"
+
+unsigned long long cache_err_dcache[NR_CPUS];
+
+/**
+ * Octeon automatically flushes the dcache on tlb changes, so
+ * from Linux's viewpoint it acts much like a physically
+ * tagged cache. No flushing is needed
+ *
+ * @param addr
+ */
+static void octeon_flush_data_cache_page(unsigned long addr)
+{
+ /* Nothing to do */
+}
+
+/* Flush local I-cache for the specified range.
+ */
+static inline void local_octeon_flush_icache_range(unsigned long start,
+ unsigned long end)
+{
+ asm volatile ("synci 0($0)\n");
+}
+
+/**
+ * Flush caches as necessary for all cores affected by a
+ * vma. If no vma is supplied, all cores are flushed.
+ *
+ * @param vma VMA to flush or NULL to flush all icaches.
+ */
+static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
+{
+ extern struct plat_smp_ops *mp_ops; /* private */
+#ifdef CONFIG_SMP
+ int i;
+ int cpu;
+#endif
+
+ preempt_disable();
+#ifdef CONFIG_SMP
+ cpu = smp_processor_id();
+#endif
+ mb();
+
+ /* If we have a vma structure, we only need to worry about cores it
+ has been used on */
+ if (vma) {
+#ifdef CONFIG_SMP
+ for (i = 0; i < NR_CPUS; i++)
+ if (cpu_isset(i, vma->vm_mm->cpu_vm_mask) && i != cpu)
+ mp_ops->send_ipi_single(i, SMP_ICACHE_FLUSH);
+#endif
+ asm volatile ("synci 0($0)\n");
+ } else {
+ /* No extra info available. Flush the icache on all cores that
+ are online */
+#ifdef CONFIG_SMP
+ for (i = 0; i < NR_CPUS; i++)
+ if (cpu_online(i) && i != cpu)
+ mp_ops->send_ipi_single(i, SMP_ICACHE_FLUSH);
+#endif
+ asm volatile ("synci 0($0)\n");
+ }
+ preempt_enable();
+}
+
+
+/**
+ * Called to flush the icache on all cores
+ */
+static void octeon_flush_icache_all(void)
+{
+ octeon_flush_icache_all_cores(NULL);
+}
+
+
+/**
+ * Called to flush all memory associated with a memory
+ * context.
+ *
+ * @param mm Memory context to flush
+ */
+static void octeon_flush_cache_mm(struct mm_struct *mm)
+{
+ /* According to the R4K version of this file, CPUs without
+ dcache aliases don't need to do anything here */
+}
+
+
+/**
+ * Flush a range of kernel addresses out of the icache
+ *
+ * @param start
+ * @param end
+ */
+static void octeon_flush_icache_range(unsigned long start, unsigned long end)
+{
+ octeon_flush_icache_all_cores(NULL);
+}
+
+
+/**
+ * Flush the icache for a trampoline. These are used for interrupt
+ * and exception hooking.
+ *
+ * @param addr Address to flush
+ */
+static void octeon_flush_cache_sigtramp(unsigned long addr)
+{
+ /* Only flush trampolines on the current core */
+ mb();
+ asm volatile ("synci 0(%0)\n" : : "r" (addr));
+}
+
+
+/**
+ * Flush a range out of a vma
+ *
+ * @param vma VMA to flush
+ * @param start
+ * @param end
+ */
+static void octeon_flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (vma->vm_flags & (VM_EXEC|VM_EXECUTABLE))
+ octeon_flush_icache_all_cores(vma);
+}
+
+
+/**
+ * Flush a specific page of a vma
+ *
+ * @param vma VMA to flush page for
+ * @param page Page to flush
+ * @param pfn
+ */
+static void octeon_flush_cache_page(struct vm_area_struct *vma,
+ unsigned long page, unsigned long pfn)
+{
+ if (vma->vm_flags & (VM_EXEC|VM_EXECUTABLE))
+ octeon_flush_icache_all_cores(vma);
+}
+
+
+/**
+ * Probe Octeon's caches
+ *
+ * @return
+ */
+static void __devinit probe_octeon(void)
+{
+ unsigned long icache_size;
+ unsigned long dcache_size;
+ unsigned int config1;
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
+ switch (c->cputype) {
+ case CPU_CAVIUM_OCTEON:
+ config1 = read_c0_config1();
+ c->icache.linesz = 2 << ((config1 >> 19) & 7);
+ c->icache.sets = 64 << ((config1 >> 22) & 7);
+ c->icache.ways = 1 + ((config1 >> 16) & 7);
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size =
+ c->icache.sets * c->icache.ways * c->icache.linesz;
+ c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
+ c->dcache.linesz = 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ c->dcache.sets = 1; /* CN3XXX has one Dcache set */
+ else
+ c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+ c->dcache.ways = 64;
+ dcache_size =
+ c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+ c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
+ default:
+ panic("Unsupported Cavium Networks CPU type\n");
+ break;
+ }
+
+ /* compute a couple of other cache variables */
+ c->icache.waysize = icache_size / c->icache.ways;
+ c->dcache.waysize = dcache_size / c->dcache.ways;
+
+ c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
+ c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
+
+ if (smp_processor_id() == 0) {
+ pr_notice("Primary instruction cache %ldkB, %s, %d way, "
+ "%d sets, linesize %d bytes.\n",
+ icache_size >> 10,
+ cpu_has_vtag_icache ?
+ "virtually tagged" : "physically tagged",
+ c->icache.ways, c->icache.sets, c->icache.linesz);
+
+ pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
+ "linesize %d bytes.\n",
+ dcache_size >> 10, c->dcache.ways,
+ c->dcache.sets, c->dcache.linesz);
+ }
+}
+
+
+/**
+ * Setup the Octeon cache flush routines
+ *
+ * @return
+ */
+void __devinit octeon_cache_init(void)
+{
+ extern unsigned long ebase;
+ extern char except_vec2_octeon;
+
+ memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
+ octeon_flush_cache_sigtramp(ebase + 0x100);
+
+ probe_octeon();
+
+ shm_align_mask = PAGE_SIZE - 1;
+
+ flush_cache_all = octeon_flush_icache_all;
+ __flush_cache_all = octeon_flush_icache_all;
+ flush_cache_mm = octeon_flush_cache_mm;
+ flush_cache_page = octeon_flush_cache_page;
+ flush_cache_range = octeon_flush_cache_range;
+ flush_cache_sigtramp = octeon_flush_cache_sigtramp;
+ flush_icache_all = octeon_flush_icache_all;
+ flush_data_cache_page = octeon_flush_data_cache_page;
+ flush_icache_range = octeon_flush_icache_range;
+ local_flush_icache_range = local_octeon_flush_icache_range;
+
+ build_clear_page();
+ build_copy_page();
+}
+
+/**
+ * Handle a cache error exception
+ */
+
+static void cache_parity_error_octeon(int non_recoverable)
+{
+ unsigned long coreid = cvmx_get_core_num();
+ uint64_t icache_err = read_c0_cacheerr();
+
+ pr_err("Cache error exception:\n");
+ pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
+ if (icache_err & 1) {
+ pr_err("CacheErr (Icache) == %llx\n",
+ (unsigned long long)icache_err);
+ write_c0_cacheerr(0);
+ }
+ if (cache_err_dcache[coreid] & 1) {
+ pr_err("CacheErr (Dcache) == %llx\n",
+ (unsigned long long)cache_err_dcache[coreid]);
+ cache_err_dcache[coreid] = 0;
+ }
+
+
+ if (non_recoverable)
+ panic("Can't handle cache error: nested exception");
+}
+
+/**
+ * Called when the the exception is not recoverable
+ */
+
+asmlinkage void cache_parity_error_octeon_recoverable(void)
+{
+ cache_parity_error_octeon(0);
+}
+
+/**
+ * Called when the the exception is recoverable
+ */
+
+asmlinkage void cache_parity_error_octeon_non_recoverable(void)
+{
+ cache_parity_error_octeon(1);
+}
+
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
new file mode 100644
index 0000000..3db8553
--- /dev/null
+++ b/arch/mips/mm/cex-oct.S
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Cavium Networks
+ * Cache error handler
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+
+/*
+ * Handle cache error. Indicate to the second level handler whether
+ * the exception is recoverable.
+ */
+ LEAF(except_vec2_octeon)
+
+ .set push
+ .set mips64r2
+ .set noreorder
+ .set noat
+
+
+ /* due to an errata we need to read the COP0 CacheErr (Dcache)
+ * before any cache/DRAM access */
+
+ rdhwr k0, $0 /* get core_id */
+ PTR_LA k1, cache_err_dcache
+ sll k0, k0, 3
+ PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
+
+ dmfc0 k0, CP0_CACHEERR, 1
+ sd k0, (k1)
+ dmtc0 $0, CP0_CACHEERR, 1
+
+ /* check whether this is a nested exception */
+ mfc0 k1, CP0_STATUS
+ andi k1, k1, ST0_EXL
+ beqz k1, 1f
+ nop
+ j cache_parity_error_octeon_non_recoverable
+ nop
+
+ /* exception is recoverable */
+1: j handle_cache_err
+ nop
+
+ .set pop
+ END(except_vec2_octeon)
+
+ /* We need to jump to handle_cache_err so that the previous handler
+ * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
+ * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */
+ LEAF(handle_cache_err)
+ .set push
+ .set noreorder
+ .set noat
+
+ SAVE_ALL
+ KMODE
+ jal cache_parity_error_octeon_recoverable
+ nop
+ j ret_from_exception
+ nop
+
+ .set pop
+ END(handle_cache_err)
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 05/37] Add Cavium OCTEON processor support files to and arch/mips/cavium-octeon/executive
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (3 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 04/37] Add Cavium OCTEON processor support files to arch/mips/mm ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 06/37] Add Cavium OCTEON processor CSR definitions ddaney
` (31 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/cavium-octeon/executive/Makefile | 26 +
arch/mips/cavium-octeon/executive/cvmx-abi.h | 66 ++
arch/mips/cavium-octeon/executive/cvmx-asm.h | 428 +++++++++
arch/mips/cavium-octeon/executive/cvmx-bootinfo.h | 238 +++++
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 946 ++++++++++++++++++++
arch/mips/cavium-octeon/executive/cvmx-bootmem.h | 404 +++++++++
arch/mips/cavium-octeon/executive/cvmx-interrupt.h | 256 ++++++
arch/mips/cavium-octeon/executive/cvmx-l2c.c | 713 +++++++++++++++
arch/mips/cavium-octeon/executive/cvmx-l2c.h | 330 +++++++
.../executive/cvmx-linux-kernel-exports.c | 30 +
arch/mips/cavium-octeon/executive/cvmx-packet.h | 64 ++
arch/mips/cavium-octeon/executive/cvmx-platform.h | 57 ++
arch/mips/cavium-octeon/executive/cvmx-spinlock.h | 376 ++++++++
arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | 113 +++
arch/mips/cavium-octeon/executive/cvmx-sysinfo.h | 145 +++
arch/mips/cavium-octeon/executive/cvmx-warn.c | 45 +
arch/mips/cavium-octeon/executive/cvmx-warn.h | 47 +
arch/mips/cavium-octeon/executive/cvmx.h | 837 +++++++++++++++++
arch/mips/cavium-octeon/executive/octeon-feature.h | 120 +++
arch/mips/cavium-octeon/executive/octeon-model.c | 328 +++++++
arch/mips/cavium-octeon/executive/octeon-model.h | 231 +++++
21 files changed, 5800 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/Makefile
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-abi.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-asm.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootinfo.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-interrupt.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-linux-kernel-exports.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-packet.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-platform.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-spinlock.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-warn.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-warn.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx.h
create mode 100644 arch/mips/cavium-octeon/executive/octeon-feature.h
create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c
create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.h
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
new file mode 100644
index 0000000..cb51c58
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -0,0 +1,26 @@
+#
+# Makefile for the Cavium Octeon specific kernel interface routines
+# under Linux.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License. See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2005-2007 Cavium Networks
+#
+
+
+source:=$(srctree)/$(src)
+EXTRA_CFLAGS += -I$(source) -I$(source)/config
+
+executive-files := cvmx-bootmem.o
+executive-files += cvmx-l2c.o
+executive-files += cvmx-sysinfo.o
+executive-files += cvmx-warn.o
+executive-files += octeon-model.o
+executive-files += cvmx-linux-kernel-exports.o
+obj-y := $(executive-files)
+
+executive-obj-files := $(executive-files:%=$(obj)/%)
+executive-src-files := $(executive-obj-files:%.o=%.c)
+
diff --git a/arch/mips/cavium-octeon/executive/cvmx-abi.h b/arch/mips/cavium-octeon/executive/cvmx-abi.h
new file mode 100644
index 0000000..3e4038b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-abi.h
@@ -0,0 +1,66 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This file defines macros for use in determining the current calling ABI.
+ *
+ * <hr>$Revision: 32636 $<hr>
+*/
+
+#ifndef __CVMX_ABI_H__
+#define __CVMX_ABI_H__
+
+/* Check for N32 ABI, defined for 32-bit Simple Exec applications
+ and Linux N32 ABI.*/
+#if (defined _ABIN32 && _MIPS_SIM == _ABIN32)
+#define CVMX_ABI_N32
+/* Check for N64 ABI, defined for 64-bit Linux toolchain. */
+#elif (defined _ABI64 && _MIPS_SIM == _ABI64)
+#define CVMX_ABI_N64
+/* Check for O32 ABI, defined for Linux 032 ABI, not supported yet. */
+#elif (defined _ABIO32 && _MIPS_SIM == _ABIO32)
+#define CVMX_ABI_O32
+/* Check for EABI ABI, defined for 64-bit Simple Exec applications. */
+#else
+#define CVMX_ABI_EABI
+#endif
+
+#ifndef __BYTE_ORDER
+#if defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
+#define __BYTE_ORDER __BIG_ENDIAN
+#elif !defined(__BIG_ENDIAN) && defined(__LITTLE_ENDIAN)
+#define __BYTE_ORDER __LITTLE_ENDIAN
+#elif !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
+#define __BIG_ENDIAN 4321
+#define __BYTE_ORDER __BIG_ENDIAN
+#else
+#error Unable to determine Endian mode
+#endif
+#endif
+
+#endif /* __CVMX_ABI_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-asm.h b/arch/mips/cavium-octeon/executive/cvmx-asm.h
new file mode 100644
index 0000000..39878c8
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-asm.h
@@ -0,0 +1,428 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This is file defines ASM primitives for the executive.
+
+ * <hr>$Revision: 32636 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_ASM_H__
+#define __CVMX_ASM_H__
+
+#include "octeon-model.h"
+
+/* other useful stuff */
+#define CVMX_BREAK asm volatile ("break")
+#define CVMX_SYNC asm volatile ("sync" : : :"memory")
+/* String version of SYNCW macro for using in inline asm constructs */
+#define CVMX_SYNCW_STR "syncw\nsyncw\n"
+#ifdef __OCTEON__
+#define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */
+#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
+#define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */
+ /* We actually use two syncw instructions in a row when we need a write
+ memory barrier. This is because the CN3XXX series of Octeons have
+ errata Core-401. This can cause a single syncw to not enforce
+ ordering under very rare conditions. Even if it is rare, better safe
+ than sorry */
+#define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory")
+ /* Define new sync instructions to be normal SYNC instructions for
+ operating systems that use threads */
+#define CVMX_SYNCWS CVMX_SYNCW
+#define CVMX_SYNCS CVMX_SYNC
+#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#else
+ /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
+#define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */
+#define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
+#define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */
+#define CVMX_SYNCW asm volatile ("sync" : : :"memory")
+#define CVMX_SYNCWS CVMX_SYNCW
+#define CVMX_SYNCS CVMX_SYNC
+#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#endif
+#define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+#define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
+#define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128)
+/* a normal prefetch */
+#define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset)
+/* normal prefetches that use the pref instruction */
+#define CVMX_PREFETCH_PREF0(address, offset) asm volatile ("pref 0, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+#define CVMX_PREFETCH_PREF1(address, offset) asm volatile ("pref 1, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+#define CVMX_PREFETCH_PREF6(address, offset) asm volatile ("pref 6, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+#define CVMX_PREFETCH_PREF7(address, offset) asm volatile ("pref 7, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+/* prefetch into L1, do not put the block in the L2 */
+#define CVMX_PREFETCH_NOTL2(address, offset) asm volatile ("pref 4, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+#define CVMX_PREFETCH_NOTL22(address, offset) asm volatile ("pref 5, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+/* prefetch into L2, do not put the block in the L1 */
+#define CVMX_PREFETCH_L2(address, offset) asm volatile ("pref 28, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+/* CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable (actually old value or zero) until */
+/* that byte is stored to (by this or another processor. Note that the value of each byte is not only */
+/* unpredictable, but may also change again - up until the point when one of the cores stores to the */
+/* byte. */
+#define CVMX_PREPARE_FOR_STORE(address, offset) asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+/* This is a command headed to the L2 controller to tell it to clear its dirty bit for a */
+/* block. Basically, SW is telling HW that the current version of the block will not be */
+/* used. */
+#define CVMX_DONT_WRITE_BACK(address, offset) asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address))
+
+#define CVMX_ICACHE_INVALIDATE { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } /* flush stores, invalidate entire icache */
+#define CVMX_ICACHE_INVALIDATE2 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } /* flush stores, invalidate entire icache */
+#define CVMX_DCACHE_INVALIDATE { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } /* complete prefetches, invalidate entire dcache */
+
+/* new instruction to make RC4 run faster */
+#define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2))
+
+/* misc v2 stuff */
+#define CVMX_ROTR(result, input1, shiftconst) asm ("rotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1))
+#define CVMX_ROTRV(result, input1, input2) asm ("rotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2))
+#define CVMX_DROTR(result, input1, shiftconst) asm ("drotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1))
+#define CVMX_DROTRV(result, input1, input2) asm ("drotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2))
+#define CVMX_SEB(result, input1) asm ("seb %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_SEH(result, input1) asm ("seh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_DSBH(result, input1) asm ("dsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_DSHD(result, input1) asm ("dshd %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_WSBH(result, input1) asm ("wsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+
+/* Endian swap */
+#define CVMX_ES64(result, input) \
+ do {\
+ CVMX_DSBH(result, input); \
+ CVMX_DSHD(result, result); \
+ } while (0)
+#define CVMX_ES32(result, input) \
+ do {\
+ CVMX_WSBH(result, input); \
+ CVMX_ROTR(result, result, 16); \
+ } while (0)
+
+/* extract and insert - NOTE that pos and len variables must be constants! */
+/* the P variants take len rather than lenm1 */
+/* the M1 variants take lenm1 rather than len */
+#define CVMX_EXTS(result,input,pos,lenm1) asm ("exts %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_EXTSP(result,input,pos,len) CVMX_EXTS(result,input,pos,(len)-1)
+
+#define CVMX_DEXT(result,input,pos,len) asm ("dext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_DEXTM1(result,input,pos,lenm1) CVMX_DEXT(result,input,pos,(lenm1)+1)
+
+#define CVMX_EXT(result,input,pos,len) asm ("ext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_EXTM1(result,input,pos,lenm1) CVMX_EXT(result,input,pos,(lenm1)+1)
+
+/* removed */
+/* #define CVMX_EXTU(result,input,pos,lenm1) asm ("extu %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) */
+/* #define CVMX_EXTUP(result,input,pos,len) CVMX_EXTU(result,input,pos,(len)-1) */
+
+#define CVMX_CINS(result,input,pos,lenm1) asm ("cins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_CINSP(result,input,pos,len) CVMX_CINS(result,input,pos,(len)-1)
+
+#define CVMX_DINS(result,input,pos,len) asm ("dins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result))
+#define CVMX_DINSM1(result,input,pos,lenm1) CVMX_DINS(result,input,pos,(lenm1)+1)
+#define CVMX_DINSC(result,pos,len) asm ("dins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result))
+#define CVMX_DINSCM1(result,pos,lenm1) CVMX_DINSC(result,pos,(lenm1)+1)
+
+#define CVMX_INS(result,input,pos,len) asm ("ins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result))
+#define CVMX_INSM1(result,input,pos,lenm1) CVMX_INS(result,input,pos,(lenm1)+1)
+#define CVMX_INSC(result,pos,len) asm ("ins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result))
+#define CVMX_INSCM1(result,pos,lenm1) CVMX_INSC(result,pos,(lenm1)+1)
+
+/* removed */
+/* #define CVMX_INS0(result,input,pos,lenm1) asm("ins0 %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) */
+/* #define CVMX_INS0P(result,input,pos,len) CVMX_INS0(result,input,pos,(len)-1) */
+/* #define CVMX_INS0C(result,pos,lenm1) asm ("ins0 %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : "[rt]" (result)) */
+/* #define CVMX_INS0CP(result,pos,len) CVMX_INS0C(result,pos,(len)-1) */
+
+#define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DCLZ(result, input) asm ("dclz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_CLO(result, input) asm ("clo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DCLO(result, input) asm ("dclo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_POP(result, input) asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DPOP(result, input) asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+
+/* some new cop0-like stuff */
+#define CVMX_RDHWR(result, regstr) asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#define CVMX_RDHWRNV(result, regstr) asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#define CVMX_DI(result) asm volatile ("di %[rt]" : [rt] "=d" (result))
+#define CVMX_DI_NULL asm volatile ("di")
+#define CVMX_EI(result) asm volatile ("ei %[rt]" : [rt] "=d" (result))
+#define CVMX_EI_NULL asm volatile ("ei")
+#define CVMX_EHB asm volatile ("ehb")
+
+/* mul stuff */
+#define CVMX_MTM0(m) asm volatile ("mtm0 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTM1(m) asm volatile ("mtm1 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTM2(m) asm volatile ("mtm2 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTP0(p) asm volatile ("mtp0 %[rs]" : : [rs] "d" (p))
+#define CVMX_MTP1(p) asm volatile ("mtp1 %[rs]" : : [rs] "d" (p))
+#define CVMX_MTP2(p) asm volatile ("mtp2 %[rs]" : : [rs] "d" (p))
+#define CVMX_VMULU(dest,mpcand,accum) asm volatile ("vmulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+#define CVMX_VMM0(dest,mpcand,accum) asm volatile ("vmm0 %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+#define CVMX_V3MULU(dest,mpcand,accum) asm volatile ("v3mulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+
+/* branch stuff */
+/* these are hard to make work because the compiler does not realize that the */
+/* instruction is a branch so may optimize away the label */
+/* the labels to these next two macros must not include a ":" at the end */
+#define CVMX_BBIT1(var, pos, label) asm volatile ("bbit1 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var))
+#define CVMX_BBIT0(var, pos, label) asm volatile ("bbit0 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var))
+/* the label to this macro must include a ":" at the end */
+#define CVMX_ASM_LABEL(label) label \
+ asm volatile (CVMX_TMP_STR(label) : : )
+
+/* */
+/* Low-latency memory stuff */
+/* */
+/* set can be 0-1 */
+#define CVMX_MT_LLM_READ_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0400+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_WRITE_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0401+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_READ64_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0404+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0405+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_DATA(set,val) asm volatile ("dmtc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MF_LLM_DATA(set,val) asm volatile ("dmfc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : [rt] "=d" (val) : )
+
+/* load linked, store conditional */
+#define CVMX_LL(dest, address, offset) asm volatile ("ll %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address))
+#define CVMX_LLD(dest, address, offset) asm volatile ("lld %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address))
+#define CVMX_SC(srcdest, address, offset) asm volatile ("sc %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+#define CVMX_SCD(srcdest, address, offset) asm volatile ("scd %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+
+/* load/store word left/right */
+#define CVMX_LWR(srcdest, address, offset) asm volatile ("lwr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+#define CVMX_LWL(srcdest, address, offset) asm volatile ("lwl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+#define CVMX_LDR(srcdest, address, offset) asm volatile ("ldr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+#define CVMX_LDL(srcdest, address, offset) asm volatile ("ldl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest))
+
+#define CVMX_SWR(src, address, offset) asm volatile ("swr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src))
+#define CVMX_SWL(src, address, offset) asm volatile ("swl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src))
+#define CVMX_SDR(src, address, offset) asm volatile ("sdr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src))
+#define CVMX_SDL(src, address, offset) asm volatile ("sdl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src))
+
+/* */
+/* Useful crypto ASM's */
+/* */
+
+/* CRC */
+
+#define CVMX_MT_CRC_POLYNOMIAL(val) asm volatile ("dmtc2 %[rt],0x4200" : : [rt] "d" (val))
+#define CVMX_MT_CRC_IV(val) asm volatile ("dmtc2 %[rt],0x0201" : : [rt] "d" (val))
+#define CVMX_MT_CRC_LEN(val) asm volatile ("dmtc2 %[rt],0x1202" : : [rt] "d" (val))
+#define CVMX_MT_CRC_BYTE(val) asm volatile ("dmtc2 %[rt],0x0204" : : [rt] "d" (val))
+#define CVMX_MT_CRC_HALF(val) asm volatile ("dmtc2 %[rt],0x0205" : : [rt] "d" (val))
+#define CVMX_MT_CRC_WORD(val) asm volatile ("dmtc2 %[rt],0x0206" : : [rt] "d" (val))
+#define CVMX_MT_CRC_DWORD(val) asm volatile ("dmtc2 %[rt],0x1207" : : [rt] "d" (val))
+#define CVMX_MT_CRC_VAR(val) asm volatile ("dmtc2 %[rt],0x1208" : : [rt] "d" (val))
+#define CVMX_MT_CRC_POLYNOMIAL_REFLECT(val) asm volatile ("dmtc2 %[rt],0x4210" : : [rt] "d" (val))
+#define CVMX_MT_CRC_IV_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0211" : : [rt] "d" (val))
+#define CVMX_MT_CRC_BYTE_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0214" : : [rt] "d" (val))
+#define CVMX_MT_CRC_HALF_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0215" : : [rt] "d" (val))
+#define CVMX_MT_CRC_WORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0216" : : [rt] "d" (val))
+#define CVMX_MT_CRC_DWORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1217" : : [rt] "d" (val))
+#define CVMX_MT_CRC_VAR_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1218" : : [rt] "d" (val))
+
+#define CVMX_MF_CRC_POLYNOMIAL(val) asm volatile ("dmfc2 %[rt],0x0200" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_IV(val) asm volatile ("dmfc2 %[rt],0x0201" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_IV_REFLECT(val) asm volatile ("dmfc2 %[rt],0x0203" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_LEN(val) asm volatile ("dmfc2 %[rt],0x0202" : [rt] "=d" (val) : )
+
+/* MD5 and SHA-1 */
+
+/* pos can be 0-6 */
+#define CVMX_MT_HSH_DAT(val, pos) asm volatile ("dmtc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+#define CVMX_MT_HSH_DATZ(pos) asm volatile ("dmtc2 $0,0x0040+" CVMX_TMP_STR(pos) : : )
+/* pos can be 0-14 */
+#define CVMX_MT_HSH_DATW(val, pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+#define CVMX_MT_HSH_DATWZ(pos) asm volatile ("dmtc2 $0,0x0240+" CVMX_TMP_STR(pos) : : )
+#define CVMX_MT_HSH_STARTMD5(val) asm volatile ("dmtc2 %[rt],0x4047" : : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA(val) asm volatile ("dmtc2 %[rt],0x4057" : : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA256(val) asm volatile ("dmtc2 %[rt],0x404f" : : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA512(val) asm volatile ("dmtc2 %[rt],0x424f" : : [rt] "d" (val))
+/* pos can be 0-3 */
+#define CVMX_MT_HSH_IV(val, pos) asm volatile ("dmtc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+/* pos can be 0-7 */
+#define CVMX_MT_HSH_IVW(val, pos) asm volatile ("dmtc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+
+/* pos can be 0-6 */
+#define CVMX_MF_HSH_DAT(val, pos) asm volatile ("dmfc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+/* pos can be 0-14 */
+#define CVMX_MF_HSH_DATW(val, pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+/* pos can be 0-3 */
+#define CVMX_MF_HSH_IV(val, pos) asm volatile ("dmfc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+/* pos can be 0-7 */
+#define CVMX_MF_HSH_IVW(val, pos) asm volatile ("dmfc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+
+/* 3DES */
+
+/* pos can be 0-2 */
+#define CVMX_MT_3DES_KEY(val, pos) asm volatile ("dmtc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+#define CVMX_MT_3DES_IV(val) asm volatile ("dmtc2 %[rt],0x0084" : : [rt] "d" (val))
+#define CVMX_MT_3DES_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4088" : : [rt] "d" (val))
+#define CVMX_MT_3DES_ENC(val) asm volatile ("dmtc2 %[rt],0x408a" : : [rt] "d" (val))
+#define CVMX_MT_3DES_DEC_CBC(val) asm volatile ("dmtc2 %[rt],0x408c" : : [rt] "d" (val))
+#define CVMX_MT_3DES_DEC(val) asm volatile ("dmtc2 %[rt],0x408e" : : [rt] "d" (val))
+#define CVMX_MT_3DES_RESULT(val) asm volatile ("dmtc2 %[rt],0x0098" : : [rt] "d" (val))
+
+/* pos can be 0-2 */
+#define CVMX_MF_3DES_KEY(val, pos) asm volatile ("dmfc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+#define CVMX_MF_3DES_IV(val) asm volatile ("dmfc2 %[rt],0x0084" : [rt] "=d" (val) : )
+#define CVMX_MF_3DES_RESULT(val) asm volatile ("dmfc2 %[rt],0x0088" : [rt] "=d" (val) : )
+
+/* KASUMI */
+
+/* pos can be 0-1 */
+#define CVMX_MT_KAS_KEY(val, pos) CVMX_MT_3DES_KEY(val, pos)
+#define CVMX_MT_KAS_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4089" : : [rt] "d" (val))
+#define CVMX_MT_KAS_ENC(val) asm volatile ("dmtc2 %[rt],0x408b" : : [rt] "d" (val))
+#define CVMX_MT_KAS_RESULT(val) CVMX_MT_3DES_RESULT(val)
+
+/* pos can be 0-1 */
+#define CVMX_MF_KAS_KEY(val, pos) CVMX_MF_3DES_KEY(val, pos)
+#define CVMX_MF_KAS_RESULT(val) CVMX_MF_3DES_RESULT(val)
+
+/* AES */
+
+#define CVMX_MT_AES_ENC_CBC0(val) asm volatile ("dmtc2 %[rt],0x0108" : : [rt] "d" (val))
+#define CVMX_MT_AES_ENC_CBC1(val) asm volatile ("dmtc2 %[rt],0x3109" : : [rt] "d" (val))
+#define CVMX_MT_AES_ENC0(val) asm volatile ("dmtc2 %[rt],0x010a" : : [rt] "d" (val))
+#define CVMX_MT_AES_ENC1(val) asm volatile ("dmtc2 %[rt],0x310b" : : [rt] "d" (val))
+#define CVMX_MT_AES_DEC_CBC0(val) asm volatile ("dmtc2 %[rt],0x010c" : : [rt] "d" (val))
+#define CVMX_MT_AES_DEC_CBC1(val) asm volatile ("dmtc2 %[rt],0x310d" : : [rt] "d" (val))
+#define CVMX_MT_AES_DEC0(val) asm volatile ("dmtc2 %[rt],0x010e" : : [rt] "d" (val))
+#define CVMX_MT_AES_DEC1(val) asm volatile ("dmtc2 %[rt],0x310f" : : [rt] "d" (val))
+/* pos can be 0-3 */
+#define CVMX_MT_AES_KEY(val, pos) asm volatile ("dmtc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+/* pos can be 0-1 */
+#define CVMX_MT_AES_IV(val, pos) asm volatile ("dmtc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+#define CVMX_MT_AES_KEYLENGTH(val) asm volatile ("dmtc2 %[rt],0x0110" : : [rt] "d" (val)) /* write the keylen */
+/* pos can be 0-1 */
+#define CVMX_MT_AES_RESULT(val, pos) asm volatile ("dmtc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : : [rt] "d" (val))
+
+/* pos can be 0-1 */
+#define CVMX_MF_AES_RESULT(val, pos) asm volatile ("dmfc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+/* pos can be 0-1 */
+#define CVMX_MF_AES_IV(val, pos) asm volatile ("dmfc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+/* pos can be 0-3 */
+#define CVMX_MF_AES_KEY(val, pos) asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : )
+#define CVMX_MF_AES_KEYLENGTH(val) asm volatile ("dmfc2 %[rt],0x0110" : [rt] "=d" (val) : ) /* read the keylen */
+#define CVMX_MF_AES_DAT0(val) asm volatile ("dmfc2 %[rt],0x0111" : [rt] "=d" (val) : ) /* first piece of input data */
+/* GFM COP2 macros */
+/* index can be 0 or 1 */
+#define CVMX_MF_GFM_MUL(val, index) asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(index) : [rt] "=d" (val) : )
+#define CVMX_MF_GFM_POLY(val) asm volatile ("dmfc2 %[rt],0x025e" : [rt] "=d" (val) : )
+#define CVMX_MF_GFM_RESINP(val, index) asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(index) : [rt] "=d" (val) : )
+
+#define CVMX_MT_GFM_MUL(val, index) asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(index) : : [rt] "d" (val))
+#define CVMX_MT_GFM_POLY(val) asm volatile ("dmtc2 %[rt],0x025e" : : [rt] "d" (val))
+#define CVMX_MT_GFM_RESINP(val, index) asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(index) : : [rt] "d" (val))
+#define CVMX_MT_GFM_XOR0(val) asm volatile ("dmtc2 %[rt],0x025c" : : [rt] "d" (val))
+#define CVMX_MT_GFM_XORMUL1(val) asm volatile ("dmtc2 %[rt],0x425d" : : [rt] "d" (val))
+
+/* check_ordering stuff */
+#if 0
+#define CVMX_MF_CHORD(dest) asm volatile ("dmfc2 %[rt],0x400" : [rt] "=d" (dest) : )
+#else
+#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30)
+#endif
+
+#if 0
+#define CVMX_MF_CYCLE(dest) asm volatile ("dmfc0 %[rt],$9,6" : [rt] "=d" (dest) : ) /* Use (64-bit) CvmCount register rather than Count */
+#else
+#define CVMX_MF_CYCLE(dest) CVMX_RDHWR(dest, 31) /* reads the current (64-bit) CvmCount value */
+#endif
+
+#define CVMX_MT_CYCLE(src) asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src))
+
+#define CVMX_MF_CACHE_ERR(val) asm volatile ("dmfc0 %[rt],$27,0" : [rt] "=d" (val):)
+#define CVMX_MF_DCACHE_ERR(val) asm volatile ("dmfc0 %[rt],$27,1" : [rt] "=d" (val):)
+#define CVMX_MF_CVM_MEM_CTL(val) asm volatile ("dmfc0 %[rt],$11,7" : [rt] "=d" (val):)
+#define CVMX_MF_CVM_CTL(val) asm volatile ("dmfc0 %[rt],$9,7" : [rt] "=d" (val):)
+#define CVMX_MT_CACHE_ERR(val) asm volatile ("dmtc0 %[rt],$27,0" : : [rt] "d" (val))
+#define CVMX_MT_DCACHE_ERR(val) asm volatile ("dmtc0 %[rt],$27,1" : : [rt] "d" (val))
+#define CVMX_MT_CVM_MEM_CTL(val) asm volatile ("dmtc0 %[rt],$11,7" : : [rt] "d" (val))
+#define CVMX_MT_CVM_CTL(val) asm volatile ("dmtc0 %[rt],$9,7" : : [rt] "d" (val))
+
+/* Macros for TLB */
+#define CVMX_TLBWI asm volatile ("tlbwi" : : )
+#define CVMX_TLBWR asm volatile ("tlbwr" : : )
+#define CVMX_TLBR asm volatile ("tlbr" : : )
+#define CVMX_MT_ENTRY_HIGH(val) asm volatile ("dmtc0 %[rt],$10,0" : : [rt] "d" (val))
+#define CVMX_MT_ENTRY_LO_0(val) asm volatile ("dmtc0 %[rt],$2,0" : : [rt] "d" (val))
+#define CVMX_MT_ENTRY_LO_1(val) asm volatile ("dmtc0 %[rt],$3,0" : : [rt] "d" (val))
+#define CVMX_MT_PAGEMASK(val) asm volatile ("mtc0 %[rt],$5,0" : : [rt] "d" (val))
+#define CVMX_MT_PAGEGRAIN(val) asm volatile ("mtc0 %[rt],$5,1" : : [rt] "d" (val))
+#define CVMX_MT_TLB_INDEX(val) asm volatile ("mtc0 %[rt],$0,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_CONTEXT(val) asm volatile ("dmtc0 %[rt],$4,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_WIRED(val) asm volatile ("mtc0 %[rt],$6,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_RANDOM(val) asm volatile ("mtc0 %[rt],$1,0" : : [rt] "d" (val))
+#define CVMX_MF_ENTRY_LO_0(val) asm volatile ("dmfc0 %[rt],$2,0" : [rt] "=d" (val):)
+#define CVMX_MF_ENTRY_LO_1(val) asm volatile ("dmfc0 %[rt],$3,0" : [rt] "=d" (val):)
+#define CVMX_MF_ENTRY_HIGH(val) asm volatile ("dmfc0 %[rt],$10,0" : [rt] "=d" (val):)
+#define CVMX_MF_PAGEMASK(val) asm volatile ("mfc0 %[rt],$5,0" : [rt] "=d" (val):)
+#define CVMX_MF_PAGEGRAIN(val) asm volatile ("mfc0 %[rt],$5,1" : [rt] "=d" (val):)
+#define CVMX_MF_TLB_WIRED(val) asm volatile ("mfc0 %[rt],$6,0" : [rt] "=d" (val):)
+#define CVMX_MF_TLB_RANDOM(val) asm volatile ("mfc0 %[rt],$1,0" : [rt] "=d" (val):)
+#define TLB_DIRTY (0x1ULL<<2)
+#define TLB_VALID (0x1ULL<<1)
+#define TLB_GLOBAL (0x1ULL<<0)
+
+/* assembler macros to guarantee byte loads/stores are used */
+/* for an unaligned 16-bit access (these use AT register) */
+/* we need the hidden argument (__a) so that GCC gets the dependencies right */
+#define CVMX_LOADUNA_INT16(result, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("ulh %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset]), "m"(__a[offset + 1])); }
+#define CVMX_LOADUNA_UINT16(result, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("ulhu %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1])); }
+#define CVMX_STOREUNA_INT16(data, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("ush %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : "=m"(__a[offset + 0]), "=m"(__a[offset + 1]): [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#define CVMX_LOADUNA_INT32(result, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("ulw %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \
+ [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3])); }
+#define CVMX_STOREUNA_INT32(data, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("usw %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \
+ "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]) : \
+ [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#define CVMX_LOADUNA_INT64(result, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("uld %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \
+ [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3]), \
+ "m"(__a[offset + 4]), "m"(__a[offset + 5]), "m"(__a[offset + 6]), "m"(__a[offset + 7])); }
+#define CVMX_STOREUNA_INT64(data, address, offset) \
+ { char *__a = (char *)(address); \
+ asm ("usd %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \
+ "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]), \
+ "=m"(__a[offset + 4]), "=m"(__a[offset + 5]), "=m"(__a[offset + 6]), "=m"(__a[offset + 7]) : \
+ [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootinfo.h b/arch/mips/cavium-octeon/executive/cvmx-bootinfo.h
new file mode 100644
index 0000000..6e2df73
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootinfo.h
@@ -0,0 +1,238 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Header file containing the ABI with the bootloader.
+ *
+ */
+
+#ifndef __CVMX_BOOTINFO_H__
+#define __CVMX_BOOTINFO_H__
+
+/* Current major and minor versions of the CVMX bootinfo block that is
+** passed from the bootloader to the application. This is versioned
+** so that applications can properly handle multiple bootloader
+** versions. */
+#define CVMX_BOOTINFO_MAJ_VER 1
+#define CVMX_BOOTINFO_MIN_VER 2
+
+#if (CVMX_BOOTINFO_MAJ_VER == 1)
+#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
+/* This structure is populated by the bootloader. For binary
+** compatibility the only changes that should be made are
+** adding members to the end of the structure, and the minor
+** version should be incremented at that time.
+** If an incompatible change is made, the major version
+** must be incremented, and the minor version should be reset
+** to 0.
+*/
+typedef struct {
+ uint32_t major_version;
+ uint32_t minor_version;
+
+ uint64_t stack_top;
+ uint64_t heap_base;
+ uint64_t heap_end;
+ uint64_t desc_vaddr;
+
+ uint32_t exception_base_addr;
+ uint32_t stack_size;
+ uint32_t flags;
+ uint32_t core_mask;
+ uint32_t dram_size;
+ /**< DRAM size in megabytes */
+ uint32_t phy_mem_desc_addr;
+ /**< physical address of free memory descriptor block*/
+ uint32_t debugger_flags_base_addr;
+ /**< used to pass flags from app to debugger */
+ uint32_t eclock_hz;
+ /**< CPU clock speed, in hz */
+ uint32_t dclock_hz;
+ /**< DRAM clock speed, in hz */
+ uint32_t reserved0;
+ uint16_t board_type;
+ uint8_t board_rev_major;
+ uint8_t board_rev_minor;
+ uint16_t reserved1;
+ uint8_t reserved2;
+ uint8_t reserved3;
+ char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+ uint8_t mac_addr_base[6];
+ uint8_t mac_addr_count;
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+ /* Several boards support compact flash on the Octeon boot bus. The CF
+ ** memory spaces may be mapped to different addresses on different boards.
+ ** These are the physical addresses, so care must be taken to use the correct
+ ** XKPHYS/KSEG0 addressing depending on the application's ABI.
+ ** These values will be 0 if CF is not present */
+ uint64_t compact_flash_common_base_addr;
+ uint64_t compact_flash_attribute_base_addr;
+ /* Base address of the LED display (as on EBT3000 board)
+ ** This will be 0 if LED display not present. */
+ uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+ uint32_t dfa_ref_clock_hz;
+ /**< DFA reference clock in hz (if applicable)*/
+ uint32_t config_flags;
+ /**< flags indicating various configuration options. These
+ ** flags supercede the 'flags' variable and should be used
+ ** instead if available */
+#endif
+
+} cvmx_bootinfo_t;
+
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
+#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
+#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
+/* This flag is set if the TLB mappings are not contained in the
+** 0x10000000 - 0x20000000 boot bus region. */
+#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
+#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
+
+#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
+
+/* Type defines for board and chip types */
+enum cvmx_board_types_enum {
+ CVMX_BOARD_TYPE_NULL = 0,
+ CVMX_BOARD_TYPE_SIM = 1,
+ CVMX_BOARD_TYPE_EBT3000 = 2,
+ CVMX_BOARD_TYPE_KODAMA = 3,
+ CVMX_BOARD_TYPE_NIAGARA = 4,
+ CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
+ CVMX_BOARD_TYPE_THUNDER = 6,
+ CVMX_BOARD_TYPE_TRANTOR = 7,
+ CVMX_BOARD_TYPE_EBH3000 = 8,
+ CVMX_BOARD_TYPE_EBH3100 = 9,
+ CVMX_BOARD_TYPE_HIKARI = 10,
+ CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
+ CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
+ CVMX_BOARD_TYPE_KBP = 13,
+ CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
+ CVMX_BOARD_TYPE_EBT5800 = 15,
+ CVMX_BOARD_TYPE_NICPRO2 = 16,
+ CVMX_BOARD_TYPE_EBH5600 = 17,
+ CVMX_BOARD_TYPE_EBH5601 = 18,
+ CVMX_BOARD_TYPE_EBH5200 = 19,
+ CVMX_BOARD_TYPE_BBGW_REF = 20,
+ CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
+ CVMX_BOARD_TYPE_EBT5600 = 22,
+ CVMX_BOARD_TYPE_EBH5201 = 23,
+ CVMX_BOARD_TYPE_MAX,
+
+ /* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
+ ** for future SDK use. */
+
+ /* Set aside a range for customer boards. These numbers are managed
+ ** by Cavium.
+ */
+ CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
+ CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
+ CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
+ CVMX_BOARD_TYPE_CUST_NB5 = 10003,
+ CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
+ CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
+
+ /* Set aside a range for customer private use. The SDK won't
+ ** use any numbers in this range. */
+ CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
+ CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
+
+ /* The remaining range is reserved for future use. */
+};
+enum cvmx_chip_types_enum {
+ CVMX_CHIP_TYPE_NULL = 0,
+ CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
+ CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
+ CVMX_CHIP_TYPE_MAX,
+};
+
+/* Compatability alias for NAC38 name change, planned to be removed from SDK 1.7 */
+#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
+
+/* Functions to return string based on type */
+#define ENUM_BRD_TYPE_CASE(x) case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
+static inline const char *cvmx_board_type_to_string(enum
+ cvmx_board_types_enum type)
+{
+ switch (type) {
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
+
+ /* Customer boards listed here */
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
+
+ /* Customer private range */
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
+ }
+ return "Unsupported Board";
+}
+
+#define ENUM_CHIP_TYPE_CASE(x) case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
+static inline const char *cvmx_chip_type_to_string(enum
+ cvmx_chip_types_enum type)
+{
+ switch (type) {
+ ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
+ ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+ ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+ ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+ }
+ return "Unsupported Chip";
+}
+
+#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
new file mode 100644
index 0000000..b6c4dab
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -0,0 +1,946 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Simple allocate only memory allocator. Used to allocate memory at application
+ * start time.
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-bootmem.h"
+
+/*#define DEBUG */
+
+#undef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+#undef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+#define ALIGN_ADDR_UP(addr, align) (((addr) + (~(align))) & (align))
+
+static cvmx_bootmem_desc_t *cvmx_bootmem_desc;
+
+/* See header file for descriptions of functions */
+
+/* Wrapper functions are provided for reading/writing the size and
+ * next block values as these may not be directly addressible (in 32
+ * bit applications, for instance.) Offsets of data elements in
+ * bootmem list, must match cvmx_bootmem_block_header_t */
+#define NEXT_OFFSET 0
+#define SIZE_OFFSET 8
+static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size)
+{
+ cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size);
+}
+
+static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next)
+{
+ cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next);
+}
+
+static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr)
+{
+ return cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63));
+}
+
+static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr)
+{
+ return cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63));
+}
+
+void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
+ uint64_t min_addr, uint64_t max_addr)
+{
+ int64_t address;
+ address =
+ cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0);
+
+ if (address > 0)
+ return cvmx_phys_to_ptr(address);
+ else
+ return NULL;
+}
+
+void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
+ uint64_t alignment)
+{
+ return cvmx_bootmem_alloc_range(size, alignment, address,
+ address + size);
+}
+
+void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
+{
+ return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
+}
+
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr, uint64_t align,
+ char *name)
+{
+ int64_t addr;
+
+ addr =
+ cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align,
+ name, 0);
+ if (addr >= 0)
+ return cvmx_phys_to_ptr(addr);
+ else
+ return NULL;
+
+}
+
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+ char *name)
+{
+ return cvmx_bootmem_alloc_named_range (size, address,
+ address + size, 0, name);
+}
+
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+{
+ return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
+}
+
+int cvmx_bootmem_free_named(char *name)
+{
+ return cvmx_bootmem_phy_named_block_free(name, 0);
+}
+
+cvmx_bootmem_named_block_desc_t *cvmx_bootmem_find_named_block(char *name)
+{
+ return cvmx_bootmem_phy_named_block_find(name, 0);
+}
+
+void cvmx_bootmem_print_named(void)
+{
+ cvmx_bootmem_phy_named_block_print();
+}
+
+#if defined(CVMX_ABI_N32)
+cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+#endif
+
+int cvmx_bootmem_init(void *mem_desc_ptr)
+{
+ /* Verify that the size of cvmx_spinlock_t meets our assumptions */
+ if (sizeof(cvmx_spinlock_t) != 4) {
+ cvmx_dprintf("ERROR: Unexpected size of cvmx_spinlock_t\n");
+ return -1;
+ }
+
+ /* Here we set the global pointer to the bootmem descriptor block. This pointer will
+ ** be used directly, so we will set it up to be directly usable by the application.
+ ** It is set up as follows for the various runtime/ABI combinations:
+ ** Linux 64 bit: Set XKPHYS bit
+ ** Linux 32 bit: use mmap to create mapping, use virtual address
+ ** CVMX 64 bit: use physical address directly
+ ** CVMX 32 bit: use physical address directly
+ ** Note that the CVMX environment assumes the use of 1-1 TLB mappings so that the physical addresses
+ ** can be used directly
+ */
+ if (!cvmx_bootmem_desc) {
+#if defined(CVMX_ABI_64)
+ /* Set XKPHYS bit */
+ cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr));
+#else
+ cvmx_bootmem_desc = (cvmx_bootmem_desc_t *) mem_desc_ptr;
+#endif
+ }
+
+ return 0;
+}
+
+uint64_t cvmx_bootmem_available_mem(uint64_t min_block_size)
+{
+ return cvmx_bootmem_phy_available_mem(min_block_size);
+}
+
+/*********************************************************************
+** The cvmx_bootmem_phy* functions below return 64 bit physical addresses,
+** and expose more features that the cvmx_bootmem_functions above. These are
+** required for full memory space access in 32 bit applications, as well as for
+** using some advance features.
+** Most applications should not need to use these.
+**
+**/
+
+int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
+ uint64_t address_max, uint64_t alignment,
+ uint32_t flags)
+{
+
+ uint64_t head_addr;
+ uint64_t ent_addr;
+ uint64_t prev_addr = 0; /* points to previous list entry, NULL current entry is head of list */
+ uint64_t new_ent_addr = 0;
+ uint64_t desired_min_addr;
+ uint64_t alignment_mask = ~(alignment - 1);
+
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_alloc: req_size: 0x%llx, min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n",
+ (unsigned long long)req_size, (unsigned long long)address_min,
+ (unsigned long long)address_max, (unsigned long long)alignment);
+#endif
+
+ if (cvmx_bootmem_desc->major_version > 3) {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ goto error_out;
+ }
+
+ /* Do a variety of checks to validate the arguments. The
+ * allocator code will later assume that these checks have
+ * been made. We validate that the requested constraints are
+ * not self-contradictory before we look through the list of
+ * available memory
+ */
+
+ /* 0 is not a valid req_size for this allocator */
+ if (!req_size)
+ goto error_out;
+
+ /* Round req_size up to mult of minimum alignment bytes */
+ req_size =
+ (req_size +
+ (CVMX_BOOTMEM_ALIGNMENT_SIZE -
+ 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
+
+ /* Convert !0 address_min and 0 address_max to special case of
+ * range that specifies an exact memory block to allocate.
+ * Do this before other checks and adjustments so that this
+ * tranformation will be validated */
+ if (address_min && !address_max)
+ address_max = address_min + req_size;
+ else if (!address_min && !address_max)
+ address_max = ~0ull; /* If no limits given, use max limits */
+
+#if defined(CVMX_ABI_N32) && !defined(CONFIG_OCTEON_U_BOOT)
+ {
+ extern uint64_t linux_mem32_min;
+ extern uint64_t linux_mem32_max;
+ cvmx_dprintf("min: 0x%llx, max: 0x%llx\n", linux_mem32_min,
+ linux_mem32_max);
+ /* For 32 bit Linux apps, we need to restrict the
+ * allocations to the range of memory configured for
+ * access from userspace. Also, we need to add
+ * mappings for the data structures that we access.*/
+
+ /* Reject specific location requests that are not fully within bounds */
+ if (req_size == address_max - address_min
+ &&
+ ((address_min > linux_mem32_max
+ || address_min < linux_mem32_min)))
+ goto error_out;
+
+ /* Narrow range requests to be bounded by the 32 bit
+ * limits. octeon_phy_mem_block_alloc() will reject
+ * inconsistent req_size/range requests, so we don't
+ * repeat those checks here. If max unspecified, set
+ * to 32 bit maximum. */
+ address_min =
+ MIN(MAX(address_min, linux_mem32_min), linux_mem32_max);
+ if (!address_max)
+ address_max = linux_mem32_max;
+ else
+ address_max =
+ MAX(MIN(address_max, linux_mem32_max),
+ linux_mem32_min);
+ }
+#endif
+
+ /* Enforce minimum alignment (this also keeps the minimum free block
+ ** req_size the same as the alignment req_size */
+ if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE) {
+ alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE;
+ }
+ alignment_mask = ~(alignment - 1);
+
+ /* Adjust address minimum based on requested alignment (round
+ * up to meet alignment). Do this here so we can reject
+ * impossible requests up front. (NOP for address_min ==
+ * 0) */
+ if (alignment)
+ address_min =
+ (address_min + (alignment - 1)) & ~(alignment - 1);
+
+ /* Reject inconsistent args. We have adjusted these, so this
+ * may fail due to our internal changes even if this check
+ * would pass for the values the user supplied. */
+ if (req_size > address_max - address_min)
+ goto error_out;
+
+ /* Walk through the list entries - first fit found is returned */
+
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+ head_addr = cvmx_bootmem_desc->head_addr;
+ ent_addr = head_addr;
+ while (ent_addr) {
+ uint64_t usable_base, usable_max;
+ uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr);
+
+ if (cvmx_bootmem_phy_get_next(ent_addr)
+ && ent_addr > cvmx_bootmem_phy_get_next(ent_addr)) {
+ cvmx_dprintf
+ ("Internal bootmem_alloc() error: ent: 0x%llx, next: 0x%llx\n",
+ (unsigned long long)ent_addr, (unsigned long long)
+ cvmx_bootmem_phy_get_next(ent_addr));
+ goto error_out;
+ }
+
+ /* Determine if this is an entry that can satisify the request */
+ /* Check to make sure entry is large enough to satisfy request */
+ usable_base =
+ ALIGN_ADDR_UP(MAX(address_min, ent_addr), alignment_mask);
+ usable_max = MIN(address_max, ent_addr + ent_size);
+ /* We should be able to allocate block at address usable_base */
+
+ desired_min_addr = usable_base;
+
+ /* Determine if request can be satisfied from the current entry */
+ if ((((ent_addr + ent_size) > usable_base
+ && ent_addr < address_max))
+ && req_size <= usable_max - usable_base) {
+ /* We have found an entry that has room to satisfy the request, so allocate it from this entry */
+
+ /* If end CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from the end of this block
+ ** rather than the beginning */
+ if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC) {
+ desired_min_addr = usable_max - req_size;
+ /* Align desired address down to required alignment */
+ desired_min_addr &= alignment_mask;
+ }
+
+ /* Match at start of entry */
+ if (desired_min_addr == ent_addr) {
+ if (req_size < ent_size) {
+ /* big enough to create a new block from top portion of block */
+ new_ent_addr = ent_addr + req_size;
+ cvmx_bootmem_phy_set_next(new_ent_addr,
+ cvmx_bootmem_phy_get_next
+ (ent_addr));
+ cvmx_bootmem_phy_set_size(new_ent_addr,
+ ent_size -
+ req_size);
+
+ /* Adjust next pointer as following code uses this */
+ cvmx_bootmem_phy_set_next(ent_addr,
+ new_ent_addr);
+ }
+
+ /* adjust prev ptr or head to remove this entry from list */
+ if (prev_addr) {
+ cvmx_bootmem_phy_set_next(prev_addr,
+ cvmx_bootmem_phy_get_next
+ (ent_addr));
+ } else {
+ /* head of list being returned, so update head ptr */
+ cvmx_bootmem_desc->head_addr =
+ cvmx_bootmem_phy_get_next(ent_addr);
+ }
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *)
+ &
+ (cvmx_bootmem_desc->lock));
+ return desired_min_addr;
+ }
+
+ /* block returned doesn't start at beginning
+ * of entry, so we know that we will be
+ * splitting a block off the front of this
+ * one. Create a new block from the
+ * beginning, add to list, and go to top of
+ * loop again.
+ *
+ * create new block from high portion of
+ * block, so that top block starts at desired
+ * addr
+ **/
+ new_ent_addr = desired_min_addr;
+ cvmx_bootmem_phy_set_next(new_ent_addr,
+ cvmx_bootmem_phy_get_next
+ (ent_addr));
+ cvmx_bootmem_phy_set_size(new_ent_addr,
+ cvmx_bootmem_phy_get_size
+ (ent_addr) -
+ (desired_min_addr -
+ ent_addr));
+ cvmx_bootmem_phy_set_size(ent_addr,
+ desired_min_addr - ent_addr);
+ cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr);
+ /* Loop again to handle actual alloc from new block */
+ }
+
+ prev_addr = ent_addr;
+ ent_addr = cvmx_bootmem_phy_get_next(ent_addr);
+ }
+error_out:
+ /* We didn't find anything, so return error */
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+ return -1;
+}
+
+int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
+{
+ uint64_t cur_addr;
+ uint64_t prev_addr = 0; /* zero is invalid */
+ int retval = 0;
+
+#ifdef DEBUG
+ cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n",
+ (unsigned long long)phy_addr, (unsigned long long)size);
+#endif
+ if (cvmx_bootmem_desc->major_version > 3) {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ return 0;
+ }
+
+ /* 0 is not a valid size for this allocator */
+ if (!size)
+ return 0;
+
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+ cur_addr = cvmx_bootmem_desc->head_addr;
+ if (cur_addr == 0 || phy_addr < cur_addr) {
+ /* add at front of list - special case with changing head ptr */
+ if (cur_addr && phy_addr + size > cur_addr)
+ goto bootmem_free_done; /* error, overlapping section */
+ else if (phy_addr + size == cur_addr) {
+ /* Add to front of existing first block */
+ cvmx_bootmem_phy_set_next(phy_addr,
+ cvmx_bootmem_phy_get_next
+ (cur_addr));
+ cvmx_bootmem_phy_set_size(phy_addr,
+ cvmx_bootmem_phy_get_size
+ (cur_addr) + size);
+ cvmx_bootmem_desc->head_addr = phy_addr;
+
+ } else {
+ /* New block before first block */
+ cvmx_bootmem_phy_set_next(phy_addr, cur_addr); /* OK if cur_addr is 0 */
+ cvmx_bootmem_phy_set_size(phy_addr, size);
+ cvmx_bootmem_desc->head_addr = phy_addr;
+ }
+ retval = 1;
+ goto bootmem_free_done;
+ }
+
+ /* Find place in list to add block */
+ while (cur_addr && phy_addr > cur_addr) {
+ prev_addr = cur_addr;
+ cur_addr = cvmx_bootmem_phy_get_next(cur_addr);
+ }
+
+ if (!cur_addr) {
+ /* We have reached the end of the list, add on to end, checking
+ ** to see if we need to combine with last block
+ **/
+ if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
+ phy_addr) {
+ cvmx_bootmem_phy_set_size(prev_addr,
+ cvmx_bootmem_phy_get_size
+ (prev_addr) + size);
+ } else {
+ cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+ cvmx_bootmem_phy_set_size(phy_addr, size);
+ cvmx_bootmem_phy_set_next(phy_addr, 0);
+ }
+ retval = 1;
+ goto bootmem_free_done;
+ } else {
+ /* insert between prev and cur nodes, checking for merge with either/both */
+
+ if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
+ phy_addr) {
+ /* Merge with previous */
+ cvmx_bootmem_phy_set_size(prev_addr,
+ cvmx_bootmem_phy_get_size
+ (prev_addr) + size);
+ if (phy_addr + size == cur_addr) {
+ /* Also merge with current */
+ cvmx_bootmem_phy_set_size(prev_addr,
+ cvmx_bootmem_phy_get_size
+ (cur_addr) +
+ cvmx_bootmem_phy_get_size
+ (prev_addr));
+ cvmx_bootmem_phy_set_next(prev_addr,
+ cvmx_bootmem_phy_get_next
+ (cur_addr));
+ }
+ retval = 1;
+ goto bootmem_free_done;
+ } else if (phy_addr + size == cur_addr) {
+ /* Merge with current */
+ cvmx_bootmem_phy_set_size(phy_addr,
+ cvmx_bootmem_phy_get_size
+ (cur_addr) + size);
+ cvmx_bootmem_phy_set_next(phy_addr,
+ cvmx_bootmem_phy_get_next
+ (cur_addr));
+ cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+ retval = 1;
+ goto bootmem_free_done;
+ }
+
+ /* It is a standalone block, add in between prev and cur */
+ cvmx_bootmem_phy_set_size(phy_addr, size);
+ cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
+ cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+
+ }
+ retval = 1;
+
+bootmem_free_done:
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+ return retval;
+
+}
+
+void cvmx_bootmem_phy_list_print(void)
+{
+ uint64_t addr;
+
+ addr = cvmx_bootmem_desc->head_addr;
+ cvmx_dprintf
+ ("\n\n\nPrinting bootmem block list, descriptor: %p, head is 0x%llx\n",
+ cvmx_bootmem_desc, (unsigned long long)addr);
+ cvmx_dprintf("Descriptor version: %d.%d\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version);
+ if (cvmx_bootmem_desc->major_version > 3) {
+ cvmx_dprintf
+ ("Warning: Bootmem descriptor version is newer than expected\n");
+ }
+ if (!addr) {
+ cvmx_dprintf("mem list is empty!\n");
+ }
+ while (addr) {
+ cvmx_dprintf
+ ("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
+ (unsigned long long)addr,
+ (unsigned long long)cvmx_bootmem_phy_get_size(addr),
+ (unsigned long long)cvmx_bootmem_phy_get_next(addr));
+ addr = cvmx_bootmem_phy_get_next(addr);
+ }
+ cvmx_dprintf("\n\n");
+
+}
+
+uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size)
+{
+ uint64_t addr;
+
+ uint64_t available_mem = 0;
+
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+ addr = cvmx_bootmem_desc->head_addr;
+ while (addr) {
+ if (cvmx_bootmem_phy_get_size(addr) >= min_block_size)
+ available_mem += cvmx_bootmem_phy_get_size(addr);
+ addr = cvmx_bootmem_phy_get_next(addr);
+ }
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+ return available_mem;
+
+}
+
+cvmx_bootmem_named_block_desc_t *cvmx_bootmem_phy_named_block_find(char *name,
+ uint32_t
+ flags)
+{
+ unsigned int i;
+ cvmx_bootmem_named_block_desc_t *named_block_array_ptr;
+
+#ifdef DEBUG
+ cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name);
+#endif
+ /* Lock the structure to make sure that it is not being
+ * changed while we are examining it.
+ */
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+
+#if !defined(CONFIG_OCTEON_U_BOOT)
+#ifdef CVMX_ABI_N32
+ /* Need to use mmapped named block pointer in 32 bit linux apps */
+ extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+ named_block_array_ptr = linux32_named_block_array_ptr;
+#else
+ /* Use XKPHYS for 64 bit linux */
+ named_block_array_ptr = (cvmx_bootmem_named_block_desc_t *)
+ cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
+#endif
+#else
+ /* Simple executive case. (and u-boot) This could be in the
+ * low 1 meg of memory that is not 1-1 mapped, so we need use
+ * XKPHYS/KSEG0 addressing for it */
+ named_block_array_ptr =
+ CASTPTR(cvmx_bootmem_named_block_desc_t,
+ CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
+ cvmx_bootmem_desc->named_block_array_addr));
+#endif
+
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n",
+ named_block_array_ptr);
+#endif
+ if (cvmx_bootmem_desc->major_version == 3) {
+ for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++) {
+ if ((name && named_block_array_ptr[i].size
+ && !strncmp(name, named_block_array_ptr[i].name,
+ cvmx_bootmem_desc->named_block_name_len
+ - 1))
+ || (!name && !named_block_array_ptr[i].size)) {
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *)
+ &
+ (cvmx_bootmem_desc->lock));
+
+ return &(named_block_array_ptr[i]);
+ }
+ }
+ } else {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ }
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+
+ return NULL;
+}
+
+int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
+{
+ cvmx_bootmem_named_block_desc_t *named_block_ptr;
+
+ if (cvmx_bootmem_desc->major_version != 3) {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ return 0;
+ }
+#ifdef DEBUG
+ cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name);
+#endif
+
+ /* Take lock here, as name lookup/block free/name free need to be atomic */
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+
+ named_block_ptr =
+ cvmx_bootmem_phy_named_block_find(name,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+ if (named_block_ptr) {
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_named_block_free: %s, base: 0x%llx, size: 0x%llx\n",
+ name, (unsigned long long)named_block_ptr->base_addr,
+ (unsigned long long)named_block_ptr->size);
+#endif
+ __cvmx_bootmem_phy_free(named_block_ptr->base_addr,
+ named_block_ptr->size,
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+ named_block_ptr->size = 0;
+ /* Set size to zero to indicate block not used. */
+ }
+
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+
+ return named_block_ptr != NULL; /* 0 on failure, 1 on success */
+}
+
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+ uint64_t max_addr,
+ uint64_t alignment, char *name,
+ uint32_t flags)
+{
+ int64_t addr_allocated;
+ cvmx_bootmem_named_block_desc_t *named_block_desc_ptr;
+
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: 0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
+ (unsigned long long)size, (unsigned long long)min_addr,
+ (unsigned long long)max_addr, (unsigned long long)alignment, name);
+#endif
+ if (cvmx_bootmem_desc->major_version != 3) {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ return -1;
+ }
+
+ /* Take lock here, as name lookup/block alloc/name add need to be atomic */
+
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+
+ /* Get pointer to first available named block descriptor */
+ named_block_desc_ptr =
+ cvmx_bootmem_phy_named_block_find(NULL,
+ flags |
+ CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+ /* Check to see if name already in use, return error if name
+ ** not available or no more room for blocks.
+ */
+ if (cvmx_bootmem_phy_named_block_find
+ (name, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING)
+ || !named_block_desc_ptr) {
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+ return -1;
+ }
+
+ /* Round size up to mult of minimum alignment bytes
+ ** We need the actual size allocated to allow for blocks to be coallesced
+ ** when they are freed. The alloc routine does the same rounding up
+ ** on all allocations. */
+ size =
+ (size +
+ (CVMX_BOOTMEM_ALIGNMENT_SIZE -
+ 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
+
+ addr_allocated =
+ cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment,
+ flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+ if (addr_allocated >= 0) {
+ named_block_desc_ptr->base_addr = addr_allocated;
+ named_block_desc_ptr->size = size;
+ strncpy(named_block_desc_ptr->name, name,
+ cvmx_bootmem_desc->named_block_name_len);
+ named_block_desc_ptr->
+ name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+ }
+
+ if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &
+ (cvmx_bootmem_desc->lock));
+
+ return addr_allocated;
+}
+
+void cvmx_bootmem_phy_named_block_print(void)
+{
+ unsigned int i;
+ int printed = 0;
+
+#if !defined(CONFIG_OCTEON_U_BOOT)
+#ifdef CVMX_ABI_N32
+ /* Need to use mmapped named block pointer in 32 bit linux apps */
+ extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+ cvmx_bootmem_named_block_desc_t *named_block_array_ptr =
+ linux32_named_block_array_ptr;
+#else
+ /* Use XKPHYS for 64 bit linux */
+ cvmx_bootmem_named_block_desc_t *named_block_array_ptr =
+ (cvmx_bootmem_named_block_desc_t *)
+ cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
+#endif
+#else
+ /* Simple executive case. (and u-boot)
+ ** This could be in the low 1 meg of memory that is not 1-1 mapped, so we need use XKPHYS/KSEG0 addressing for it */
+ cvmx_bootmem_named_block_desc_t *named_block_array_ptr =
+ CASTPTR(cvmx_bootmem_named_block_desc_t,
+ CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
+ cvmx_bootmem_desc->named_block_array_addr));
+#endif
+#ifdef DEBUG
+ cvmx_dprintf("cvmx_bootmem_phy_named_block_print, desc addr: %p\n",
+ cvmx_bootmem_desc);
+#endif
+ if (cvmx_bootmem_desc->major_version != 3) {
+ cvmx_dprintf
+ ("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+ (int)cvmx_bootmem_desc->major_version,
+ (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+ return;
+ }
+ cvmx_dprintf("List of currently allocated named bootmem blocks:\n");
+ for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++) {
+ if (named_block_array_ptr[i].size) {
+ printed++;
+ cvmx_dprintf
+ ("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
+ named_block_array_ptr[i].name,
+ (unsigned long long)
+ named_block_array_ptr[i].base_addr,
+ (unsigned long long)named_block_array_ptr[i].size,
+ i);
+
+ }
+ }
+ if (!printed) {
+ cvmx_dprintf("No named bootmem blocks exist.\n");
+ }
+
+}
+
+/* Real physical addresses of memory regions */
+#define OCTEON_DDR0_BASE (0x0ULL)
+#define OCTEON_DDR0_SIZE (0x010000000ULL)
+#define OCTEON_DDR1_BASE (0x410000000ULL)
+#define OCTEON_DDR1_SIZE (0x010000000ULL)
+#define OCTEON_DDR2_BASE (0x020000000ULL)
+#define OCTEON_DDR2_SIZE (0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
+int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size,
+ uint32_t low_reserved_bytes,
+ cvmx_bootmem_desc_t *desc_buffer)
+{
+ uint64_t cur_block_addr;
+ int64_t addr;
+
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_mem_list_init (arg desc ptr: %p, cvmx_bootmem_desc: %p)\n",
+ desc_buffer, cvmx_bootmem_desc);
+#endif
+
+ /* Descriptor buffer needs to be in 32 bit addressable space to be compatible with
+ ** 32 bit applications */
+ if (!desc_buffer) {
+ cvmx_dprintf
+ ("ERROR: no memory for cvmx_bootmem descriptor provided\n");
+ return 0;
+ }
+
+ if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
+ mem_size = OCTEON_MAX_PHY_MEM_SIZE;
+ cvmx_dprintf
+ ("ERROR: requested memory size too large, truncating to maximum size\n");
+ }
+
+ if (cvmx_bootmem_desc)
+ return 1;
+
+ /* Initialize cvmx pointer to descriptor */
+ cvmx_bootmem_init(desc_buffer);
+
+ /* Set up global pointer to start of list, exclude low 64k for exception vectors, space for global descriptor */
+ memset(cvmx_bootmem_desc, 0x0, sizeof(cvmx_bootmem_desc_t));
+ /* Set version of bootmem descriptor */
+ cvmx_bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
+ cvmx_bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
+
+ cur_block_addr = cvmx_bootmem_desc->head_addr =
+ (OCTEON_DDR0_BASE + low_reserved_bytes);
+
+ cvmx_bootmem_desc->head_addr = 0;
+
+ if (mem_size <= OCTEON_DDR0_SIZE) {
+ __cvmx_bootmem_phy_free(cur_block_addr,
+ mem_size - low_reserved_bytes, 0);
+ goto frees_done;
+ }
+
+ __cvmx_bootmem_phy_free(cur_block_addr,
+ OCTEON_DDR0_SIZE - low_reserved_bytes, 0);
+
+ mem_size -= OCTEON_DDR0_SIZE;
+
+ /* Add DDR2 block next if present */
+ if (mem_size > OCTEON_DDR1_SIZE) {
+ __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
+ __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
+ mem_size - OCTEON_DDR1_SIZE, 0);
+ } else {
+ __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
+
+ }
+frees_done:
+
+ /* Initialize the named block structure */
+ cvmx_bootmem_desc->named_block_name_len = CVMX_BOOTMEM_NAME_LEN;
+ cvmx_bootmem_desc->named_block_num_blocks =
+ CVMX_BOOTMEM_NUM_NAMED_BLOCKS;
+ cvmx_bootmem_desc->named_block_array_addr = 0;
+
+ /* Allocate this near the top of the low 256 MBytes of memory */
+ addr =
+ cvmx_bootmem_phy_alloc(CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
+ sizeof(cvmx_bootmem_named_block_desc_t), 0,
+ 0x10000000, 0, CVMX_BOOTMEM_FLAG_END_ALLOC);
+ if (addr >= 0)
+ cvmx_bootmem_desc->named_block_array_addr = addr;
+
+#ifdef DEBUG
+ cvmx_dprintf
+ ("cvmx_bootmem_phy_mem_list_init: named_block_array_addr: 0x%llx)\n",
+ (unsigned long long)cvmx_bootmem_desc->named_block_array_addr);
+#endif
+ if (!cvmx_bootmem_desc->named_block_array_addr) {
+ cvmx_dprintf
+ ("FATAL ERROR: unable to allocate memory for bootmem descriptor!\n");
+ return 0;
+ }
+ memset((void *)(unsigned long)cvmx_bootmem_desc->named_block_array_addr,
+ 0x0,
+ CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
+ sizeof(cvmx_bootmem_named_block_desc_t));
+
+ return 1;
+}
+
+void cvmx_bootmem_lock(void)
+{
+ cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+}
+
+void cvmx_bootmem_unlock(void)
+{
+ cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
+}
+
+void *__cvmx_bootmem_internal_get_desc_ptr(void)
+{
+ return cvmx_bootmem_desc;
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.h b/arch/mips/cavium-octeon/executive/cvmx-bootmem.h
new file mode 100644
index 0000000..61f7644
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.h
@@ -0,0 +1,404 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Simple allocate only memory allocator. Used to allocate memory at application
+ * start time.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ *
+ */
+
+#ifndef __CVMX_BOOTMEM_H__
+#define __CVMX_BOOTMEM_H__
+
+#define CVMX_BOOTMEM_NAME_LEN 128 /* Must be multiple of 8, changing breaks ABI */
+#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 /* Can change without breaking ABI */
+#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) /* minimum alignment of bootmem alloced blocks */
+
+/* Flags for cvmx_bootmem_phy_mem* functions */
+#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0) /* Allocate from end of block instead of beginning */
+#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1) /* Don't do any locking. */
+
+/* First bytes of each free physical block of memory contain this structure,
+ * which is used to maintain the free memory list. Since the bootloader is
+ * only 32 bits, there is a union providing 64 and 32 bit versions. The
+ * application init code converts addresses to 64 bit addresses before the
+ * application starts.
+ */
+typedef struct {
+ /* Note: these are referenced from assembly routines in the bootloader, so this structure
+ ** should not be changed without changing those routines as well. */
+ uint64_t next_block_addr;
+ uint64_t size;
+
+} cvmx_bootmem_block_header_t;
+
+/* Structure for named memory blocks
+** Number of descriptors
+** available can be changed without affecting compatiblity,
+** but name length changes require a bump in the bootmem
+** descriptor version
+** Note: This structure must be naturally 64 bit aligned, as a single
+** memory image will be used by both 32 and 64 bit programs.
+*/
+typedef struct {
+ uint64_t base_addr;
+ /**< Base address of named block */
+ uint64_t size;
+ /**< Size actually allocated for named block (may differ from requested) */
+ char name[CVMX_BOOTMEM_NAME_LEN];
+ /**< name of named block */
+} cvmx_bootmem_named_block_desc_t;
+
+/* Current descriptor versions */
+#define CVMX_BOOTMEM_DESC_MAJ_VER 3 /* CVMX bootmem descriptor major version */
+#define CVMX_BOOTMEM_DESC_MIN_VER 0 /* CVMX bootmem descriptor minor version */
+
+/* First three members of cvmx_bootmem_desc_t are left in original
+** positions for backwards compatibility.
+*/
+typedef struct {
+ uint32_t lock;
+ /**< spinlock to control access to list */
+ uint32_t flags;
+ /**< flags for indicating various conditions */
+ uint64_t head_addr;
+
+ uint32_t major_version;
+ /**< incremented changed when incompatible changes made */
+ uint32_t minor_version;
+ /**< incremented changed when compatible changes made, reset to zero when major incremented */
+ uint64_t app_data_addr;
+ uint64_t app_data_size;
+
+ uint32_t named_block_num_blocks;
+ /**< number of elements in named blocks array */
+ uint32_t named_block_name_len;
+ /**< length of name array in bootmem blocks */
+ uint64_t named_block_array_addr;
+ /**< address of named memory block descriptors */
+
+} cvmx_bootmem_desc_t;
+
+/**
+ * Initialize the boot alloc memory structures. This is
+ * normally called inside of cvmx_user_app_init()
+ *
+ * @param mem_desc_ptr Address of the free memory list
+ * @return
+ */
+extern int cvmx_bootmem_init(void *mem_desc_ptr);
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader.
+ * This is an allocate-only algorithm, so freeing memory is not possible.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
+
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader at a specific
+ * address. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated at the specified address.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param address Physical address to allocate memory at. If this memory is not
+ * available, the allocation fails.
+ * @param alignment Alignment required - must be power of 2
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
+ uint64_t alignment);
+
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader within a specified
+ * address range. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated in the requested range.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param min_addr defines the minimum address of the range
+ * @param max_addr defines the maximum address of the range
+ * @param alignment Alignment required - must be power of 2
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
+ uint64_t min_addr, uint64_t max_addr);
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+ char *name);
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param address Physical address to allocate memory at. If this memory is not
+ * available, the allocation fails.
+ * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_address(uint64_t size,
+ uint64_t address, char *name);
+
+/**
+ * Allocate a block of memory from a specific range of the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ * If request cannot be satisfied within the address range specified, NULL is returned
+ *
+ * @param size Size in bytes of block to allocate
+ * @param min_addr minimum address of range
+ * @param max_addr maximum address of range
+ * @param align Alignment of memory to be allocated. (must be a power of 2)
+ * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size,
+ uint64_t min_addr,
+ uint64_t max_addr,
+ uint64_t align, char *name);
+
+/**
+ * Frees a previously allocated named bootmem block.
+ *
+ * @param name name of block to free
+ *
+ * @return 0 on failure,
+ * !0 on success
+ */
+extern int cvmx_bootmem_free_named(char *name);
+
+/**
+ * Finds a named bootmem block by name.
+ *
+ * @param name name of block to free
+ *
+ * @return pointer to named block descriptor on success
+ * 0 on failure
+ */
+cvmx_bootmem_named_block_desc_t *cvmx_bootmem_find_named_block(char
+ *name);
+
+/**
+ * Returns the size of available memory in bytes, only
+ * counting blocks that are at least as big as the minimum block
+ * size.
+ *
+ * @param min_block_size
+ * Minimum block size to count in total.
+ *
+ * @return Number of bytes available for allocation that meet the block size requirement
+ */
+uint64_t cvmx_bootmem_available_mem(uint64_t min_block_size);
+
+/**
+ * Prints out the list of named blocks that have been allocated
+ * along with their addresses and sizes.
+ * This is primarily used for debugging purposes
+ */
+void cvmx_bootmem_print_named(void);
+
+/**
+ * Allocates a block of physical memory from the free list, at (optional) requested address and alignment.
+ *
+ * @param req_size size of region to allocate. All requests are rounded up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ * @param address_min
+ * Minimum address that block can occupy.
+ * @param address_max
+ * Specifies the maximum address_min (inclusive) that the allocation can use.
+ * @param alignment Requested alignment of the block. If this alignment cannot be met, the allocation fails.
+ * This must be a power of 2.
+ * (Note: Alignment of CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and internally enforced. Requested alignments of
+ * less than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param flags Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
+ uint64_t address_max, uint64_t alignment,
+ uint32_t flags);
+
+/**
+ * Allocates a named block of physical memory from the free list, at (optional) requested address and alignment.
+ *
+ * @param size size of region to allocate. All requests are rounded up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ * @param min_addr
+ * Minimum address that block can occupy.
+ * @param max_addr
+ * Specifies the maximum address_min (inclusive) that the allocation can use.
+ * @param alignment Requested alignment of the block. If this alignment cannot be met, the allocation fails.
+ * This must be a power of 2.
+ * (Note: Alignment of CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and internally enforced. Requested alignments of
+ * less than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name name to assign to named block
+ * @param flags Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size,
+ uint64_t min_addr,
+ uint64_t max_addr,
+ uint64_t alignment,
+ char *name, uint32_t flags);
+
+/**
+ * Finds a named memory block by name.
+ * Also used for finding an unused entry in the named block table.
+ *
+ * @param name Name of memory block to find.
+ * If NULL pointer given, then finds unused descriptor, if available.
+ * @param flags Flags to control options for the allocation.
+ *
+ * @return Pointer to memory block descriptor, NULL if not found.
+ * If NULL returned when name parameter is NULL, then no memory
+ * block descriptors are available.
+ */
+cvmx_bootmem_named_block_desc_t *cvmx_bootmem_phy_named_block_find(char
+ *name,
+ uint32_t
+ flags);
+
+/**
+ * Returns the size of available memory in bytes, only
+ * counting blocks that are at least as big as the minimum block
+ * size.
+ *
+ * @param min_block_size
+ * Minimum block size to count in total.
+ *
+ * @return Number of bytes available for allocation that meet the block size requirement
+ */
+uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size);
+
+/**
+ * Frees a named block.
+ *
+ * @param name name of block to free
+ * @param flags flags for passing options
+ *
+ * @return 0 on failure
+ * 1 on success
+ */
+int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
+
+/**
+ * Frees a block to the bootmem allocator list. This must
+ * be used with care, as the size provided must match the size
+ * of the block that was allocated, or the list will become
+ * corrupted.
+ *
+ * IMPORTANT: This is only intended to be used as part of named block
+ * frees and initial population of the free memory list.
+ * *
+ *
+ * @param phy_addr physical address of block
+ * @param size size of block in bytes.
+ * @param flags flags for passing options
+ *
+ * @return 1 on success,
+ * 0 on failure
+ */
+int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
+
+/**
+ * Prints the list of currently allocated named blocks
+ *
+ */
+void cvmx_bootmem_phy_named_block_print(void);
+
+/**
+ * Prints the list of available memory.
+ *
+ */
+void cvmx_bootmem_phy_list_print(void);
+
+/**
+ * This function initializes the free memory list used by cvmx_bootmem.
+ * This must be called before any allocations can be done.
+ *
+ * @param mem_size Total memory available, in bytes
+ * @param low_reserved_bytes
+ * Number of bytes to reserve (leave out of free list) at address 0x0.
+ * @param desc_buffer
+ * Buffer for the bootmem descriptor. This must be a 32 bit addressable
+ * address.
+ *
+ * @return 1 on success
+ * 0 on failure
+ */
+int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size,
+ uint32_t low_reserved_bytes,
+ cvmx_bootmem_desc_t *desc_buffer);
+
+/**
+ * Locks the bootmem allocator. This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_lock(void);
+
+/**
+ * Unlocks the bootmem allocator. This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_unlock(void);
+
+/**
+ * Internal use function to get the current descriptor pointer */
+void *__cvmx_bootmem_internal_get_desc_ptr(void);
+
+#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt.h b/arch/mips/cavium-octeon/executive/cvmx-interrupt.h
new file mode 100644
index 0000000..4d42fee
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt.h
@@ -0,0 +1,256 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to the Mips interrupts.
+ *
+ * <hr>$Revision: 33997 $<hr>
+ */
+#ifndef __CVMX_INTERRUPT_H__
+#define __CVMX_INTERRUPT_H__
+
+/**
+ * Enumeration of Interrupt numbers
+ */
+typedef enum {
+ /* 0 - 7 represent the 8 MIPS standard interrupt sources */
+ CVMX_IRQ_SW0 = 0,
+ CVMX_IRQ_SW1 = 1,
+ CVMX_IRQ_CIU0 = 2,
+ CVMX_IRQ_CIU1 = 3,
+ CVMX_IRQ_4 = 4,
+ CVMX_IRQ_5 = 5,
+ CVMX_IRQ_6 = 6,
+ CVMX_IRQ_7 = 7,
+
+ /* 8 - 71 represent the sources in CIU_INTX_EN0 */
+ CVMX_IRQ_WORKQ0 = 8,
+ CVMX_IRQ_WORKQ1 = 9,
+ CVMX_IRQ_WORKQ2 = 10,
+ CVMX_IRQ_WORKQ3 = 11,
+ CVMX_IRQ_WORKQ4 = 12,
+ CVMX_IRQ_WORKQ5 = 13,
+ CVMX_IRQ_WORKQ6 = 14,
+ CVMX_IRQ_WORKQ7 = 15,
+ CVMX_IRQ_WORKQ8 = 16,
+ CVMX_IRQ_WORKQ9 = 17,
+ CVMX_IRQ_WORKQ10 = 18,
+ CVMX_IRQ_WORKQ11 = 19,
+ CVMX_IRQ_WORKQ12 = 20,
+ CVMX_IRQ_WORKQ13 = 21,
+ CVMX_IRQ_WORKQ14 = 22,
+ CVMX_IRQ_WORKQ15 = 23,
+ CVMX_IRQ_GPIO0 = 24,
+ CVMX_IRQ_GPIO1 = 25,
+ CVMX_IRQ_GPIO2 = 26,
+ CVMX_IRQ_GPIO3 = 27,
+ CVMX_IRQ_GPIO4 = 28,
+ CVMX_IRQ_GPIO5 = 29,
+ CVMX_IRQ_GPIO6 = 30,
+ CVMX_IRQ_GPIO7 = 31,
+ CVMX_IRQ_GPIO8 = 32,
+ CVMX_IRQ_GPIO9 = 33,
+ CVMX_IRQ_GPIO10 = 34,
+ CVMX_IRQ_GPIO11 = 35,
+ CVMX_IRQ_GPIO12 = 36,
+ CVMX_IRQ_GPIO13 = 37,
+ CVMX_IRQ_GPIO14 = 38,
+ CVMX_IRQ_GPIO15 = 39,
+ CVMX_IRQ_MBOX0 = 40,
+ CVMX_IRQ_MBOX1 = 41,
+ CVMX_IRQ_UART0 = 42,
+ CVMX_IRQ_UART1 = 43,
+ CVMX_IRQ_PCI_INT0 = 44,
+ CVMX_IRQ_PCI_INT1 = 45,
+ CVMX_IRQ_PCI_INT2 = 46,
+ CVMX_IRQ_PCI_INT3 = 47,
+ CVMX_IRQ_PCI_MSI0 = 48,
+ CVMX_IRQ_PCI_MSI1 = 49,
+ CVMX_IRQ_PCI_MSI2 = 50,
+ CVMX_IRQ_PCI_MSI3 = 51,
+ CVMX_IRQ_RESERVED44 = 52,
+ CVMX_IRQ_TWSI = 53,
+ CVMX_IRQ_RML = 54,
+ CVMX_IRQ_TRACE = 55,
+ CVMX_IRQ_GMX_DRP0 = 56,
+ CVMX_IRQ_GMX_DRP1 = 57,
+ CVMX_IRQ_IPD_DRP = 58,
+ CVMX_IRQ_KEY_ZERO = 59,
+ CVMX_IRQ_TIMER0 = 60,
+ CVMX_IRQ_TIMER1 = 61,
+ CVMX_IRQ_TIMER2 = 62,
+ CVMX_IRQ_TIMER3 = 63,
+ CVMX_IRQ_USB = 64, /* Doesn't apply on CN38XX or CN58XX */
+ CVMX_IRQ_PCM = 65,
+ CVMX_IRQ_MPI = 66,
+ CVMX_IRQ_TWSI2 = 67, /* Added in CN56XX */
+ CVMX_IRQ_POWIQ = 68, /* Added in CN56XX */
+ CVMX_IRQ_IPDPPTHR = 69, /* Added in CN56XX */
+ CVMX_IRQ_MII = 70, /* Added in CN56XX */
+ CVMX_IRQ_BOOTDMA = 71, /* Added in CN56XX */
+
+ /* 72 - 135 represent the sources in CIU_INTX_EN1 */
+ CVMX_IRQ_WDOG0 = 72,
+ CVMX_IRQ_WDOG1 = 73,
+ CVMX_IRQ_WDOG2 = 74,
+ CVMX_IRQ_WDOG3 = 75,
+ CVMX_IRQ_WDOG4 = 76,
+ CVMX_IRQ_WDOG5 = 77,
+ CVMX_IRQ_WDOG6 = 78,
+ CVMX_IRQ_WDOG7 = 79,
+ CVMX_IRQ_WDOG8 = 80,
+ CVMX_IRQ_WDOG9 = 81,
+ CVMX_IRQ_WDOG10 = 82,
+ CVMX_IRQ_WDOG11 = 83,
+ CVMX_IRQ_WDOG12 = 84,
+ CVMX_IRQ_WDOG13 = 85,
+ CVMX_IRQ_WDOG14 = 86,
+ CVMX_IRQ_WDOG15 = 87
+ /* numbers 88 - 135 are reserved */
+} cvmx_irq_t;
+
+/**
+ * Function prototype for the exception handler
+ */
+typedef void (*cvmx_interrupt_exception_t) (uint64_t registers[32]);
+
+/**
+ * Function prototype for interrupt handlers
+ */
+typedef void (*cvmx_interrupt_func_t) (int irq_number, uint64_t registers[32],
+ void *user_arg);
+
+/**
+ * Register an interrupt handler for the specified interrupt number.
+ *
+ * @param irq_number Interrupt number to register for (0-135)
+ * @param func Function to call on interrupt.
+ * @param user_arg User data to pass to the interrupt handler
+ */
+void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func,
+ void *user_arg);
+
+/**
+ * Set the exception handler for all non interrupt sources.
+ *
+ * @param handler New exception handler
+ * @return Old exception handler
+ */
+cvmx_interrupt_exception_t
+cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
+
+/**
+ * Masks a given interrupt number.
+ * EN0 sources are masked on IP2
+ * EN1 sources are masked on IP3
+ *
+ * @param irq_number interrupt number to mask (0-135)
+ */
+static inline void cvmx_interrupt_mask_irq(int irq_number)
+{
+ if (irq_number < 8) {
+ uint32_t mask;
+ asm volatile ("mfc0 %0,$12,0":"=r" (mask));
+ mask &= ~(1 << (8 + irq_number));
+ asm volatile ("mtc0 %0,$12,0"::"r" (mask));
+ } else if (irq_number < 8 + 64) {
+ int ciu_bit = (irq_number - 8) & 63;
+ int ciu_offset = cvmx_get_core_num() * 2;
+ uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
+ mask &= ~(1ull << ciu_bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
+ } else {
+ int ciu_bit = (irq_number - 8) & 63;
+ int ciu_offset = cvmx_get_core_num() * 2 + 1;
+ uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
+ mask &= ~(1ull << ciu_bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
+ }
+}
+
+/**
+ * Unmasks a given interrupt number
+ * EN0 sources are unmasked on IP2
+ * EN1 sources are unmasked on IP3
+ *
+ * @param irq_number interrupt number to unmask (0-135)
+ */
+static inline void cvmx_interrupt_unmask_irq(int irq_number)
+{
+ if (irq_number < 8) {
+ uint32_t mask;
+ asm volatile ("mfc0 %0,$12,0":"=r" (mask));
+ mask |= (1 << (8 + irq_number));
+ asm volatile ("mtc0 %0,$12,0"::"r" (mask));
+ } else if (irq_number < 8 + 64) {
+ int ciu_bit = (irq_number - 8) & 63;
+ int ciu_offset = cvmx_get_core_num() * 2;
+ uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
+ mask |= (1ull << ciu_bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
+ } else {
+ int ciu_bit = (irq_number - 8) & 63;
+ int ciu_offset = cvmx_get_core_num() * 2 + 1;
+ uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
+ mask |= (1ull << ciu_bit);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
+ }
+}
+
+/* Disable interrupts by clearing bit 0 of the COP0 status register,
+** and return the previous contents of the status register.
+** Note: this is only used to track interrupt status. */
+static inline uint32_t cvmx_interrupt_disable_save(void)
+{
+ uint32_t flags;
+ asm volatile ("DI %[flags]\n":[flags] "=r"(flags));
+ return (flags);
+}
+
+/* Restore the contents of the cop0 status register. Used with
+** cvmx_interrupt_disable_save to allow recursive interrupt disabling */
+static inline void cvmx_interrupt_restore(uint32_t flags)
+{
+ /* If flags value indicates interrupts should be enabled, then enable them */
+ if (flags & 1) {
+ asm volatile ("EI \n"::);
+ }
+}
+
+/**
+ * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
+ * into error messages.
+ */
+extern void cvmx_interrupt_rsl_decode(void);
+
+/**
+ * Utility function to enable all RSL error interupts
+ */
+extern void cvmx_interrupt_rsl_enable(void);
+
+#endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
new file mode 100644
index 0000000..ce6eb9a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -0,0 +1,713 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
+ *
+ *
+ */
+#include "cvmx.h"
+#include "cvmx-l2c.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-interrupt.h"
+
+/* This spinlock is used internally to ensure that only one core is performing
+** certain L2 operations at a time.
+**
+** NOTE: This only protects calls from within a single application -
+** if multiple applications or operating systems are running, then it
+** is up to the user program to coordinate between them.
+*/
+CVMX_SHARED cvmx_spinlock_t cvmx_l2c_spinlock;
+
+static inline int l2_size_half(void)
+{
+ uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
+ return !!(val & (1ull << 34));
+}
+
+int cvmx_l2c_get_core_way_partition(uint32_t core)
+{
+ uint32_t field;
+
+ /* Validate the core number */
+ if (core >= cvmx_octeon_num_cores())
+ return -1;
+
+ /* Use the lower two bits of the coreNumber to determine the bit offset
+ * of the UMSK[] field in the L2C_SPAR register.
+ */
+ field = (core & 0x3) * 8;
+
+ /* Return the UMSK[] field from the appropriate L2C_SPAR register based
+ * on the coreNumber.
+ */
+
+ switch (core & 0xC) {
+ case 0x0:
+ return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
+ field;
+ case 0x4:
+ return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
+ field;
+ case 0x8:
+ return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
+ field;
+ case 0xC:
+ return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
+ field;
+ }
+ return 0;
+}
+
+int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
+{
+ uint32_t field;
+ uint32_t valid_mask;
+
+ valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
+
+ mask &= valid_mask;
+
+ /* A UMSK setting which blocks all L2C Ways is an error. */
+ if (mask == valid_mask)
+ return -1;
+
+ /* Validate the core number */
+ if (core >= cvmx_octeon_num_cores())
+ return -1;
+
+ /* Check to make sure current mask & new mask don't block all ways */
+ if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
+ valid_mask)
+ return -1;
+
+ /* Use the lower two bits of core to determine the bit offset of the
+ * UMSK[] field in the L2C_SPAR register.
+ */
+ field = (core & 0x3) * 8;
+
+ /* Assign the new mask setting to the UMSK[] field in the appropriate
+ * L2C_SPAR register based on the core_num.
+ *
+ */
+ switch (core & 0xC) {
+ case 0x0:
+ cvmx_write_csr(CVMX_L2C_SPAR0,
+ (cvmx_read_csr(CVMX_L2C_SPAR0) &
+ ~(0xFF << field)) | mask << field);
+ break;
+ case 0x4:
+ cvmx_write_csr(CVMX_L2C_SPAR1,
+ (cvmx_read_csr(CVMX_L2C_SPAR1) &
+ ~(0xFF << field)) | mask << field);
+ break;
+ case 0x8:
+ cvmx_write_csr(CVMX_L2C_SPAR2,
+ (cvmx_read_csr(CVMX_L2C_SPAR2) &
+ ~(0xFF << field)) | mask << field);
+ break;
+ case 0xC:
+ cvmx_write_csr(CVMX_L2C_SPAR3,
+ (cvmx_read_csr(CVMX_L2C_SPAR3) &
+ ~(0xFF << field)) | mask << field);
+ break;
+ }
+ return 0;
+}
+
+int cvmx_l2c_set_hw_way_partition(uint32_t mask)
+{
+ uint32_t valid_mask;
+
+ valid_mask = 0xff;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+ if (l2_size_half())
+ valid_mask = 0xf;
+ } else if (l2_size_half())
+ valid_mask = 0x3;
+
+ mask &= valid_mask;
+
+ /* A UMSK setting which blocks all L2C Ways is an error. */
+ if (mask == valid_mask)
+ return -1;
+ /* Check to make sure current mask & new mask don't block all ways */
+ if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
+ valid_mask)
+ return -1;
+
+ cvmx_write_csr(CVMX_L2C_SPAR4,
+ (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+ return 0;
+}
+
+int cvmx_l2c_get_hw_way_partition(void)
+{
+ return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
+}
+
+void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event,
+ uint32_t clear_on_read)
+{
+ cvmx_l2c_pfctl_t pfctl;
+
+ pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+
+ switch (counter) {
+ case 0:
+ pfctl.s.cnt0sel = event;
+ pfctl.s.cnt0ena = 1;
+ if (!cvmx_octeon_is_pass1())
+ pfctl.s.cnt0rdclr = clear_on_read;
+ break;
+ case 1:
+ pfctl.s.cnt1sel = event;
+ pfctl.s.cnt1ena = 1;
+ if (!cvmx_octeon_is_pass1())
+ pfctl.s.cnt1rdclr = clear_on_read;
+ break;
+ case 2:
+ pfctl.s.cnt2sel = event;
+ pfctl.s.cnt2ena = 1;
+ if (!cvmx_octeon_is_pass1())
+ pfctl.s.cnt2rdclr = clear_on_read;
+ break;
+ case 3:
+ default:
+ pfctl.s.cnt3sel = event;
+ pfctl.s.cnt3ena = 1;
+ if (!cvmx_octeon_is_pass1())
+ pfctl.s.cnt3rdclr = clear_on_read;
+ break;
+ }
+
+ cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+}
+
+uint64_t cvmx_l2c_read_perf(uint32_t counter)
+{
+ switch (counter) {
+ case 0:
+ return cvmx_read_csr(CVMX_L2C_PFC0);
+ case 1:
+ return cvmx_read_csr(CVMX_L2C_PFC1);
+ case 2:
+ return cvmx_read_csr(CVMX_L2C_PFC2);
+ case 3:
+ default:
+ return cvmx_read_csr(CVMX_L2C_PFC3);
+ }
+}
+
+/**
+ * @INTERNAL
+ * Helper function use to fault in cache lines for L2 cache locking
+ *
+ * @param addr Address of base of memory region to read into L2 cache
+ * @param len Length (in bytes) of region to fault in
+ */
+static void fault_in(uint64_t addr, int len)
+{
+ volatile char *ptr;
+ volatile char dummy;
+ /* Adjust addr and length so we get all cache lines even for
+ ** small ranges spanning two cache lines */
+ len += addr & CVMX_CACHE_LINE_MASK;
+ addr &= ~CVMX_CACHE_LINE_MASK;
+ ptr = (volatile char *)cvmx_phys_to_ptr(addr);
+ /* Invalidate L1 cache to make sure all loads result in data
+ * being in L2 */
+ CVMX_DCACHE_INVALIDATE;
+ while (len > 0) {
+ dummy += *ptr;
+ len -= CVMX_CACHE_LINE_SIZE;
+ ptr += CVMX_CACHE_LINE_SIZE;
+ }
+}
+
+int cvmx_l2c_lock_line(uint64_t addr)
+{
+ int retval = 0;
+ cvmx_l2c_dbg_t l2cdbg;
+ cvmx_l2c_lckbase_t lckbase;
+ cvmx_l2c_lckoff_t lckoff;
+ cvmx_l2t_err_t l2t_err;
+ l2cdbg.u64 = 0;
+ lckbase.u64 = 0;
+ lckoff.u64 = 0;
+
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+
+ /* Clear l2t error bits if set */
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ l2t_err.s.lckerr = 1;
+ l2t_err.s.lckerr2 = 1;
+ cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+
+ addr &= ~CVMX_CACHE_LINE_MASK;
+
+ /* Set this core as debug core */
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+ cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+ cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+ if (((cvmx_l2c_cfg_t) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+ int alias_shift =
+ CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+ uint64_t addr_tmp =
+ addr ^ (addr & ((1 << alias_shift) - 1)) >>
+ CVMX_L2_SET_BITS;
+ lckbase.s.lck_base = addr_tmp >> 7;
+ } else {
+ lckbase.s.lck_base = addr >> 7;
+ }
+
+ lckbase.s.lck_ena = 1;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+
+ fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+ lckbase.s.lck_ena = 0;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+
+ /* Stop being debug core */
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+ retval = 1; /* We were unable to lock the line */
+
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+
+ return retval;
+}
+
+int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
+{
+ int retval = 0;
+
+ /* Round start/end to cache line boundaries */
+ len += start & CVMX_CACHE_LINE_MASK;
+ start &= ~CVMX_CACHE_LINE_MASK;
+ len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
+
+ while (len) {
+ retval += cvmx_l2c_lock_line(start);
+ start += CVMX_CACHE_LINE_SIZE;
+ len -= CVMX_CACHE_LINE_SIZE;
+ }
+
+ return retval;
+}
+
+void cvmx_l2c_flush(void)
+{
+ uint64_t assoc, set;
+ uint64_t n_assoc, n_set;
+ cvmx_l2c_dbg_t l2cdbg;
+
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+
+ l2cdbg.u64 = 0;
+ if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ l2cdbg.s.finv = 1;
+ n_set = CVMX_L2_SETS;
+ n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
+ for (set = 0; set < n_set; set++) {
+ for (assoc = 0; assoc < n_assoc; assoc++) {
+ l2cdbg.s.set = assoc;
+ /* Enter debug mode, and make sure all other
+ ** writes complete before we enter debug
+ ** mode */
+ CVMX_SYNCW;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
+ (CVMX_MIPS_SPACE_XKPHYS,
+ set * CVMX_CACHE_LINE_SIZE), 0);
+ CVMX_SYNCW; /* Push STF out to L2 */
+ /* Exit debug mode */
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+ }
+ }
+
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+}
+
+int cvmx_l2c_unlock_line(uint64_t address)
+{
+ int assoc;
+ cvmx_l2c_tag_t tag;
+ cvmx_l2c_dbg_t l2cdbg;
+ uint32_t tag_addr;
+
+ uint32_t index = cvmx_l2c_address_to_index(address);
+
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+ /* Compute portion of address that is stored in tag */
+ tag_addr =
+ ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
+ ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+ for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+ tag = cvmx_get_l2c_tag(assoc, index);
+
+ if (tag.s.V && (tag.s.addr == tag_addr)) {
+ l2cdbg.u64 = 0;
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ l2cdbg.s.set = assoc;
+ l2cdbg.s.finv = 1;
+
+ CVMX_SYNC;
+ /* Enter debug mode */
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
+ (CVMX_MIPS_SPACE_XKPHYS,
+ address), 0);
+ CVMX_SYNC;
+ /* Exit debug mode */
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ return tag.s.L;
+ }
+ }
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ return 0;
+}
+
+int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
+{
+ int num_unlocked = 0;
+ /* Round start/end to cache line boundaries */
+ len += start & CVMX_CACHE_LINE_MASK;
+ start &= ~CVMX_CACHE_LINE_MASK;
+ len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
+ while (len > 0) {
+ num_unlocked += cvmx_l2c_unlock_line(start);
+ start += CVMX_CACHE_LINE_SIZE;
+ len -= CVMX_CACHE_LINE_SIZE;
+ }
+
+ return num_unlocked;
+}
+
+/* Internal l2c tag types. These are converted to a generic structure
+** that can be used on all chips */
+typedef union {
+ uint64_t u64;
+#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_l2c_tag_cn50xx {
+ uint64_t reserved:40;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:20; /* Phys mem addr (33..14) */
+ } cn50xx;
+ struct cvmx_l2c_tag_cn30xx {
+ uint64_t reserved:41;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:19; /* Phys mem addr (33..15) */
+ } cn30xx;
+ struct cvmx_l2c_tag_cn31xx {
+ uint64_t reserved:42;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:18; /* Phys mem addr (33..16) */
+ } cn31xx;
+ struct cvmx_l2c_tag_cn38xx {
+ uint64_t reserved:43;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:17; /* Phys mem addr (33..17) */
+ } cn38xx;
+ struct cvmx_l2c_tag_cn58xx {
+ uint64_t reserved:44;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:16; /* Phys mem addr (33..18) */
+ } cn58xx;
+ struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
+ struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
+#endif
+} __cvmx_l2c_tag_t;
+
+/**
+ * @INTERNAL
+ * Function to read a L2C tag. This code make the current core
+ * the 'debug core' for the L2. This code must only be executed by
+ * 1 core at a time.
+ *
+ * @param assoc Association (way) of the tag to dump
+ * @param index Index of the cacheline
+ *
+ * @return The Octeon model specific tag structure. This is translated by a wrapper
+ * function to a generic form that is easier for applications to use.
+ */
+static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
+{
+
+ uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+ uint64_t core = cvmx_get_core_num();
+ __cvmx_l2c_tag_t tag_val;
+ uint64_t dbg_addr = CVMX_L2C_DBG;
+ uint32_t flags;
+
+ cvmx_l2c_dbg_t debug_val;
+ debug_val.u64 = 0;
+ /* For low core count parts, the core number is always small enough
+ ** to stay in the correct field and not set any reserved bits */
+ debug_val.s.ppnum = core;
+ debug_val.s.l2t = 1;
+ debug_val.s.set = assoc;
+
+ CVMX_SYNC; /* Make sure core is quiet (no prefetches, etc.) before entering debug mode */
+ CVMX_DCACHE_INVALIDATE; /* Flush L1 to make sure debug load misses L1 */
+
+ flags = cvmx_interrupt_disable_save();
+
+ /* The following must be done in assembly as when in debug
+ * mode all data loads from L2 return special debug data, not
+ * normal memory contents. Also, interrupts must be
+ * disabled, since if an interrupt occurs while in debug mode
+ * the ISR will get debug data from all its memory reads
+ * instead of the contents of memory */
+
+ asm volatile (" .set push \n"
+ " .set mips64 \n"
+ " .set noreorder \n"
+ " sd %[dbg_val], 0(%[dbg_addr]) \n" /* Enter debug mode, wait for store */
+ " ld $0, 0(%[dbg_addr]) \n"
+ " ld %[tag_val], 0(%[tag_addr]) \n" /* Read L2C tag data */
+ " sd $0, 0(%[dbg_addr]) \n" /* Exit debug mode, wait for store */
+ " ld $0, 0(%[dbg_addr]) \n"
+ " cache 9, 0($0) \n" /* Invalidate dcache to discard debug data */
+ " .set pop \n" :
+ [tag_val] "=r"(tag_val) : [dbg_addr] "r"(dbg_addr),
+ [dbg_val] "r"(debug_val),
+ [tag_addr] "r"(debug_tag_addr) : "memory");
+
+ cvmx_interrupt_restore(flags);
+
+ return tag_val;
+
+}
+
+cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
+{
+ __cvmx_l2c_tag_t tmp_tag;
+ cvmx_l2c_tag_t tag;
+ tag.u64 = 0;
+
+ if ((int)association >= cvmx_l2c_get_num_assoc()) {
+ cvmx_dprintf
+ ("ERROR: cvmx_get_l2c_tag association out of range\n");
+ return tag;
+ }
+ if ((int)index >= cvmx_l2c_get_num_sets()) {
+ cvmx_dprintf ("ERROR: cvmx_get_l2c_tag "
+ "index out of range (arg: %d, max: %d\n",
+ index, cvmx_l2c_get_num_sets());
+ return tag;
+ }
+ /* __read_l2_tag is intended for internal use only */
+ tmp_tag = __read_l2_tag(association, index);
+
+ /* Convert all tag structure types to generic version, as it can represent all models */
+ if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+ tag.s.V = tmp_tag.cn58xx.V;
+ tag.s.D = tmp_tag.cn58xx.D;
+ tag.s.L = tmp_tag.cn58xx.L;
+ tag.s.U = tmp_tag.cn58xx.U;
+ tag.s.addr = tmp_tag.cn58xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+ tag.s.V = tmp_tag.cn38xx.V;
+ tag.s.D = tmp_tag.cn38xx.D;
+ tag.s.L = tmp_tag.cn38xx.L;
+ tag.s.U = tmp_tag.cn38xx.U;
+ tag.s.addr = tmp_tag.cn38xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+ tag.s.V = tmp_tag.cn31xx.V;
+ tag.s.D = tmp_tag.cn31xx.D;
+ tag.s.L = tmp_tag.cn31xx.L;
+ tag.s.U = tmp_tag.cn31xx.U;
+ tag.s.addr = tmp_tag.cn31xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+ tag.s.V = tmp_tag.cn30xx.V;
+ tag.s.D = tmp_tag.cn30xx.D;
+ tag.s.L = tmp_tag.cn30xx.L;
+ tag.s.U = tmp_tag.cn30xx.U;
+ tag.s.addr = tmp_tag.cn30xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+ tag.s.V = tmp_tag.cn50xx.V;
+ tag.s.D = tmp_tag.cn50xx.D;
+ tag.s.L = tmp_tag.cn50xx.L;
+ tag.s.U = tmp_tag.cn50xx.U;
+ tag.s.addr = tmp_tag.cn50xx.addr;
+ } else {
+ cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+ }
+
+ return tag;
+}
+
+uint32_t cvmx_l2c_address_to_index(uint64_t addr)
+{
+ uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
+ cvmx_l2c_cfg_t l2c_cfg;
+ l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+
+ if (l2c_cfg.s.idxalias) {
+ idx ^=
+ ((addr & CVMX_L2C_ALIAS_MASK) >>
+ CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+ }
+ idx &= CVMX_L2C_IDX_MASK;
+ return idx;
+}
+
+int cvmx_l2c_get_cache_size_bytes(void)
+{
+ return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() *
+ CVMX_CACHE_LINE_SIZE;
+}
+
+/**
+ * Return log base 2 of the number of sets in the L2 cache
+ * @return
+ */
+int cvmx_l2c_get_set_bits(void)
+{
+ int l2_set_bits;
+ if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+ l2_set_bits = 11; /* 2048 sets */
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+ l2_set_bits = 10; /* 1024 sets */
+ else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX))
+ l2_set_bits = 9; /* 512 sets */
+ else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+ l2_set_bits = 8; /* 256 sets */
+ else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+ l2_set_bits = 7; /* 128 sets */
+ else {
+ cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+ l2_set_bits = 11; /* 2048 sets */
+ }
+ return l2_set_bits;
+
+}
+
+/* Return the number of sets in the L2 Cache */
+int cvmx_l2c_get_num_sets(void)
+{
+ return 1 << cvmx_l2c_get_set_bits();
+}
+
+/* Return the number of associations in the L2 Cache */
+int cvmx_l2c_get_num_assoc(void)
+{
+ int l2_assoc;
+ if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN52XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN58XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
+ l2_assoc = 8;
+ else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN30XX))
+ l2_assoc = 4;
+ else {
+ cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+ l2_assoc = 8;
+ }
+
+ /* Check to see if part of the cache is disabled */
+ if (cvmx_fuse_read(265))
+ l2_assoc = l2_assoc >> 2;
+ else if (cvmx_fuse_read(264))
+ l2_assoc = l2_assoc >> 1;
+
+ return l2_assoc;
+}
+
+/**
+ * Flush a line from the L2 cache
+ * This should only be called from one core at a time, as this routine
+ * sets the core to the 'debug' core in order to flush the line.
+ *
+ * @param assoc Association (or way) to flush
+ * @param index Index to flush
+ */
+void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
+{
+ cvmx_l2c_dbg_t l2cdbg;
+
+ l2cdbg.u64 = 0;
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ l2cdbg.s.finv = 1;
+
+ l2cdbg.s.set = assoc;
+ /* Enter debug mode, and make sure all other writes complete before we
+ ** enter debug mode */
+ asm volatile ("sync \n":::"memory");
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
+ /* Exit debug mode */
+ asm volatile ("sync \n":::"memory");
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.h b/arch/mips/cavium-octeon/executive/cvmx-l2c.h
new file mode 100644
index 0000000..bf3c4d4
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.h
@@ -0,0 +1,330 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
+ * facilities.
+ *
+ */
+
+#ifndef __CVMX_L2C_H__
+#define __CVMX_L2C_H__
+
+#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
+#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
+
+#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
+#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
+
+/* Defines for index aliasing computations */
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+
+ /*------------*/
+ /* TYPEDEFS */
+ /*------------*/
+typedef union { /* L2C Tag/Data Store Debug Register */
+ uint64_t u64;
+ struct {
+ uint64_t reserved:32;
+ uint64_t lfb_enum:4;
+ uint64_t lfb_dmp:1;
+ uint64_t ppnum:4;
+ uint64_t set:3;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+ };
+} cvmx_l2c_dbg;
+
+typedef union {
+ uint64_t u64;
+#if __BYTE_ORDER == __BIG_ENDIAN
+ struct {
+ uint64_t reserved:28;
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
+ uint64_t addr:32; /* Phys mem (not all bits valid) */
+ } s;
+#endif
+} cvmx_l2c_tag_t;
+
+ /* L2C Performance Counter events. */
+typedef enum {
+ CVMX_L2C_EVENT_CYCLES = 0,
+ CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
+ CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
+ CVMX_L2C_EVENT_DATA_MISS = 3,
+ CVMX_L2C_EVENT_DATA_HIT = 4,
+ CVMX_L2C_EVENT_MISS = 5,
+ CVMX_L2C_EVENT_HIT = 6,
+ CVMX_L2C_EVENT_VICTIM_HIT = 7,
+ CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
+ CVMX_L2C_EVENT_TAG_PROBE = 9,
+ CVMX_L2C_EVENT_TAG_UPDATE = 10,
+ CVMX_L2C_EVENT_TAG_COMPLETE = 11,
+ CVMX_L2C_EVENT_TAG_DIRTY = 12,
+ CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
+ CVMX_L2C_EVENT_DATA_STORE_READ = 14,
+ CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
+ CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
+ CVMX_L2C_EVENT_WRITE_REQUEST = 17,
+ CVMX_L2C_EVENT_READ_REQUEST = 18,
+ CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
+ CVMX_L2C_EVENT_XMC_NOP = 20,
+ CVMX_L2C_EVENT_XMC_LDT = 21,
+ CVMX_L2C_EVENT_XMC_LDI = 22,
+ CVMX_L2C_EVENT_XMC_LDD = 23,
+ CVMX_L2C_EVENT_XMC_STF = 24,
+ CVMX_L2C_EVENT_XMC_STT = 25,
+ CVMX_L2C_EVENT_XMC_STP = 26,
+ CVMX_L2C_EVENT_XMC_STC = 27,
+ CVMX_L2C_EVENT_XMC_DWB = 28,
+ CVMX_L2C_EVENT_XMC_PL2 = 29,
+ CVMX_L2C_EVENT_XMC_PSL1 = 30,
+ CVMX_L2C_EVENT_XMC_IOBLD = 31,
+ CVMX_L2C_EVENT_XMC_IOBST = 32,
+ CVMX_L2C_EVENT_XMC_IOBDMA = 33,
+ CVMX_L2C_EVENT_XMC_IOBRSP = 34,
+ CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
+ CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
+ CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
+ CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
+ CVMX_L2C_EVENT_RSC_NOP = 39,
+ CVMX_L2C_EVENT_RSC_STDN = 40,
+ CVMX_L2C_EVENT_RSC_FILL = 41,
+ CVMX_L2C_EVENT_RSC_REFL = 42,
+ CVMX_L2C_EVENT_RSC_STIN = 43,
+ CVMX_L2C_EVENT_RSC_SCIN = 44,
+ CVMX_L2C_EVENT_RSC_SCFL = 45,
+ CVMX_L2C_EVENT_RSC_SCDN = 46,
+ CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
+ CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
+ CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
+ CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
+ CVMX_L2C_EVENT_LRF_REQ = 51,
+ CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
+ CVMX_L2C_EVENT_DT_WR_INVAL = 53
+} cvmx_l2c_event_t;
+
+/**
+ * Configure one of the four L2 Cache performance counters to capture event
+ * occurences.
+ *
+ * @param counter The counter to configure. Range 0..3.
+ * @param event The type of L2 Cache event occurrence to count.
+ * @param clear_on_read When asserted, any read of the performance counter
+ * clears the counter.
+ *
+ * @note The routine does not clear the counter.
+ */
+void cvmx_l2c_config_perf(uint32_t counter,
+ cvmx_l2c_event_t event, uint32_t clear_on_read);
+/**
+ * Read the given L2 Cache performance counter. The counter must be configured
+ * before reading, but this routine does not enforce this requirement.
+ *
+ * @param counter The counter to configure. Range 0..3.
+ *
+ * @return The current counter value.
+ */
+uint64_t cvmx_l2c_read_perf(uint32_t counter);
+
+/**
+ * Return the L2 Cache way partitioning for a given core.
+ *
+ * @param core The core processor of interest.
+ *
+ * @return The mask specifying the partitioning. 0 bits in mask indicates
+ * the cache 'ways' that a core can evict from.
+ * -1 on error
+ */
+int cvmx_l2c_get_core_way_partition(uint32_t core);
+
+/**
+ * Partitions the L2 cache for a core
+ *
+ * @param core The core that the partitioning applies to.
+ * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
+ * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
+ * from that way. There must be at least one allowed way (0 bit) in the mask.
+ *
+ * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
+ * any cache lines evicted from them. All cores and the hardware blocks are free to read from
+ * all ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
+
+/**
+ * Return the L2 Cache way partitioning for the hw blocks.
+ *
+ * @return The mask specifying the reserved way. 0 bits in mask indicates
+ * the cache 'ways' that a core can evict from.
+ * -1 on error
+ */
+int cvmx_l2c_get_hw_way_partition(void);
+
+/**
+ * Partitions the L2 cache for the hardware blocks.
+ *
+ * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
+ * to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
+ * from that way. There must be at least one allowed way (0 bit) in the mask.
+ *
+ * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
+ * any cache lines evicted from them. All cores and the hardware blocks are free to read from
+ * all ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_hw_way_partition(uint32_t mask);
+
+/**
+ * Locks a line in the L2 cache at the specified physical address
+ *
+ * @param addr physical address of line to lock
+ *
+ * @return 0 on success,
+ * 1 if line not locked.
+ */
+int cvmx_l2c_lock_line(uint64_t addr);
+
+/**
+ * Locks a specified memory region in the L2 cache.
+ *
+ * Note that if not all lines can be locked, that means that all
+ * but one of the ways (associations) available to the locking
+ * core are locked. Having only 1 association available for
+ * normal caching may have a significant adverse affect on performance.
+ * Care should be taken to ensure that enough of the L2 cache is left
+ * unlocked to allow for normal caching of DRAM.
+ *
+ * @param start Physical address of the start of the region to lock
+ * @param len Length (in bytes) of region to lock
+ *
+ * @return Number of requested lines that where not locked.
+ * 0 on success (all locked)
+ */
+int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
+
+/**
+ * Unlock and flush a cache line from the L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ * Note that this function will flush a matching but unlocked cache line.
+ * (If address is not in L2, no lines are flushed.)
+ *
+ * @param address Physical address to unlock
+ *
+ * @return 0: line not unlocked
+ * 1: line unlocked
+ */
+int cvmx_l2c_unlock_line(uint64_t address);
+
+/**
+ * Unlocks a region of memory that is locked in the L2 cache
+ *
+ * @param start start physical address
+ * @param len length (in bytes) to unlock
+ *
+ * @return Number of locked lines that the call unlocked
+ */
+int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
+
+/**
+ * Read the L2 controller tag for a given location in L2
+ *
+ * @param association
+ * Which association to read line from
+ * @param index Which way to read from.
+ *
+ * @return l2c tag structure for line requested.
+ */
+cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index);
+
+/* Wrapper around deprecated old function name */
+static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association,
+ uint32_t index)
+{
+ return cvmx_l2c_get_tag(association, index);
+}
+
+/**
+ * Returns the cache index for a given physical address
+ *
+ * @param addr physical address
+ *
+ * @return L2 cache index
+ */
+uint32_t cvmx_l2c_address_to_index(uint64_t addr);
+
+/**
+ * Flushes (and unlocks) the entire L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ */
+void cvmx_l2c_flush(void);
+
+/**
+ *
+ * @return Returns the size of the L2 cache in bytes,
+ * -1 on error (unrecognized model)
+ */
+int cvmx_l2c_get_cache_size_bytes(void);
+
+/**
+ * Return the number of sets in the L2 Cache
+ *
+ * @return
+ */
+int cvmx_l2c_get_num_sets(void);
+
+/**
+ * Return log base 2 of the number of sets in the L2 cache
+ * @return
+ */
+int cvmx_l2c_get_set_bits(void);
+/**
+ * Return the number of associations in the L2 Cache
+ *
+ * @return
+ */
+int cvmx_l2c_get_num_assoc(void);
+
+/**
+ * Flush a line from the L2 cache
+ * This should only be called from one core at a time, as this routine
+ * sets the core to the 'debug' core in order to flush the line.
+ *
+ * @param assoc Association (or way) to flush
+ * @param index Index to flush
+ */
+void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
+
+#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-linux-kernel-exports.c b/arch/mips/cavium-octeon/executive/cvmx-linux-kernel-exports.c
new file mode 100644
index 0000000..1384717
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-linux-kernel-exports.c
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-warn.h"
+
+/* Exports for cvmx-bootmem.c */
+EXPORT_SYMBOL(cvmx_bootmem_alloc);
+EXPORT_SYMBOL(cvmx_bootmem_alloc_address);
+EXPORT_SYMBOL(cvmx_bootmem_alloc_range);
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named);
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named_address);
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named_range);
+EXPORT_SYMBOL(cvmx_bootmem_free_named);
+EXPORT_SYMBOL(cvmx_bootmem_find_named_block);
+EXPORT_SYMBOL(cvmx_bootmem_available_mem);
+
+/* Exports for cvmx-sysinfo.c */
+EXPORT_SYMBOL(cvmx_sysinfo_get);
+
+/* Exports for cvmx-warn.c */
+EXPORT_SYMBOL(cvmx_warn);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-packet.h b/arch/mips/cavium-octeon/executive/cvmx-packet.h
new file mode 100644
index 0000000..a982207
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-packet.h
@@ -0,0 +1,64 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Packet buffer defines.
+ *
+ *
+ */
+
+#ifndef __CVMX_PACKET_H__
+#define __CVMX_PACKET_H__
+
+/**
+ * This structure defines a buffer pointer on Octeon
+ */
+typedef union {
+ void *ptr;
+ uint64_t u64;
+ struct {
+ /* if set, invert the "free" pick of the overall
+ * packet. HW always sets this bit to 0 on inbound
+ * packet */
+ uint64_t i:1;
+
+ /* Indicates the amount to back up to get to the
+ * buffer start in cache lines. In most cases this is
+ * less than one complete cache line, so the value is
+ * zero */
+ uint64_t back:4;
+ /* The pool that the buffer came from / goes to */
+ uint64_t pool:3;
+ /* The size of the segment pointed to by addr (in bytes) */
+ uint64_t size:16;
+ /* Pointer to the first byte of the data, NOT buffer */
+ uint64_t addr:40;
+ } s;
+} cvmx_buf_ptr_t;
+
+#endif /* __CVMX_PACKET_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-platform.h b/arch/mips/cavium-octeon/executive/cvmx-platform.h
new file mode 100644
index 0000000..5fca57a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-platform.h
@@ -0,0 +1,57 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This file is resposible for including all system dependent
+ * headers for the cvmx-* files.
+ *
+*/
+
+#ifndef __CVMX_PLATFORM_H__
+#define __CVMX_PLATFORM_H__
+
+#include "cvmx-abi.h"
+
+/* This file defines macros for use in determining the current
+ building environment. It defines a single CVMX_BUILD_FOR_*
+ macro representing the target of the build. The current
+ possibilities are:
+ CVMX_BUILD_FOR_UBOOT
+ CVMX_BUILD_FOR_LINUX_KERNEL
+ CVMX_BUILD_FOR_LINUX_USER
+ CVMX_BUILD_FOR_LINUX_HOST
+ CVMX_BUILD_FOR_VXWORKS
+ CVMX_BUILD_FOR_STANDALONE */
+/* We are in the Linux kernel on Octeon */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <stdarg.h>
+
+#endif /* __CVMX_PLATFORM_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spinlock.h b/arch/mips/cavium-octeon/executive/cvmx-spinlock.h
new file mode 100644
index 0000000..1b7f63c
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-spinlock.h
@@ -0,0 +1,376 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Implementation of spinlocks.
+ *
+ */
+
+#ifndef __CVMX_SPINLOCK_H__
+#define __CVMX_SPINLOCK_H__
+
+#include "cvmx-asm.h"
+
+/* Spinlocks for Octeon */
+
+/* define these to enable recursive spinlock debugging */
+/*#define CVMX_SPINLOCK_DEBUG */
+
+/**
+ * Spinlocks for Octeon
+ */
+typedef struct {
+ volatile uint32_t value;
+} cvmx_spinlock_t;
+
+/* note - macros not expanded in inline ASM, so values hardcoded */
+#define CVMX_SPINLOCK_UNLOCKED_VAL 0
+#define CVMX_SPINLOCK_LOCKED_VAL 1
+
+#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL}
+
+/**
+ * Initialize a spinlock
+ *
+ * @param lock Lock to initialize
+ */
+static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
+{
+ lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+ * Return non-zero if the spinlock is currently locked
+ *
+ * @param lock Lock to check
+ * @return Non-zero if locked
+ */
+static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
+{
+ return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+ * Releases lock
+ *
+ * @param lock pointer to lock structure
+ */
+static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
+{
+ CVMX_SYNCWS;
+ lock->value = 0;
+ CVMX_SYNCWS;
+}
+
+/**
+ * Attempts to take the lock, but does not spin if lock is not available.
+ * May take some time to acquire the lock even if it is available
+ * due to the ll/sc not succeeding.
+ *
+ * @param lock pointer to lock structure
+ *
+ * @return 0: lock successfully taken
+ * 1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+
+static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__(".set noreorder \n" "1: ll %[tmp], %[val] \n" " bnez %[tmp], 2f \n" /* if lock held, fail immediately */
+ " li %[tmp], 1 \n"
+ " sc %[tmp], %[val] \n"
+ " beqz %[tmp], 1b \n"
+ " li %[tmp], 0 \n"
+ "2: \n"
+ ".set reorder \n" :
+ [val] "+m"(lock->value), [tmp] "=&r"(tmp)
+ : : "memory");
+
+ return tmp != 0; /* normalize to 0 or 1 */
+}
+
+/**
+ * Gets lock, spins until lock is taken
+ *
+ * @param lock pointer to lock structure
+ */
+static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__(".set noreorder \n"
+ "1: ll %[tmp], %[val] \n"
+ " bnez %[tmp], 1b \n"
+ " li %[tmp], 1 \n"
+ " sc %[tmp], %[val] \n"
+ " beqz %[tmp], 1b \n"
+ " nop \n"
+ ".set reorder \n" :
+ [val] "+m"(lock->value), [tmp] "=&r"(tmp)
+ : : "memory");
+
+}
+
+/** ********************************************************************
+ * Bit spinlocks
+ * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
+ * The rest of the bits in the word are left undisturbed. This enables more
+ * compact data structures as only 1 bit is consumed for the lock.
+ *
+ */
+
+/**
+ * Gets lock, spins until lock is taken
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @param word word to lock bit 31 of
+ */
+static inline void cvmx_spinlock_bit_lock(uint32_t * word)
+{
+ unsigned int tmp;
+ unsigned int sav;
+
+ __asm__ __volatile__(".set noreorder \n"
+ ".set noat \n"
+ "1: ll %[tmp], %[val] \n"
+ " bbit1 %[tmp], 31, 1b \n"
+ " li $at, 1 \n"
+ " ins %[tmp], $at, 31, 1 \n"
+ " sc %[tmp], %[val] \n"
+ " beqz %[tmp], 1b \n"
+ " nop \n"
+ ".set at \n"
+ ".set reorder \n" :
+ [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
+ : : "memory");
+
+}
+
+/**
+ * Attempts to get lock, returns immediately with success/failure
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @param word word to lock bit 31 of
+ * @return 0: lock successfully taken
+ * 1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__(".set noreorder \n" ".set noat \n" "1: ll %[tmp], %[val] \n" " bbit1 %[tmp], 31, 2f \n" /* if lock held, fail immediately */
+ " li $at, 1 \n"
+ " ins %[tmp], $at, 31, 1 \n"
+ " sc %[tmp], %[val] \n"
+ " beqz %[tmp], 1b \n"
+ " li %[tmp], 0 \n"
+ "2: \n"
+ ".set at \n"
+ ".set reorder \n" :
+ [val] "+m"(*word), [tmp] "=&r"(tmp)
+ : : "memory");
+
+ return tmp != 0; /* normalize to 0 or 1 */
+}
+
+/**
+ * Releases bit lock
+ *
+ * Unconditionally clears bit 31 of the lock word. Note that this is
+ * done non-atomically, as this implementation assumes that the rest
+ * of the bits in the word are protected by the lock.
+ *
+ * @param word word to unlock bit 31 in
+ */
+static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
+{
+ CVMX_SYNCWS;
+ *word &= ~(1UL << 31);
+ CVMX_SYNCWS;
+}
+
+/** ********************************************************************
+ * Recursive spinlocks
+ */
+typedef struct {
+ volatile unsigned int value;
+ volatile unsigned int core_num;
+} cvmx_spinlock_rec_t;
+
+/**
+ * Initialize a recursive spinlock
+ *
+ * @param lock Lock to initialize
+ */
+static inline void cvmx_spinlock_rec_init(cvmx_spinlock_rec_t *lock)
+{
+ lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+ * Return non-zero if the recursive spinlock is currently locked
+ *
+ * @param lock Lock to check
+ * @return Non-zero if locked
+ */
+static inline int cvmx_spinlock_rec_locked(cvmx_spinlock_rec_t *lock)
+{
+ return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+/**
+* Unlocks one level of recursive spinlock. Lock is not unlocked
+* unless this is the final unlock call for that spinlock
+*
+* @param lock ptr to recursive spinlock structure
+*/
+static inline void cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock);
+
+#ifdef CVMX_SPINLOCK_DEBUG
+#define cvmx_spinlock_rec_unlock(x) _int_cvmx_spinlock_rec_unlock((x), __FILE__, __LINE__)
+static inline void _int_cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock,
+ char *filename, int linenum)
+#else
+static inline void cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock)
+#endif
+{
+
+ unsigned int temp, result;
+ int core_num;
+ core_num = cvmx_get_core_num();
+
+#ifdef CVMX_SPINLOCK_DEBUG
+ {
+ if (lock->core_num != core_num) {
+ cvmx_dprintf
+ ("ERROR: Recursive spinlock release attemped by non-owner! file: %s, line: %d\n",
+ filename, linenum);
+ return;
+ }
+ }
+#endif
+
+ __asm__ __volatile__(".set noreorder \n"
+ " addi %[tmp], %[pid], 0x80 \n"
+ " sw %[tmp], %[lid] # set lid to invalid value\n"
+ CVMX_SYNCWS_STR
+ "1: ll %[tmp], %[val] \n"
+ " addu %[res], %[tmp], -1 # decrement lock count\n"
+ " sc %[res], %[val] \n"
+ " beqz %[res], 1b \n"
+ " nop \n"
+ " beq %[tmp], %[res], 2f # res is 1 on successful sc \n"
+ " nop \n"
+ " sw %[pid], %[lid] # set lid to pid, only if lock still held\n"
+ "2: \n"
+ CVMX_SYNCWS_STR
+ ".set reorder \n":[res]
+ "=&r"(result),[tmp] "=&r"(temp),
+ [val] "+m"(lock->value),[lid] "+m"(lock->core_num)
+ :[pid] "r"(core_num)
+ :"memory");
+
+#ifdef CVMX_SPINLOCK_DEBUG
+ {
+ if (lock->value == ~0UL) {
+ cvmx_dprintf
+ ("ERROR: Recursive spinlock released too many times! file: %s, line: %d\n",
+ filename, linenum);
+ }
+ }
+#endif
+
+}
+
+/**
+ * Takes recursive spinlock for a given core. A core can take the lock multiple
+ * times, and the lock is released only when the corresponding number of
+ * unlocks have taken place.
+ *
+ * NOTE: This assumes only one thread per core, and that the core ID is used as
+ * the lock 'key'. (This implementation cannot be generalized to allow
+ * multiple threads to use the same key (core id) .)
+ *
+ * @param lock address of recursive spinlock structure. Note that this is
+ * distinct from the standard spinlock
+ */
+static inline void cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock);
+
+#ifdef CVMX_SPINLOCK_DEBUG
+#define cvmx_spinlock_rec_lock(x) _int_cvmx_spinlock_rec_lock((x), __FILE__, __LINE__)
+static inline void _int_cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock,
+ char *filename, int linenum)
+#else
+static inline void cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock)
+#endif
+{
+
+ volatile unsigned int tmp;
+ volatile int core_num;
+
+ core_num = cvmx_get_core_num();
+
+ __asm__ __volatile__(".set noreorder \n"
+ "1: ll %[tmp], %[val] # load the count\n"
+ " bnez %[tmp], 2f # if count!=zero branch to 2\n"
+ " addu %[tmp], %[tmp], 1 \n"
+ " sc %[tmp], %[val] \n"
+ " beqz %[tmp], 1b # go back if not success\n"
+ " nop \n"
+ " j 3f # go to write core_num \n"
+ "2: lw %[tmp], %[lid] # load the core_num \n"
+ " bne %[tmp], %[pid], 1b # core_num no match, restart\n"
+ " nop \n"
+ " lw %[tmp], %[val] \n"
+ " addu %[tmp], %[tmp], 1 \n"
+ " sw %[tmp], %[val] # update the count\n"
+ "3: sw %[pid], %[lid] # store the core_num\n"
+ CVMX_SYNCWS_STR
+ ".set reorder \n":[tmp] "=&r"(tmp),
+ [val] "+m"(lock->value),[lid] "+m"(lock->core_num)
+ :[pid] "r"(core_num)
+ :"memory");
+
+#ifdef CVMX_SPINLOCK_DEBUG
+ if (lock->core_num != core_num) {
+ cvmx_dprintf
+ ("cvmx_spinlock_rec_lock: lock taken, but core_num is incorrect. file: %s, line: %d\n",
+ filename, linenum);
+ }
+#endif
+
+}
+
+#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
new file mode 100644
index 0000000..4f3c7ca
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -0,0 +1,113 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This module provides system/board/application information obtained by the bootloader.
+ *
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-sysinfo.h"
+
+/**
+ * This structure defines the private state maintained by sysinfo module.
+ *
+ */
+CVMX_SHARED static struct {
+
+ cvmx_sysinfo_t sysinfo; /**< system information */
+ cvmx_spinlock_t lock; /**< mutex spinlock */
+
+} state = {
+.lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER};
+
+
+/* Global variables that define the min/max of the memory region set up for 32 bit userspace access */
+uint64_t linux_mem32_min;
+uint64_t linux_mem32_max;
+uint64_t linux_mem32_wired;
+uint64_t linux_mem32_offset;
+
+/**
+ * This function returns the application information as obtained
+ * by the bootloader. This provides the core mask of the cores
+ * running the same application image, as well as the physical
+ * memory regions available to the core.
+ *
+ * @return Pointer to the boot information structure
+ *
+ */
+cvmx_sysinfo_t *cvmx_sysinfo_get(void)
+{
+ return &(state.sysinfo);
+}
+
+/**
+ * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
+ * to configure the minimal fields that are required to use
+ * simple executive files directly.
+ *
+ * Locking (if required) must be handled outside of this
+ * function
+ *
+ * @param phy_mem_desc_ptr
+ * Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param board_type Octeon board type enumeration
+ *
+ * @param board_rev_major
+ * Board major revision
+ * @param board_rev_minor
+ * Board minor revision
+ * @param cpu_clock_hz
+ * CPU clock freqency in hertz
+ *
+ * @return 0: Failure
+ * 1: success
+ */
+int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type,
+ uint8_t board_rev_major,
+ uint8_t board_rev_minor,
+ uint32_t cpu_clock_hz)
+{
+
+ /* The sysinfo structure was already initialized */
+ if (state.sysinfo.board_type)
+ return 0;
+
+ memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo));
+ state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr;
+ state.sysinfo.board_type = board_type;
+ state.sysinfo.board_rev_major = board_rev_major;
+ state.sysinfo.board_rev_minor = board_rev_minor;
+ state.sysinfo.cpu_clock_hz = cpu_clock_hz;
+
+ return 1;
+}
+
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.h b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.h
new file mode 100644
index 0000000..654624b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.h
@@ -0,0 +1,145 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * This module provides system/board information obtained by the bootloader.
+ *
+ * <hr>$Revision: 33999 $<hr>
+ *
+ */
+
+#ifndef __CVMX_SYSINFO_H__
+#define __CVMX_SYSINFO_H__
+
+#define OCTEON_SERIAL_LEN 20
+/**
+ * Structure describing application specific information.
+ * __cvmx_app_init() populates this from the cvmx boot descriptor.
+ * This structure is private to simple executive applications, so
+ * no versioning is required.
+ *
+ * This structure must be provided with some fields set in order to use
+ * simple executive functions in other applications (Linux kernel, u-boot, etc.)
+ * The cvmx_sysinfo_minimal_initialize() function is provided to set the required values
+ * in these cases.
+ *
+ *
+ */
+typedef struct {
+ /* System wide variables */
+ uint64_t system_dram_size;
+ /**< installed DRAM in system, in bytes */
+ void *phy_mem_desc_ptr;
+ /**< ptr to memory descriptor block */
+
+ /* Application image specific variables */
+ uint64_t stack_top;
+ /**< stack top address (virtual) */
+ uint64_t heap_base;
+ /**< heap base address (virtual) */
+ uint32_t stack_size;
+ /**< stack size in bytes */
+ uint32_t heap_size;
+ /**< heap size in bytes */
+ uint32_t core_mask;
+ /**< coremask defining cores running application */
+ uint32_t init_core;
+ /**< Deprecated, use cvmx_coremask_first_core() to select init core */
+ uint64_t exception_base_addr;
+ /**< exception base address, as set by bootloader */
+ uint32_t cpu_clock_hz;
+ /**< cpu clock speed in hz */
+ uint32_t dram_data_rate_hz;
+ /**< dram data rate in hz (data rate = 2 * clock rate */
+
+ uint16_t board_type;
+ uint8_t board_rev_major;
+ uint8_t board_rev_minor;
+ uint8_t mac_addr_base[6];
+ uint8_t mac_addr_count;
+ char board_serial_number[OCTEON_SERIAL_LEN];
+ /* Several boards support compact flash on the Octeon boot bus. The CF
+ ** memory spaces may be mapped to different addresses on different boards.
+ ** These values will be 0 if CF is not present.
+ ** Note that these addresses are physical addresses, and it is up to the application
+ ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
+ uint64_t compact_flash_common_base_addr;
+ uint64_t compact_flash_attribute_base_addr;
+ /* Base address of the LED display (as on EBT3000 board)
+ ** This will be 0 if LED display not present.
+ ** Note that this address is a physical address, and it is up to the application
+ ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
+ uint64_t led_display_base_addr;
+ uint32_t dfa_ref_clock_hz;
+ /**< DFA reference clock in hz (if applicable)*/
+ uint32_t bootloader_config_flags;
+ /**< configuration flags from bootloader */
+ uint8_t console_uart_num;
+ /** < Uart number used for console */
+} cvmx_sysinfo_t;
+
+/**
+ * This function returns the system/board information as obtained
+ * by the bootloader.
+ *
+ *
+ * @return Pointer to the boot information structure
+ *
+ */
+
+extern cvmx_sysinfo_t *cvmx_sysinfo_get(void);
+
+/**
+ * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
+ * to configure the minimal fields that are required to use
+ * simple executive files directly.
+ *
+ * Locking (if required) must be handled outside of this
+ * function
+ *
+ * @param phy_mem_desc_ptr
+ * Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param board_type Octeon board type enumeration
+ *
+ * @param board_rev_major
+ * Board major revision
+ * @param board_rev_minor
+ * Board minor revision
+ * @param cpu_clock_hz
+ * CPU clock freqency in hertz
+ *
+ * @return 0: Failure
+ * 1: success
+ */
+extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
+ uint16_t board_type,
+ uint8_t board_rev_major,
+ uint8_t board_rev_minor,
+ uint32_t cpu_clock_hz);
+
+#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-warn.c b/arch/mips/cavium-octeon/executive/cvmx-warn.c
new file mode 100644
index 0000000..46d2d58
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-warn.c
@@ -0,0 +1,45 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for warning users about errors and such.
+ *
+ * <hr>$Revision: 33871 $<hr>
+ *
+ */
+#include "cvmx.h"
+#include "cvmx-warn.h"
+
+void cvmx_warn(const char *format, ...)
+{
+ va_list args;
+ va_start(args, format);
+ printk("WARNING:");
+ vprintk(format, args);
+ va_end(args);
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-warn.h b/arch/mips/cavium-octeon/executive/cvmx-warn.h
new file mode 100644
index 0000000..2433f7b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-warn.h
@@ -0,0 +1,47 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for warning users about errors and such.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ *
+ */
+#ifndef __CVMX_WARN_H__
+#define __CVMX_WARN_H__
+
+#ifdef printf
+extern void cvmx_warn(const char *format, ...);
+#else
+extern void cvmx_warn(const char *format, ...)
+ __attribute__ ((format(printf, 1, 2)));
+#endif
+
+#define cvmx_warn_if(expression, format, ...) if (expression) cvmx_warn(format, ##__VA_ARGS__)
+
+#endif /* __CVMX_WARN_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx.h b/arch/mips/cavium-octeon/executive/cvmx.h
new file mode 100644
index 0000000..7e7e0e3
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx.h
@@ -0,0 +1,837 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Main Octeon executive header file (This should be the second header
+ * file included by an application).
+ *
+ */
+#ifndef __CVMX_H__
+#define __CVMX_H__
+
+/* Control whether simple executive applications use 1-1 TLB mappings
+** to access physical memory addresses. This must be disabled to
+** allow large programs that use more than the 0x10000000 - 0x20000000
+** virtual address range.
+*/
+#ifndef CVMX_USE_1_TO_1_TLB_MAPPINGS
+#define CVMX_USE_1_TO_1_TLB_MAPPINGS 1
+#endif
+
+#include "cvmx-platform.h"
+#include "cvmx-asm.h"
+#include "cvmx-packet.h"
+#include "cvmx-warn.h"
+#include "cvmx-sysinfo.h"
+
+/* To have a global variable be shared among all cores,
+ * declare with the CVMX_SHARED attribute. Ex:
+ * CVMX_SHARED int myglobal;
+ * This will cause the variable to be placed in a special
+ * section that the loader will map as shared for all cores
+ * This is for data structures use by software ONLY,
+ * as it is not 1-1 VA-PA mapped.
+ */
+#define CVMX_SHARED __attribute__ ((cvmx_shared))
+
+#define EXTERN_ASM extern
+
+#ifndef CVMX_ENABLE_PARAMETER_CHECKING
+#define CVMX_ENABLE_PARAMETER_CHECKING 1
+#endif
+
+#ifndef CVMX_ENABLE_DEBUG_PRINTS
+#define CVMX_ENABLE_DEBUG_PRINTS 1
+#endif
+
+#if CVMX_ENABLE_DEBUG_PRINTS
+#define cvmx_dprintf printk
+#else
+#define cvmx_dprintf(...) {}
+#endif
+
+#define CVMX_MAX_CORES (16)
+#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
+#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
+#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
+#define CAST64(v) ((long long)(long)(v))
+#define CASTPTR(type, v) ((type *)(long)(v))
+
+/* simprintf uses simulator tricks to speed up printouts. The format
+** and args are passed to the simulator and processed natively on the host.
+** Simprintf is limited to 7 arguments, and they all must use %ll (long long)
+** format specifiers to be displayed correctly.
+*/
+EXTERN_ASM void simprintf(const char *format, ...);
+
+/**
+ * This function performs some default initialization of the Octeon
+ * executive. It initializes the cvmx_bootmem memory allocator with
+ * the list of physical memory provided by the bootloader, and creates
+ * 1-1 TLB mappings for this memory. This function should be called
+ * on all cores that will use either the bootmem allocator or the 1-1
+ * TLB mappings. Applications which require a different configuration
+ * can replace this function with a suitable application specific one.
+ *
+ * @return 0 on success
+ * -1 on failure
+ */
+int cvmx_user_app_init(void);
+
+/* Returns processor ID, different Linux and simple exec versions
+** provided in the cvmx-app-init*.c files */
+static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
+static inline uint32_t cvmx_get_proc_id(void)
+{
+ uint32_t id;
+ asm("mfc0 %0, $15,0" : "=r"(id));
+ return id;
+}
+
+/* turn the variable name into a string */
+#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
+#define CVMX_TMP_STR2(x) #x
+/*
+ * The macros cvmx_likely and cvmx_unlikely use the
+ * __builtin_expect GCC operation to control branch
+ * probabilities for a conditional. For example, an "if"
+ * statement in the code that will almost always be
+ * executed should be written as "if (cvmx_likely(...))".
+ * If the "else" section of an if statement is more
+ * probable, use "if (cvmx_unlikey(...))".
+ */
+#define cvmx_likely(x) __builtin_expect(!!(x), 1)
+#define cvmx_unlikely(x) __builtin_expect(!!(x), 0)
+/**
+ * Builds a bit mask given the required size in bits.
+ *
+ * @param bits Number of bits in the mask
+ * @return The mask
+ */ static inline uint64_t cvmx_build_mask(uint64_t bits)
+{
+ return ~((~0x0ull) << bits);
+}
+
+/**
+ * Builds a memory address for I/O based on the Major and Sub DID.
+ *
+ * @param major_did 5 bit major did
+ * @param sub_did 3 bit sub did
+ * @return I/O base address
+ */
+static inline uint64_t cvmx_build_io_address(uint64_t major_did,
+ uint64_t sub_did)
+{
+ return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
+}
+
+/**
+ * Perform mask and shift to place the supplied value into
+ * the supplied bit rage.
+ *
+ * Example: cvmx_build_bits(39,24,value)
+ * <pre>
+ * 6 5 4 3 3 2 1
+ * 3 5 7 9 1 3 5 7 0
+ * +-------+-------+-------+-------+-------+-------+-------+------+
+ * 000000000000000000000000___________value000000000000000000000000
+ * </pre>
+ *
+ * @param high_bit Highest bit value can occupy (inclusive) 0-63
+ * @param low_bit Lowest bit value can occupy inclusive 0-high_bit
+ * @param value Value to use
+ * @return Value masked and shifted
+ */
+static inline uint64_t cvmx_build_bits(uint64_t high_bit,
+ uint64_t low_bit, uint64_t value)
+{
+ return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
+}
+
+#ifndef TRUE
+#define FALSE 0
+#define TRUE (!(FALSE))
+#endif
+
+typedef enum {
+ CVMX_MIPS_SPACE_XKSEG = 3LL,
+ CVMX_MIPS_SPACE_XKPHYS = 2LL,
+ CVMX_MIPS_SPACE_XSSEG = 1LL,
+ CVMX_MIPS_SPACE_XUSEG = 0LL
+} cvmx_mips_space_t;
+
+typedef enum {
+ CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
+ CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
+ CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
+ CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
+} cvmx_mips_xkseg_space_t;
+
+/* decodes <14:13> of a kseg3 window address */
+typedef enum {
+ CVMX_ADD_WIN_SCR = 0L,
+ /* see cvmx_add_win_dma_dec_t for further decode */
+ CVMX_ADD_WIN_DMA = 1L,
+ CVMX_ADD_WIN_UNUSED = 2L,
+ CVMX_ADD_WIN_UNUSED2 = 3L
+} cvmx_add_win_dec_t;
+
+/* decode within DMA space */
+typedef enum {
+ /* add store data to the write buffer entry, allocating it if
+ * necessary */
+ CVMX_ADD_WIN_DMA_ADD = 0L,
+ /* send out the write buffer entry to DRAM */
+ CVMX_ADD_WIN_DMA_SENDMEM = 1L,
+ /* store data must be normal DRAM memory space address in this
+ * case send out the write buffer entry as an IOBDMA
+ * command */
+ CVMX_ADD_WIN_DMA_SENDDMA = 2L,
+ /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
+ /* send out the write buffer entry as an IO write */
+ CVMX_ADD_WIN_DMA_SENDIO = 3L,
+ /* store data must be normal IO space address in this case */
+ /* send out a single-tick command on the NCB bus */
+ CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
+ /* no write buffer data needed/used */
+} cvmx_add_win_dma_dec_t;
+
+/**
+ * Physical Address Decode
+ *
+ * Octeon-I HW never interprets this X (<39:36> reserved
+ * for future expansion), software should set to 0.
+ *
+ * - 0x0 XXX0 0000 0000 to DRAM Cached
+ * - 0x0 XXX0 0FFF FFFF
+ *
+ * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
+ * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
+ *
+ * - 0x0 XXX0 2000 0000 to DRAM Cached
+ * - 0x0 XXXF FFFF FFFF
+ *
+ * - 0x1 00X0 0000 0000 to Boot Bus Uncached
+ * - 0x1 00XF FFFF FFFF
+ *
+ * - 0x1 01X0 0000 0000 to Other NCB Uncached
+ * - 0x1 FFXF FFFF FFFF devices
+ *
+ * Decode of all Octeon addresses
+ */
+typedef union {
+
+ uint64_t u64;
+
+ struct {
+ cvmx_mips_space_t R:2;
+ uint64_t offset:62;
+ } sva; /* mapped or unmapped virtual address */
+
+ struct {
+ uint64_t zeroes:33;
+ uint64_t offset:31;
+ } suseg; /* mapped USEG virtual addresses (typically) */
+
+ struct {
+ uint64_t ones:33;
+ cvmx_mips_xkseg_space_t sp:2;
+ uint64_t offset:29;
+ } sxkseg; /* mapped or unmapped virtual address */
+
+ struct {
+ cvmx_mips_space_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
+ uint64_t cca:3; /* ignored by octeon */
+ uint64_t mbz:10;
+ uint64_t pa:49; /* physical address */
+ } sxkphys; /* physical address accessed through xkphys unmapped virtual address */
+
+ struct {
+ uint64_t mbz:15;
+ uint64_t is_io:1; /* if set, the address is uncached and resides on MCB bus */
+ uint64_t did:8; /* the hardware ignores this field when is_io==0, else device ID */
+ uint64_t unaddr:4; /* the hardware ignores <39:36> in Octeon I */
+ uint64_t offset:36;
+ } sphys; /* physical address */
+
+ struct {
+ uint64_t zeroes:24; /* techically, <47:40> are dont-cares */
+ uint64_t unaddr:4; /* the hardware ignores <39:36> in Octeon I */
+ uint64_t offset:36;
+ } smem; /* physical mem address */
+
+ struct {
+ uint64_t mem_region:2;
+ uint64_t mbz:13;
+ uint64_t is_io:1; /* 1 in this case */
+ uint64_t did:8; /* the hardware ignores this field when is_io==0, else device ID */
+ uint64_t unaddr:4; /* the hardware ignores <39:36> in Octeon I */
+ uint64_t offset:36;
+ } sio; /* physical IO address */
+
+ struct {
+ uint64_t ones:49;
+ cvmx_add_win_dec_t csrdec:2; /* CVMX_ADD_WIN_SCR (0) in this case */
+ uint64_t addr:13;
+ } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */
+
+ /* there should only be stores to IOBDMA space, no loads */
+ struct {
+ uint64_t ones:49;
+ cvmx_add_win_dec_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */
+ uint64_t unused2:3;
+ cvmx_add_win_dma_dec_t type:3;
+ uint64_t addr:7;
+ } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */
+
+ struct {
+ uint64_t didspace:24;
+ uint64_t unused:40;
+ } sfilldidspace;
+
+} cvmx_addr_t;
+
+/* These macros for used by 32 bit applications */
+
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) (((int32_t)segment << 31) | (int32_t)(add))
+
+/* Currently all IOs are performed using XKPHYS addressing. Linux uses the
+ CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
+ Future OSes may need to change the upper bits of IO addresses. The
+ following define controls the upper two bits for all IO addresses generated
+ by the simple executive library */
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
+#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
+#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
+
+/* from include/ncb_rsl_id.v */
+#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
+#define CVMX_OCT_DID_GMX0 1ULL
+#define CVMX_OCT_DID_GMX1 2ULL
+#define CVMX_OCT_DID_PCI 3ULL
+#define CVMX_OCT_DID_KEY 4ULL
+#define CVMX_OCT_DID_FPA 5ULL
+#define CVMX_OCT_DID_DFA 6ULL
+#define CVMX_OCT_DID_ZIP 7ULL
+#define CVMX_OCT_DID_RNG 8ULL
+#define CVMX_OCT_DID_IPD 9ULL
+#define CVMX_OCT_DID_PKT 10ULL
+#define CVMX_OCT_DID_TIM 11ULL
+#define CVMX_OCT_DID_TAG 12ULL
+/* the rest are not on the IO bus */
+#define CVMX_OCT_DID_L2C 16ULL
+#define CVMX_OCT_DID_LMC 17ULL
+#define CVMX_OCT_DID_SPX0 18ULL
+#define CVMX_OCT_DID_SPX1 19ULL
+#define CVMX_OCT_DID_PIP 20ULL
+#define CVMX_OCT_DID_ASX0 22ULL
+#define CVMX_OCT_DID_ASX1 23ULL
+#define CVMX_OCT_DID_IOB 30ULL
+
+#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
+#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
+#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
+#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
+#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
+#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
+#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
+#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
+#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
+#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
+#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
+#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
+#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
+#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
+#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
+#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
+#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
+
+/**
+ * Convert a memory pointer (void*) into a hardware compatable
+ * memory address (uint64_t). Octeon hardware widgets don't
+ * understand logical addresses.
+ *
+ * @param ptr C style memory pointer
+ * @return Hardware physical address
+ */
+static inline uint64_t cvmx_ptr_to_phys(void *ptr)
+{
+ if (CVMX_ENABLE_PARAMETER_CHECKING)
+ cvmx_warn_if(ptr == NULL,
+ "cvmx_ptr_to_phys() passed a NULL pointer\n");
+ if (sizeof(void *) == 8) {
+ /* We're running in 64 bit mode. Normally this means that we can use
+ 40 bits of address space (the hardware limit). Unfortunately there
+ is one case were we need to limit this to 30 bits, sign extended
+ 32 bit. Although these are 64 bits wide, only 30 bits can be used */
+ if ((CAST64(ptr) >> 62) == 3)
+ return CAST64(ptr) & cvmx_build_mask(30);
+ else
+ return CAST64(ptr) & cvmx_build_mask(40);
+ } else {
+ return (long)(ptr) & 0x1fffffff;
+ }
+}
+
+/**
+ * Convert a hardware physical address (uint64_t) into a
+ * memory pointer (void *).
+ *
+ * @param physical_address
+ * Hardware physical address to memory
+ * @return Pointer to memory
+ */
+static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
+{
+ if (CVMX_ENABLE_PARAMETER_CHECKING)
+ cvmx_warn_if(physical_address == 0,
+ "cvmx_phys_to_ptr() passed a zero address\n");
+ if (sizeof(void *) == 8) {
+ /* Just set the top bit, avoiding any TLB uglyness */
+ return CASTPTR(void,
+ CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ physical_address));
+ } else {
+ return CASTPTR(void,
+ CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
+ physical_address));
+ }
+}
+
+#include "cvmx-csr.h"
+
+/* The following #if controls the definition of the macro
+ CVMX_BUILD_WRITE64. This macro is used to build a store operation to
+ a full 64bit address. With a 64bit ABI, this can be done with a simple
+ pointer access. 32bit ABIs require more complicated assembly */
+#if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+ a simple volatile pointer */
+#define CVMX_BUILD_WRITE64(TYPE, ST) \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
+{ \
+ *CASTPTR(volatile TYPE##_t, addr) = val; \
+}
+
+#elif defined(CVMX_ABI_N32)
+
+/* The N32 ABI passes all 64bit quantities in a single register, so it is
+ possible to use the arguments directly. We have to use inline assembly
+ for the actual store since a pointer would truncate the address */
+#define CVMX_BUILD_WRITE64(TYPE, ST) \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
+{ \
+ asm volatile (ST " %[v], 0(%[c])" : : [v] "r" (val), [c] "r" (addr)); \
+}
+
+#elif defined(CVMX_ABI_O32)
+
+#define CVMX_BUILD_WRITE64(TYPE, LT) extern void cvmx_write64_##TYPE(uint64_t csr_addr, TYPE##_t val);
+
+#else
+
+/* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
+#error Unsupported ABI
+
+#endif
+
+/* The following #if controls the definition of the macro
+ CVMX_BUILD_READ64. This macro is used to build a load operation from
+ a full 64bit address. With a 64bit ABI, this can be done with a simple
+ pointer access. 32bit ABIs require more complicated assembly */
+#if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+ a simple volatile pointer */
+#define CVMX_BUILD_READ64(TYPE, LT) \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
+{ \
+ return *CASTPTR(volatile TYPE##_t, addr); \
+}
+
+#elif defined(CVMX_ABI_N32)
+
+/* The N32 ABI passes all 64bit quantities in a single register, so it is
+ possible to use the arguments directly. We have to use inline assembly
+ for the actual store since a pointer would truncate the address */
+#define CVMX_BUILD_READ64(TYPE, LT) \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
+{ \
+ TYPE##_t val; \
+ asm volatile (LT " %[v], 0(%[c])" : [v] "=r" (val) : [c] "r" (addr)); \
+ return val; \
+}
+
+#elif defined(CVMX_ABI_O32)
+
+#define CVMX_BUILD_READ64(TYPE, LT) extern TYPE##_t cvmx_read64_##TYPE(uint64_t csr_addr);
+
+#else
+
+/* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
+#error Unsupported ABI
+
+#endif
+
+/* The following defines 8 functions for writing to a 64bit address. Each
+ takes two arguments, the address and the value to write.
+ cvmx_write64_int64 cvmx_write64_uint64
+ cvmx_write64_int32 cvmx_write64_uint32
+ cvmx_write64_int16 cvmx_write64_uint16
+ cvmx_write64_int8 cvmx_write64_uint8 */
+CVMX_BUILD_WRITE64(int64, "sd");
+CVMX_BUILD_WRITE64(int32, "sw");
+CVMX_BUILD_WRITE64(int16, "sh");
+CVMX_BUILD_WRITE64(int8, "sb");
+CVMX_BUILD_WRITE64(uint64, "sd");
+CVMX_BUILD_WRITE64(uint32, "sw");
+CVMX_BUILD_WRITE64(uint16, "sh");
+CVMX_BUILD_WRITE64(uint8, "sb");
+#define cvmx_write64 cvmx_write64_uint64
+
+/* The following defines 8 functions for reading from a 64bit address. Each
+ takes the address as the only argument
+ cvmx_read64_int64 cvmx_read64_uint64
+ cvmx_read64_int32 cvmx_read64_uint32
+ cvmx_read64_int16 cvmx_read64_uint16
+ cvmx_read64_int8 cvmx_read64_uint8 */
+CVMX_BUILD_READ64(int64, "ld");
+CVMX_BUILD_READ64(int32, "lw");
+CVMX_BUILD_READ64(int16, "lh");
+CVMX_BUILD_READ64(int8, "lb");
+CVMX_BUILD_READ64(uint64, "ld");
+CVMX_BUILD_READ64(uint32, "lw");
+CVMX_BUILD_READ64(uint16, "lhu");
+CVMX_BUILD_READ64(uint8, "lbu");
+#define cvmx_read64 cvmx_read64_uint64
+
+
+static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
+{
+ cvmx_write64(csr_addr, val);
+
+ /* Perform an immediate read after every write to an RSL register to force
+ the write to complete. It doesn't matter what RSL read we do, so we
+ choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
+ if ((csr_addr >> 40) == (0x800118))
+ cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
+}
+
+static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
+{
+ cvmx_write64(io_addr, val);
+
+}
+
+static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
+{
+ uint64_t val = cvmx_read64(csr_addr);
+ return val;
+}
+
+
+static inline void cvmx_send_single(uint64_t data)
+{
+ const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
+ cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
+}
+
+static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
+{
+ union {
+ uint64_t u64;
+ struct {
+ uint64_t scraddr:8;
+ uint64_t len:8;
+ uint64_t addr:48;
+ } s;
+ } addr;
+ addr.u64 = csr_addr;
+ addr.s.scraddr = scraddr >> 3;
+ addr.s.len = 1;
+ cvmx_send_single(addr.u64);
+}
+
+/* Return true if Octeon is CN38XX pass 1 */
+static inline int cvmx_octeon_is_pass1(void)
+{
+#if OCTEON_IS_COMMON_BINARY()
+ return 0; /* Pass 1 isn't supported for common binaries */
+#else
+/* Now that we know we're built for a specific model, only check CN38XX */
+#if OCTEON_IS_MODEL(OCTEON_CN38XX)
+ return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
+#else
+ return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
+#endif
+#endif
+}
+
+static inline unsigned int cvmx_get_core_num(void)
+{
+ unsigned int core_num;
+ CVMX_RDHWRNV(core_num, 0);
+ return core_num;
+}
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for POP instruction.
+ *
+ * @param val 32 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+static inline uint32_t cvmx_pop(uint32_t val)
+{
+ uint32_t pop;
+ CVMX_POP(pop, val);
+ return pop;
+}
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for DPOP instruction.
+ *
+ * @param val 64 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+static inline int cvmx_dpop(uint64_t val)
+{
+ int pop;
+ CVMX_DPOP(pop, val);
+ return pop;
+}
+
+/**
+ * Provide current cycle counter as a return value
+ *
+ * @return current cycle counter
+ */
+
+#if defined(CVMX_ABI_O32)
+static inline uint64_t cvmx_get_cycle(void)
+{
+ uint32_t tmp_low, tmp_hi;
+
+ asm volatile (" .set push \n"
+ " .set mips64r2 \n"
+ " .set noreorder \n"
+ " rdhwr %[tmpl], $31 \n"
+ " dsrl %[tmph], %[tmpl], 32 \n"
+ " sll %[tmpl], 0 \n"
+ " sll %[tmph], 0 \n"
+ " .set pop \n"
+ : [tmpl] "=&r"(tmp_low), [tmph] "=&r"(tmp_hi) :);
+
+ return ((uint64_t) tmp_hi << 32) + tmp_low;
+}
+#else
+static inline uint64_t cvmx_get_cycle(void)
+{
+ uint64_t cycle;
+ CVMX_RDHWR(cycle, 31);
+ return cycle;
+}
+#endif
+
+/**
+ * Reads a chip global cycle counter. This counts CPU cycles since
+ * chip reset. The counter is 64 bit.
+ * This register does not exist on CN38XX pass 1 silicion
+ *
+ * @return Global chip cycle count since chip reset.
+ */
+static inline uint64_t cvmx_get_cycle_global(void)
+{
+ if (cvmx_octeon_is_pass1())
+ return 0;
+ else
+ return cvmx_read64(CVMX_IPD_CLK_COUNT);
+}
+
+/**
+ * Wait for the specified number of cycle
+ *
+ * @param cycles
+ */
+static inline void cvmx_wait(uint64_t cycles)
+{
+ uint64_t done = cvmx_get_cycle() + cycles;
+
+ while (cvmx_get_cycle() < done) {
+ /* Spin */
+ }
+}
+
+/**
+ * Wait for the specified number of micro seconds
+ *
+ * @param usec micro seconds to wait
+ */
+static inline void cvmx_wait_usec(uint64_t usec)
+{
+ uint64_t done =
+ cvmx_get_cycle() +
+ usec * cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+ while (cvmx_get_cycle() < done) {
+ /* Spin */
+ }
+}
+
+/**
+ * This macro spins on a field waiting for it to reach a value. It
+ * is common in code to need to wait for a specific field in a CSR
+ * to match a specific value. Conceptually this macro expands to:
+ *
+ * 1) read csr at "address" with a csr typedef of "type"
+ * 2) Check if ("type".s."field" "op" "value")
+ * 3) If #2 isn't true loop to #1 unless too much time has passed.
+ */
+#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
+ ( \
+{ \
+ int result; \
+ do { \
+ uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
+ cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
+ type c; \
+ while (1) { \
+ c.u64 = cvmx_read_csr(address); \
+ if ((c.s.field) op(value)) { \
+ result = 0; \
+ break; \
+ } else if (cvmx_get_cycle() > done) { \
+ result = -1; \
+ break; \
+ } else \
+ cvmx_wait(100); \
+ } \
+ } while (0); \
+ result; \
+})
+
+/***************************************************************************/
+
+/* Watchdog defines, to be moved.... */
+typedef enum {
+ CVMX_CIU_WDOG_MODE_OFF = 0,
+ CVMX_CIU_WDOG_MODE_INT = 1,
+ CVMX_CIU_WDOG_MODE_INT_NMI = 2,
+ CVMX_CIU_WDOG_MODE_INT_NMI_SR = 3
+} cvmx_ciu_wdog_mode_t;
+
+static inline void cvmx_reset_octeon(void)
+{
+ cvmx_ciu_soft_rst_t ciu_soft_rst;
+ ciu_soft_rst.u64 = 0;
+ ciu_soft_rst.s.soft_rst = 1;
+ cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
+}
+
+/* Return the number of cores available in the chip */
+static inline uint32_t cvmx_octeon_num_cores(void)
+{
+ uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
+ return cvmx_pop(ciu_fuse);
+}
+
+/**
+ * Read a byte of fuse data
+ * @param byte_addr address to read
+ *
+ * @return fuse value: 0 or 1
+ */
+static uint8_t cvmx_fuse_read_byte(int byte_addr)
+{
+ cvmx_mio_fus_rcmd_t read_cmd;
+
+ read_cmd.u64 = 0;
+ read_cmd.s.addr = byte_addr;
+ read_cmd.s.pend = 1;
+ cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
+ while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
+ && read_cmd.s.pend)
+ ;
+ return read_cmd.s.dat;
+}
+
+/**
+ * Read a single fuse bit
+ *
+ * @param fuse Fuse number (0-1024)
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline int cvmx_fuse_read(int fuse)
+{
+ return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
+}
+
+static inline int cvmx_octeon_model_CN36XX(void)
+{
+ return OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && !cvmx_octeon_is_pass1()
+ && cvmx_fuse_read(264);
+}
+
+static inline int cvmx_octeon_zip_present(void)
+{
+ return octeon_has_feature(OCTEON_FEATURE_ZIP);
+}
+
+static inline int cvmx_octeon_dfa_present(void)
+{
+ if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && !OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && !OCTEON_IS_MODEL(OCTEON_CN58XX))
+ return 0;
+ else if (OCTEON_IS_MODEL(OCTEON_CN3020))
+ return 0;
+ else if (cvmx_octeon_is_pass1())
+ return 1;
+ else
+ return !cvmx_fuse_read(120);
+}
+
+static inline int cvmx_octeon_crypto_present(void)
+{
+ return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
+}
+
+#endif /* __CVMX_H__ */
diff --git a/arch/mips/cavium-octeon/executive/octeon-feature.h b/arch/mips/cavium-octeon/executive/octeon-feature.h
new file mode 100644
index 0000000..e57bd75
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/octeon-feature.h
@@ -0,0 +1,120 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * File defining checks for different Octeon features.
+ *
+ */
+
+#ifndef __OCTEON_FEATURE_H__
+#define __OCTEON_FEATURE_H__
+
+typedef enum {
+ /* Octeon models in the CN5XXX family and higher support
+ * atomic add instructions to memory (saa/saad) */
+ OCTEON_FEATURE_SAAD,
+ /* Does this Octeon support the ZIP offload engine? */
+ OCTEON_FEATURE_ZIP,
+ /* Does this Octeon support crypto acceleration using COP2? */
+ OCTEON_FEATURE_CRYPTO,
+ /* Does this Octeon support PCI express? */
+ OCTEON_FEATURE_PCIE,
+ /* Some Octeon models support internal memory for storing
+ * cryptographic keys */
+ OCTEON_FEATURE_KEY_MEMORY,
+ /* Octeon has a LED controller for banks of external LEDs */
+ OCTEON_FEATURE_LED_CONTROLLER,
+ /* Octeon has a trace buffer */
+ OCTEON_FEATURE_TRA,
+ /* Octeon has a management port */
+ OCTEON_FEATURE_MGMT_PORT,
+ /* Octeon has a raid unit */
+ OCTEON_FEATURE_RAID,
+ /* Octeon has a builtin USB */
+ OCTEON_FEATURE_USB,
+} octeon_feature_t;
+
+static inline int cvmx_fuse_read(int fuse);
+
+/**
+ * Determine if the current Octeon supports a specific feature. These
+ * checks have been optimized to be fairly quick, but they should still
+ * be kept out of fast path code.
+ *
+ * @param feature Feature to check for. This should always be a constant so the
+ * compiler can remove the switch statement through optimization.
+ *
+ * @return Non zero if the feature exists. Zero if the feature does not
+ * exist.
+ */
+static inline int octeon_has_feature(octeon_feature_t feature)
+{
+ switch (feature) {
+ case OCTEON_FEATURE_SAAD:
+ return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
+
+ case OCTEON_FEATURE_ZIP:
+ if (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX))
+ return 0;
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+ return 1;
+ else
+ return !cvmx_fuse_read(121);
+
+ case OCTEON_FEATURE_CRYPTO:
+ return !cvmx_fuse_read(90);
+
+ case OCTEON_FEATURE_PCIE:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+ case OCTEON_FEATURE_KEY_MEMORY:
+ case
+ OCTEON_FEATURE_LED_CONTROLLER:
+ return OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX);
+ case OCTEON_FEATURE_TRA:
+ return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX));
+ case OCTEON_FEATURE_MGMT_PORT:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX);
+ case OCTEON_FEATURE_RAID:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX);
+ case OCTEON_FEATURE_USB:
+ return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX));
+ }
+ return 0;
+}
+
+#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
new file mode 100644
index 0000000..ce079b6
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -0,0 +1,328 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * File defining functions for working with different Octeon
+ * models.
+ *
+ */
+#include "cvmx.h"
+
+#include "cvmx-warn.h"
+
+/**
+ * Given the chip processor ID from COP0, this function returns a
+ * string representing the chip model number. The string is of the
+ * form CNXXXXpX.X-FREQ-SUFFIX.
+ * - XXXX = The chip model number
+ * - X.X = Chip pass number
+ * - FREQ = Current frequency in Mhz
+ * - SUFFIX = NSP, EXP, SCP, SSP, or CP
+ *
+ * @param chip_id Chip ID
+ *
+ * @return Model string
+ */
+const char *octeon_model_get_string(uint32_t chip_id)
+{
+ static char buffer[32];
+ return octeon_model_get_string_buffer(chip_id, buffer);
+}
+
+/* Version of octeon_model_get_string() that takes buffer as argument, as
+** running early in u-boot static/global variables don't work when running from
+** flash
+*/
+const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
+{
+ extern uint64_t octeon_get_clock_rate(void);
+ const char *family;
+ const char *core_model;
+ char pass[4];
+ int clock_mhz;
+ const char *suffix;
+ cvmx_l2d_fus3_t fus3;
+ int num_cores;
+ cvmx_mio_fus_dat2_t fus_dat2;
+ cvmx_mio_fus_dat3_t fus_dat3;
+ char fuse_model[10];
+ uint32_t fuse_data = 0;
+
+ fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+ fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+ fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+ num_cores = __builtin_popcount(cvmx_read_csr(CVMX_CIU_FUSE));
+
+ /* Make sure the non existant devices look disabled */
+ switch ((chip_id >> 8) & 0xff) {
+ case 6: /* CN50XX */
+ case 2: /* CN30XX */
+ fus_dat3.s.nodfa_dte = 1;
+ fus_dat3.s.nozip = 1;
+ break;
+ case 4: /* CN57XX or CN56XX */
+ fus_dat3.s.nodfa_dte = 1;
+ break;
+ default:
+ break;
+ }
+
+ /* Make a guess at the suffix */
+ /* NSP = everything */
+ /* EXP = No crypto */
+ /* SCP = No DFA, No zip */
+ /* CP = No DFA, No crypto, No zip */
+ if (fus_dat3.s.nodfa_dte) {
+ if (fus_dat2.s.nocrypto)
+ suffix = "CP";
+ else
+ suffix = "SCP";
+ } else if (fus_dat2.s.nocrypto)
+ suffix = "EXP";
+ else
+ suffix = "NSP";
+
+ /* Assume pass number is encoded using <5:3><2:0>. Exceptions will be
+ fixed later */
+ sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
+
+ /* Use the number of cores to determine the last 2 digits of the model
+ number. There are some exceptions that are fixed later */
+ switch (num_cores) {
+ case 16:
+ core_model = "60";
+ break;
+ case 15:
+ case 14:
+ core_model = "55";
+ break;
+ case 13:
+ case 12:
+ core_model = "50";
+ break;
+ case 11:
+ case 10:
+ core_model = "45";
+ break;
+ case 9:
+ core_model = "42";
+ break;
+ case 8:
+ core_model = "40";
+ break;
+ case 7:
+ case 6:
+ core_model = "34";
+ break;
+ case 5:
+ core_model = "32";
+ break;
+ case 4:
+ core_model = "30";
+ break;
+ case 3:
+ core_model = "25";
+ break;
+ case 2:
+ core_model = "20";
+ break;
+ case 1:
+ core_model = "10";
+ break;
+ default:
+ core_model = "XX";
+ break;
+ }
+
+ /* Now figure out the family, the first two digits */
+ switch ((chip_id >> 8) & 0xff) {
+ case 0: /* CN38XX, CN37XX or CN36XX */
+ if (fus3.cn38xx.crip_512k) {
+ /* For some unknown reason, the 16 core one is
+ * called 37 instead of 36 */
+ if (num_cores >= 16)
+ family = "37";
+ else
+ family = "36";
+ } else
+ family = "38";
+ /* This series of chips didn't follow the standard
+ * pass numbering */
+ switch (chip_id & 0xf) {
+ case 0:
+ strcpy(pass, "1.X");
+ break;
+ case 1:
+ strcpy(pass, "2.X");
+ break;
+ case 3:
+ strcpy(pass, "3.X");
+ break;
+ default:
+ strcpy(pass, "X.X");
+ break;
+ }
+ break;
+ case 1: /* CN31XX or CN3020 */
+ if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
+ family = "30";
+ else
+ family = "31";
+ /* This series of chips didn't follow the standard
+ * pass numbering */
+ switch (chip_id & 0xf) {
+ case 0:
+ strcpy(pass, "1.0");
+ break;
+ case 2:
+ strcpy(pass, "1.1");
+ break;
+ default:
+ strcpy(pass, "X.X");
+ break;
+ }
+ break;
+ case 2: /* CN3010 or CN3005 */
+ family = "30";
+ /* A chip with half cache is an 05 */
+ if (fus3.cn30xx.crip_64k)
+ core_model = "05";
+ /* This series of chips didn't follow the standard
+ * pass numbering */
+ switch (chip_id & 0xf) {
+ case 0:
+ strcpy(pass, "1.0");
+ break;
+ case 2:
+ strcpy(pass, "1.1");
+ break;
+ default:
+ strcpy(pass, "X.X");
+ break;
+ }
+ break;
+ case 3: /* CN58XX */
+ family = "58";
+ /* Special case. 4 core, no crypto */
+ if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
+ core_model = "29";
+
+ /* Pass 1 uses different encodings for pass numbers */
+ if ((chip_id & 0xFF) < 0x8) {
+ switch (chip_id & 0x3) {
+ case 0:
+ strcpy(pass, "1.0");
+ break;
+ case 1:
+ strcpy(pass, "1.1");
+ break;
+ case 3:
+ strcpy(pass, "1.2");
+ break;
+ default:
+ strcpy(pass, "1.X");
+ break;
+ }
+ }
+ break;
+ case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
+ if (fus_dat2.cn56xx.raid_en) {
+ if (fus3.cn56xx.crip_1024k)
+ family = "55";
+ else
+ family = "57";
+ if (fus_dat2.cn56xx.nocrypto)
+ suffix = "SP";
+ else
+ suffix = "SSP";
+ } else {
+ if (fus_dat2.cn56xx.nocrypto)
+ suffix = "CP";
+ else {
+ suffix = "NSP";
+ if (fus_dat3.s.nozip)
+ suffix = "SCP";
+ }
+ if (fus3.cn56xx.crip_1024k)
+ family = "54";
+ else
+ family = "56";
+ }
+ break;
+ case 6: /* CN50XX */
+ family = "50";
+ break;
+ case 7: /* CN52XX */
+ family = "52";
+ break;
+ case 8: /* CN51XX */
+ family = "51";
+ break;
+ default:
+ family = "XX";
+ core_model = "XX";
+ strcpy(pass, "X.X");
+ suffix = "XXX";
+ break;
+ }
+
+ clock_mhz = octeon_get_clock_rate() / 1000000;
+
+ /* Check for model in fuses, overrides normal decode */
+ fuse_data |= cvmx_fuse_read_byte(51);
+ fuse_data = fuse_data << 8;
+ fuse_data |= cvmx_fuse_read_byte(50);
+ fuse_data = fuse_data << 8;
+ fuse_data |= cvmx_fuse_read_byte(49);
+ fuse_data = fuse_data << 8;
+ fuse_data |= cvmx_fuse_read_byte(48);
+ if (fuse_data & 0x7ffff) {
+ int model = fuse_data & 0x3fff;
+ int suffix = (fuse_data >> 14) & 0x1f;
+ if (suffix && model) {
+ /* Have both number and suffix in fuses, so both */
+ sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
+ core_model = "";
+ family = fuse_model;
+ } else if (suffix && !model) {
+ /* Only have suffix, so add suffix to 'normal'
+ * model number */
+ sprintf(fuse_model, "%s%c", core_model,
+ 'A' + suffix - 1);
+ core_model = fuse_model;
+ } else {
+ /* Don't have suffix, so just use model from fuses */
+ sprintf(fuse_model, "%d", model);
+ core_model = "";
+ family = fuse_model;
+ }
+ }
+ sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz,
+ suffix);
+ return buffer;
+}
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.h b/arch/mips/cavium-octeon/executive/octeon-model.h
new file mode 100644
index 0000000..3f58f00
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/octeon-model.h
@@ -0,0 +1,231 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * File defining different Octeon model IDs and macros to
+ * compare them.
+ *
+ */
+
+#ifndef __OCTEON_MODEL_H__
+#define __OCTEON_MODEL_H__
+
+/* NOTE: These must match what is checked in common-config.mk */
+/* Defines to represent the different versions of Octeon. */
+
+/* IMPORTANT: When the default pass is updated for an Octeon Model,
+** the corresponding change must also be made in the oct-sim script. */
+
+/* The defines below should be used with the OCTEON_IS_MODEL() macro to
+** determine what model of chip the software is running on. Models ending
+** in 'XX' match multiple models (families), while specific models match only
+** that model. If a pass (revision) is specified, then only that revision
+** will be matched. Care should be taken when checking for both specific
+** models and families that the specific models are checked for first.
+** While these defines are similar to the processor ID, they are not intended
+** to be used by anything other that the OCTEON_IS_MODEL framework, and
+** the values are subject to change at anytime without notice.
+**
+** NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* macros
+** should be used outside of this file. All other macros are for internal
+** use only, and may change without notice.
+*/
+
+/* Flag bits in top byte */
+/* Ignores revision in model checks */
+#define OM_IGNORE_REVISION 0x01000000
+/* Ignores submodels */
+#define OM_IGNORE_SUBMODEL 0x02000000
+/* Match all models previous than the one specified */
+#define OM_MATCH_PREVIOUS_MODELS 0x04000000
+
+#define OCTEON_CN56XX_PASS1 0x000d0400
+#define OCTEON_CN56XX_PASS1_1 0x000d0401
+#define OCTEON_CN56XX_PASS2 0x000d0408
+#define OCTEON_CN56XX (OCTEON_CN56XX_PASS1 \
+ | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)
+
+/* NOTE: Octeon CN57XX, CN55XX, and CN54XX models are not identifiable
+ using the OCTEON_IS_MODEL() functions, but are treated as
+ CN56XX */
+
+#define OCTEON_CN58XX_PASS1 0x000d0300
+#define OCTEON_CN58XX_PASS1_1 0x000d0301
+#define OCTEON_CN58XX_PASS1_2 0x000d0303
+#define OCTEON_CN58XX_PASS2 0x000d0308
+#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+
+#define OCTEON_CN50XX_PASS1 0x000d0600
+#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+
+/* NOTE: Octeon CN5000F model is not identifiable using the OCTEON_IS_MODEL()
+ functions, but are treated as CN50XX */
+
+#define OCTEON_CN52XX_PASS1 0x000d0700
+#define OCTEON_CN52XX (OCTEON_CN52XX_PASS1 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+
+#define OCTEON_CN38XX_PASS1 0x000d0000
+#define OCTEON_CN38XX_PASS2 0x000d0001
+#define OCTEON_CN38XX_PASS3 0x000d0003
+#define OCTEON_CN38XX (OCTEON_CN38XX_PASS2 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+
+/* NOTE: OCTEON CN36XX models are not identifiable using the
+** OCTEON_IS_MODEL() functions, but are treated as 38XX with a smaller
+** L2 cache. Setting OCTEON_MODEL to OCTEON_CN36XX will not affect
+** how the program is built (it will be built for OCTEON_CN38XX) but
+** does cause the simulator to properly simulate the smaller L2
+** cache. */
+
+/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
+#define OCTEON_CN31XX_PASS1 0x000d0100
+#define OCTEON_CN31XX_PASS1_1 0x000d0102
+#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+
+#define OCTEON_CN3005_PASS1 0x000d0210
+#define OCTEON_CN3005_PASS1_1 0x000d0212
+#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN3010_PASS1 0x000d0200
+#define OCTEON_CN3010_PASS1_1 0x000d0202
+#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN3020_PASS1 0x000d0110
+#define OCTEON_CN3020_PASS1_1 0x000d0112
+#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION)
+
+/* This model is only used for internal checks, it
+** is not valid model for the OCTEON_MODEL environment variable.
+** This matches the CN3010 and CN3005 but NOT the CN3020*/
+#define OCTEON_CN30XX (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
+ | OM_IGNORE_SUBMODEL)
+#define OCTEON_CN30XX_PASS1 (OCTEON_CN3010_PASS1 | OM_IGNORE_SUBMODEL)
+#define OCTEON_CN30XX_PASS1_1 (OCTEON_CN3010_PASS1_1 | OM_IGNORE_SUBMODEL)
+
+/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
+#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1 \
+ | OM_MATCH_PREVIOUS_MODELS \
+ | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)
+
+/* The revision byte (low byte) has two different encodings.
+** CN3XXX:
+**
+** bits
+** <7:5>: reserved (0)
+** <4>: alternate package
+** <3:0>: revision
+**
+** CN5XXX:
+**
+** bits
+** <7>: reserved (0)
+** <6>: alternate package
+** <5:3>: major revision
+** <2:0>: minor revision
+**
+*/
+
+/* Masks used for the various types of model/family/revision matching */
+#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
+#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
+#define OCTEON_38XX_MODEL_MASK 0x00ffff10
+#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
+ | OCTEON_38XX_MODEL_MASK)
+
+/* CN5XXX and use different layout of bits in the revision ID field */
+#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
+#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
+#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
+#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
+ | OCTEON_58XX_MODEL_MASK)
+
+#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
+
+/* NOTE: This for internal use only!!!!! */
+#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
+ ((((arg_model & OCTEON_38XX_FAMILY_MASK) <= OCTEON_CN3010_PASS1) && (\
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == OM_IGNORE_REVISION) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == OM_IGNORE_SUBMODEL) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == (OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == 0) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
+ )) || \
+ (((arg_model & OCTEON_38XX_FAMILY_MASK) > OCTEON_CN3010_PASS1) && (\
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == OM_IGNORE_REVISION) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == OM_IGNORE_SUBMODEL) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == (OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION | OM_IGNORE_SUBMODEL)) == 0) && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
+ ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
+ )))
+
+#if defined(USE_RUNTIME_MODEL_CHECKS) \
+ || (defined(__linux__) && defined(__KERNEL__))
+/* forward declarations */
+static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
+static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
+
+/* NOTE: This for internal use only!!!!! */
+static inline int __octeon_is_model_runtime__(uint32_t model)
+{
+ uint32_t cpuid = cvmx_get_proc_id();
+
+ /* Check for special case of mismarked 3005 samples. We only
+ need to check if the sub model isn't being ignored */
+ if ((model & OM_IGNORE_SUBMODEL) == 0) {
+ if (cpuid == OCTEON_CN3010_PASS1
+ && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+ cpuid |= 0x10;
+ }
+ return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
+}
+
+/* The OCTEON_IS_MODEL macro should be used for all Octeon model
+** checking done in a program. This should be kept runtime if at all
+** possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
+** condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
+** support is required.
+**
+*/
+#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
+#define OCTEON_IS_COMMON_BINARY() 1
+#undef OCTEON_MODEL
+#else
+#define OCTEON_IS_MODEL(x) __OCTEON_IS_MODEL_COMPILE__(x, OCTEON_MODEL)
+#define OCTEON_IS_COMMON_BINARY() 0
+#endif
+
+const char *octeon_model_get_string(uint32_t chip_id);
+const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
+
+#include "octeon-feature.h"
+
+#endif /* __OCTEON_MODEL_H__ */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 06/37] Add Cavium OCTEON processor CSR definitions
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (4 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 05/37] Add Cavium OCTEON processor support files to and arch/mips/cavium-octeon/executive ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 07/37] Don't assume boot CPU is CPU0 if MIPS_DISABLE_BOOT_CPU_ZERO set ddaney
` (30 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
.../cavium-octeon/executive/cvmx-csr-addresses.h |17513 ++++++++
arch/mips/cavium-octeon/executive/cvmx-csr-enums.h | 86 +
.../cavium-octeon/executive/cvmx-csr-typedefs.h |44156 ++++++++++++++++++++
arch/mips/cavium-octeon/executive/cvmx-csr.h | 202 +
4 files changed, 61957 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-csr-addresses.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-csr-enums.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-csr-typedefs.h
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-csr.h
diff --git a/arch/mips/cavium-octeon/executive/cvmx-csr-addresses.h b/arch/mips/cavium-octeon/executive/cvmx-csr-addresses.h
new file mode 100644
index 0000000..c9e340e
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-csr-addresses.h
@@ -0,0 +1,17513 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and for
+ * Octeon. Include cvmx-csr.h instead of this file directly.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 35609 $<hr>
+ *
+ */
+#ifndef __CVMX_CSR_ADDRESSES_H__
+#define __CVMX_CSR_ADDRESSES_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#include "cvmx-warn.h"
+#endif
+
+#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
+}
+
+#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
+}
+
+#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC()
+static inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
+}
+
+#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + (offset & 1) * 8;
+}
+
+#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
+}
+
+#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + (offset & 1) * 2048;
+}
+
+#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + (offset & 1) * 2048;
+}
+
+#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
+}
+
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
+}
+
+#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
+}
+
+#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
+}
+
+#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
+}
+
+#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
+}
+
+#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
+}
+
+#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
+}
+
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
+}
+
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
+}
+
+#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
+}
+
+#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
+}
+
+static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000180ull) +
+ (block_id & 0) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000188ull) +
+ (block_id & 0) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000018ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000010ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000190ull) +
+ (block_id & 0) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000040ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000248ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000250ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000220ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000218ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000210ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000230ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000240ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000228ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000238ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000258ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000000ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000100ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000108ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000118ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000110ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000068ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000008ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+#define CVMX_CIU_BIST CVMX_CIU_BIST_FUNC()
+static inline uint64_t CVMX_CIU_BIST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000730ull);
+}
+
+#define CVMX_CIU_DINT CVMX_CIU_DINT_FUNC()
+static inline uint64_t CVMX_CIU_DINT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000720ull);
+}
+
+#define CVMX_CIU_FUSE CVMX_CIU_FUSE_FUNC()
+static inline uint64_t CVMX_CIU_FUSE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000728ull);
+}
+
+#define CVMX_CIU_GSTOP CVMX_CIU_GSTOP_FUNC()
+static inline uint64_t CVMX_CIU_GSTOP_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000710ull);
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 1) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))))
+ cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000200ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000002200ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000006200ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 1) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))))
+ cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000208ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000002208ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000006208ull) + (offset & 63) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+ cvmx_warn
+ ("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + (offset & 15) * 16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 23) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 1) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 3) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 7) || (offset == 32)))))
+ cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000000ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + (offset & 15) * 8;
+}
+
+#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
+static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000108ull);
+}
+
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset & 15) * 8;
+}
+
+static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset & 15) * 8;
+}
+
+#define CVMX_CIU_NMI CVMX_CIU_NMI_FUNC()
+static inline uint64_t CVMX_CIU_NMI_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000718ull);
+}
+
+#define CVMX_CIU_PCI_INTA CVMX_CIU_PCI_INTA_FUNC()
+static inline uint64_t CVMX_CIU_PCI_INTA_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000750ull);
+}
+
+#define CVMX_CIU_PP_DBG CVMX_CIU_PP_DBG_FUNC()
+static inline uint64_t CVMX_CIU_PP_DBG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000708ull);
+}
+
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset & 15) * 8;
+}
+
+#define CVMX_CIU_PP_RST CVMX_CIU_PP_RST_FUNC()
+static inline uint64_t CVMX_CIU_PP_RST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000700ull);
+}
+
+#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
+static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000760ull);
+}
+
+#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000768ull);
+}
+
+#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000770ull);
+}
+
+#define CVMX_CIU_SOFT_BIST CVMX_CIU_SOFT_BIST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_BIST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000738ull);
+}
+
+#define CVMX_CIU_SOFT_PRST CVMX_CIU_SOFT_PRST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000748ull);
+}
+
+#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000758ull);
+}
+
+#define CVMX_CIU_SOFT_RST CVMX_CIU_SOFT_RST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_RST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000740ull);
+}
+
+static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000480ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset & 15) * 8;
+}
+
+#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
+static inline uint64_t CVMX_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
+}
+
+#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
+static inline uint64_t CVMX_DFA_BST0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
+}
+
+#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
+static inline uint64_t CVMX_DFA_BST1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
+}
+
+#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
+static inline uint64_t CVMX_DFA_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000000ull);
+}
+
+#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
+static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001370000000000ull);
+}
+
+#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000210ull);
+}
+
+#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000080ull);
+}
+
+#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000208ull);
+}
+
+#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000090ull);
+}
+
+#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000268ull);
+}
+
+#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000078ull);
+}
+
+#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000260ull);
+}
+
+#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000070ull);
+}
+
+#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000088ull);
+}
+
+#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000218ull);
+}
+
+#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
+static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001370600000000ull);
+}
+
+#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
+static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001370200000000ull);
+}
+
+#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
+static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000200ull);
+}
+
+#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
+static inline uint64_t CVMX_DFA_ERR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000028ull);
+}
+
+#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000008ull);
+}
+
+#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000010ull);
+}
+
+#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000060ull);
+}
+
+#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000030ull);
+}
+
+#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000038ull);
+}
+
+#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
+static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000018ull);
+}
+
+#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
+static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000020ull);
+}
+
+#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
+static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000068ull);
+}
+
+#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000040ull);
+}
+
+#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000048ull);
+}
+
+#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000050ull);
+}
+
+#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180030000058ull);
+}
+
+#define CVMX_FPA_BIST_STATUS CVMX_FPA_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_BIST_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800280000E8ull);
+}
+
+#define CVMX_FPA_CTL_STATUS CVMX_FPA_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_CTL_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180028000050ull);
+}
+
+#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180028000000ull);
+}
+
+#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180028000058ull);
+}
+
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 1) && (offset <= 7))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset >= 1) && (offset <= 7))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset >= 1) && (offset <= 7))))))
+ cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180028000008ull) + (offset & 7) * 8 -
+ 8 * 1;
+}
+
+static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 1) && (offset <= 7))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset >= 1) && (offset <= 7))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset >= 1) && (offset <= 7))))))
+ cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180028000060ull) + (offset & 7) * 8 -
+ 8 * 1;
+}
+
+#define CVMX_FPA_INT_ENB CVMX_FPA_INT_ENB_FUNC()
+static inline uint64_t CVMX_FPA_INT_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180028000048ull);
+}
+
+#define CVMX_FPA_INT_SUM CVMX_FPA_INT_SUM_FUNC()
+static inline uint64_t CVMX_FPA_INT_SUM_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180028000040ull);
+}
+
+#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
+#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
+#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
+#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
+#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
+#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
+#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
+#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
+static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180028000098ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + (offset & 7) * 8;
+}
+
+#define CVMX_FPA_QUE_ACT CVMX_FPA_QUE_ACT_FUNC()
+static inline uint64_t CVMX_FPA_QUE_ACT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180028000138ull);
+}
+
+#define CVMX_FPA_QUE_EXP CVMX_FPA_QUE_EXP_FUNC()
+static inline uint64_t CVMX_FPA_QUE_EXP_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180028000130ull);
+}
+
+#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC()
+static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800280000D8ull);
+}
+
+#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800280000E0ull);
+}
+
+static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000518ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000400ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080007F0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000550ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080007F8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000510ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset == 0)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset == 0)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((offset & 0) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000030ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000028ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000060ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000548ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080005F8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 15)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 15)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((offset & 15) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000410ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004E8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080007E8ull) +
+ (block_id & 0) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000538ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000530ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000520ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset == 0)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset == 0)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((offset & 0) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset == 0)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset == 0)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((offset & 0) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000208ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 2)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x10000ull) * 2048;
+}
+
+static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004D0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 1)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 1)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000780ull) + ((offset & 1) +
+ (block_id & 0) *
+ 0x0ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000498ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004D8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000558ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000560ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000488ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000508ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000500ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000490ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004F8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004C8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004A0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004A8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000480ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004C0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004E0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004B0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 31)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000680ull) + ((offset & 31) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800080004B8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000528ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180008000540ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+ cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000800ull) + (offset & 15) * 8;
+}
+
+#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
+}
+
+static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + (offset & 3) * 8;
+}
+
+#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
+}
+
+#define CVMX_GPIO_INT_CLR CVMX_GPIO_INT_CLR_FUNC()
+static inline uint64_t CVMX_GPIO_INT_CLR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000898ull);
+}
+
+#define CVMX_GPIO_RX_DAT CVMX_GPIO_RX_DAT_FUNC()
+static inline uint64_t CVMX_GPIO_RX_DAT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000880ull);
+}
+
+#define CVMX_GPIO_TX_CLR CVMX_GPIO_TX_CLR_FUNC()
+static inline uint64_t CVMX_GPIO_TX_CLR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000890ull);
+}
+
+#define CVMX_GPIO_TX_SET CVMX_GPIO_TX_SET_FUNC()
+static inline uint64_t CVMX_GPIO_TX_SET_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001070000000888ull);
+}
+
+static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset >= 16) && (offset <= 23))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset >= 16) && (offset <= 23))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset >= 16) && (offset <= 23))))))
+ cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000000900ull) + (offset & 31) * 8 -
+ 8 * 16;
+}
+
+#define CVMX_IOB_BIST_STATUS CVMX_IOB_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_IOB_BIST_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F00007F8ull);
+}
+
+#define CVMX_IOB_CTL_STATUS CVMX_IOB_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_IOB_CTL_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000050ull);
+}
+
+#define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
+}
+
+#define CVMX_IOB_FAU_TIMEOUT CVMX_IOB_FAU_TIMEOUT_FUNC()
+static inline uint64_t CVMX_IOB_FAU_TIMEOUT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000000ull);
+}
+
+#define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
+}
+
+#define CVMX_IOB_INB_CONTROL_MATCH CVMX_IOB_INB_CONTROL_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000078ull);
+}
+
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000088ull);
+}
+
+#define CVMX_IOB_INB_DATA_MATCH CVMX_IOB_INB_DATA_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_INB_DATA_MATCH_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000070ull);
+}
+
+#define CVMX_IOB_INB_DATA_MATCH_ENB CVMX_IOB_INB_DATA_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INB_DATA_MATCH_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000080ull);
+}
+
+#define CVMX_IOB_INT_ENB CVMX_IOB_INT_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INT_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000060ull);
+}
+
+#define CVMX_IOB_INT_SUM CVMX_IOB_INT_SUM_FUNC()
+static inline uint64_t CVMX_IOB_INT_SUM_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000058ull);
+}
+
+#define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
+}
+
+#define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
+}
+
+#define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
+}
+
+#define CVMX_IOB_OUTB_CONTROL_MATCH CVMX_IOB_OUTB_CONTROL_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000098ull);
+}
+
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F00000A8ull);
+}
+
+#define CVMX_IOB_OUTB_DATA_MATCH CVMX_IOB_OUTB_DATA_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000090ull);
+}
+
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F00000A0ull);
+}
+
+#define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
+}
+
+#define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
+}
+
+#define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
+}
+
+#define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
+static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
+}
+
+#define CVMX_IPD_1ST_MBUFF_SKIP CVMX_IPD_1ST_MBUFF_SKIP_FUNC()
+static inline uint64_t CVMX_IPD_1ST_MBUFF_SKIP_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000000ull);
+}
+
+#define CVMX_IPD_1st_NEXT_PTR_BACK CVMX_IPD_1st_NEXT_PTR_BACK_FUNC()
+static inline uint64_t CVMX_IPD_1st_NEXT_PTR_BACK_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000150ull);
+}
+
+#define CVMX_IPD_2nd_NEXT_PTR_BACK CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC()
+static inline uint64_t CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000158ull);
+}
+
+#define CVMX_IPD_BIST_STATUS CVMX_IPD_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_IPD_BIST_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F00000007F8ull);
+}
+
+#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC()
+static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
+}
+
+#define CVMX_IPD_CLK_COUNT CVMX_IPD_CLK_COUNT_FUNC()
+static inline uint64_t CVMX_IPD_CLK_COUNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000338ull);
+}
+
+#define CVMX_IPD_CTL_STATUS CVMX_IPD_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_IPD_CTL_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000018ull);
+}
+
+#define CVMX_IPD_INT_ENB CVMX_IPD_INT_ENB_FUNC()
+static inline uint64_t CVMX_IPD_INT_ENB_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000160ull);
+}
+
+#define CVMX_IPD_INT_SUM CVMX_IPD_INT_SUM_FUNC()
+static inline uint64_t CVMX_IPD_INT_SUM_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000168ull);
+}
+
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC()
+static inline uint64_t CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000008ull);
+}
+
+#define CVMX_IPD_PACKET_MBUFF_SIZE CVMX_IPD_PACKET_MBUFF_SIZE_FUNC()
+static inline uint64_t CVMX_IPD_PACKET_MBUFF_SIZE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000010ull);
+}
+
+#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000358ull);
+}
+
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 36) && (offset <= 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset >= 36) && (offset <= 39))))))
+ cvmx_warn
+ ("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + (offset & 63) * 8 -
+ 8 * 36;
+}
+
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 36) && (offset <= 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset >= 36) && (offset <= 39))))))
+ cvmx_warn
+ ("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + (offset & 63) * 8 -
+ 8 * 36;
+}
+
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || (offset == 32)))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset == 0) || (offset == 2) || (offset == 4)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset == 0) || (offset == 4)))))
+ cvmx_warn
+ ("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset == 0) || (offset == 2) || (offset == 4)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset == 0) || (offset == 4)))))
+ cvmx_warn
+ ("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 31) || ((offset >= 128) && (offset <= 159))
+ || ((offset >= 256) && (offset <= 319))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 31) || ((offset >= 288) && (offset <= 319))))))
+ cvmx_warn
+ ("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + (offset & 511) * 8;
+}
+
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000348ull);
+}
+
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000350ull);
+}
+
+#define CVMX_IPD_PTR_COUNT CVMX_IPD_PTR_COUNT_FUNC()
+static inline uint64_t CVMX_IPD_PTR_COUNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000320ull);
+}
+
+#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000340ull);
+}
+
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + (offset & 7) * 8;
+}
+
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC()
+static inline uint64_t CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000330ull);
+}
+
+#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F00000002D8ull);
+}
+
+#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
+}
+
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + (offset & 7) * 8;
+}
+
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000148ull);
+}
+
+#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000170ull);
+}
+
+#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
+}
+
+#define CVMX_IPD_WQE_FPA_QUEUE CVMX_IPD_WQE_FPA_QUEUE_FUNC()
+static inline uint64_t CVMX_IPD_WQE_FPA_QUEUE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000020ull);
+}
+
+#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00014F0000000360ull);
+}
+
+#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
+static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180020000018ull);
+}
+
+#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180020000010ull);
+}
+
+#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
+static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180020000008ull);
+}
+
+#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
+static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180020000000ull);
+}
+
+#define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC()
+static inline uint64_t CVMX_L2C_BST0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
+}
+
+#define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC()
+static inline uint64_t CVMX_L2C_BST1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
+}
+
+#define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC()
+static inline uint64_t CVMX_L2C_BST2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
+}
+
+#define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
+static inline uint64_t CVMX_L2C_CFG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000000ull);
+}
+
+#define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC()
+static inline uint64_t CVMX_L2C_DBG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000030ull);
+}
+
+#define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC()
+static inline uint64_t CVMX_L2C_DUT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000050ull);
+}
+
+#define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000C8ull);
+}
+
+#define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000D0ull);
+}
+
+#define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC()
+static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180080000100ull);
+}
+
+#define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC()
+static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000F8ull);
+}
+
+#define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC()
+static inline uint64_t CVMX_L2C_LCKBASE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000058ull);
+}
+
+#define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC()
+static inline uint64_t CVMX_L2C_LCKOFF_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000060ull);
+}
+
+#define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC()
+static inline uint64_t CVMX_L2C_LFB0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000038ull);
+}
+
+#define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC()
+static inline uint64_t CVMX_L2C_LFB1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000040ull);
+}
+
+#define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC()
+static inline uint64_t CVMX_L2C_LFB2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000048ull);
+}
+
+#define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC()
+static inline uint64_t CVMX_L2C_LFB3_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800000B8ull);
+}
+
+#define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC()
+static inline uint64_t CVMX_L2C_OOB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_OOB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000D8ull);
+}
+
+#define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC()
+static inline uint64_t CVMX_L2C_OOB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000E0ull);
+}
+
+#define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC()
+static inline uint64_t CVMX_L2C_OOB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000E8ull);
+}
+
+#define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC()
+static inline uint64_t CVMX_L2C_OOB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000F0ull);
+}
+
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC()
+static inline uint64_t CVMX_L2C_PFCTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000090ull);
+}
+
+static inline uint64_t CVMX_L2C_PFCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180080000098ull) + (offset & 3) * 8;
+}
+
+#define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC()
+static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800800000C0ull);
+}
+
+#define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
+static inline uint64_t CVMX_L2C_SPAR0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000068ull);
+}
+
+#define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC()
+static inline uint64_t CVMX_L2C_SPAR1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180080000070ull);
+}
+
+#define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC()
+static inline uint64_t CVMX_L2C_SPAR2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180080000078ull);
+}
+
+#define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC()
+static inline uint64_t CVMX_L2C_SPAR3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180080000080ull);
+}
+
+#define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC()
+static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000088ull);
+}
+
+#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
+static inline uint64_t CVMX_L2D_BST0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000780ull);
+}
+
+#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
+static inline uint64_t CVMX_L2D_BST1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000788ull);
+}
+
+#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
+static inline uint64_t CVMX_L2D_BST2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000790ull);
+}
+
+#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
+static inline uint64_t CVMX_L2D_BST3_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000798ull);
+}
+
+#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
+static inline uint64_t CVMX_L2D_ERR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000010ull);
+}
+
+#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
+static inline uint64_t CVMX_L2D_FADR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000018ull);
+}
+
+#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
+static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000020ull);
+}
+
+#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
+static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000028ull);
+}
+
+#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
+static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
+}
+
+#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
+static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
+}
+
+#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
+static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
+}
+
+#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
+static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
+}
+
+#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
+static inline uint64_t CVMX_L2T_ERR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180080000008ull);
+}
+
+#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
+static inline uint64_t CVMX_LED_BLINK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
+}
+
+#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
+static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
+}
+
+#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
+static inline uint64_t CVMX_LED_CYLON_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
+}
+
+#define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
+static inline uint64_t CVMX_LED_DBG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
+}
+
+#define CVMX_LED_EN CVMX_LED_EN_FUNC()
+static inline uint64_t CVMX_LED_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
+}
+
+#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
+static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
+}
+
+#define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
+}
+
+#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
+}
+
+static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + (offset & 1) * 16;
+}
+
+static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + (offset & 1) * 16;
+}
+
+static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000F0ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000F8ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000028ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000010ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000090ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000070ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000068ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000B8ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000018ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000088ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000C0ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000098ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000038ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000020ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000050ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000048ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000000ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000008ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000C8ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000060ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000058ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000040ull) +
+ (block_id & 0) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000A8ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000B0ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000140ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000148ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000100ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0xC000000ull) * 8;
+}
+
+static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn
+ ("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800880000A0ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000078ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000030ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+ cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180088000080ull) +
+ (block_id & 1) * 0x60000000ull;
+}
+
+#define CVMX_MIO_BOOT_BIST_STAT CVMX_MIO_BOOT_BIST_STAT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_BIST_STAT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800000000F8ull);
+}
+
+#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000100ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000138ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000150ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000120ull) + (offset & 3) * 8;
+}
+
+#define CVMX_MIO_BOOT_ERR CVMX_MIO_BOOT_ERR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_ERR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800000000A0ull);
+}
+
+#define CVMX_MIO_BOOT_INT CVMX_MIO_BOOT_INT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_INT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800000000A8ull);
+}
+
+#define CVMX_MIO_BOOT_LOC_ADR CVMX_MIO_BOOT_LOC_ADR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_LOC_ADR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000000090ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000080ull) + (offset & 1) * 8;
+}
+
+#define CVMX_MIO_BOOT_LOC_DAT CVMX_MIO_BOOT_LOC_DAT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_LOC_DAT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000000098ull);
+}
+
+#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000000ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn
+ ("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000040ull) + (offset & 7) * 8;
+}
+
+#define CVMX_MIO_BOOT_THR CVMX_MIO_BOOT_THR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_THR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800000000B0ull);
+}
+
+static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001520ull) + (offset & 3) * 8;
+}
+
+#define CVMX_MIO_FUS_DAT0 CVMX_MIO_FUS_DAT0_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001400ull);
+}
+
+#define CVMX_MIO_FUS_DAT1 CVMX_MIO_FUS_DAT1_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001408ull);
+}
+
+#define CVMX_MIO_FUS_DAT2 CVMX_MIO_FUS_DAT2_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001410ull);
+}
+
+#define CVMX_MIO_FUS_DAT3 CVMX_MIO_FUS_DAT3_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT3_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001418ull);
+}
+
+#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
+static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001550ull);
+}
+
+#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001420ull);
+}
+
+#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001580ull);
+}
+
+#define CVMX_MIO_FUS_PROG CVMX_MIO_FUS_PROG_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PROG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001510ull);
+}
+
+#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn
+ ("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001518ull);
+}
+
+#define CVMX_MIO_FUS_RCMD CVMX_MIO_FUS_RCMD_FUNC()
+static inline uint64_t CVMX_MIO_FUS_RCMD_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001500ull);
+}
+
+#define CVMX_MIO_FUS_SPR_REPAIR_RES CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001548ull);
+}
+
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC()
+static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001540ull);
+}
+
+#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
+static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001578ull);
+}
+
+#define CVMX_MIO_FUS_WADR CVMX_MIO_FUS_WADR_FUNC()
+static inline uint64_t CVMX_MIO_FUS_WADR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180000001508ull);
+}
+
+#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000168ull);
+}
+
+#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000170ull);
+}
+
+#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn
+ ("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000178ull);
+}
+
+#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
+static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001448ull);
+}
+
+#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+ cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001440ull);
+}
+
+static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001010ull) + (offset & 1) * 512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001000ull) + (offset & 1) * 512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001018ull) + (offset & 1) * 512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001008ull) + (offset & 1) * 512;
+}
+
+#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000488ull);
+}
+
+#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000480ull);
+}
+
+#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000520ull);
+}
+
+#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000450ull);
+}
+
+#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
+static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000708ull);
+}
+
+#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000408ull);
+}
+
+#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000410ull);
+}
+
+#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000418ull);
+}
+
+#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000428ull);
+}
+
+#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000420ull);
+}
+
+#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000430ull);
+}
+
+#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000400ull);
+}
+
+#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000608ull);
+}
+
+#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000530ull);
+}
+
+#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000620ull);
+}
+
+#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000438ull);
+}
+
+#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000630ull);
+}
+
+#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000610ull);
+}
+
+#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000638ull);
+}
+
+#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000618ull);
+}
+
+#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000700ull);
+}
+
+#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000600ull);
+}
+
+#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000528ull);
+}
+
+#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000440ull);
+}
+
+#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000538ull);
+}
+
+static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000888ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000880ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000920ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000850ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000808ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000810ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000818ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000828ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000820ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000830ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000800ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000930ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000838ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000928ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000840ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000000938ull) + (offset & 1) * 1024;
+}
+
+static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100078ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100020ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100050ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100030ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100028ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100010ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100018ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100048ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100040ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100038ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100000ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100008ull) + (offset & 1) * 2048;
+}
+
+static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000100058ull) + (offset & 1) * 2048;
+}
+
+#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
+static inline uint64_t CVMX_MPI_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000001000ull);
+}
+
+static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
+ cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000001080ull) + (offset & 15) * 8;
+}
+
+#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
+static inline uint64_t CVMX_MPI_STS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000001008ull);
+}
+
+#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
+static inline uint64_t CVMX_MPI_TX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000001010ull);
+}
+
+#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
+static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000018ull);
+}
+
+#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
+static inline uint64_t CVMX_NDF_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000000ull);
+}
+
+#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
+static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000030ull);
+}
+
+#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
+static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000010ull);
+}
+
+#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
+static inline uint64_t CVMX_NDF_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000020ull);
+}
+
+#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
+static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000028ull);
+}
+
+#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
+static inline uint64_t CVMX_NDF_MISC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000008ull);
+}
+
+#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
+static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+ cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070001000038ull);
+}
+
+static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000000ull + (offset & 31) * 16;
+}
+
+#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
+#endif
+ return 0x0000000000000580ull;
+}
+
+#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
+#endif
+ return 0x0000000000000680ull;
+}
+
+#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
+#endif
+ return 0x0000000000000250ull;
+}
+
+#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
+#endif
+ return 0x0000000000000260ull;
+}
+
+#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
+#endif
+ return 0x0000000000000570ull;
+}
+
+#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
+#endif
+ return 0x0000000000003C00ull;
+}
+
+#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
+#endif
+ return 0x00000000000005F0ull;
+}
+
+#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
+#endif
+ return 0x0000000000000510ull;
+}
+
+#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
+#endif
+ return 0x0000000000000500ull;
+}
+
+#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+#endif
+ return 0x00000000000005C0ull;
+}
+
+#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+#endif
+ return 0x00000000000005D0ull;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000450ull + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000003B0ull + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000400ull + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000004A0ull + (offset & 7) * 16;
+}
+
+#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
+#endif
+ return 0x00000000000005E0ull;
+}
+
+#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
+#endif
+ return 0x00000000000003A0ull;
+}
+
+#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000000560ull;
+}
+
+#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
+#endif
+ return 0x0000000000003CE0ull;
+}
+
+#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
+#endif
+ return 0x0000000000000550ull;
+}
+
+#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000000540ull;
+}
+
+#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
+#endif
+ return 0x0000000000003CD0ull;
+}
+
+#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
+#endif
+ return 0x0000000000000590ull;
+}
+
+#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
+#endif
+ return 0x0000000000000530ull;
+}
+
+#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
+#endif
+ return 0x0000000000003CC0ull;
+}
+
+#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+#endif
+ return 0x0000000000000600ull;
+}
+
+#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+#endif
+ return 0x0000000000000610ull;
+}
+
+#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+#endif
+ return 0x00000000000004F0ull;
+}
+
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 12) && (offset <= 27))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset >= 12) && (offset <= 27))))))
+ cvmx_warn
+ ("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000340ull + (offset & 31) * 16 - 16 * 12;
+}
+
+#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
+#endif
+ return 0x0000000000003C50ull;
+}
+
+#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
+#endif
+ return 0x0000000000003C60ull;
+}
+
+#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
+#endif
+ return 0x0000000000003C70ull;
+}
+
+#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
+#endif
+ return 0x0000000000003C80ull;
+}
+
+#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
+#endif
+ return 0x0000000000003C10ull;
+}
+
+#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
+#endif
+ return 0x0000000000003C20ull;
+}
+
+#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
+#endif
+ return 0x0000000000003C30ull;
+}
+
+#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
+#endif
+ return 0x0000000000003C40ull;
+}
+
+#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
+#endif
+ return 0x0000000000003CA0ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+#endif
+ return 0x0000000000003CF0ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+#endif
+ return 0x0000000000003D00ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+#endif
+ return 0x0000000000003D10ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+#endif
+ return 0x0000000000003D20ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+#endif
+ return 0x0000000000003D30ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+#endif
+ return 0x0000000000003D40ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+#endif
+ return 0x0000000000003D50ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+#endif
+ return 0x0000000000003D60ull;
+}
+
+#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
+#endif
+ return 0x0000000000003C90ull;
+}
+
+#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+#endif
+ return 0x0000000000003D70ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+#endif
+ return 0x0000000000003CB0ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+#endif
+ return 0x0000000000000650ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+#endif
+ return 0x0000000000000660ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+#endif
+ return 0x0000000000000670ull;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000002400ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000002800ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000002C00ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000003000ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000003400ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000003800ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000001400ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000001800ull + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000001C00ull + (offset & 31) * 16;
+}
+
+#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
+#endif
+ return 0x0000000000001110ull;
+}
+
+#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000001130ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+#endif
+ return 0x00000000000010B0ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+#endif
+ return 0x00000000000010A0ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+#endif
+ return 0x0000000000001090ull;
+}
+
+#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
+#endif
+ return 0x0000000000001080ull;
+}
+
+#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+#endif
+ return 0x0000000000001150ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000001000ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+#endif
+ return 0x0000000000001190ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+#endif
+ return 0x0000000000001020ull;
+}
+
+#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+#endif
+ return 0x0000000000001100ull;
+}
+
+#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
+#endif
+ return 0x00000000000006B0ull;
+}
+
+static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000002000ull + (offset & 31) * 16;
+}
+
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+#endif
+ return 0x00000000000006A0ull;
+}
+
+#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+#endif
+ return 0x00000000000011A0ull;
+}
+
+#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
+#endif
+ return 0x0000000000001070ull;
+}
+
+#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+#endif
+ return 0x0000000000001160ull;
+}
+
+#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+#endif
+ return 0x00000000000010D0ull;
+}
+
+#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000001010ull;
+}
+
+#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+#endif
+ return 0x00000000000010E0ull;
+}
+
+#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+#endif
+ return 0x0000000000000690ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
+#endif
+ return 0x0000000000001050ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+#endif
+ return 0x0000000000001180ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
+#endif
+ return 0x0000000000001040ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+#endif
+ return 0x0000000000001030ull;
+}
+
+#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
+#endif
+ return 0x0000000000001120ull;
+}
+
+#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000001140ull;
+}
+
+#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+ return 0x0000000000000520ull;
+}
+
+#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
+#endif
+ return 0x0000000000000270ull;
+}
+
+#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
+#endif
+ return 0x0000000000000620ull;
+}
+
+#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
+#endif
+ return 0x0000000000000630ull;
+}
+
+#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
+#endif
+ return 0x0000000000000640ull;
+}
+
+#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
+#endif
+ return 0x0000000000000380ull;
+}
+
+#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
+#endif
+ return 0x0000000000000210ull;
+}
+
+#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
+#endif
+ return 0x0000000000000240ull;
+}
+
+#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
+#endif
+ return 0x0000000000000200ull;
+}
+
+#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
+#endif
+ return 0x0000000000000220ull;
+}
+
+#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
+#endif
+ return 0x0000000000000230ull;
+}
+
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + (offset & 3) * 16;
+}
+
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + (offset & 3) * 8;
+}
+
+#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
+}
+
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + (offset & 3) * 8;
+}
+
+#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
+static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
+}
+
+#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
+}
+
+#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
+}
+
+#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
+}
+
+#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
+}
+
+#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
+}
+
+#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
+}
+
+#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
+}
+
+#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
+}
+
+#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
+}
+
+#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
+}
+
+#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
+}
+
+#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
+}
+
+#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
+}
+
+#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
+}
+
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset >= 3) && (offset <= 6))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset >= 3) && (offset <= 6))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset >= 3) && (offset <= 6))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset >= 3) && (offset <= 6))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset >= 3) && (offset <= 6))))))
+ cvmx_warn
+ ("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + (offset & 7) * 8 -
+ 8 * 3;
+}
+
+#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
+#endif
+ return 0x0000000000000190ull;
+}
+
+#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
+}
+
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + (offset & 3) * 8;
+}
+
+#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
+}
+
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + (offset & 31) * 4;
+}
+
+#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
+}
+
+#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
+}
+
+#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
+}
+
+#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
+}
+
+#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
+}
+
+#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
+}
+
+#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
+}
+
+#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
+}
+
+#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
+}
+
+#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
+}
+
+#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
+}
+
+#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
+}
+
+#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
+}
+
+#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
+}
+
+#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
+}
+
+#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
+}
+
+#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
+}
+
+#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
+}
+
+#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
+}
+
+#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
+}
+
+#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
+}
+
+#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
+}
+
+#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
+}
+
+#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
+}
+
+#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
+}
+
+#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
+}
+
+#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
+}
+
+#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
+}
+
+#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
+}
+
+#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
+}
+
+#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
+}
+
+#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
+}
+
+#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
+}
+
+#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
+}
+
+#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
+}
+
+#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
+}
+
+#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
+}
+
+#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
+}
+
+#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
+}
+
+#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
+}
+
+#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
+}
+
+#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
+}
+
+#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
+}
+
+#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
+}
+
+static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + (offset & 3) * 8;
+}
+
+static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + (offset & 3) * 8;
+}
+
+#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
+}
+
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + (offset & 3) * 16;
+}
+
+#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
+static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
+}
+
+#define CVMX_PCIEEP_CFG000 CVMX_PCIEEP_CFG000_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG000_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG000 not supported on this chip\n");
+#endif
+ return 0x0000000000000000ull;
+}
+
+#define CVMX_PCIEEP_CFG001 CVMX_PCIEEP_CFG001_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG001_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG001 not supported on this chip\n");
+#endif
+ return 0x0000000000000004ull;
+}
+
+#define CVMX_PCIEEP_CFG002 CVMX_PCIEEP_CFG002_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG002_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG002 not supported on this chip\n");
+#endif
+ return 0x0000000000000008ull;
+}
+
+#define CVMX_PCIEEP_CFG003 CVMX_PCIEEP_CFG003_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG003_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG003 not supported on this chip\n");
+#endif
+ return 0x000000000000000Cull;
+}
+
+#define CVMX_PCIEEP_CFG004 CVMX_PCIEEP_CFG004_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG004_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG004 not supported on this chip\n");
+#endif
+ return 0x0000000000000010ull;
+}
+
+#define CVMX_PCIEEP_CFG004_MASK CVMX_PCIEEP_CFG004_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG004_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG004_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000010ull;
+}
+
+#define CVMX_PCIEEP_CFG005 CVMX_PCIEEP_CFG005_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG005_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG005 not supported on this chip\n");
+#endif
+ return 0x0000000000000014ull;
+}
+
+#define CVMX_PCIEEP_CFG005_MASK CVMX_PCIEEP_CFG005_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG005_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG005_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000014ull;
+}
+
+#define CVMX_PCIEEP_CFG006 CVMX_PCIEEP_CFG006_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG006_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG006 not supported on this chip\n");
+#endif
+ return 0x0000000000000018ull;
+}
+
+#define CVMX_PCIEEP_CFG006_MASK CVMX_PCIEEP_CFG006_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG006_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG006_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000018ull;
+}
+
+#define CVMX_PCIEEP_CFG007 CVMX_PCIEEP_CFG007_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG007_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG007 not supported on this chip\n");
+#endif
+ return 0x000000000000001Cull;
+}
+
+#define CVMX_PCIEEP_CFG007_MASK CVMX_PCIEEP_CFG007_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG007_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG007_MASK not supported on this chip\n");
+#endif
+ return 0x000000008000001Cull;
+}
+
+#define CVMX_PCIEEP_CFG008 CVMX_PCIEEP_CFG008_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG008_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG008 not supported on this chip\n");
+#endif
+ return 0x0000000000000020ull;
+}
+
+#define CVMX_PCIEEP_CFG008_MASK CVMX_PCIEEP_CFG008_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG008_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG008_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000020ull;
+}
+
+#define CVMX_PCIEEP_CFG009 CVMX_PCIEEP_CFG009_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG009_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG009 not supported on this chip\n");
+#endif
+ return 0x0000000000000024ull;
+}
+
+#define CVMX_PCIEEP_CFG009_MASK CVMX_PCIEEP_CFG009_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG009_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG009_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000024ull;
+}
+
+#define CVMX_PCIEEP_CFG010 CVMX_PCIEEP_CFG010_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG010_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG010 not supported on this chip\n");
+#endif
+ return 0x0000000000000028ull;
+}
+
+#define CVMX_PCIEEP_CFG011 CVMX_PCIEEP_CFG011_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG011_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG011 not supported on this chip\n");
+#endif
+ return 0x000000000000002Cull;
+}
+
+#define CVMX_PCIEEP_CFG012 CVMX_PCIEEP_CFG012_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG012_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG012 not supported on this chip\n");
+#endif
+ return 0x0000000000000030ull;
+}
+
+#define CVMX_PCIEEP_CFG012_MASK CVMX_PCIEEP_CFG012_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG012_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PCIEEP_CFG012_MASK not supported on this chip\n");
+#endif
+ return 0x0000000080000030ull;
+}
+
+#define CVMX_PCIEEP_CFG013 CVMX_PCIEEP_CFG013_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG013_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG013 not supported on this chip\n");
+#endif
+ return 0x0000000000000034ull;
+}
+
+#define CVMX_PCIEEP_CFG015 CVMX_PCIEEP_CFG015_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG015_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG015 not supported on this chip\n");
+#endif
+ return 0x000000000000003Cull;
+}
+
+#define CVMX_PCIEEP_CFG016 CVMX_PCIEEP_CFG016_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG016_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG016 not supported on this chip\n");
+#endif
+ return 0x0000000000000040ull;
+}
+
+#define CVMX_PCIEEP_CFG017 CVMX_PCIEEP_CFG017_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG017_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG017 not supported on this chip\n");
+#endif
+ return 0x0000000000000044ull;
+}
+
+#define CVMX_PCIEEP_CFG020 CVMX_PCIEEP_CFG020_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG020_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG020 not supported on this chip\n");
+#endif
+ return 0x0000000000000050ull;
+}
+
+#define CVMX_PCIEEP_CFG021 CVMX_PCIEEP_CFG021_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG021_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG021 not supported on this chip\n");
+#endif
+ return 0x0000000000000054ull;
+}
+
+#define CVMX_PCIEEP_CFG022 CVMX_PCIEEP_CFG022_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG022_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG022 not supported on this chip\n");
+#endif
+ return 0x0000000000000058ull;
+}
+
+#define CVMX_PCIEEP_CFG023 CVMX_PCIEEP_CFG023_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG023_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG023 not supported on this chip\n");
+#endif
+ return 0x000000000000005Cull;
+}
+
+#define CVMX_PCIEEP_CFG028 CVMX_PCIEEP_CFG028_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG028_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG028 not supported on this chip\n");
+#endif
+ return 0x0000000000000070ull;
+}
+
+#define CVMX_PCIEEP_CFG029 CVMX_PCIEEP_CFG029_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG029_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG029 not supported on this chip\n");
+#endif
+ return 0x0000000000000074ull;
+}
+
+#define CVMX_PCIEEP_CFG030 CVMX_PCIEEP_CFG030_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG030_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG030 not supported on this chip\n");
+#endif
+ return 0x0000000000000078ull;
+}
+
+#define CVMX_PCIEEP_CFG031 CVMX_PCIEEP_CFG031_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG031_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG031 not supported on this chip\n");
+#endif
+ return 0x000000000000007Cull;
+}
+
+#define CVMX_PCIEEP_CFG032 CVMX_PCIEEP_CFG032_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG032_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG032 not supported on this chip\n");
+#endif
+ return 0x0000000000000080ull;
+}
+
+#define CVMX_PCIEEP_CFG033 CVMX_PCIEEP_CFG033_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG033_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG033 not supported on this chip\n");
+#endif
+ return 0x0000000000000084ull;
+}
+
+#define CVMX_PCIEEP_CFG034 CVMX_PCIEEP_CFG034_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG034_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG034 not supported on this chip\n");
+#endif
+ return 0x0000000000000088ull;
+}
+
+#define CVMX_PCIEEP_CFG037 CVMX_PCIEEP_CFG037_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG037_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG037 not supported on this chip\n");
+#endif
+ return 0x0000000000000094ull;
+}
+
+#define CVMX_PCIEEP_CFG038 CVMX_PCIEEP_CFG038_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG038_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG038 not supported on this chip\n");
+#endif
+ return 0x0000000000000098ull;
+}
+
+#define CVMX_PCIEEP_CFG039 CVMX_PCIEEP_CFG039_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG039_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG039 not supported on this chip\n");
+#endif
+ return 0x000000000000009Cull;
+}
+
+#define CVMX_PCIEEP_CFG040 CVMX_PCIEEP_CFG040_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG040_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG040 not supported on this chip\n");
+#endif
+ return 0x00000000000000A0ull;
+}
+
+#define CVMX_PCIEEP_CFG041 CVMX_PCIEEP_CFG041_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG041_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG041 not supported on this chip\n");
+#endif
+ return 0x00000000000000A4ull;
+}
+
+#define CVMX_PCIEEP_CFG042 CVMX_PCIEEP_CFG042_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG042_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG042 not supported on this chip\n");
+#endif
+ return 0x00000000000000A8ull;
+}
+
+#define CVMX_PCIEEP_CFG064 CVMX_PCIEEP_CFG064_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG064_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG064 not supported on this chip\n");
+#endif
+ return 0x0000000000000100ull;
+}
+
+#define CVMX_PCIEEP_CFG065 CVMX_PCIEEP_CFG065_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG065_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG065 not supported on this chip\n");
+#endif
+ return 0x0000000000000104ull;
+}
+
+#define CVMX_PCIEEP_CFG066 CVMX_PCIEEP_CFG066_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG066_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG066 not supported on this chip\n");
+#endif
+ return 0x0000000000000108ull;
+}
+
+#define CVMX_PCIEEP_CFG067 CVMX_PCIEEP_CFG067_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG067_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG067 not supported on this chip\n");
+#endif
+ return 0x000000000000010Cull;
+}
+
+#define CVMX_PCIEEP_CFG068 CVMX_PCIEEP_CFG068_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG068_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG068 not supported on this chip\n");
+#endif
+ return 0x0000000000000110ull;
+}
+
+#define CVMX_PCIEEP_CFG069 CVMX_PCIEEP_CFG069_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG069_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG069 not supported on this chip\n");
+#endif
+ return 0x0000000000000114ull;
+}
+
+#define CVMX_PCIEEP_CFG070 CVMX_PCIEEP_CFG070_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG070_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG070 not supported on this chip\n");
+#endif
+ return 0x0000000000000118ull;
+}
+
+#define CVMX_PCIEEP_CFG071 CVMX_PCIEEP_CFG071_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG071_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG071 not supported on this chip\n");
+#endif
+ return 0x000000000000011Cull;
+}
+
+#define CVMX_PCIEEP_CFG072 CVMX_PCIEEP_CFG072_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG072_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG072 not supported on this chip\n");
+#endif
+ return 0x0000000000000120ull;
+}
+
+#define CVMX_PCIEEP_CFG073 CVMX_PCIEEP_CFG073_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG073_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG073 not supported on this chip\n");
+#endif
+ return 0x0000000000000124ull;
+}
+
+#define CVMX_PCIEEP_CFG074 CVMX_PCIEEP_CFG074_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG074_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG074 not supported on this chip\n");
+#endif
+ return 0x0000000000000128ull;
+}
+
+#define CVMX_PCIEEP_CFG448 CVMX_PCIEEP_CFG448_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG448_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG448 not supported on this chip\n");
+#endif
+ return 0x0000000000000700ull;
+}
+
+#define CVMX_PCIEEP_CFG449 CVMX_PCIEEP_CFG449_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG449_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG449 not supported on this chip\n");
+#endif
+ return 0x0000000000000704ull;
+}
+
+#define CVMX_PCIEEP_CFG450 CVMX_PCIEEP_CFG450_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG450_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG450 not supported on this chip\n");
+#endif
+ return 0x0000000000000708ull;
+}
+
+#define CVMX_PCIEEP_CFG451 CVMX_PCIEEP_CFG451_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG451_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG451 not supported on this chip\n");
+#endif
+ return 0x000000000000070Cull;
+}
+
+#define CVMX_PCIEEP_CFG452 CVMX_PCIEEP_CFG452_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG452_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG452 not supported on this chip\n");
+#endif
+ return 0x0000000000000710ull;
+}
+
+#define CVMX_PCIEEP_CFG453 CVMX_PCIEEP_CFG453_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG453_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG453 not supported on this chip\n");
+#endif
+ return 0x0000000000000714ull;
+}
+
+#define CVMX_PCIEEP_CFG454 CVMX_PCIEEP_CFG454_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG454_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG454 not supported on this chip\n");
+#endif
+ return 0x0000000000000718ull;
+}
+
+#define CVMX_PCIEEP_CFG455 CVMX_PCIEEP_CFG455_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG455_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG455 not supported on this chip\n");
+#endif
+ return 0x000000000000071Cull;
+}
+
+#define CVMX_PCIEEP_CFG456 CVMX_PCIEEP_CFG456_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG456_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG456 not supported on this chip\n");
+#endif
+ return 0x0000000000000720ull;
+}
+
+#define CVMX_PCIEEP_CFG458 CVMX_PCIEEP_CFG458_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG458_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG458 not supported on this chip\n");
+#endif
+ return 0x0000000000000728ull;
+}
+
+#define CVMX_PCIEEP_CFG459 CVMX_PCIEEP_CFG459_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG459_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG459 not supported on this chip\n");
+#endif
+ return 0x000000000000072Cull;
+}
+
+#define CVMX_PCIEEP_CFG460 CVMX_PCIEEP_CFG460_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG460_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG460 not supported on this chip\n");
+#endif
+ return 0x0000000000000730ull;
+}
+
+#define CVMX_PCIEEP_CFG461 CVMX_PCIEEP_CFG461_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG461_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG461 not supported on this chip\n");
+#endif
+ return 0x0000000000000734ull;
+}
+
+#define CVMX_PCIEEP_CFG462 CVMX_PCIEEP_CFG462_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG462_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG462 not supported on this chip\n");
+#endif
+ return 0x0000000000000738ull;
+}
+
+#define CVMX_PCIEEP_CFG463 CVMX_PCIEEP_CFG463_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG463_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG463 not supported on this chip\n");
+#endif
+ return 0x000000000000073Cull;
+}
+
+#define CVMX_PCIEEP_CFG464 CVMX_PCIEEP_CFG464_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG464_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG464 not supported on this chip\n");
+#endif
+ return 0x0000000000000740ull;
+}
+
+#define CVMX_PCIEEP_CFG465 CVMX_PCIEEP_CFG465_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG465_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG465 not supported on this chip\n");
+#endif
+ return 0x0000000000000744ull;
+}
+
+#define CVMX_PCIEEP_CFG466 CVMX_PCIEEP_CFG466_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG466_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG466 not supported on this chip\n");
+#endif
+ return 0x0000000000000748ull;
+}
+
+#define CVMX_PCIEEP_CFG467 CVMX_PCIEEP_CFG467_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG467_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG467 not supported on this chip\n");
+#endif
+ return 0x000000000000074Cull;
+}
+
+#define CVMX_PCIEEP_CFG468 CVMX_PCIEEP_CFG468_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG468_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG468 not supported on this chip\n");
+#endif
+ return 0x0000000000000750ull;
+}
+
+#define CVMX_PCIEEP_CFG490 CVMX_PCIEEP_CFG490_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG490_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG490 not supported on this chip\n");
+#endif
+ return 0x00000000000007A8ull;
+}
+
+#define CVMX_PCIEEP_CFG491 CVMX_PCIEEP_CFG491_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG491_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG491 not supported on this chip\n");
+#endif
+ return 0x00000000000007ACull;
+}
+
+#define CVMX_PCIEEP_CFG492 CVMX_PCIEEP_CFG492_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG492_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG492 not supported on this chip\n");
+#endif
+ return 0x00000000000007B0ull;
+}
+
+#define CVMX_PCIEEP_CFG516 CVMX_PCIEEP_CFG516_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG516_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG516 not supported on this chip\n");
+#endif
+ return 0x0000000000000810ull;
+}
+
+#define CVMX_PCIEEP_CFG517 CVMX_PCIEEP_CFG517_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG517_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PCIEEP_CFG517 not supported on this chip\n");
+#endif
+ return 0x0000000000000814ull;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000000ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000004ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000008ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000000Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000010ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000014ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000018ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000001Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000020ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000024ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000028ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000002Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000030ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000034ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000038ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000003Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000040ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000044ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000050ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000054ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000058ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000005Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000070ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000074ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000078ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000007Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000080ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000084ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000088ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000008Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000090ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000094ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000098ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000009Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000A0ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000A4ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000A8ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000100ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000104ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000108ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000010Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000110ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000114ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000118ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000011Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000120ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000124ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000128ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000012Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000130ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000134ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000700ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000704ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000708ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000070Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000710ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000714ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000718ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000071Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000720ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000728ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000072Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000730ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000734ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000738ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000073Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000740ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000744ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000748ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000074Cull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000750ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000007A8ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000007ACull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000007B0ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000810ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000814ull + (offset & 1) * 0;
+}
+
+static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+ cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000100ull + (offset & 31) * 4;
+}
+
+#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+ cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n");
+#endif
+ return 0x00000000000001C0ull;
+}
+
+#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_PCI_CFG00_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n");
+#endif
+ return 0x0000000000000000ull;
+}
+
+#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_PCI_CFG01_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n");
+#endif
+ return 0x0000000000000004ull;
+}
+
+#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_PCI_CFG02_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n");
+#endif
+ return 0x0000000000000008ull;
+}
+
+#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_PCI_CFG03_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n");
+#endif
+ return 0x000000000000000Cull;
+}
+
+#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_PCI_CFG04_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n");
+#endif
+ return 0x0000000000000010ull;
+}
+
+#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_PCI_CFG05_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n");
+#endif
+ return 0x0000000000000014ull;
+}
+
+#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_PCI_CFG06_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n");
+#endif
+ return 0x0000000000000018ull;
+}
+
+#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_PCI_CFG07_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n");
+#endif
+ return 0x000000000000001Cull;
+}
+
+#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_PCI_CFG08_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n");
+#endif
+ return 0x0000000000000020ull;
+}
+
+#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_PCI_CFG09_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n");
+#endif
+ return 0x0000000000000024ull;
+}
+
+#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_PCI_CFG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n");
+#endif
+ return 0x0000000000000028ull;
+}
+
+#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_PCI_CFG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n");
+#endif
+ return 0x000000000000002Cull;
+}
+
+#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_PCI_CFG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n");
+#endif
+ return 0x0000000000000030ull;
+}
+
+#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_PCI_CFG13_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n");
+#endif
+ return 0x0000000000000034ull;
+}
+
+#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_PCI_CFG15_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n");
+#endif
+ return 0x000000000000003Cull;
+}
+
+#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_PCI_CFG16_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n");
+#endif
+ return 0x0000000000000040ull;
+}
+
+#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_PCI_CFG17_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n");
+#endif
+ return 0x0000000000000044ull;
+}
+
+#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_PCI_CFG18_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n");
+#endif
+ return 0x0000000000000048ull;
+}
+
+#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_PCI_CFG19_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n");
+#endif
+ return 0x000000000000004Cull;
+}
+
+#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_PCI_CFG20_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n");
+#endif
+ return 0x0000000000000050ull;
+}
+
+#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_PCI_CFG21_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n");
+#endif
+ return 0x0000000000000054ull;
+}
+
+#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_PCI_CFG22_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n");
+#endif
+ return 0x0000000000000058ull;
+}
+
+#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_PCI_CFG56_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n");
+#endif
+ return 0x00000000000000E0ull;
+}
+
+#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_PCI_CFG57_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n");
+#endif
+ return 0x00000000000000E4ull;
+}
+
+#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_PCI_CFG58_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n");
+#endif
+ return 0x00000000000000E8ull;
+}
+
+#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_PCI_CFG59_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n");
+#endif
+ return 0x00000000000000ECull;
+}
+
+#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_PCI_CFG60_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n");
+#endif
+ return 0x00000000000000F0ull;
+}
+
+#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_PCI_CFG61_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n");
+#endif
+ return 0x00000000000000F4ull;
+}
+
+#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_PCI_CFG62_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n");
+#endif
+ return 0x00000000000000F8ull;
+}
+
+#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_PCI_CFG63_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n");
+#endif
+ return 0x00000000000000FCull;
+}
+
+#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n");
+#endif
+ return 0x00000000000001B8ull;
+}
+
+#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n");
+#endif
+ return 0x000000000000018Cull;
+}
+
+static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000080ull + (offset & 3) * 8;
+}
+
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000A0ull + (offset & 1) * 8;
+}
+
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000A4ull + (offset & 1) * 8;
+}
+
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x00000000000000B0ull + (offset & 1) * 4;
+}
+
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000084ull + (offset & 3) * 8;
+}
+
+#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n");
+#endif
+ return 0x0000000000000038ull;
+}
+
+#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n");
+#endif
+ return 0x00000000000001A0ull;
+}
+
+#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n");
+#endif
+ return 0x0000000000000030ull;
+}
+
+#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n");
+#endif
+ return 0x0000000000000198ull;
+}
+
+#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n");
+#endif
+ return 0x00000000000000F0ull;
+}
+
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000040ull + (offset & 3) * 16;
+}
+
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000048ull + (offset & 3) * 16;
+}
+
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x000000000000004Cull + (offset & 3) * 16;
+}
+
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+ cvmx_warn
+ ("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return 0x0000000000000044ull + (offset & 3) * 16;
+}
+
+#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n");
+#endif
+ return 0x0000000000000180ull;
+}
+
+#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n");
+#endif
+ return 0x0000000000000184ull;
+}
+
+#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n");
+#endif
+ return 0x0000000000000188ull;
+}
+
+#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC()
+static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000000B0ull);
+}
+
+#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n");
+#endif
+ return 0x00000000000001A8ull;
+}
+
+#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n");
+#endif
+ return 0x00000000000001B0ull;
+}
+
+#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n");
+#endif
+ return 0x0000000000000008ull;
+}
+
+#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n");
+#endif
+ return 0x0000000000000020ull;
+}
+
+#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n");
+#endif
+ return 0x0000000000000000ull;
+}
+
+#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n");
+#endif
+ return 0x0000000000000010ull;
+}
+
+#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n");
+#endif
+ return 0x0000000000000018ull;
+}
+
+static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010018ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010020ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010028ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010068ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010060ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010058ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010010ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010030ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010050ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010048ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010080ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010088ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010090ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010098ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010040ull) + (offset & 3) * 16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010000ull) + (offset & 1) * 16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010038ull) + (offset & 1) * 16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001070000010008ull) + (offset & 1) * 16384;
+}
+
+static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000828ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000870ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000850ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000800ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000818ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000860ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000858ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000868ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000848ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000838ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000810ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000808ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000820ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000840ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0000830ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id == 0))))))
+ cvmx_warn
+ ("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x20000ull) * 1024;
+}
+
+static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000018ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000418ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000030ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000028ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000098ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000000ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000400ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000008ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000020ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000080ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000088ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000090ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x800000ull) * 16;
+}
+
+static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 3)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 3)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + ((offset & 3) +
+ (block_id & 1) *
+ 0x800000ull) * 16;
+}
+
+static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800C8000038ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + (offset & 31) * 16;
+}
+
+#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
+}
+
+#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
+}
+
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
+}
+
+#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
+}
+
+#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + (offset & 7) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + (offset & 7) * 16;
+}
+
+#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
+}
+
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
+}
+
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
+}
+
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset >= 12) && (offset <= 27))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset >= 12) && (offset <= 27))))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + (offset & 31) * 16 -
+ 16 * 12;
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long
+ offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long
+ offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long
+ offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + (offset & 31) * 16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long
+ offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + (offset & 31) * 16;
+}
+
+#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + (offset & 31) * 16;
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
+}
+
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
+}
+
+#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
+}
+
+#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
+}
+
+#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
+static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
+}
+
+#define CVMX_PIP_BIST_STATUS CVMX_PIP_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PIP_BIST_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000000ull);
+}
+
+static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + (offset & 1) * 8;
+}
+
+static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + (offset & 3) * 8;
+}
+
+#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
+}
+
+#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
+}
+
+static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + (offset & 1) * 8;
+}
+
+#define CVMX_PIP_GBL_CFG CVMX_PIP_GBL_CFG_FUNC()
+static inline uint64_t CVMX_PIP_GBL_CFG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000028ull);
+}
+
+#define CVMX_PIP_GBL_CTL CVMX_PIP_GBL_CTL_FUNC()
+static inline uint64_t CVMX_PIP_GBL_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000020ull);
+}
+
+#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
+static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
+}
+
+#define CVMX_PIP_INT_EN CVMX_PIP_INT_EN_FUNC()
+static inline uint64_t CVMX_PIP_INT_EN_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000010ull);
+}
+
+#define CVMX_PIP_INT_REG CVMX_PIP_INT_REG_FUNC()
+static inline uint64_t CVMX_PIP_INT_REG_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000008ull);
+}
+
+#define CVMX_PIP_IP_OFFSET CVMX_PIP_IP_OFFSET_FUNC()
+static inline uint64_t CVMX_PIP_IP_OFFSET_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000060ull);
+}
+
+static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
+ cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + (offset & 63) * 8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + (offset & 7) * 8;
+}
+
+#define CVMX_PIP_RAW_WORD CVMX_PIP_RAW_WORD_FUNC()
+static inline uint64_t CVMX_PIP_RAW_WORD_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A00000B0ull);
+}
+
+#define CVMX_PIP_SFT_RST CVMX_PIP_SFT_RST_FUNC()
+static inline uint64_t CVMX_PIP_SFT_RST_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000030ull);
+}
+
+static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + (offset & 63) * 80;
+}
+
+static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + (offset & 63) * 80;
+}
+
+#define CVMX_PIP_STAT_CTL CVMX_PIP_STAT_CTL_FUNC()
+static inline uint64_t CVMX_PIP_STAT_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000018ull);
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn
+ ("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + (offset & 63) * 32;
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn
+ ("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + (offset & 63) * 32;
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((offset <= 3) || ((offset >= 16) && (offset <= 19))
+ || ((offset >= 32) && (offset <= 35)) || ((offset >= 36)
+ && (offset <=
+ 39))))
+ || (OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((offset <= 2) || ((offset >= 32) && (offset <= 33))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35)))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((offset <= 3) || ((offset >= 32) && (offset <= 35))
+ || ((offset >= 36) && (offset <= 39))))))
+ cvmx_warn
+ ("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + (offset & 63) * 32;
+}
+
+static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
+ cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + (offset & 63) * 8;
+}
+
+#define CVMX_PIP_TAG_MASK CVMX_PIP_TAG_MASK_FUNC()
+static inline uint64_t CVMX_PIP_TAG_MASK_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000070ull);
+}
+
+#define CVMX_PIP_TAG_SECRET CVMX_PIP_TAG_SECRET_FUNC()
+static inline uint64_t CVMX_PIP_TAG_SECRET_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000068ull);
+}
+
+#define CVMX_PIP_TODO_ENTRY CVMX_PIP_TODO_ENTRY_FUNC()
+static inline uint64_t CVMX_PIP_TODO_ENTRY_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00011800A0000078ull);
+}
+
+#define CVMX_PKO_MEM_COUNT0 CVMX_PKO_MEM_COUNT0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_COUNT0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001080ull);
+}
+
+#define CVMX_PKO_MEM_COUNT1 CVMX_PKO_MEM_COUNT1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_COUNT1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001088ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG0 CVMX_PKO_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001100ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG1 CVMX_PKO_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001108ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG10 CVMX_PKO_MEM_DEBUG10_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG10_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001150ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG11 CVMX_PKO_MEM_DEBUG11_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG11_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001158ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG12 CVMX_PKO_MEM_DEBUG12_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG12_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001160ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG13 CVMX_PKO_MEM_DEBUG13_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG13_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001168ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050001170ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG2 CVMX_PKO_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001110ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG3 CVMX_PKO_MEM_DEBUG3_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG3_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001118ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG4 CVMX_PKO_MEM_DEBUG4_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG4_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001120ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG5 CVMX_PKO_MEM_DEBUG5_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG5_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001128ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG6 CVMX_PKO_MEM_DEBUG6_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG6_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001130ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG7 CVMX_PKO_MEM_DEBUG7_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG7_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001138ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG8 CVMX_PKO_MEM_DEBUG8_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG8_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001140ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG9 CVMX_PKO_MEM_DEBUG9_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG9_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001148ull);
+}
+
+#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050001010ull);
+}
+
+#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050001018ull);
+}
+
+#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050001020ull);
+}
+
+#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050001028ull);
+}
+
+#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001000ull);
+}
+
+#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050001008ull);
+}
+
+#define CVMX_PKO_REG_BIST_RESULT CVMX_PKO_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_PKO_REG_BIST_RESULT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000080ull);
+}
+
+#define CVMX_PKO_REG_CMD_BUF CVMX_PKO_REG_CMD_BUF_FUNC()
+static inline uint64_t CVMX_PKO_REG_CMD_BUF_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000010ull);
+}
+
+static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn
+ ("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000028ull) + (offset & 1) * 8;
+}
+
+#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
+static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000020ull);
+}
+
+static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000038ull) + (offset & 1) * 8;
+}
+
+#define CVMX_PKO_REG_DEBUG0 CVMX_PKO_REG_DEBUG0_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000098ull);
+}
+
+#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
+}
+
+#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
+}
+
+#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
+}
+
+#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000050ull);
+}
+
+#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000058ull);
+}
+
+#define CVMX_PKO_REG_ERROR CVMX_PKO_REG_ERROR_FUNC()
+static inline uint64_t CVMX_PKO_REG_ERROR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000088ull);
+}
+
+#define CVMX_PKO_REG_FLAGS CVMX_PKO_REG_FLAGS_FUNC()
+static inline uint64_t CVMX_PKO_REG_FLAGS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000000ull);
+}
+
+#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
+static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000018ull);
+}
+
+#define CVMX_PKO_REG_INT_MASK CVMX_PKO_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_PKO_REG_INT_MASK_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000090ull);
+}
+
+#define CVMX_PKO_REG_QUEUE_MODE CVMX_PKO_REG_QUEUE_MODE_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_MODE_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000048ull);
+}
+
+#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn
+ ("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180050000100ull);
+}
+
+#define CVMX_PKO_REG_READ_IDX CVMX_PKO_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_PKO_REG_READ_IDX_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180050000008ull);
+}
+
+#define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
+static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
+}
+
+#define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
+static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000398ull);
+}
+
+#define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
+static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000218ull);
+}
+
+#define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
+static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000220ull);
+}
+
+static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000340ull) + (offset & 7) * 8;
+}
+
+#define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
+static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000388ull);
+}
+
+#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000238ull);
+}
+
+#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000240ull);
+}
+
+static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + (offset & 7) * 8;
+}
+
+#define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
+static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000228ull);
+}
+
+#define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
+static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000210ull);
+}
+
+#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
+static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+ cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000230ull);
+}
+
+static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000000ull) + (offset & 15) * 8;
+}
+
+static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + (offset & 7) * 8;
+}
+
+static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000180ull) + (offset & 7) * 8;
+}
+
+#define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
+static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000390ull);
+}
+
+#define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
+static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000380ull);
+}
+
+static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+ cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000300ull) + (offset & 7) * 8;
+}
+
+#define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000200ull);
+}
+
+static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+ cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000100ull) + (offset & 15) * 8;
+}
+
+#define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001670000000208ull);
+}
+
+static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+ cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000080ull) + (offset & 15) * 8;
+}
+
+static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+ cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001670000000280ull) + (offset & 15) * 8;
+}
+
+#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070001000ull);
+}
+
+#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070001008ull);
+}
+
+#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070001010ull);
+}
+
+#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000080ull);
+}
+
+#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
+static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000008ull);
+}
+
+#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
+static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000000ull);
+}
+
+#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000100ull);
+}
+
+#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000108ull);
+}
+
+#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000150ull);
+}
+
+#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000158ull);
+}
+
+#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000160ull);
+}
+
+#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000110ull);
+}
+
+#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000118ull);
+}
+
+#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000120ull);
+}
+
+#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000128ull);
+}
+
+#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000130ull);
+}
+
+#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000138ull);
+}
+
+#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000140ull);
+}
+
+#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000148ull);
+}
+
+#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
+static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000088ull);
+}
+
+#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000090ull);
+}
+
+#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
+static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn
+ ("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000010ull);
+}
+
+#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+ cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180070000018ull);
+}
+
+#define CVMX_RNM_BIST_STATUS CVMX_RNM_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_RNM_BIST_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180040000008ull);
+}
+
+#define CVMX_RNM_CTL_STATUS CVMX_RNM_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_RNM_CTL_STATUS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180040000000ull);
+}
+
+static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset & 1) * 256;
+}
+
+static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset & 1) * 256;
+}
+
+static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset & 1) * 256;
+}
+
+static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset & 1) * 256;
+}
+
+static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n",
+ offset);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset & 1) * 256;
+}
+
+#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+ cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000388ull);
+}
+
+#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+ cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000380ull);
+}
+
+static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000340ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800900007F8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000348ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000350ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000368ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000370ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000358ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000320ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000318ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000308ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000300ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000310ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000338ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000330ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000328ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000360ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000200ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000218ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 31)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 31)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000000ull) + ((offset & 31) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000208ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000220ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000228ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000608ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000688ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000600ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000690ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000610ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800900006A0ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000698ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800900006A8ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000618ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX)
+ && (((offset <= 31)) && ((block_id <= 1))))
+ || (OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && (((offset <= 31)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000400ull) + ((offset & 31) +
+ (block_id & 1) *
+ 0x1000000ull) * 8;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000628ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000630ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000648ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000680ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000638ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180090000640ull) +
+ (block_id & 1) * 0x8000000ull;
+}
+
+#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058001100ull);
+}
+
+#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058001108ull);
+}
+
+#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058001110ull);
+}
+
+#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058001000ull);
+}
+
+#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058001008ull);
+}
+
+#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058000080ull);
+}
+
+#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC()
+static inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058000088ull);
+}
+
+#define CVMX_TIM_REG_FLAGS CVMX_TIM_REG_FLAGS_FUNC()
+static inline uint64_t CVMX_TIM_REG_FLAGS_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058000000ull);
+}
+
+#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058000090ull);
+}
+
+#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void)
+{
+ return CVMX_ADD_IO_SEG(0x0001180058000008ull);
+}
+
+#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
+}
+
+#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
+static inline uint64_t CVMX_TRA_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
+}
+
+#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
+}
+
+#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
+}
+
+#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
+}
+
+#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
+}
+
+#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
+static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
+}
+
+#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
+}
+
+#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
+}
+
+#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
+}
+
+#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
+static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
+}
+
+#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
+}
+
+#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
+}
+
+#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
+}
+
+#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
+}
+
+#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
+}
+
+#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
+}
+
+#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
+}
+
+#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
+}
+
+#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
+}
+
+#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
+}
+
+static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000818ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000081Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000800ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000804ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000810ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000814ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 4)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 4)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && ((((offset >= 1) && (offset <= 4)))
+ && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x40000000000ull) * 4;
+}
+
+static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000808ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000820ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000824ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000830ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000834ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000008ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000044ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000048ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000004Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000050ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000018ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000014ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000028ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000002Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000000ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000004ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000010ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000024ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010040020ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000020ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001004001Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000001Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000040ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000000Cull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000414ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000418ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000400ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x8000000000ull) * 32;
+}
+
+static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000404ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000408ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000440ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000100ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000410ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset,
+ unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN50XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ && (((offset <= 7)) && ((block_id == 0))))
+ || (OCTEON_IS_MODEL(OCTEON_CN52XX)
+ && (((offset <= 7)) && ((block_id <= 1))))))
+ cvmx_warn
+ ("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n",
+ offset, block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + ((offset & 7) +
+ (block_id & 1) *
+ 0x100000000ull) * 4096;
+}
+
+static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800680007F8ull) +
+ (block_id & 1) * 0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180068000010ull) +
+ (block_id & 1) * 0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000800ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000818ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000820ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000828ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000830ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000838ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000840ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000848ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000850ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000858ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000860ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000868ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000870ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000878ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000880ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000888ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000890ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x00016F0000000808ull) +
+ (block_id & 1) * 0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180068000008ull) +
+ (block_id & 1) * 0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180068000000ull) +
+ (block_id & 1) * 0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!((OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+ cvmx_warn
+ ("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n",
+ block_id);
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180068000018ull) +
+ (block_id & 1) * 0x10000000ull;
+}
+
+#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn
+ ("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000080ull);
+}
+
+#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000008ull);
+}
+
+#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000000ull);
+}
+
+#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
+static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
+}
+
+#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
+static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000098ull);
+}
+
+#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
+static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000088ull);
+}
+
+#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
+static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+ if (!
+ (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+ cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
+#endif
+ return CVMX_ADD_IO_SEG(0x0001180038000090ull);
+}
+
+#endif /* __CVMX_CSR_ADDRESSES_H__ */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-csr-enums.h b/arch/mips/cavium-octeon/executive/cvmx-csr-enums.h
new file mode 100644
index 0000000..387cf80
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-csr-enums.h
@@ -0,0 +1,86 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_CSR_ENUMS_H__
+#define __CVMX_CSR_ENUMS_H__
+
+typedef enum {
+ CVMX_IPD_OPC_MODE_STT = 0LL,
+ CVMX_IPD_OPC_MODE_STF = 1LL,
+ CVMX_IPD_OPC_MODE_STF1_STT = 2LL,
+ CVMX_IPD_OPC_MODE_STF2_STT = 3LL
+} cvmx_ipd_mode_t;
+
+typedef enum {
+ CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
+
+ CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
+
+ CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
+
+} cvmx_pip_port_parse_mode_t;
+
+typedef enum {
+ CVMX_PIP_QOS_WATCH_DISABLE = 0ull,
+
+ CVMX_PIP_QOS_WATCH_PROTNH = 1ull,
+ CVMX_PIP_QOS_WATCH_TCP = 2ull,
+ CVMX_PIP_QOS_WATCH_UDP = 3ull
+} cvmx_pip_qos_watch_types;
+
+typedef enum {
+ CVMX_PIP_TAG_MODE_TUPLE = 0ull,
+ CVMX_PIP_TAG_MODE_MASK = 1ull,
+ CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull,
+ CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull
+
+} cvmx_pip_tag_mode_t;
+
+typedef enum {
+ CVMX_POW_TAG_TYPE_ORDERED = 0L,
+ CVMX_POW_TAG_TYPE_ATOMIC = 1L,
+ CVMX_POW_TAG_TYPE_NULL = 2L,
+ CVMX_POW_TAG_TYPE_NULL_NULL = 3L
+} cvmx_pow_tag_type_t;
+
+typedef enum {
+ CVMX_UART_BITS5 = 0,
+ CVMX_UART_BITS6 = 1,
+ CVMX_UART_BITS7 = 2,
+ CVMX_UART_BITS8 = 3
+} cvmx_uart_bits_t;
+
+typedef enum {
+ CVMX_UART_IID_NONE = 1,
+ CVMX_UART_IID_RX_ERROR = 6,
+ CVMX_UART_IID_RX_DATA = 4,
+ CVMX_UART_IID_RX_TIMEOUT = 12,
+ CVMX_UART_IID_TX_EMPTY = 2,
+ CVMX_UART_IID_MODEM = 0,
+ CVMX_UART_IID_BUSY = 7
+} cvmx_uart_iid_t;
+
+#endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-csr-typedefs.h b/arch/mips/cavium-octeon/executive/cvmx-csr-typedefs.h
new file mode 100644
index 0000000..a7879d7
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-csr-typedefs.h
@@ -0,0 +1,44156 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_CSR_TYPEDEFS_H__
+#define __CVMX_CSR_TYPEDEFS_H__
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_bad_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t txpsh1:1;
+ uint64_t txpop1:1;
+ uint64_t ovrflw1:1;
+ uint64_t txpsh:1;
+ uint64_t txpop:1;
+ uint64_t ovrflw:1;
+ uint64_t reserved_27_31:5;
+ uint64_t statovr:1;
+ uint64_t reserved_23_25:3;
+ uint64_t loststat:1;
+ uint64_t reserved_4_21:18;
+ uint64_t out_ovr:2;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t out_ovr:2;
+ uint64_t reserved_4_21:18;
+ uint64_t loststat:1;
+ uint64_t reserved_23_25:3;
+ uint64_t statovr:1;
+ uint64_t reserved_27_31:5;
+ uint64_t ovrflw:1;
+ uint64_t txpop:1;
+ uint64_t txpsh:1;
+ uint64_t ovrflw1:1;
+ uint64_t txpop1:1;
+ uint64_t txpsh1:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_agl_gmx_bad_reg_s cn52xx;
+ struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+ struct cvmx_agl_gmx_bad_reg_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_35_63:29;
+ uint64_t txpsh:1;
+ uint64_t txpop:1;
+ uint64_t ovrflw:1;
+ uint64_t reserved_27_31:5;
+ uint64_t statovr:1;
+ uint64_t reserved_23_25:3;
+ uint64_t loststat:1;
+ uint64_t reserved_3_21:19;
+ uint64_t out_ovr:1;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t out_ovr:1;
+ uint64_t reserved_3_21:19;
+ uint64_t loststat:1;
+ uint64_t reserved_23_25:3;
+ uint64_t statovr:1;
+ uint64_t reserved_27_31:5;
+ uint64_t ovrflw:1;
+ uint64_t txpop:1;
+ uint64_t txpsh:1;
+ uint64_t reserved_35_63:29;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+} cvmx_agl_gmx_bad_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_bist_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t status:10;
+#else
+ uint64_t status:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_agl_gmx_bist_s cn52xx;
+ struct cvmx_agl_gmx_bist_s cn52xxp1;
+ struct cvmx_agl_gmx_bist_s cn56xx;
+ struct cvmx_agl_gmx_bist_s cn56xxp1;
+} cvmx_agl_gmx_bist_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_drv_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t byp_en1:1;
+ uint64_t reserved_45_47:3;
+ uint64_t pctl1:5;
+ uint64_t reserved_37_39:3;
+ uint64_t nctl1:5;
+ uint64_t reserved_17_31:15;
+ uint64_t byp_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+ uint64_t reserved_13_15:3;
+ uint64_t byp_en:1;
+ uint64_t reserved_17_31:15;
+ uint64_t nctl1:5;
+ uint64_t reserved_37_39:3;
+ uint64_t pctl1:5;
+ uint64_t reserved_45_47:3;
+ uint64_t byp_en1:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_agl_gmx_drv_ctl_s cn52xx;
+ struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t byp_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+ uint64_t reserved_13_15:3;
+ uint64_t byp_en:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
+} cvmx_agl_gmx_drv_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_inf_mode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t en:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t en:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_agl_gmx_inf_mode_s cn52xx;
+ struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
+ struct cvmx_agl_gmx_inf_mode_s cn56xx;
+ struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
+} cvmx_agl_gmx_inf_mode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_prtx_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t tx_en:1;
+ uint64_t rx_en:1;
+ uint64_t slottime:1;
+ uint64_t duplex:1;
+ uint64_t speed:1;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t speed:1;
+ uint64_t duplex:1;
+ uint64_t slottime:1;
+ uint64_t rx_en:1;
+ uint64_t tx_en:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+} cvmx_agl_gmx_prtx_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t en:8;
+#else
+ uint64_t en:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t cam_mode:1;
+ uint64_t mcst:2;
+ uint64_t bcst:1;
+#else
+ uint64_t bcst:1;
+ uint64_t mcst:2;
+ uint64_t cam_mode:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_decision_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t cnt:5;
+#else
+ uint64_t cnt:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_decision_s cn52xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_decision_s cn56xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+} cvmx_agl_gmx_rxx_decision_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_frm_chk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_chk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pre_align:1;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t vlan_len:1;
+ uint64_t pad_len:1;
+ uint64_t pre_align:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_frm_max_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t len:16;
+#else
+ uint64_t len:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_max_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_frm_min_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t len:16;
+#else
+ uint64_t len:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_min_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_ifg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ifg:4;
+#else
+ uint64_t ifg:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+} cvmx_agl_gmx_rxx_ifg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+} cvmx_agl_gmx_rxx_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t reserved_1_1:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+} cvmx_agl_gmx_rxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_jabber_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+} cvmx_agl_gmx_rxx_jabber_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t status:16;
+#else
+ uint64_t status:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+} cvmx_agl_gmx_rxx_pause_drop_time_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rd_clr:1;
+#else
+ uint64_t rd_clr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_octs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_drp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_bad_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_drp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_udd_skp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t fcssel:1;
+ uint64_t reserved_7_7:1;
+ uint64_t len:7;
+#else
+ uint64_t len:7;
+ uint64_t reserved_7_7:1;
+ uint64_t fcssel:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+} cvmx_agl_gmx_rxx_udd_skp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rx_bp_dropx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mark:6;
+#else
+ uint64_t mark:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+} cvmx_agl_gmx_rx_bp_dropx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rx_bp_offx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mark:6;
+#else
+ uint64_t mark:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+} cvmx_agl_gmx_rx_bp_offx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rx_bp_onx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t mark:9;
+#else
+ uint64_t mark:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+} cvmx_agl_gmx_rx_bp_onx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rx_prt_info_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t drop:2;
+ uint64_t reserved_2_15:14;
+ uint64_t commit:2;
+#else
+ uint64_t commit:2;
+ uint64_t reserved_2_15:14;
+ uint64_t drop:2;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
+ struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
+ struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t drop:1;
+ uint64_t reserved_1_15:15;
+ uint64_t commit:1;
+#else
+ uint64_t commit:1;
+ uint64_t reserved_1_15:15;
+ uint64_t drop:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+} cvmx_agl_gmx_rx_prt_info_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rx_tx_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t tx:2;
+ uint64_t reserved_2_3:2;
+ uint64_t rx:2;
+#else
+ uint64_t rx:2;
+ uint64_t reserved_2_3:2;
+ uint64_t tx:2;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
+ struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
+ struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t tx:1;
+ uint64_t reserved_1_3:3;
+ uint64_t rx:1;
+#else
+ uint64_t rx:1;
+ uint64_t reserved_1_3:3;
+ uint64_t tx:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+} cvmx_agl_gmx_rx_tx_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_smacx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t smac:48;
+#else
+ uint64_t smac:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_smacx_s cn52xx;
+ struct cvmx_agl_gmx_smacx_s cn52xxp1;
+ struct cvmx_agl_gmx_smacx_s cn56xx;
+ struct cvmx_agl_gmx_smacx_s cn56xxp1;
+} cvmx_agl_gmx_smacx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_stat_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t bp:1;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t bp:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_agl_gmx_stat_bp_s cn52xx;
+ struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
+ struct cvmx_agl_gmx_stat_bp_s cn56xx;
+ struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+} cvmx_agl_gmx_stat_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_append_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t force_fcs:1;
+ uint64_t fcs:1;
+ uint64_t pad:1;
+ uint64_t preamble:1;
+#else
+ uint64_t preamble:1;
+ uint64_t pad:1;
+ uint64_t fcs:1;
+ uint64_t force_fcs:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_append_s cn52xx;
+ struct cvmx_agl_gmx_txx_append_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_append_s cn56xx;
+ struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+} cvmx_agl_gmx_txx_append_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t xsdef_en:1;
+ uint64_t xscol_en:1;
+#else
+ uint64_t xscol_en:1;
+ uint64_t xsdef_en:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_ctl_s cn52xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_ctl_s cn56xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+} cvmx_agl_gmx_txx_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_min_pkt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t min_size:8;
+#else
+ uint64_t min_size:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+} cvmx_agl_gmx_txx_min_pkt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t interval:16;
+#else
+ uint64_t interval:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_pkt_interval_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_pkt_time_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_pause_togo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_togo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_pause_zero_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t send:1;
+#else
+ uint64_t send:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_zero_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_soft_pause_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+} cvmx_agl_gmx_txx_soft_pause_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t xsdef:32;
+ uint64_t xscol:32;
+#else
+ uint64_t xscol:32;
+ uint64_t xsdef:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat0_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat0_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t scol:32;
+ uint64_t mcol:32;
+#else
+ uint64_t mcol:32;
+ uint64_t scol:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat1_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat1_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t octs:48;
+#else
+ uint64_t octs:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat2_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat2_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pkts:32;
+#else
+ uint64_t pkts:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat3_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat3_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist1:32;
+ uint64_t hist0:32;
+#else
+ uint64_t hist0:32;
+ uint64_t hist1:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat4_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat4_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist3:32;
+ uint64_t hist2:32;
+#else
+ uint64_t hist2:32;
+ uint64_t hist3:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat5_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat5_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist5:32;
+ uint64_t hist4:32;
+#else
+ uint64_t hist4:32;
+ uint64_t hist5:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat6_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat6_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist7:32;
+ uint64_t hist6:32;
+#else
+ uint64_t hist6:32;
+ uint64_t hist7:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat7_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat7_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat8_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mcst:32;
+ uint64_t bcst:32;
+#else
+ uint64_t bcst:32;
+ uint64_t mcst:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat8_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat8_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat8_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stat9_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t undflw:32;
+ uint64_t ctl:32;
+#else
+ uint64_t ctl:32;
+ uint64_t undflw:32;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stat9_s cn52xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stat9_s cn56xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+} cvmx_agl_gmx_txx_stat9_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_stats_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rd_clr:1;
+#else
+ uint64_t rd_clr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+} cvmx_agl_gmx_txx_stats_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_thresh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t cnt:6;
+#else
+ uint64_t cnt:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_agl_gmx_txx_thresh_s cn52xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
+ struct cvmx_agl_gmx_txx_thresh_s cn56xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+} cvmx_agl_gmx_txx_thresh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t bp:2;
+#else
+ uint64_t bp:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_bp_s cn52xx;
+ struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_bp_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t bp:1;
+#else
+ uint64_t bp:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_col_attempt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t limit:5;
+#else
+ uint64_t limit:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+} cvmx_agl_gmx_tx_col_attempt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_ifg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ifg2:4;
+ uint64_t ifg1:4;
+#else
+ uint64_t ifg1:4;
+ uint64_t ifg2:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_ifg_s cn52xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_ifg_s cn56xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+} cvmx_agl_gmx_tx_ifg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:2;
+ uint64_t reserved_4_7:4;
+ uint64_t xscol:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_14_15:2;
+ uint64_t late_col:2;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_int_en_s cn52xx;
+ struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_en_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t late_col:1;
+ uint64_t reserved_13_15:3;
+ uint64_t xsdef:1;
+ uint64_t reserved_9_11:3;
+ uint64_t xscol:1;
+ uint64_t reserved_3_7:5;
+ uint64_t undflw:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:1;
+ uint64_t reserved_3_7:5;
+ uint64_t xscol:1;
+ uint64_t reserved_9_11:3;
+ uint64_t xsdef:1;
+ uint64_t reserved_13_15:3;
+ uint64_t late_col:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:2;
+ uint64_t reserved_4_7:4;
+ uint64_t xscol:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_14_15:2;
+ uint64_t late_col:2;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
+ struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t late_col:1;
+ uint64_t reserved_13_15:3;
+ uint64_t xsdef:1;
+ uint64_t reserved_9_11:3;
+ uint64_t xscol:1;
+ uint64_t reserved_3_7:5;
+ uint64_t undflw:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:1;
+ uint64_t reserved_3_7:5;
+ uint64_t xscol:1;
+ uint64_t reserved_9_11:3;
+ uint64_t xsdef:1;
+ uint64_t reserved_13_15:3;
+ uint64_t late_col:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_jam_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t jam:8;
+#else
+ uint64_t jam:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_jam_s cn52xx;
+ struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_jam_s cn56xx;
+ struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+} cvmx_agl_gmx_tx_jam_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_lfsr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t lfsr:16;
+#else
+ uint64_t lfsr:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+} cvmx_agl_gmx_tx_lfsr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_ovr_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t en:2;
+ uint64_t reserved_6_7:2;
+ uint64_t bp:2;
+ uint64_t reserved_2_3:2;
+ uint64_t ign_full:2;
+#else
+ uint64_t ign_full:2;
+ uint64_t reserved_2_3:2;
+ uint64_t bp:2;
+ uint64_t reserved_6_7:2;
+ uint64_t en:2;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t en:1;
+ uint64_t reserved_5_7:3;
+ uint64_t bp:1;
+ uint64_t reserved_1_3:3;
+ uint64_t ign_full:1;
+#else
+ uint64_t ign_full:1;
+ uint64_t reserved_1_3:3;
+ uint64_t bp:1;
+ uint64_t reserved_5_7:3;
+ uint64_t en:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn56xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_ovr_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t dmac:48;
+#else
+ uint64_t dmac:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+} cvmx_agl_gmx_tx_pause_pkt_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t type:16;
+#else
+ uint64_t type:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+} cvmx_agl_gmx_tx_pause_pkt_type_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_gmii_rx_clk_set_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
+} cvmx_asxx_gmii_rx_clk_set_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_gmii_rx_dat_set_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
+} cvmx_asxx_gmii_rx_dat_set_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t txpsh:4;
+ uint64_t txpop:4;
+ uint64_t ovrflw:4;
+#else
+ uint64_t ovrflw:4;
+ uint64_t txpop:4;
+ uint64_t txpsh:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_asxx_int_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t txpsh:3;
+ uint64_t reserved_7_7:1;
+ uint64_t txpop:3;
+ uint64_t reserved_3_3:1;
+ uint64_t ovrflw:3;
+#else
+ uint64_t ovrflw:3;
+ uint64_t reserved_3_3:1;
+ uint64_t txpop:3;
+ uint64_t reserved_7_7:1;
+ uint64_t txpsh:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_int_en_cn30xx cn31xx;
+ struct cvmx_asxx_int_en_s cn38xx;
+ struct cvmx_asxx_int_en_s cn38xxp2;
+ struct cvmx_asxx_int_en_cn30xx cn50xx;
+ struct cvmx_asxx_int_en_s cn58xx;
+ struct cvmx_asxx_int_en_s cn58xxp1;
+} cvmx_asxx_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t txpsh:4;
+ uint64_t txpop:4;
+ uint64_t ovrflw:4;
+#else
+ uint64_t ovrflw:4;
+ uint64_t txpop:4;
+ uint64_t txpsh:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_asxx_int_reg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t txpsh:3;
+ uint64_t reserved_7_7:1;
+ uint64_t txpop:3;
+ uint64_t reserved_3_3:1;
+ uint64_t ovrflw:3;
+#else
+ uint64_t ovrflw:3;
+ uint64_t reserved_3_3:1;
+ uint64_t txpop:3;
+ uint64_t reserved_7_7:1;
+ uint64_t txpsh:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_int_reg_cn30xx cn31xx;
+ struct cvmx_asxx_int_reg_s cn38xx;
+ struct cvmx_asxx_int_reg_s cn38xxp2;
+ struct cvmx_asxx_int_reg_cn30xx cn50xx;
+ struct cvmx_asxx_int_reg_s cn58xx;
+ struct cvmx_asxx_int_reg_s cn58xxp1;
+} cvmx_asxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_mii_rx_dat_set_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
+ struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
+} cvmx_asxx_mii_rx_dat_set_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_prt_loop_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ext_loop:4;
+ uint64_t int_loop:4;
+#else
+ uint64_t int_loop:4;
+ uint64_t ext_loop:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_asxx_prt_loop_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t ext_loop:3;
+ uint64_t reserved_3_3:1;
+ uint64_t int_loop:3;
+#else
+ uint64_t int_loop:3;
+ uint64_t reserved_3_3:1;
+ uint64_t ext_loop:3;
+ uint64_t reserved_7_63:57;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_prt_loop_cn30xx cn31xx;
+ struct cvmx_asxx_prt_loop_s cn38xx;
+ struct cvmx_asxx_prt_loop_s cn38xxp2;
+ struct cvmx_asxx_prt_loop_cn30xx cn50xx;
+ struct cvmx_asxx_prt_loop_s cn58xx;
+ struct cvmx_asxx_prt_loop_s cn58xxp1;
+} cvmx_asxx_prt_loop_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_bypass_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t bypass:1;
+#else
+ uint64_t bypass:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_asxx_rld_bypass_s cn38xx;
+ struct cvmx_asxx_rld_bypass_s cn38xxp2;
+ struct cvmx_asxx_rld_bypass_s cn58xx;
+ struct cvmx_asxx_rld_bypass_s cn58xxp1;
+} cvmx_asxx_rld_bypass_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_bypass_setting_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rld_bypass_setting_s cn38xx;
+ struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
+ struct cvmx_asxx_rld_bypass_setting_s cn58xx;
+ struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
+} cvmx_asxx_rld_bypass_setting_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_comp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t pctl:5;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:5;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_asxx_rld_comp_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t pctl:4;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn38xx;
+ struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
+ struct cvmx_asxx_rld_comp_s cn58xx;
+ struct cvmx_asxx_rld_comp_s cn58xxp1;
+} cvmx_asxx_rld_comp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_data_drv_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t pctl:4;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_asxx_rld_data_drv_s cn38xx;
+ struct cvmx_asxx_rld_data_drv_s cn38xxp2;
+ struct cvmx_asxx_rld_data_drv_s cn58xx;
+ struct cvmx_asxx_rld_data_drv_s cn58xxp1;
+} cvmx_asxx_rld_data_drv_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_fcram_mode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t mode:1;
+#else
+ uint64_t mode:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_asxx_rld_fcram_mode_s cn38xx;
+ struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
+} cvmx_asxx_rld_fcram_mode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_nctl_strong_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rld_nctl_strong_s cn38xx;
+ struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
+ struct cvmx_asxx_rld_nctl_strong_s cn58xx;
+ struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
+} cvmx_asxx_rld_nctl_strong_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_nctl_weak_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rld_nctl_weak_s cn38xx;
+ struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
+ struct cvmx_asxx_rld_nctl_weak_s cn58xx;
+ struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
+} cvmx_asxx_rld_nctl_weak_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_pctl_strong_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t pctl:5;
+#else
+ uint64_t pctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rld_pctl_strong_s cn38xx;
+ struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
+ struct cvmx_asxx_rld_pctl_strong_s cn58xx;
+ struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
+} cvmx_asxx_rld_pctl_strong_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_pctl_weak_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t pctl:5;
+#else
+ uint64_t pctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rld_pctl_weak_s cn38xx;
+ struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
+ struct cvmx_asxx_rld_pctl_weak_s cn58xx;
+ struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
+} cvmx_asxx_rld_pctl_weak_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rld_setting_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t dfaset:5;
+ uint64_t dfalag:1;
+ uint64_t dfalead:1;
+ uint64_t dfalock:1;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t dfalock:1;
+ uint64_t dfalead:1;
+ uint64_t dfalag:1;
+ uint64_t dfaset:5;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_asxx_rld_setting_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn38xx;
+ struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
+ struct cvmx_asxx_rld_setting_s cn58xx;
+ struct cvmx_asxx_rld_setting_s cn58xxp1;
+} cvmx_asxx_rld_setting_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_clk_setx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_rx_clk_setx_s cn30xx;
+ struct cvmx_asxx_rx_clk_setx_s cn31xx;
+ struct cvmx_asxx_rx_clk_setx_s cn38xx;
+ struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
+ struct cvmx_asxx_rx_clk_setx_s cn50xx;
+ struct cvmx_asxx_rx_clk_setx_s cn58xx;
+ struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
+} cvmx_asxx_rx_clk_setx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_prt_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t prt_en:4;
+#else
+ uint64_t prt_en:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_asxx_rx_prt_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t prt_en:3;
+#else
+ uint64_t prt_en:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
+ struct cvmx_asxx_rx_prt_en_s cn38xx;
+ struct cvmx_asxx_rx_prt_en_s cn38xxp2;
+ struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
+ struct cvmx_asxx_rx_prt_en_s cn58xx;
+ struct cvmx_asxx_rx_prt_en_s cn58xxp1;
+} cvmx_asxx_rx_prt_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_wol_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t status:1;
+ uint64_t enable:1;
+#else
+ uint64_t enable:1;
+ uint64_t status:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_asxx_rx_wol_s cn38xx;
+ struct cvmx_asxx_rx_wol_s cn38xxp2;
+} cvmx_asxx_rx_wol_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_wol_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t msk:64;
+#else
+ uint64_t msk:64;
+#endif
+ } s;
+ struct cvmx_asxx_rx_wol_msk_s cn38xx;
+ struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
+} cvmx_asxx_rx_wol_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_wol_powok_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t powerok:1;
+#else
+ uint64_t powerok:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_asxx_rx_wol_powok_s cn38xx;
+ struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
+} cvmx_asxx_rx_wol_powok_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_rx_wol_sig_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t sig:32;
+#else
+ uint64_t sig:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_asxx_rx_wol_sig_s cn38xx;
+ struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
+} cvmx_asxx_rx_wol_sig_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_tx_clk_setx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t setting:5;
+#else
+ uint64_t setting:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_asxx_tx_clk_setx_s cn30xx;
+ struct cvmx_asxx_tx_clk_setx_s cn31xx;
+ struct cvmx_asxx_tx_clk_setx_s cn38xx;
+ struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
+ struct cvmx_asxx_tx_clk_setx_s cn50xx;
+ struct cvmx_asxx_tx_clk_setx_s cn58xx;
+ struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
+} cvmx_asxx_tx_clk_setx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_tx_comp_byp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_asxx_tx_comp_byp_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t bypass:1;
+ uint64_t pctl:4;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:4;
+ uint64_t bypass:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
+ struct cvmx_asxx_tx_comp_byp_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t pctl:4;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn38xx;
+ struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
+ struct cvmx_asxx_tx_comp_byp_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t bypass:1;
+ uint64_t reserved_13_15:3;
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+ uint64_t reserved_13_15:3;
+ uint64_t bypass:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn50xx;
+ struct cvmx_asxx_tx_comp_byp_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn58xx;
+ struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
+} cvmx_asxx_tx_comp_byp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_tx_hi_waterx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t mark:4;
+#else
+ uint64_t mark:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t mark:3;
+#else
+ uint64_t mark:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
+ struct cvmx_asxx_tx_hi_waterx_s cn38xx;
+ struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
+ struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
+ struct cvmx_asxx_tx_hi_waterx_s cn58xx;
+ struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
+} cvmx_asxx_tx_hi_waterx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asxx_tx_prt_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t prt_en:4;
+#else
+ uint64_t prt_en:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_asxx_tx_prt_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t prt_en:3;
+#else
+ uint64_t prt_en:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
+ struct cvmx_asxx_tx_prt_en_s cn38xx;
+ struct cvmx_asxx_tx_prt_en_s cn38xxp2;
+ struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
+ struct cvmx_asxx_tx_prt_en_s cn58xx;
+ struct cvmx_asxx_tx_prt_en_s cn58xxp1;
+} cvmx_asxx_tx_prt_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asx0_dbg_data_drv_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t pctl:5;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:5;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_asx0_dbg_data_drv_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t pctl:4;
+ uint64_t nctl:4;
+#else
+ uint64_t nctl:4;
+ uint64_t pctl:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn38xx;
+ struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2;
+ struct cvmx_asx0_dbg_data_drv_s cn58xx;
+ struct cvmx_asx0_dbg_data_drv_s cn58xxp1;
+} cvmx_asx0_dbg_data_drv_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_asx0_dbg_data_enable_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_asx0_dbg_data_enable_s cn38xx;
+ struct cvmx_asx0_dbg_data_enable_s cn38xxp2;
+ struct cvmx_asx0_dbg_data_enable_s cn58xx;
+ struct cvmx_asx0_dbg_data_enable_s cn58xxp1;
+} cvmx_asx0_dbg_data_enable_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_bist_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t bist:4;
+#else
+ uint64_t bist:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_ciu_bist_s cn30xx;
+ struct cvmx_ciu_bist_s cn31xx;
+ struct cvmx_ciu_bist_s cn38xx;
+ struct cvmx_ciu_bist_s cn38xxp2;
+ struct cvmx_ciu_bist_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t bist:2;
+#else
+ uint64_t bist:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn50xx;
+ struct cvmx_ciu_bist_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t bist:3;
+#else
+ uint64_t bist:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_bist_cn52xx cn52xxp1;
+ struct cvmx_ciu_bist_s cn56xx;
+ struct cvmx_ciu_bist_s cn56xxp1;
+ struct cvmx_ciu_bist_s cn58xx;
+ struct cvmx_ciu_bist_s cn58xxp1;
+} cvmx_ciu_bist_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_dint_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dint:16;
+#else
+ uint64_t dint:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ciu_dint_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t dint:1;
+#else
+ uint64_t dint:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_dint_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dint:2;
+#else
+ uint64_t dint:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_dint_s cn38xx;
+ struct cvmx_ciu_dint_s cn38xxp2;
+ struct cvmx_ciu_dint_cn31xx cn50xx;
+ struct cvmx_ciu_dint_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t dint:4;
+#else
+ uint64_t dint:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_dint_cn52xx cn52xxp1;
+ struct cvmx_ciu_dint_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t dint:12;
+#else
+ uint64_t dint:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_dint_cn56xx cn56xxp1;
+ struct cvmx_ciu_dint_s cn58xx;
+ struct cvmx_ciu_dint_s cn58xxp1;
+} cvmx_ciu_dint_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_fuse_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t fuse:16;
+#else
+ uint64_t fuse:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ciu_fuse_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t fuse:1;
+#else
+ uint64_t fuse:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_fuse_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t fuse:2;
+#else
+ uint64_t fuse:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_fuse_s cn38xx;
+ struct cvmx_ciu_fuse_s cn38xxp2;
+ struct cvmx_ciu_fuse_cn31xx cn50xx;
+ struct cvmx_ciu_fuse_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t fuse:4;
+#else
+ uint64_t fuse:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_fuse_cn52xx cn52xxp1;
+ struct cvmx_ciu_fuse_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t fuse:12;
+#else
+ uint64_t fuse:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_fuse_cn56xx cn56xxp1;
+ struct cvmx_ciu_fuse_s cn58xx;
+ struct cvmx_ciu_fuse_s cn58xxp1;
+} cvmx_ciu_fuse_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_gstop_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t gstop:1;
+#else
+ uint64_t gstop:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_ciu_gstop_s cn30xx;
+ struct cvmx_ciu_gstop_s cn31xx;
+ struct cvmx_ciu_gstop_s cn38xx;
+ struct cvmx_ciu_gstop_s cn38xxp2;
+ struct cvmx_ciu_gstop_s cn50xx;
+ struct cvmx_ciu_gstop_s cn52xx;
+ struct cvmx_ciu_gstop_s cn52xxp1;
+ struct cvmx_ciu_gstop_s cn56xx;
+ struct cvmx_ciu_gstop_s cn56xxp1;
+ struct cvmx_ciu_gstop_s cn58xx;
+ struct cvmx_ciu_gstop_s cn58xxp1;
+} cvmx_ciu_gstop_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_47_47:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t reserved_47_47:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_intx_en0_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_intx_en0_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
+ struct cvmx_ciu_intx_en0_cn30xx cn50xx;
+ struct cvmx_ciu_intx_en0_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
+ struct cvmx_ciu_intx_en0_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_en0_cn38xx cn58xx;
+ struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+} cvmx_ciu_intx_en0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en0_w1c_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en0_w1c_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en0_w1c_s cn56xx;
+ struct cvmx_ciu_intx_en0_w1c_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en0_w1c_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en0_w1s_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en0_w1s_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en0_w1s_s cn56xx;
+ struct cvmx_ciu_intx_en0_w1s_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en0_w1s_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en1_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t wdog:1;
+#else
+ uint64_t wdog:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_intx_en1_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t wdog:2;
+#else
+ uint64_t wdog:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_intx_en1_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
+ struct cvmx_ciu_intx_en1_cn31xx cn50xx;
+ struct cvmx_ciu_intx_en1_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en1_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn52xxp1;
+ struct cvmx_ciu_intx_en1_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_en1_cn38xx cn58xx;
+ struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+} cvmx_ciu_intx_en1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en1_w1c_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en1_w1c_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en1_w1c_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en1_w1c_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en1_w1c_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en1_w1s_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en1_w1s_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en1_w1s_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en1_w1s_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en1_w1s_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_0_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_47_47:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t reserved_47_47:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn50xx;
+ struct cvmx_ciu_intx_en4_0_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
+ struct cvmx_ciu_intx_en4_0_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_en4_0_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+ struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+} cvmx_ciu_intx_en4_0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_0_w1c_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en4_0_w1c_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_0_w1s_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t reserved_44_44:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t reserved_44_44:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en4_0_w1s_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_1_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t wdog:2;
+#else
+ uint64_t wdog:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn50xx;
+ struct cvmx_ciu_intx_en4_1_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_1_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn52xxp1;
+ struct cvmx_ciu_intx_en4_1_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_en4_1_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn58xx;
+ struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+} cvmx_ciu_intx_en4_1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_1_w1c_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en4_1_w1c_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_en4_1_w1s_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn58xx;
+} cvmx_ciu_intx_en4_1_w1s_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_sum0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_sum0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_47_47:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t reserved_47_47:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_intx_sum0_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_intx_sum0_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
+ struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
+ struct cvmx_ciu_intx_sum0_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
+ struct cvmx_ciu_intx_sum0_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
+ struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+} cvmx_ciu_intx_sum0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_intx_sum4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } s;
+ struct cvmx_ciu_intx_sum4_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t mpi:1;
+ uint64_t pcm:1;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_47_47:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t reserved_47_47:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t pcm:1;
+ uint64_t mpi:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } cn50xx;
+ struct cvmx_ciu_intx_sum4_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_51_51:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
+ struct cvmx_ciu_intx_sum4_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t usb:1;
+ uint64_t reserved_57_58:2;
+ uint64_t twsi2:1;
+ uint64_t powiq:1;
+ uint64_t ipdppthr:1;
+ uint64_t mii:1;
+ uint64_t bootdma:1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
+ struct cvmx_ciu_intx_sum4_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t timer:4;
+ uint64_t key_zero:1;
+ uint64_t ipd_drp:1;
+ uint64_t gmx_drp:2;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+#else
+ uint64_t workq:16;
+ uint64_t gpio:16;
+ uint64_t mbox:2;
+ uint64_t uart:2;
+ uint64_t pci_int:4;
+ uint64_t pci_msi:4;
+ uint64_t wdog_sum:1;
+ uint64_t twsi:1;
+ uint64_t rml:1;
+ uint64_t trace:1;
+ uint64_t gmx_drp:2;
+ uint64_t ipd_drp:1;
+ uint64_t key_zero:1;
+ uint64_t timer:4;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn58xx;
+ struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+} cvmx_ciu_intx_sum4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_int_sum1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_ciu_int_sum1_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t wdog:1;
+#else
+ uint64_t wdog:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_int_sum1_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t wdog:2;
+#else
+ uint64_t wdog:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_int_sum1_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t wdog:16;
+#else
+ uint64_t wdog:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
+ struct cvmx_ciu_int_sum1_cn31xx cn50xx;
+ struct cvmx_ciu_int_sum1_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t nand:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_int_sum1_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t mii1:1;
+ uint64_t usb1:1;
+ uint64_t uart2:1;
+ uint64_t reserved_4_15:12;
+ uint64_t wdog:4;
+#else
+ uint64_t wdog:4;
+ uint64_t reserved_4_15:12;
+ uint64_t uart2:1;
+ uint64_t usb1:1;
+ uint64_t mii1:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn52xxp1;
+ struct cvmx_ciu_int_sum1_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t wdog:12;
+#else
+ uint64_t wdog:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
+ struct cvmx_ciu_int_sum1_cn38xx cn58xx;
+ struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+} cvmx_ciu_int_sum1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_mbox_clrx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bits:32;
+#else
+ uint64_t bits:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_ciu_mbox_clrx_s cn30xx;
+ struct cvmx_ciu_mbox_clrx_s cn31xx;
+ struct cvmx_ciu_mbox_clrx_s cn38xx;
+ struct cvmx_ciu_mbox_clrx_s cn38xxp2;
+ struct cvmx_ciu_mbox_clrx_s cn50xx;
+ struct cvmx_ciu_mbox_clrx_s cn52xx;
+ struct cvmx_ciu_mbox_clrx_s cn52xxp1;
+ struct cvmx_ciu_mbox_clrx_s cn56xx;
+ struct cvmx_ciu_mbox_clrx_s cn56xxp1;
+ struct cvmx_ciu_mbox_clrx_s cn58xx;
+ struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+} cvmx_ciu_mbox_clrx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_mbox_setx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bits:32;
+#else
+ uint64_t bits:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_ciu_mbox_setx_s cn30xx;
+ struct cvmx_ciu_mbox_setx_s cn31xx;
+ struct cvmx_ciu_mbox_setx_s cn38xx;
+ struct cvmx_ciu_mbox_setx_s cn38xxp2;
+ struct cvmx_ciu_mbox_setx_s cn50xx;
+ struct cvmx_ciu_mbox_setx_s cn52xx;
+ struct cvmx_ciu_mbox_setx_s cn52xxp1;
+ struct cvmx_ciu_mbox_setx_s cn56xx;
+ struct cvmx_ciu_mbox_setx_s cn56xxp1;
+ struct cvmx_ciu_mbox_setx_s cn58xx;
+ struct cvmx_ciu_mbox_setx_s cn58xxp1;
+} cvmx_ciu_mbox_setx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_nmi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t nmi:16;
+#else
+ uint64_t nmi:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ciu_nmi_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t nmi:1;
+#else
+ uint64_t nmi:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_nmi_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t nmi:2;
+#else
+ uint64_t nmi:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_nmi_s cn38xx;
+ struct cvmx_ciu_nmi_s cn38xxp2;
+ struct cvmx_ciu_nmi_cn31xx cn50xx;
+ struct cvmx_ciu_nmi_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t nmi:4;
+#else
+ uint64_t nmi:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_nmi_cn52xx cn52xxp1;
+ struct cvmx_ciu_nmi_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t nmi:12;
+#else
+ uint64_t nmi:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_nmi_cn56xx cn56xxp1;
+ struct cvmx_ciu_nmi_s cn58xx;
+ struct cvmx_ciu_nmi_s cn58xxp1;
+} cvmx_ciu_nmi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_pci_inta_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t intr:2;
+#else
+ uint64_t intr:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_ciu_pci_inta_s cn30xx;
+ struct cvmx_ciu_pci_inta_s cn31xx;
+ struct cvmx_ciu_pci_inta_s cn38xx;
+ struct cvmx_ciu_pci_inta_s cn38xxp2;
+ struct cvmx_ciu_pci_inta_s cn50xx;
+ struct cvmx_ciu_pci_inta_s cn52xx;
+ struct cvmx_ciu_pci_inta_s cn52xxp1;
+ struct cvmx_ciu_pci_inta_s cn56xx;
+ struct cvmx_ciu_pci_inta_s cn56xxp1;
+ struct cvmx_ciu_pci_inta_s cn58xx;
+ struct cvmx_ciu_pci_inta_s cn58xxp1;
+} cvmx_ciu_pci_inta_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_pp_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ppdbg:16;
+#else
+ uint64_t ppdbg:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ciu_pp_dbg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t ppdbg:1;
+#else
+ uint64_t ppdbg:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_pp_dbg_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t ppdbg:2;
+#else
+ uint64_t ppdbg:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_pp_dbg_s cn38xx;
+ struct cvmx_ciu_pp_dbg_s cn38xxp2;
+ struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
+ struct cvmx_ciu_pp_dbg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ppdbg:4;
+#else
+ uint64_t ppdbg:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
+ struct cvmx_ciu_pp_dbg_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t ppdbg:12;
+#else
+ uint64_t ppdbg:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
+ struct cvmx_ciu_pp_dbg_s cn58xx;
+ struct cvmx_ciu_pp_dbg_s cn58xxp1;
+} cvmx_ciu_pp_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_pp_pokex_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_ciu_pp_pokex_s cn30xx;
+ struct cvmx_ciu_pp_pokex_s cn31xx;
+ struct cvmx_ciu_pp_pokex_s cn38xx;
+ struct cvmx_ciu_pp_pokex_s cn38xxp2;
+ struct cvmx_ciu_pp_pokex_s cn50xx;
+ struct cvmx_ciu_pp_pokex_s cn52xx;
+ struct cvmx_ciu_pp_pokex_s cn52xxp1;
+ struct cvmx_ciu_pp_pokex_s cn56xx;
+ struct cvmx_ciu_pp_pokex_s cn56xxp1;
+ struct cvmx_ciu_pp_pokex_s cn58xx;
+ struct cvmx_ciu_pp_pokex_s cn58xxp1;
+} cvmx_ciu_pp_pokex_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_pp_rst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t rst:15;
+ uint64_t rst0:1;
+#else
+ uint64_t rst0:1;
+ uint64_t rst:15;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ciu_pp_rst_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rst0:1;
+#else
+ uint64_t rst0:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn30xx;
+ struct cvmx_ciu_pp_rst_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t rst:1;
+ uint64_t rst0:1;
+#else
+ uint64_t rst0:1;
+ uint64_t rst:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_ciu_pp_rst_s cn38xx;
+ struct cvmx_ciu_pp_rst_s cn38xxp2;
+ struct cvmx_ciu_pp_rst_cn31xx cn50xx;
+ struct cvmx_ciu_pp_rst_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t rst:3;
+ uint64_t rst0:1;
+#else
+ uint64_t rst0:1;
+ uint64_t rst:3;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
+ struct cvmx_ciu_pp_rst_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t rst:11;
+ uint64_t rst0:1;
+#else
+ uint64_t rst0:1;
+ uint64_t rst:11;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
+ struct cvmx_ciu_pp_rst_s cn58xx;
+ struct cvmx_ciu_pp_rst_s cn58xxp1;
+} cvmx_ciu_pp_rst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_qlm_dcok_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t qlm_dcok:4;
+#else
+ uint64_t qlm_dcok:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_ciu_qlm_dcok_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t qlm_dcok:2;
+#else
+ uint64_t qlm_dcok:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
+ struct cvmx_ciu_qlm_dcok_s cn56xx;
+ struct cvmx_ciu_qlm_dcok_s cn56xxp1;
+} cvmx_ciu_qlm_dcok_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_qlm_jtgc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t clk_div:3;
+ uint64_t reserved_6_7:2;
+ uint64_t mux_sel:2;
+ uint64_t bypass:4;
+#else
+ uint64_t bypass:4;
+ uint64_t mux_sel:2;
+ uint64_t reserved_6_7:2;
+ uint64_t clk_div:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_ciu_qlm_jtgc_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t clk_div:3;
+ uint64_t reserved_5_7:3;
+ uint64_t mux_sel:1;
+ uint64_t reserved_2_3:2;
+ uint64_t bypass:2;
+#else
+ uint64_t bypass:2;
+ uint64_t reserved_2_3:2;
+ uint64_t mux_sel:1;
+ uint64_t reserved_5_7:3;
+ uint64_t clk_div:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
+ struct cvmx_ciu_qlm_jtgc_s cn56xx;
+ struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+} cvmx_ciu_qlm_jtgc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_qlm_jtgd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t capture:1;
+ uint64_t shift:1;
+ uint64_t update:1;
+ uint64_t reserved_44_60:17;
+ uint64_t select:4;
+ uint64_t reserved_37_39:3;
+ uint64_t shft_cnt:5;
+ uint64_t shft_reg:32;
+#else
+ uint64_t shft_reg:32;
+ uint64_t shft_cnt:5;
+ uint64_t reserved_37_39:3;
+ uint64_t select:4;
+ uint64_t reserved_44_60:17;
+ uint64_t update:1;
+ uint64_t shift:1;
+ uint64_t capture:1;
+#endif
+ } s;
+ struct cvmx_ciu_qlm_jtgd_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t capture:1;
+ uint64_t shift:1;
+ uint64_t update:1;
+ uint64_t reserved_42_60:19;
+ uint64_t select:2;
+ uint64_t reserved_37_39:3;
+ uint64_t shft_cnt:5;
+ uint64_t shft_reg:32;
+#else
+ uint64_t shft_reg:32;
+ uint64_t shft_cnt:5;
+ uint64_t reserved_37_39:3;
+ uint64_t select:2;
+ uint64_t reserved_42_60:19;
+ uint64_t update:1;
+ uint64_t shift:1;
+ uint64_t capture:1;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
+ struct cvmx_ciu_qlm_jtgd_s cn56xx;
+ struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t capture:1;
+ uint64_t shift:1;
+ uint64_t update:1;
+ uint64_t reserved_37_60:24;
+ uint64_t shft_cnt:5;
+ uint64_t shft_reg:32;
+#else
+ uint64_t shft_reg:32;
+ uint64_t shft_cnt:5;
+ uint64_t reserved_37_60:24;
+ uint64_t update:1;
+ uint64_t shift:1;
+ uint64_t capture:1;
+#endif
+ } cn56xxp1;
+} cvmx_ciu_qlm_jtgd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_soft_bist_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t soft_bist:1;
+#else
+ uint64_t soft_bist:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_ciu_soft_bist_s cn30xx;
+ struct cvmx_ciu_soft_bist_s cn31xx;
+ struct cvmx_ciu_soft_bist_s cn38xx;
+ struct cvmx_ciu_soft_bist_s cn38xxp2;
+ struct cvmx_ciu_soft_bist_s cn50xx;
+ struct cvmx_ciu_soft_bist_s cn52xx;
+ struct cvmx_ciu_soft_bist_s cn52xxp1;
+ struct cvmx_ciu_soft_bist_s cn56xx;
+ struct cvmx_ciu_soft_bist_s cn56xxp1;
+ struct cvmx_ciu_soft_bist_s cn58xx;
+ struct cvmx_ciu_soft_bist_s cn58xxp1;
+} cvmx_ciu_soft_bist_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_soft_prst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t host64:1;
+ uint64_t npi:1;
+ uint64_t soft_prst:1;
+#else
+ uint64_t soft_prst:1;
+ uint64_t npi:1;
+ uint64_t host64:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_ciu_soft_prst_s cn30xx;
+ struct cvmx_ciu_soft_prst_s cn31xx;
+ struct cvmx_ciu_soft_prst_s cn38xx;
+ struct cvmx_ciu_soft_prst_s cn38xxp2;
+ struct cvmx_ciu_soft_prst_s cn50xx;
+ struct cvmx_ciu_soft_prst_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t soft_prst:1;
+#else
+ uint64_t soft_prst:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn52xx;
+ struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
+ struct cvmx_ciu_soft_prst_cn52xx cn56xx;
+ struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
+ struct cvmx_ciu_soft_prst_s cn58xx;
+ struct cvmx_ciu_soft_prst_s cn58xxp1;
+} cvmx_ciu_soft_prst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_soft_prst1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t soft_prst:1;
+#else
+ uint64_t soft_prst:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_ciu_soft_prst1_s cn52xx;
+ struct cvmx_ciu_soft_prst1_s cn52xxp1;
+ struct cvmx_ciu_soft_prst1_s cn56xx;
+ struct cvmx_ciu_soft_prst1_s cn56xxp1;
+} cvmx_ciu_soft_prst1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_soft_rst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t soft_rst:1;
+#else
+ uint64_t soft_rst:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_ciu_soft_rst_s cn30xx;
+ struct cvmx_ciu_soft_rst_s cn31xx;
+ struct cvmx_ciu_soft_rst_s cn38xx;
+ struct cvmx_ciu_soft_rst_s cn38xxp2;
+ struct cvmx_ciu_soft_rst_s cn50xx;
+ struct cvmx_ciu_soft_rst_s cn52xx;
+ struct cvmx_ciu_soft_rst_s cn52xxp1;
+ struct cvmx_ciu_soft_rst_s cn56xx;
+ struct cvmx_ciu_soft_rst_s cn56xxp1;
+ struct cvmx_ciu_soft_rst_s cn58xx;
+ struct cvmx_ciu_soft_rst_s cn58xxp1;
+} cvmx_ciu_soft_rst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_timx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t one_shot:1;
+ uint64_t len:36;
+#else
+ uint64_t len:36;
+ uint64_t one_shot:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } s;
+ struct cvmx_ciu_timx_s cn30xx;
+ struct cvmx_ciu_timx_s cn31xx;
+ struct cvmx_ciu_timx_s cn38xx;
+ struct cvmx_ciu_timx_s cn38xxp2;
+ struct cvmx_ciu_timx_s cn50xx;
+ struct cvmx_ciu_timx_s cn52xx;
+ struct cvmx_ciu_timx_s cn52xxp1;
+ struct cvmx_ciu_timx_s cn56xx;
+ struct cvmx_ciu_timx_s cn56xxp1;
+ struct cvmx_ciu_timx_s cn58xx;
+ struct cvmx_ciu_timx_s cn58xxp1;
+} cvmx_ciu_timx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ciu_wdogx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_46_63:18;
+ uint64_t gstopen:1;
+ uint64_t dstop:1;
+ uint64_t cnt:24;
+ uint64_t len:16;
+ uint64_t state:2;
+ uint64_t mode:2;
+#else
+ uint64_t mode:2;
+ uint64_t state:2;
+ uint64_t len:16;
+ uint64_t cnt:24;
+ uint64_t dstop:1;
+ uint64_t gstopen:1;
+ uint64_t reserved_46_63:18;
+#endif
+ } s;
+ struct cvmx_ciu_wdogx_s cn30xx;
+ struct cvmx_ciu_wdogx_s cn31xx;
+ struct cvmx_ciu_wdogx_s cn38xx;
+ struct cvmx_ciu_wdogx_s cn38xxp2;
+ struct cvmx_ciu_wdogx_s cn50xx;
+ struct cvmx_ciu_wdogx_s cn52xx;
+ struct cvmx_ciu_wdogx_s cn52xxp1;
+ struct cvmx_ciu_wdogx_s cn56xx;
+ struct cvmx_ciu_wdogx_s cn56xxp1;
+ struct cvmx_ciu_wdogx_s cn58xx;
+ struct cvmx_ciu_wdogx_s cn58xxp1;
+} cvmx_ciu_wdogx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dbg_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_dbg_data_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t pll_mul:3;
+ uint64_t reserved_23_27:5;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t reserved_23_27:5;
+ uint64_t pll_mul:3;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn30xx;
+ struct cvmx_dbg_data_cn30xx cn31xx;
+ struct cvmx_dbg_data_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t d_mul:4;
+ uint64_t dclk_mul2:1;
+ uint64_t cclk_div2:1;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t cclk_div2:1;
+ uint64_t dclk_mul2:1;
+ uint64_t d_mul:4;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn38xx;
+ struct cvmx_dbg_data_cn38xx cn38xxp2;
+ struct cvmx_dbg_data_cn30xx cn50xx;
+ struct cvmx_dbg_data_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t rem:6;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t rem:6;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn58xx;
+ struct cvmx_dbg_data_cn58xx cn58xxp1;
+} cvmx_dbg_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_bst0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rdf:16;
+ uint64_t pdf:16;
+#else
+ uint64_t pdf:16;
+ uint64_t rdf:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_dfa_bst0_s cn31xx;
+ struct cvmx_dfa_bst0_s cn38xx;
+ struct cvmx_dfa_bst0_s cn38xxp2;
+ struct cvmx_dfa_bst0_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t rdf:4;
+ uint64_t reserved_4_15:12;
+ uint64_t pdf:4;
+#else
+ uint64_t pdf:4;
+ uint64_t reserved_4_15:12;
+ uint64_t rdf:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn58xx;
+ struct cvmx_dfa_bst0_cn58xx cn58xxp1;
+} cvmx_dfa_bst0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_bst1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t crq:1;
+ uint64_t ifu:1;
+ uint64_t gfu:1;
+ uint64_t drf:1;
+ uint64_t crf:1;
+ uint64_t p0_bwb:1;
+ uint64_t p1_bwb:1;
+ uint64_t p0_brf:8;
+ uint64_t p1_brf:8;
+#else
+ uint64_t p1_brf:8;
+ uint64_t p0_brf:8;
+ uint64_t p1_bwb:1;
+ uint64_t p0_bwb:1;
+ uint64_t crf:1;
+ uint64_t drf:1;
+ uint64_t gfu:1;
+ uint64_t ifu:1;
+ uint64_t crq:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_dfa_bst1_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t crq:1;
+ uint64_t ifu:1;
+ uint64_t gfu:1;
+ uint64_t drf:1;
+ uint64_t crf:1;
+ uint64_t reserved_0_17:18;
+#else
+ uint64_t reserved_0_17:18;
+ uint64_t crf:1;
+ uint64_t drf:1;
+ uint64_t gfu:1;
+ uint64_t ifu:1;
+ uint64_t crq:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } cn31xx;
+ struct cvmx_dfa_bst1_s cn38xx;
+ struct cvmx_dfa_bst1_s cn38xxp2;
+ struct cvmx_dfa_bst1_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t crq:1;
+ uint64_t ifu:1;
+ uint64_t gfu:1;
+ uint64_t reserved_19_19:1;
+ uint64_t crf:1;
+ uint64_t p0_bwb:1;
+ uint64_t p1_bwb:1;
+ uint64_t p0_brf:8;
+ uint64_t p1_brf:8;
+#else
+ uint64_t p1_brf:8;
+ uint64_t p0_brf:8;
+ uint64_t p1_bwb:1;
+ uint64_t p0_bwb:1;
+ uint64_t crf:1;
+ uint64_t reserved_19_19:1;
+ uint64_t gfu:1;
+ uint64_t ifu:1;
+ uint64_t crq:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } cn58xx;
+ struct cvmx_dfa_bst1_cn58xx cn58xxp1;
+} cvmx_dfa_bst1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t nrpl_ena:1;
+ uint64_t nxor_ena:1;
+ uint64_t gxor_ena:1;
+ uint64_t sarb:1;
+#else
+ uint64_t sarb:1;
+ uint64_t gxor_ena:1;
+ uint64_t nxor_ena:1;
+ uint64_t nrpl_ena:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_dfa_cfg_s cn38xx;
+ struct cvmx_dfa_cfg_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t sarb:1;
+#else
+ uint64_t sarb:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn38xxp2;
+ struct cvmx_dfa_cfg_s cn58xx;
+ struct cvmx_dfa_cfg_s cn58xxp1;
+} cvmx_dfa_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t dbell:20;
+#else
+ uint64_t dbell:20;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_dfa_dbell_s cn31xx;
+ struct cvmx_dfa_dbell_s cn38xx;
+ struct cvmx_dfa_dbell_s cn38xxp2;
+ struct cvmx_dfa_dbell_s cn58xx;
+ struct cvmx_dfa_dbell_s cn58xxp1;
+} cvmx_dfa_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t rdimm_ena:1;
+ uint64_t num_rnks:2;
+ uint64_t rnk_lo:1;
+ uint64_t num_colrows:3;
+ uint64_t num_cols:2;
+#else
+ uint64_t num_cols:2;
+ uint64_t num_colrows:3;
+ uint64_t rnk_lo:1;
+ uint64_t num_rnks:2;
+ uint64_t rdimm_ena:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_addr_s cn31xx;
+} cvmx_dfa_ddr2_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_bus_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_47_63:17;
+ uint64_t bus_cnt:47;
+#else
+ uint64_t bus_cnt:47;
+ uint64_t reserved_47_63:17;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_bus_s cn31xx;
+} cvmx_dfa_ddr2_bus_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_41_63:23;
+ uint64_t trfc:5;
+ uint64_t mrs_pgm:1;
+ uint64_t fpip:3;
+ uint64_t reserved_29_31:3;
+ uint64_t ref_int:13;
+ uint64_t reserved_14_15:2;
+ uint64_t tskw:2;
+ uint64_t rnk_msk:4;
+ uint64_t silo_qc:1;
+ uint64_t silo_hc:1;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch:1;
+ uint64_t init:1;
+ uint64_t prtena:1;
+#else
+ uint64_t prtena:1;
+ uint64_t init:1;
+ uint64_t fprch:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t silo_hc:1;
+ uint64_t silo_qc:1;
+ uint64_t rnk_msk:4;
+ uint64_t tskw:2;
+ uint64_t reserved_14_15:2;
+ uint64_t ref_int:13;
+ uint64_t reserved_29_31:3;
+ uint64_t fpip:3;
+ uint64_t mrs_pgm:1;
+ uint64_t trfc:5;
+ uint64_t reserved_41_63:23;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_cfg_s cn31xx;
+} cvmx_dfa_ddr2_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_comp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dfa__pctl:4;
+ uint64_t dfa__nctl:4;
+ uint64_t reserved_9_55:47;
+ uint64_t pctl_csr:4;
+ uint64_t nctl_csr:4;
+ uint64_t comp_bypass:1;
+#else
+ uint64_t comp_bypass:1;
+ uint64_t nctl_csr:4;
+ uint64_t pctl_csr:4;
+ uint64_t reserved_9_55:47;
+ uint64_t dfa__nctl:4;
+ uint64_t dfa__pctl:4;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_comp_s cn31xx;
+} cvmx_dfa_ddr2_comp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_emrs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t emrs1_ocd:15;
+ uint64_t reserved_15_15:1;
+ uint64_t emrs1:15;
+#else
+ uint64_t emrs1:15;
+ uint64_t reserved_15_15:1;
+ uint64_t emrs1_ocd:15;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_emrs_s cn31xx;
+} cvmx_dfa_ddr2_emrs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_fcnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_47_63:17;
+ uint64_t fcyc_cnt:47;
+#else
+ uint64_t fcyc_cnt:47;
+ uint64_t reserved_47_63:17;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_fcnt_s cn31xx;
+} cvmx_dfa_ddr2_fcnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_mrs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t mrs:15;
+ uint64_t reserved_15_15:1;
+ uint64_t mrs_dll:15;
+#else
+ uint64_t mrs_dll:15;
+ uint64_t reserved_15_15:1;
+ uint64_t mrs:15;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_mrs_s cn31xx;
+} cvmx_dfa_ddr2_mrs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_opt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t max_read_batch:5;
+ uint64_t max_write_batch:5;
+#else
+ uint64_t max_write_batch:5;
+ uint64_t max_read_batch:5;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_opt_s cn31xx;
+} cvmx_dfa_ddr2_opt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_pll_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pll_setting:17;
+ uint64_t reserved_32_46:15;
+ uint64_t setting90:5;
+ uint64_t reserved_21_26:6;
+ uint64_t dll_setting:5;
+ uint64_t dll_byp:1;
+ uint64_t qdll_ena:1;
+ uint64_t bw_ctl:4;
+ uint64_t bw_upd:1;
+ uint64_t pll_div2:1;
+ uint64_t reserved_7_7:1;
+ uint64_t pll_ratio:5;
+ uint64_t pll_bypass:1;
+ uint64_t pll_init:1;
+#else
+ uint64_t pll_init:1;
+ uint64_t pll_bypass:1;
+ uint64_t pll_ratio:5;
+ uint64_t reserved_7_7:1;
+ uint64_t pll_div2:1;
+ uint64_t bw_upd:1;
+ uint64_t bw_ctl:4;
+ uint64_t qdll_ena:1;
+ uint64_t dll_byp:1;
+ uint64_t dll_setting:5;
+ uint64_t reserved_21_26:6;
+ uint64_t setting90:5;
+ uint64_t reserved_32_46:15;
+ uint64_t pll_setting:17;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_pll_s cn31xx;
+} cvmx_dfa_ddr2_pll_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ddr2_tmg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_47_63:17;
+ uint64_t fcnt_mode:1;
+ uint64_t cnt_clr:1;
+ uint64_t cavmipo:1;
+ uint64_t ctr_rst:1;
+ uint64_t odt_rtt:2;
+ uint64_t dqsn_ena:1;
+ uint64_t dic:1;
+ uint64_t r2r_slot:1;
+ uint64_t tfaw:5;
+ uint64_t twtr:4;
+ uint64_t twr:3;
+ uint64_t trp:4;
+ uint64_t tras:5;
+ uint64_t trrd:3;
+ uint64_t trcd:4;
+ uint64_t addlat:3;
+ uint64_t pocas:1;
+ uint64_t caslat:3;
+ uint64_t tmrd:2;
+ uint64_t ddr2t:1;
+#else
+ uint64_t ddr2t:1;
+ uint64_t tmrd:2;
+ uint64_t caslat:3;
+ uint64_t pocas:1;
+ uint64_t addlat:3;
+ uint64_t trcd:4;
+ uint64_t trrd:3;
+ uint64_t tras:5;
+ uint64_t trp:4;
+ uint64_t twr:3;
+ uint64_t twtr:4;
+ uint64_t tfaw:5;
+ uint64_t r2r_slot:1;
+ uint64_t dic:1;
+ uint64_t dqsn_ena:1;
+ uint64_t odt_rtt:2;
+ uint64_t ctr_rst:1;
+ uint64_t cavmipo:1;
+ uint64_t cnt_clr:1;
+ uint64_t fcnt_mode:1;
+ uint64_t reserved_47_63:17;
+#endif
+ } s;
+ struct cvmx_dfa_ddr2_tmg_s cn31xx;
+} cvmx_dfa_ddr2_tmg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_difctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t dwbcnt:8;
+ uint64_t pool:3;
+ uint64_t size:9;
+#else
+ uint64_t size:9;
+ uint64_t pool:3;
+ uint64_t dwbcnt:8;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_dfa_difctl_s cn31xx;
+ struct cvmx_dfa_difctl_s cn38xx;
+ struct cvmx_dfa_difctl_s cn38xxp2;
+ struct cvmx_dfa_difctl_s cn58xx;
+ struct cvmx_dfa_difctl_s cn58xxp1;
+} cvmx_dfa_difctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_difrdptr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t rdptr:31;
+ uint64_t reserved_0_4:5;
+#else
+ uint64_t reserved_0_4:5;
+ uint64_t rdptr:31;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_dfa_difrdptr_s cn31xx;
+ struct cvmx_dfa_difrdptr_s cn38xx;
+ struct cvmx_dfa_difrdptr_s cn38xxp2;
+ struct cvmx_dfa_difrdptr_s cn58xx;
+ struct cvmx_dfa_difrdptr_s cn58xxp1;
+} cvmx_dfa_difrdptr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_eclkcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t sbdnum:3;
+ uint64_t reserved_15_15:1;
+ uint64_t sbdlck:1;
+ uint64_t dcmode:1;
+ uint64_t dtmode:1;
+ uint64_t pmode:1;
+ uint64_t qmode:1;
+ uint64_t imode:1;
+ uint64_t sarb:1;
+ uint64_t reserved_3_7:5;
+ uint64_t dteclkdis:1;
+ uint64_t maxbnk:1;
+ uint64_t dfa_frstn:1;
+#else
+ uint64_t dfa_frstn:1;
+ uint64_t maxbnk:1;
+ uint64_t dteclkdis:1;
+ uint64_t reserved_3_7:5;
+ uint64_t sarb:1;
+ uint64_t imode:1;
+ uint64_t qmode:1;
+ uint64_t pmode:1;
+ uint64_t dtmode:1;
+ uint64_t dcmode:1;
+ uint64_t sbdlck:1;
+ uint64_t reserved_15_15:1;
+ uint64_t sbdnum:3;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_dfa_eclkcfg_s cn31xx;
+} cvmx_dfa_eclkcfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_33_63:31;
+ uint64_t dblina:1;
+ uint64_t dblovf:1;
+ uint64_t cp2pina:1;
+ uint64_t cp2perr:1;
+ uint64_t cp2parena:1;
+ uint64_t dtepina:1;
+ uint64_t dteperr:1;
+ uint64_t dteparena:1;
+ uint64_t dtesyn:7;
+ uint64_t dtedbina:1;
+ uint64_t dtesbina:1;
+ uint64_t dtedbe:1;
+ uint64_t dtesbe:1;
+ uint64_t dteeccena:1;
+ uint64_t cp2syn:8;
+ uint64_t cp2dbina:1;
+ uint64_t cp2sbina:1;
+ uint64_t cp2dbe:1;
+ uint64_t cp2sbe:1;
+ uint64_t cp2eccena:1;
+#else
+ uint64_t cp2eccena:1;
+ uint64_t cp2sbe:1;
+ uint64_t cp2dbe:1;
+ uint64_t cp2sbina:1;
+ uint64_t cp2dbina:1;
+ uint64_t cp2syn:8;
+ uint64_t dteeccena:1;
+ uint64_t dtesbe:1;
+ uint64_t dtedbe:1;
+ uint64_t dtesbina:1;
+ uint64_t dtedbina:1;
+ uint64_t dtesyn:7;
+ uint64_t dteparena:1;
+ uint64_t dteperr:1;
+ uint64_t dtepina:1;
+ uint64_t cp2parena:1;
+ uint64_t cp2perr:1;
+ uint64_t cp2pina:1;
+ uint64_t dblovf:1;
+ uint64_t dblina:1;
+ uint64_t reserved_33_63:31;
+#endif
+ } s;
+ struct cvmx_dfa_err_s cn31xx;
+ struct cvmx_dfa_err_s cn38xx;
+ struct cvmx_dfa_err_s cn38xxp2;
+ struct cvmx_dfa_err_s cn58xx;
+ struct cvmx_dfa_err_s cn58xxp1;
+} cvmx_dfa_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memcfg0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rldqck90_rst:1;
+ uint64_t rldck_rst:1;
+ uint64_t clkdiv:2;
+ uint64_t lpp_ena:1;
+ uint64_t bunk_init:2;
+ uint64_t init_p0:1;
+ uint64_t init_p1:1;
+ uint64_t r2r_pbunk:1;
+ uint64_t pbunk:3;
+ uint64_t blen:1;
+ uint64_t bprch:2;
+ uint64_t fprch:2;
+ uint64_t wr_dly:4;
+ uint64_t rw_dly:4;
+ uint64_t sil_lat:2;
+ uint64_t mtype:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ena_p0:1;
+ uint64_t ena_p1:1;
+#else
+ uint64_t ena_p1:1;
+ uint64_t ena_p0:1;
+ uint64_t reserved_2_2:1;
+ uint64_t mtype:1;
+ uint64_t sil_lat:2;
+ uint64_t rw_dly:4;
+ uint64_t wr_dly:4;
+ uint64_t fprch:2;
+ uint64_t bprch:2;
+ uint64_t blen:1;
+ uint64_t pbunk:3;
+ uint64_t r2r_pbunk:1;
+ uint64_t init_p1:1;
+ uint64_t init_p0:1;
+ uint64_t bunk_init:2;
+ uint64_t lpp_ena:1;
+ uint64_t clkdiv:2;
+ uint64_t rldck_rst:1;
+ uint64_t rldqck90_rst:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_dfa_memcfg0_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lpp_ena:1;
+ uint64_t bunk_init:2;
+ uint64_t init_p0:1;
+ uint64_t init_p1:1;
+ uint64_t r2r_pbunk:1;
+ uint64_t pbunk:3;
+ uint64_t blen:1;
+ uint64_t bprch:2;
+ uint64_t fprch:2;
+ uint64_t wr_dly:4;
+ uint64_t rw_dly:4;
+ uint64_t sil_lat:2;
+ uint64_t mtype:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ena_p0:1;
+ uint64_t ena_p1:1;
+#else
+ uint64_t ena_p1:1;
+ uint64_t ena_p0:1;
+ uint64_t reserved_2_2:1;
+ uint64_t mtype:1;
+ uint64_t sil_lat:2;
+ uint64_t rw_dly:4;
+ uint64_t wr_dly:4;
+ uint64_t fprch:2;
+ uint64_t bprch:2;
+ uint64_t blen:1;
+ uint64_t pbunk:3;
+ uint64_t r2r_pbunk:1;
+ uint64_t init_p1:1;
+ uint64_t init_p0:1;
+ uint64_t bunk_init:2;
+ uint64_t lpp_ena:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn38xx;
+ struct cvmx_dfa_memcfg0_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t bunk_init:2;
+ uint64_t init_p0:1;
+ uint64_t init_p1:1;
+ uint64_t r2r_pbunk:1;
+ uint64_t pbunk:3;
+ uint64_t blen:1;
+ uint64_t bprch:2;
+ uint64_t fprch:2;
+ uint64_t wr_dly:4;
+ uint64_t rw_dly:4;
+ uint64_t sil_lat:2;
+ uint64_t mtype:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ena_p0:1;
+ uint64_t ena_p1:1;
+#else
+ uint64_t ena_p1:1;
+ uint64_t ena_p0:1;
+ uint64_t reserved_2_2:1;
+ uint64_t mtype:1;
+ uint64_t sil_lat:2;
+ uint64_t rw_dly:4;
+ uint64_t wr_dly:4;
+ uint64_t fprch:2;
+ uint64_t bprch:2;
+ uint64_t blen:1;
+ uint64_t pbunk:3;
+ uint64_t r2r_pbunk:1;
+ uint64_t init_p1:1;
+ uint64_t init_p0:1;
+ uint64_t bunk_init:2;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn38xxp2;
+ struct cvmx_dfa_memcfg0_s cn58xx;
+ struct cvmx_dfa_memcfg0_s cn58xxp1;
+} cvmx_dfa_memcfg0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memcfg1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ref_intlo:9;
+ uint64_t aref_ena:1;
+ uint64_t mrs_ena:1;
+ uint64_t tmrsc:3;
+ uint64_t trc:4;
+ uint64_t twl:4;
+ uint64_t trl:4;
+ uint64_t reserved_6_7:2;
+ uint64_t tskw:2;
+ uint64_t ref_int:4;
+#else
+ uint64_t ref_int:4;
+ uint64_t tskw:2;
+ uint64_t reserved_6_7:2;
+ uint64_t trl:4;
+ uint64_t twl:4;
+ uint64_t trc:4;
+ uint64_t tmrsc:3;
+ uint64_t mrs_ena:1;
+ uint64_t aref_ena:1;
+ uint64_t ref_intlo:9;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_dfa_memcfg1_s cn38xx;
+ struct cvmx_dfa_memcfg1_s cn38xxp2;
+ struct cvmx_dfa_memcfg1_s cn58xx;
+ struct cvmx_dfa_memcfg1_s cn58xxp1;
+} cvmx_dfa_memcfg1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memcfg2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t dteclkdis:1;
+ uint64_t silrst:1;
+ uint64_t trfc:5;
+ uint64_t refshort:1;
+ uint64_t ua_start:2;
+ uint64_t maxbnk:1;
+ uint64_t fcram2p:1;
+#else
+ uint64_t fcram2p:1;
+ uint64_t maxbnk:1;
+ uint64_t ua_start:2;
+ uint64_t refshort:1;
+ uint64_t trfc:5;
+ uint64_t silrst:1;
+ uint64_t dteclkdis:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_dfa_memcfg2_s cn38xx;
+ struct cvmx_dfa_memcfg2_s cn38xxp2;
+ struct cvmx_dfa_memcfg2_s cn58xx;
+ struct cvmx_dfa_memcfg2_s cn58xxp1;
+} cvmx_dfa_memcfg2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memfadr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t maddr:24;
+#else
+ uint64_t maddr:24;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_dfa_memfadr_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t fdst:9;
+ uint64_t fsrc:2;
+ uint64_t pnum:1;
+ uint64_t bnum:3;
+ uint64_t maddr:25;
+#else
+ uint64_t maddr:25;
+ uint64_t bnum:3;
+ uint64_t pnum:1;
+ uint64_t fsrc:2;
+ uint64_t fdst:9;
+ uint64_t reserved_40_63:24;
+#endif
+ } cn31xx;
+ struct cvmx_dfa_memfadr_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t fdst:9;
+ uint64_t fsrc:2;
+ uint64_t pnum:1;
+ uint64_t bnum:3;
+ uint64_t maddr:24;
+#else
+ uint64_t maddr:24;
+ uint64_t bnum:3;
+ uint64_t pnum:1;
+ uint64_t fsrc:2;
+ uint64_t fdst:9;
+ uint64_t reserved_39_63:25;
+#endif
+ } cn38xx;
+ struct cvmx_dfa_memfadr_cn38xx cn38xxp2;
+ struct cvmx_dfa_memfadr_cn38xx cn58xx;
+ struct cvmx_dfa_memfadr_cn38xx cn58xxp1;
+} cvmx_dfa_memfadr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memfcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_47_63:17;
+ uint64_t emrs2:15;
+ uint64_t reserved_31_31:1;
+ uint64_t emrs:15;
+ uint64_t reserved_15_15:1;
+ uint64_t mrs:15;
+#else
+ uint64_t mrs:15;
+ uint64_t reserved_15_15:1;
+ uint64_t emrs:15;
+ uint64_t reserved_31_31:1;
+ uint64_t emrs2:15;
+ uint64_t reserved_47_63:17;
+#endif
+ } s;
+ struct cvmx_dfa_memfcr_s cn38xx;
+ struct cvmx_dfa_memfcr_s cn38xxp2;
+ struct cvmx_dfa_memfcr_s cn58xx;
+ struct cvmx_dfa_memfcr_s cn58xxp1;
+} cvmx_dfa_memfcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_memrld_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t mrsdat:23;
+#else
+ uint64_t mrsdat:23;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_dfa_memrld_s cn38xx;
+ struct cvmx_dfa_memrld_s cn38xxp2;
+ struct cvmx_dfa_memrld_s cn58xx;
+ struct cvmx_dfa_memrld_s cn58xxp1;
+} cvmx_dfa_memrld_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_ncbctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t sbdnum:5;
+ uint64_t sbdlck:1;
+ uint64_t dcmode:1;
+ uint64_t dtmode:1;
+ uint64_t pmode:1;
+ uint64_t qmode:1;
+ uint64_t imode:1;
+#else
+ uint64_t imode:1;
+ uint64_t qmode:1;
+ uint64_t pmode:1;
+ uint64_t dtmode:1;
+ uint64_t dcmode:1;
+ uint64_t sbdlck:1;
+ uint64_t sbdnum:5;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_dfa_ncbctl_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t sbdnum:4;
+ uint64_t sbdlck:1;
+ uint64_t dcmode:1;
+ uint64_t dtmode:1;
+ uint64_t pmode:1;
+ uint64_t qmode:1;
+ uint64_t imode:1;
+#else
+ uint64_t imode:1;
+ uint64_t qmode:1;
+ uint64_t pmode:1;
+ uint64_t dtmode:1;
+ uint64_t dcmode:1;
+ uint64_t sbdlck:1;
+ uint64_t sbdnum:4;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn38xx;
+ struct cvmx_dfa_ncbctl_cn38xx cn38xxp2;
+ struct cvmx_dfa_ncbctl_s cn58xx;
+ struct cvmx_dfa_ncbctl_s cn58xxp1;
+} cvmx_dfa_ncbctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_rodt_comp_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t enable:1;
+ uint64_t reserved_12_15:4;
+ uint64_t nctl:4;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+#else
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:4;
+ uint64_t reserved_12_15:4;
+ uint64_t enable:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_dfa_rodt_comp_ctl_s cn58xx;
+ struct cvmx_dfa_rodt_comp_ctl_s cn58xxp1;
+} cvmx_dfa_rodt_comp_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_sbd_dbg0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t sbd0:64;
+#else
+ uint64_t sbd0:64;
+#endif
+ } s;
+ struct cvmx_dfa_sbd_dbg0_s cn31xx;
+ struct cvmx_dfa_sbd_dbg0_s cn38xx;
+ struct cvmx_dfa_sbd_dbg0_s cn38xxp2;
+ struct cvmx_dfa_sbd_dbg0_s cn58xx;
+ struct cvmx_dfa_sbd_dbg0_s cn58xxp1;
+} cvmx_dfa_sbd_dbg0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_sbd_dbg1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t sbd1:64;
+#else
+ uint64_t sbd1:64;
+#endif
+ } s;
+ struct cvmx_dfa_sbd_dbg1_s cn31xx;
+ struct cvmx_dfa_sbd_dbg1_s cn38xx;
+ struct cvmx_dfa_sbd_dbg1_s cn38xxp2;
+ struct cvmx_dfa_sbd_dbg1_s cn58xx;
+ struct cvmx_dfa_sbd_dbg1_s cn58xxp1;
+} cvmx_dfa_sbd_dbg1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_sbd_dbg2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t sbd2:64;
+#else
+ uint64_t sbd2:64;
+#endif
+ } s;
+ struct cvmx_dfa_sbd_dbg2_s cn31xx;
+ struct cvmx_dfa_sbd_dbg2_s cn38xx;
+ struct cvmx_dfa_sbd_dbg2_s cn38xxp2;
+ struct cvmx_dfa_sbd_dbg2_s cn58xx;
+ struct cvmx_dfa_sbd_dbg2_s cn58xxp1;
+} cvmx_dfa_sbd_dbg2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_dfa_sbd_dbg3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t sbd3:64;
+#else
+ uint64_t sbd3:64;
+#endif
+ } s;
+ struct cvmx_dfa_sbd_dbg3_s cn31xx;
+ struct cvmx_dfa_sbd_dbg3_s cn38xx;
+ struct cvmx_dfa_sbd_dbg3_s cn38xxp2;
+ struct cvmx_dfa_sbd_dbg3_s cn58xx;
+ struct cvmx_dfa_sbd_dbg3_s cn58xxp1;
+} cvmx_dfa_sbd_dbg3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t frd:1;
+ uint64_t fpf0:1;
+ uint64_t fpf1:1;
+ uint64_t ffr:1;
+ uint64_t fdr:1;
+#else
+ uint64_t fdr:1;
+ uint64_t ffr:1;
+ uint64_t fpf1:1;
+ uint64_t fpf0:1;
+ uint64_t frd:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_fpa_bist_status_s cn30xx;
+ struct cvmx_fpa_bist_status_s cn31xx;
+ struct cvmx_fpa_bist_status_s cn38xx;
+ struct cvmx_fpa_bist_status_s cn38xxp2;
+ struct cvmx_fpa_bist_status_s cn50xx;
+ struct cvmx_fpa_bist_status_s cn52xx;
+ struct cvmx_fpa_bist_status_s cn52xxp1;
+ struct cvmx_fpa_bist_status_s cn56xx;
+ struct cvmx_fpa_bist_status_s cn56xxp1;
+ struct cvmx_fpa_bist_status_s cn58xx;
+ struct cvmx_fpa_bist_status_s cn58xxp1;
+} cvmx_fpa_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t reset:1;
+ uint64_t use_ldt:1;
+ uint64_t use_stt:1;
+ uint64_t enb:1;
+ uint64_t mem1_err:7;
+ uint64_t mem0_err:7;
+#else
+ uint64_t mem0_err:7;
+ uint64_t mem1_err:7;
+ uint64_t enb:1;
+ uint64_t use_stt:1;
+ uint64_t use_ldt:1;
+ uint64_t reset:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_fpa_ctl_status_s cn30xx;
+ struct cvmx_fpa_ctl_status_s cn31xx;
+ struct cvmx_fpa_ctl_status_s cn38xx;
+ struct cvmx_fpa_ctl_status_s cn38xxp2;
+ struct cvmx_fpa_ctl_status_s cn50xx;
+ struct cvmx_fpa_ctl_status_s cn52xx;
+ struct cvmx_fpa_ctl_status_s cn52xxp1;
+ struct cvmx_fpa_ctl_status_s cn56xx;
+ struct cvmx_fpa_ctl_status_s cn56xxp1;
+ struct cvmx_fpa_ctl_status_s cn58xx;
+ struct cvmx_fpa_ctl_status_s cn58xxp1;
+} cvmx_fpa_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_fpfx_marks_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_22_63:42;
+ uint64_t fpf_wr:11;
+ uint64_t fpf_rd:11;
+#else
+ uint64_t fpf_rd:11;
+ uint64_t fpf_wr:11;
+ uint64_t reserved_22_63:42;
+#endif
+ } s;
+ struct cvmx_fpa_fpfx_marks_s cn38xx;
+ struct cvmx_fpa_fpfx_marks_s cn38xxp2;
+ struct cvmx_fpa_fpfx_marks_s cn56xx;
+ struct cvmx_fpa_fpfx_marks_s cn56xxp1;
+ struct cvmx_fpa_fpfx_marks_s cn58xx;
+ struct cvmx_fpa_fpfx_marks_s cn58xxp1;
+} cvmx_fpa_fpfx_marks_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_fpfx_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t fpf_siz:11;
+#else
+ uint64_t fpf_siz:11;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_fpa_fpfx_size_s cn38xx;
+ struct cvmx_fpa_fpfx_size_s cn38xxp2;
+ struct cvmx_fpa_fpfx_size_s cn56xx;
+ struct cvmx_fpa_fpfx_size_s cn56xxp1;
+ struct cvmx_fpa_fpfx_size_s cn58xx;
+ struct cvmx_fpa_fpfx_size_s cn58xxp1;
+} cvmx_fpa_fpfx_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_fpf0_marks_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t fpf_wr:12;
+ uint64_t fpf_rd:12;
+#else
+ uint64_t fpf_rd:12;
+ uint64_t fpf_wr:12;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_fpa_fpf0_marks_s cn38xx;
+ struct cvmx_fpa_fpf0_marks_s cn38xxp2;
+ struct cvmx_fpa_fpf0_marks_s cn56xx;
+ struct cvmx_fpa_fpf0_marks_s cn56xxp1;
+ struct cvmx_fpa_fpf0_marks_s cn58xx;
+ struct cvmx_fpa_fpf0_marks_s cn58xxp1;
+} cvmx_fpa_fpf0_marks_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_fpf0_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t fpf_siz:12;
+#else
+ uint64_t fpf_siz:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_fpa_fpf0_size_s cn38xx;
+ struct cvmx_fpa_fpf0_size_s cn38xxp2;
+ struct cvmx_fpa_fpf0_size_s cn56xx;
+ struct cvmx_fpa_fpf0_size_s cn56xxp1;
+ struct cvmx_fpa_fpf0_size_s cn58xx;
+ struct cvmx_fpa_fpf0_size_s cn58xxp1;
+} cvmx_fpa_fpf0_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t q7_perr:1;
+ uint64_t q7_coff:1;
+ uint64_t q7_und:1;
+ uint64_t q6_perr:1;
+ uint64_t q6_coff:1;
+ uint64_t q6_und:1;
+ uint64_t q5_perr:1;
+ uint64_t q5_coff:1;
+ uint64_t q5_und:1;
+ uint64_t q4_perr:1;
+ uint64_t q4_coff:1;
+ uint64_t q4_und:1;
+ uint64_t q3_perr:1;
+ uint64_t q3_coff:1;
+ uint64_t q3_und:1;
+ uint64_t q2_perr:1;
+ uint64_t q2_coff:1;
+ uint64_t q2_und:1;
+ uint64_t q1_perr:1;
+ uint64_t q1_coff:1;
+ uint64_t q1_und:1;
+ uint64_t q0_perr:1;
+ uint64_t q0_coff:1;
+ uint64_t q0_und:1;
+ uint64_t fed1_dbe:1;
+ uint64_t fed1_sbe:1;
+ uint64_t fed0_dbe:1;
+ uint64_t fed0_sbe:1;
+#else
+ uint64_t fed0_sbe:1;
+ uint64_t fed0_dbe:1;
+ uint64_t fed1_sbe:1;
+ uint64_t fed1_dbe:1;
+ uint64_t q0_und:1;
+ uint64_t q0_coff:1;
+ uint64_t q0_perr:1;
+ uint64_t q1_und:1;
+ uint64_t q1_coff:1;
+ uint64_t q1_perr:1;
+ uint64_t q2_und:1;
+ uint64_t q2_coff:1;
+ uint64_t q2_perr:1;
+ uint64_t q3_und:1;
+ uint64_t q3_coff:1;
+ uint64_t q3_perr:1;
+ uint64_t q4_und:1;
+ uint64_t q4_coff:1;
+ uint64_t q4_perr:1;
+ uint64_t q5_und:1;
+ uint64_t q5_coff:1;
+ uint64_t q5_perr:1;
+ uint64_t q6_und:1;
+ uint64_t q6_coff:1;
+ uint64_t q6_perr:1;
+ uint64_t q7_und:1;
+ uint64_t q7_coff:1;
+ uint64_t q7_perr:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } s;
+ struct cvmx_fpa_int_enb_s cn30xx;
+ struct cvmx_fpa_int_enb_s cn31xx;
+ struct cvmx_fpa_int_enb_s cn38xx;
+ struct cvmx_fpa_int_enb_s cn38xxp2;
+ struct cvmx_fpa_int_enb_s cn50xx;
+ struct cvmx_fpa_int_enb_s cn52xx;
+ struct cvmx_fpa_int_enb_s cn52xxp1;
+ struct cvmx_fpa_int_enb_s cn56xx;
+ struct cvmx_fpa_int_enb_s cn56xxp1;
+ struct cvmx_fpa_int_enb_s cn58xx;
+ struct cvmx_fpa_int_enb_s cn58xxp1;
+} cvmx_fpa_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t q7_perr:1;
+ uint64_t q7_coff:1;
+ uint64_t q7_und:1;
+ uint64_t q6_perr:1;
+ uint64_t q6_coff:1;
+ uint64_t q6_und:1;
+ uint64_t q5_perr:1;
+ uint64_t q5_coff:1;
+ uint64_t q5_und:1;
+ uint64_t q4_perr:1;
+ uint64_t q4_coff:1;
+ uint64_t q4_und:1;
+ uint64_t q3_perr:1;
+ uint64_t q3_coff:1;
+ uint64_t q3_und:1;
+ uint64_t q2_perr:1;
+ uint64_t q2_coff:1;
+ uint64_t q2_und:1;
+ uint64_t q1_perr:1;
+ uint64_t q1_coff:1;
+ uint64_t q1_und:1;
+ uint64_t q0_perr:1;
+ uint64_t q0_coff:1;
+ uint64_t q0_und:1;
+ uint64_t fed1_dbe:1;
+ uint64_t fed1_sbe:1;
+ uint64_t fed0_dbe:1;
+ uint64_t fed0_sbe:1;
+#else
+ uint64_t fed0_sbe:1;
+ uint64_t fed0_dbe:1;
+ uint64_t fed1_sbe:1;
+ uint64_t fed1_dbe:1;
+ uint64_t q0_und:1;
+ uint64_t q0_coff:1;
+ uint64_t q0_perr:1;
+ uint64_t q1_und:1;
+ uint64_t q1_coff:1;
+ uint64_t q1_perr:1;
+ uint64_t q2_und:1;
+ uint64_t q2_coff:1;
+ uint64_t q2_perr:1;
+ uint64_t q3_und:1;
+ uint64_t q3_coff:1;
+ uint64_t q3_perr:1;
+ uint64_t q4_und:1;
+ uint64_t q4_coff:1;
+ uint64_t q4_perr:1;
+ uint64_t q5_und:1;
+ uint64_t q5_coff:1;
+ uint64_t q5_perr:1;
+ uint64_t q6_und:1;
+ uint64_t q6_coff:1;
+ uint64_t q6_perr:1;
+ uint64_t q7_und:1;
+ uint64_t q7_coff:1;
+ uint64_t q7_perr:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } s;
+ struct cvmx_fpa_int_sum_s cn30xx;
+ struct cvmx_fpa_int_sum_s cn31xx;
+ struct cvmx_fpa_int_sum_s cn38xx;
+ struct cvmx_fpa_int_sum_s cn38xxp2;
+ struct cvmx_fpa_int_sum_s cn50xx;
+ struct cvmx_fpa_int_sum_s cn52xx;
+ struct cvmx_fpa_int_sum_s cn52xxp1;
+ struct cvmx_fpa_int_sum_s cn56xx;
+ struct cvmx_fpa_int_sum_s cn56xxp1;
+ struct cvmx_fpa_int_sum_s cn58xx;
+ struct cvmx_fpa_int_sum_s cn58xxp1;
+} cvmx_fpa_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_quex_available_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t que_siz:29;
+#else
+ uint64_t que_siz:29;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_fpa_quex_available_s cn30xx;
+ struct cvmx_fpa_quex_available_s cn31xx;
+ struct cvmx_fpa_quex_available_s cn38xx;
+ struct cvmx_fpa_quex_available_s cn38xxp2;
+ struct cvmx_fpa_quex_available_s cn50xx;
+ struct cvmx_fpa_quex_available_s cn52xx;
+ struct cvmx_fpa_quex_available_s cn52xxp1;
+ struct cvmx_fpa_quex_available_s cn56xx;
+ struct cvmx_fpa_quex_available_s cn56xxp1;
+ struct cvmx_fpa_quex_available_s cn58xx;
+ struct cvmx_fpa_quex_available_s cn58xxp1;
+} cvmx_fpa_quex_available_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_quex_page_index_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_25_63:39;
+ uint64_t pg_num:25;
+#else
+ uint64_t pg_num:25;
+ uint64_t reserved_25_63:39;
+#endif
+ } s;
+ struct cvmx_fpa_quex_page_index_s cn30xx;
+ struct cvmx_fpa_quex_page_index_s cn31xx;
+ struct cvmx_fpa_quex_page_index_s cn38xx;
+ struct cvmx_fpa_quex_page_index_s cn38xxp2;
+ struct cvmx_fpa_quex_page_index_s cn50xx;
+ struct cvmx_fpa_quex_page_index_s cn52xx;
+ struct cvmx_fpa_quex_page_index_s cn52xxp1;
+ struct cvmx_fpa_quex_page_index_s cn56xx;
+ struct cvmx_fpa_quex_page_index_s cn56xxp1;
+ struct cvmx_fpa_quex_page_index_s cn58xx;
+ struct cvmx_fpa_quex_page_index_s cn58xxp1;
+} cvmx_fpa_quex_page_index_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_que_act_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t act_que:3;
+ uint64_t act_indx:26;
+#else
+ uint64_t act_indx:26;
+ uint64_t act_que:3;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_fpa_que_act_s cn30xx;
+ struct cvmx_fpa_que_act_s cn31xx;
+ struct cvmx_fpa_que_act_s cn38xx;
+ struct cvmx_fpa_que_act_s cn38xxp2;
+ struct cvmx_fpa_que_act_s cn50xx;
+ struct cvmx_fpa_que_act_s cn52xx;
+ struct cvmx_fpa_que_act_s cn52xxp1;
+ struct cvmx_fpa_que_act_s cn56xx;
+ struct cvmx_fpa_que_act_s cn56xxp1;
+ struct cvmx_fpa_que_act_s cn58xx;
+ struct cvmx_fpa_que_act_s cn58xxp1;
+} cvmx_fpa_que_act_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_que_exp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t exp_que:3;
+ uint64_t exp_indx:26;
+#else
+ uint64_t exp_indx:26;
+ uint64_t exp_que:3;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_fpa_que_exp_s cn30xx;
+ struct cvmx_fpa_que_exp_s cn31xx;
+ struct cvmx_fpa_que_exp_s cn38xx;
+ struct cvmx_fpa_que_exp_s cn38xxp2;
+ struct cvmx_fpa_que_exp_s cn50xx;
+ struct cvmx_fpa_que_exp_s cn52xx;
+ struct cvmx_fpa_que_exp_s cn52xxp1;
+ struct cvmx_fpa_que_exp_s cn56xx;
+ struct cvmx_fpa_que_exp_s cn56xxp1;
+ struct cvmx_fpa_que_exp_s cn58xx;
+ struct cvmx_fpa_que_exp_s cn58xxp1;
+} cvmx_fpa_que_exp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_wart_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ctl:16;
+#else
+ uint64_t ctl:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_fpa_wart_ctl_s cn30xx;
+ struct cvmx_fpa_wart_ctl_s cn31xx;
+ struct cvmx_fpa_wart_ctl_s cn38xx;
+ struct cvmx_fpa_wart_ctl_s cn38xxp2;
+ struct cvmx_fpa_wart_ctl_s cn50xx;
+ struct cvmx_fpa_wart_ctl_s cn52xx;
+ struct cvmx_fpa_wart_ctl_s cn52xxp1;
+ struct cvmx_fpa_wart_ctl_s cn56xx;
+ struct cvmx_fpa_wart_ctl_s cn56xxp1;
+ struct cvmx_fpa_wart_ctl_s cn58xx;
+ struct cvmx_fpa_wart_ctl_s cn58xxp1;
+} cvmx_fpa_wart_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_fpa_wart_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t status:32;
+#else
+ uint64_t status:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_fpa_wart_status_s cn30xx;
+ struct cvmx_fpa_wart_status_s cn31xx;
+ struct cvmx_fpa_wart_status_s cn38xx;
+ struct cvmx_fpa_wart_status_s cn38xxp2;
+ struct cvmx_fpa_wart_status_s cn50xx;
+ struct cvmx_fpa_wart_status_s cn52xx;
+ struct cvmx_fpa_wart_status_s cn52xxp1;
+ struct cvmx_fpa_wart_status_s cn56xx;
+ struct cvmx_fpa_wart_status_s cn56xxp1;
+ struct cvmx_fpa_wart_status_s cn58xx;
+ struct cvmx_fpa_wart_status_s cn58xxp1;
+} cvmx_fpa_wart_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_bad_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t inb_nxa:4;
+ uint64_t statovr:1;
+ uint64_t loststat:4;
+ uint64_t reserved_18_21:4;
+ uint64_t out_ovr:16;
+ uint64_t ncb_ovr:1;
+ uint64_t out_col:1;
+#else
+ uint64_t out_col:1;
+ uint64_t ncb_ovr:1;
+ uint64_t out_ovr:16;
+ uint64_t reserved_18_21:4;
+ uint64_t loststat:4;
+ uint64_t statovr:1;
+ uint64_t inb_nxa:4;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_gmxx_bad_reg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t inb_nxa:4;
+ uint64_t statovr:1;
+ uint64_t reserved_25_25:1;
+ uint64_t loststat:3;
+ uint64_t reserved_5_21:17;
+ uint64_t out_ovr:3;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t out_ovr:3;
+ uint64_t reserved_5_21:17;
+ uint64_t loststat:3;
+ uint64_t reserved_25_25:1;
+ uint64_t statovr:1;
+ uint64_t inb_nxa:4;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
+ struct cvmx_gmxx_bad_reg_s cn38xx;
+ struct cvmx_gmxx_bad_reg_s cn38xxp2;
+ struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
+ struct cvmx_gmxx_bad_reg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t inb_nxa:4;
+ uint64_t statovr:1;
+ uint64_t loststat:4;
+ uint64_t reserved_6_21:16;
+ uint64_t out_ovr:4;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t out_ovr:4;
+ uint64_t reserved_6_21:16;
+ uint64_t loststat:4;
+ uint64_t statovr:1;
+ uint64_t inb_nxa:4;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
+ struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
+ struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
+ struct cvmx_gmxx_bad_reg_s cn58xx;
+ struct cvmx_gmxx_bad_reg_s cn58xxp1;
+} cvmx_gmxx_bad_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_bist_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t status:17;
+#else
+ uint64_t status:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_gmxx_bist_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t status:10;
+#else
+ uint64_t status:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_bist_cn30xx cn31xx;
+ struct cvmx_gmxx_bist_cn30xx cn38xx;
+ struct cvmx_gmxx_bist_cn30xx cn38xxp2;
+ struct cvmx_gmxx_bist_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t status:12;
+#else
+ uint64_t status:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn50xx;
+ struct cvmx_gmxx_bist_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t status:16;
+#else
+ uint64_t status:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_bist_cn52xx cn52xxp1;
+ struct cvmx_gmxx_bist_cn52xx cn56xx;
+ struct cvmx_gmxx_bist_cn52xx cn56xxp1;
+ struct cvmx_gmxx_bist_s cn58xx;
+ struct cvmx_gmxx_bist_s cn58xxp1;
+} cvmx_gmxx_bist_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_clk_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t clk_en:1;
+#else
+ uint64_t clk_en:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_clk_en_s cn52xx;
+ struct cvmx_gmxx_clk_en_s cn52xxp1;
+ struct cvmx_gmxx_clk_en_s cn56xx;
+ struct cvmx_gmxx_clk_en_s cn56xxp1;
+} cvmx_gmxx_clk_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_hg2_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t hg2tx_en:1;
+ uint64_t hg2rx_en:1;
+ uint64_t phys_en:1;
+ uint64_t logl_en:16;
+#else
+ uint64_t logl_en:16;
+ uint64_t phys_en:1;
+ uint64_t hg2rx_en:1;
+ uint64_t hg2tx_en:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_gmxx_hg2_control_s cn52xx;
+ struct cvmx_gmxx_hg2_control_s cn52xxp1;
+ struct cvmx_gmxx_hg2_control_s cn56xx;
+} cvmx_gmxx_hg2_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_inf_mode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t speed:2;
+ uint64_t reserved_6_7:2;
+ uint64_t mode:2;
+ uint64_t reserved_3_3:1;
+ uint64_t p0mii:1;
+ uint64_t en:1;
+ uint64_t type:1;
+#else
+ uint64_t type:1;
+ uint64_t en:1;
+ uint64_t p0mii:1;
+ uint64_t reserved_3_3:1;
+ uint64_t mode:2;
+ uint64_t reserved_6_7:2;
+ uint64_t speed:2;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_gmxx_inf_mode_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t p0mii:1;
+ uint64_t en:1;
+ uint64_t type:1;
+#else
+ uint64_t type:1;
+ uint64_t en:1;
+ uint64_t p0mii:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_inf_mode_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t en:1;
+ uint64_t type:1;
+#else
+ uint64_t type:1;
+ uint64_t en:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn31xx;
+ struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
+ struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
+ struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
+ struct cvmx_gmxx_inf_mode_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t speed:2;
+ uint64_t reserved_6_7:2;
+ uint64_t mode:2;
+ uint64_t reserved_2_3:2;
+ uint64_t en:1;
+ uint64_t type:1;
+#else
+ uint64_t type:1;
+ uint64_t en:1;
+ uint64_t reserved_2_3:2;
+ uint64_t mode:2;
+ uint64_t reserved_6_7:2;
+ uint64_t speed:2;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
+ struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
+ struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
+ struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
+ struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
+} cvmx_gmxx_inf_mode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_nxa_adr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t prt:6;
+#else
+ uint64_t prt:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_gmxx_nxa_adr_s cn30xx;
+ struct cvmx_gmxx_nxa_adr_s cn31xx;
+ struct cvmx_gmxx_nxa_adr_s cn38xx;
+ struct cvmx_gmxx_nxa_adr_s cn38xxp2;
+ struct cvmx_gmxx_nxa_adr_s cn50xx;
+ struct cvmx_gmxx_nxa_adr_s cn52xx;
+ struct cvmx_gmxx_nxa_adr_s cn52xxp1;
+ struct cvmx_gmxx_nxa_adr_s cn56xx;
+ struct cvmx_gmxx_nxa_adr_s cn56xxp1;
+ struct cvmx_gmxx_nxa_adr_s cn58xx;
+ struct cvmx_gmxx_nxa_adr_s cn58xxp1;
+} cvmx_gmxx_nxa_adr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t phys_en:16;
+ uint64_t logl_en:16;
+ uint64_t phys_bp:16;
+ uint64_t reserved_4_15:12;
+ uint64_t bck_en:1;
+ uint64_t drp_en:1;
+ uint64_t tx_en:1;
+ uint64_t rx_en:1;
+#else
+ uint64_t rx_en:1;
+ uint64_t tx_en:1;
+ uint64_t drp_en:1;
+ uint64_t bck_en:1;
+ uint64_t reserved_4_15:12;
+ uint64_t phys_bp:16;
+ uint64_t logl_en:16;
+ uint64_t phys_en:16;
+#endif
+ } s;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
+} cvmx_gmxx_prtx_cbfc_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_prtx_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t tx_idle:1;
+ uint64_t rx_idle:1;
+ uint64_t reserved_9_11:3;
+ uint64_t speed_msb:1;
+ uint64_t reserved_4_7:4;
+ uint64_t slottime:1;
+ uint64_t duplex:1;
+ uint64_t speed:1;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t speed:1;
+ uint64_t duplex:1;
+ uint64_t slottime:1;
+ uint64_t reserved_4_7:4;
+ uint64_t speed_msb:1;
+ uint64_t reserved_9_11:3;
+ uint64_t rx_idle:1;
+ uint64_t tx_idle:1;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_gmxx_prtx_cfg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t slottime:1;
+ uint64_t duplex:1;
+ uint64_t speed:1;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t speed:1;
+ uint64_t duplex:1;
+ uint64_t slottime:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
+ struct cvmx_gmxx_prtx_cfg_s cn52xx;
+ struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
+ struct cvmx_gmxx_prtx_cfg_s cn56xx;
+ struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
+ struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
+} cvmx_gmxx_prtx_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t adr:64;
+#else
+ uint64_t adr:64;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t en:8;
+#else
+ uint64_t en:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t cam_mode:1;
+ uint64_t mcst:2;
+ uint64_t bcst:1;
+#else
+ uint64_t bcst:1;
+ uint64_t mcst:2;
+ uint64_t cam_mode:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_adr_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_decision_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t cnt:5;
+#else
+ uint64_t cnt:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_decision_s cn30xx;
+ struct cvmx_gmxx_rxx_decision_s cn31xx;
+ struct cvmx_gmxx_rxx_decision_s cn38xx;
+ struct cvmx_gmxx_rxx_decision_s cn38xxp2;
+ struct cvmx_gmxx_rxx_decision_s cn50xx;
+ struct cvmx_gmxx_rxx_decision_s cn52xx;
+ struct cvmx_gmxx_rxx_decision_s cn52xxp1;
+ struct cvmx_gmxx_rxx_decision_s cn56xx;
+ struct cvmx_gmxx_rxx_decision_s cn56xxp1;
+ struct cvmx_gmxx_rxx_decision_s cn58xx;
+ struct cvmx_gmxx_rxx_decision_s cn58xxp1;
+} cvmx_gmxx_rxx_decision_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_frm_chk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
+ struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
+ struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
+ struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
+ struct cvmx_gmxx_rxx_frm_chk_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn50xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
+ struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
+ struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
+ struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
+} cvmx_gmxx_rxx_frm_chk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_frm_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t null_dis:1;
+ uint64_t pre_align:1;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t vlan_len:1;
+ uint64_t pad_len:1;
+ uint64_t pre_align:1;
+ uint64_t null_dis:1;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t vlan_len:1;
+ uint64_t pad_len:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t vlan_len:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn31xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
+ struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t null_dis:1;
+ uint64_t pre_align:1;
+ uint64_t reserved_7_8:2;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t reserved_7_8:2;
+ uint64_t pre_align:1;
+ uint64_t null_dis:1;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn50xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
+ struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pre_align:1;
+ uint64_t reserved_7_8:2;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+#else
+ uint64_t pre_chk:1;
+ uint64_t pre_strp:1;
+ uint64_t ctl_drp:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_smac:1;
+ uint64_t pre_free:1;
+ uint64_t reserved_7_8:2;
+ uint64_t pre_align:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn56xxp1;
+ struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
+} cvmx_gmxx_rxx_frm_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_frm_max_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t len:16;
+#else
+ uint64_t len:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_frm_max_s cn30xx;
+ struct cvmx_gmxx_rxx_frm_max_s cn31xx;
+ struct cvmx_gmxx_rxx_frm_max_s cn38xx;
+ struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
+ struct cvmx_gmxx_rxx_frm_max_s cn58xx;
+ struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
+} cvmx_gmxx_rxx_frm_max_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_frm_min_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t len:16;
+#else
+ uint64_t len:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_frm_min_s cn30xx;
+ struct cvmx_gmxx_rxx_frm_min_s cn31xx;
+ struct cvmx_gmxx_rxx_frm_min_s cn38xx;
+ struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
+ struct cvmx_gmxx_rxx_frm_min_s cn58xx;
+ struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
+} cvmx_gmxx_rxx_frm_min_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_ifg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ifg:4;
+#else
+ uint64_t ifg:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_ifg_s cn30xx;
+ struct cvmx_gmxx_rxx_ifg_s cn31xx;
+ struct cvmx_gmxx_rxx_ifg_s cn38xx;
+ struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
+ struct cvmx_gmxx_rxx_ifg_s cn50xx;
+ struct cvmx_gmxx_rxx_ifg_s cn52xx;
+ struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
+ struct cvmx_gmxx_rxx_ifg_s cn56xx;
+ struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
+ struct cvmx_gmxx_rxx_ifg_s cn58xx;
+ struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
+} cvmx_gmxx_rxx_ifg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t hg2cc:1;
+ uint64_t hg2fld:1;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t hg2fld:1;
+ uint64_t hg2cc:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_int_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
+ struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
+ struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
+ struct cvmx_gmxx_rxx_int_en_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn50xx;
+ struct cvmx_gmxx_rxx_int_en_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t hg2cc:1;
+ uint64_t hg2fld:1;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t hg2fld:1;
+ uint64_t hg2cc:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
+ struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
+ struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn56xxp1;
+ struct cvmx_gmxx_rxx_int_en_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn58xx;
+ struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
+} cvmx_gmxx_rxx_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t hg2cc:1;
+ uint64_t hg2fld:1;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t hg2fld:1;
+ uint64_t hg2cc:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_int_reg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
+ struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
+ struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
+ struct cvmx_gmxx_rxx_int_reg_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t reserved_6_6:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn50xx;
+ struct cvmx_gmxx_rxx_int_reg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t hg2cc:1;
+ uint64_t hg2fld:1;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t hg2fld:1;
+ uint64_t hg2cc:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
+ struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
+ struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t undat:1;
+ uint64_t uneop:1;
+ uint64_t unsop:1;
+ uint64_t bad_term:1;
+ uint64_t bad_seq:1;
+ uint64_t rem_fault:1;
+ uint64_t loc_fault:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_16_18:3;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t reserved_2_2:1;
+ uint64_t carext:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t carext:1;
+ uint64_t reserved_2_2:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t reserved_5_6:2;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t reserved_9_9:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t pause_drp:1;
+ uint64_t loc_fault:1;
+ uint64_t rem_fault:1;
+ uint64_t bad_seq:1;
+ uint64_t bad_term:1;
+ uint64_t unsop:1;
+ uint64_t uneop:1;
+ uint64_t undat:1;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn56xxp1;
+ struct cvmx_gmxx_rxx_int_reg_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+#else
+ uint64_t minerr:1;
+ uint64_t carext:1;
+ uint64_t maxerr:1;
+ uint64_t jabber:1;
+ uint64_t fcserr:1;
+ uint64_t alnerr:1;
+ uint64_t lenerr:1;
+ uint64_t rcverr:1;
+ uint64_t skperr:1;
+ uint64_t niberr:1;
+ uint64_t ovrerr:1;
+ uint64_t pcterr:1;
+ uint64_t rsverr:1;
+ uint64_t falerr:1;
+ uint64_t coldet:1;
+ uint64_t ifgerr:1;
+ uint64_t phy_link:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_dupx:1;
+ uint64_t pause_drp:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn58xx;
+ struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
+} cvmx_gmxx_rxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_jabber_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_jabber_s cn30xx;
+ struct cvmx_gmxx_rxx_jabber_s cn31xx;
+ struct cvmx_gmxx_rxx_jabber_s cn38xx;
+ struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
+ struct cvmx_gmxx_rxx_jabber_s cn50xx;
+ struct cvmx_gmxx_rxx_jabber_s cn52xx;
+ struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
+ struct cvmx_gmxx_rxx_jabber_s cn56xx;
+ struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
+ struct cvmx_gmxx_rxx_jabber_s cn58xx;
+ struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
+} cvmx_gmxx_rxx_jabber_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_pause_drop_time_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t status:16;
+#else
+ uint64_t status:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+} cvmx_gmxx_rxx_pause_drop_time_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_rx_inbnd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t duplex:1;
+ uint64_t speed:2;
+ uint64_t status:1;
+#else
+ uint64_t status:1;
+ uint64_t speed:2;
+ uint64_t duplex:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
+ struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
+} cvmx_gmxx_rxx_rx_inbnd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rd_clr:1;
+#else
+ uint64_t rd_clr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_octs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t cnt:48;
+#else
+ uint64_t cnt:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_drp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_pkts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_bad_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_drp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_udd_skp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t fcssel:1;
+ uint64_t reserved_7_7:1;
+ uint64_t len:7;
+#else
+ uint64_t len:7;
+ uint64_t reserved_7_7:1;
+ uint64_t fcssel:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
+ struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
+ struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
+ struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
+} cvmx_gmxx_rxx_udd_skp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_bp_dropx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mark:6;
+#else
+ uint64_t mark:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
+ struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
+ struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
+ struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
+} cvmx_gmxx_rx_bp_dropx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_bp_offx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mark:6;
+#else
+ uint64_t mark:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_bp_offx_s cn30xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn31xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn38xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
+ struct cvmx_gmxx_rx_bp_offx_s cn50xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn52xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
+ struct cvmx_gmxx_rx_bp_offx_s cn56xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
+ struct cvmx_gmxx_rx_bp_offx_s cn58xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
+} cvmx_gmxx_rx_bp_offx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_bp_onx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t mark:9;
+#else
+ uint64_t mark:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_bp_onx_s cn30xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn31xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn38xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
+ struct cvmx_gmxx_rx_bp_onx_s cn50xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn52xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
+ struct cvmx_gmxx_rx_bp_onx_s cn56xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
+ struct cvmx_gmxx_rx_bp_onx_s cn58xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
+} cvmx_gmxx_rx_bp_onx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_hg2_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t phtim2go:16;
+ uint64_t xof:16;
+ uint64_t lgtim2go:16;
+#else
+ uint64_t lgtim2go:16;
+ uint64_t xof:16;
+ uint64_t phtim2go:16;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_hg2_status_s cn52xx;
+ struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
+ struct cvmx_gmxx_rx_hg2_status_s cn56xx;
+} cvmx_gmxx_rx_hg2_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_pass_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t en:16;
+#else
+ uint64_t en:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_pass_en_s cn38xx;
+ struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
+ struct cvmx_gmxx_rx_pass_en_s cn58xx;
+ struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
+} cvmx_gmxx_rx_pass_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_pass_mapx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t dprt:4;
+#else
+ uint64_t dprt:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
+ struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
+ struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
+ struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
+} cvmx_gmxx_rx_pass_mapx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_prt_info_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t drop:16;
+ uint64_t commit:16;
+#else
+ uint64_t commit:16;
+ uint64_t drop:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_prt_info_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t drop:3;
+ uint64_t reserved_3_15:13;
+ uint64_t commit:3;
+#else
+ uint64_t commit:3;
+ uint64_t reserved_3_15:13;
+ uint64_t drop:3;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
+ struct cvmx_gmxx_rx_prt_info_s cn38xx;
+ struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
+ struct cvmx_gmxx_rx_prt_info_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t drop:4;
+ uint64_t reserved_4_15:12;
+ uint64_t commit:4;
+#else
+ uint64_t commit:4;
+ uint64_t reserved_4_15:12;
+ uint64_t drop:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
+ struct cvmx_gmxx_rx_prt_info_s cn58xx;
+ struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
+} cvmx_gmxx_rx_prt_info_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_prts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t prts:3;
+#else
+ uint64_t prts:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_prts_s cn30xx;
+ struct cvmx_gmxx_rx_prts_s cn31xx;
+ struct cvmx_gmxx_rx_prts_s cn38xx;
+ struct cvmx_gmxx_rx_prts_s cn38xxp2;
+ struct cvmx_gmxx_rx_prts_s cn50xx;
+ struct cvmx_gmxx_rx_prts_s cn52xx;
+ struct cvmx_gmxx_rx_prts_s cn52xxp1;
+ struct cvmx_gmxx_rx_prts_s cn56xx;
+ struct cvmx_gmxx_rx_prts_s cn56xxp1;
+ struct cvmx_gmxx_rx_prts_s cn58xx;
+ struct cvmx_gmxx_rx_prts_s cn58xxp1;
+} cvmx_gmxx_rx_prts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_tx_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t tx:3;
+ uint64_t reserved_3_3:1;
+ uint64_t rx:3;
+#else
+ uint64_t rx:3;
+ uint64_t reserved_3_3:1;
+ uint64_t tx:3;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_tx_status_s cn30xx;
+ struct cvmx_gmxx_rx_tx_status_s cn31xx;
+ struct cvmx_gmxx_rx_tx_status_s cn50xx;
+} cvmx_gmxx_rx_tx_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_xaui_bad_col_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t val:1;
+ uint64_t state:3;
+ uint64_t lane_rxc:4;
+ uint64_t lane_rxd:32;
+#else
+ uint64_t lane_rxd:32;
+ uint64_t lane_rxc:4;
+ uint64_t state:3;
+ uint64_t val:1;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
+} cvmx_gmxx_rx_xaui_bad_col_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_rx_xaui_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t status:2;
+#else
+ uint64_t status:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
+} cvmx_gmxx_rx_xaui_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_smacx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t smac:48;
+#else
+ uint64_t smac:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_smacx_s cn30xx;
+ struct cvmx_gmxx_smacx_s cn31xx;
+ struct cvmx_gmxx_smacx_s cn38xx;
+ struct cvmx_gmxx_smacx_s cn38xxp2;
+ struct cvmx_gmxx_smacx_s cn50xx;
+ struct cvmx_gmxx_smacx_s cn52xx;
+ struct cvmx_gmxx_smacx_s cn52xxp1;
+ struct cvmx_gmxx_smacx_s cn56xx;
+ struct cvmx_gmxx_smacx_s cn56xxp1;
+ struct cvmx_gmxx_smacx_s cn58xx;
+ struct cvmx_gmxx_smacx_s cn58xxp1;
+} cvmx_gmxx_smacx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_stat_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t bp:1;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t bp:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_gmxx_stat_bp_s cn30xx;
+ struct cvmx_gmxx_stat_bp_s cn31xx;
+ struct cvmx_gmxx_stat_bp_s cn38xx;
+ struct cvmx_gmxx_stat_bp_s cn38xxp2;
+ struct cvmx_gmxx_stat_bp_s cn50xx;
+ struct cvmx_gmxx_stat_bp_s cn52xx;
+ struct cvmx_gmxx_stat_bp_s cn52xxp1;
+ struct cvmx_gmxx_stat_bp_s cn56xx;
+ struct cvmx_gmxx_stat_bp_s cn56xxp1;
+ struct cvmx_gmxx_stat_bp_s cn58xx;
+ struct cvmx_gmxx_stat_bp_s cn58xxp1;
+} cvmx_gmxx_stat_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_append_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t force_fcs:1;
+ uint64_t fcs:1;
+ uint64_t pad:1;
+ uint64_t preamble:1;
+#else
+ uint64_t preamble:1;
+ uint64_t pad:1;
+ uint64_t fcs:1;
+ uint64_t force_fcs:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_append_s cn30xx;
+ struct cvmx_gmxx_txx_append_s cn31xx;
+ struct cvmx_gmxx_txx_append_s cn38xx;
+ struct cvmx_gmxx_txx_append_s cn38xxp2;
+ struct cvmx_gmxx_txx_append_s cn50xx;
+ struct cvmx_gmxx_txx_append_s cn52xx;
+ struct cvmx_gmxx_txx_append_s cn52xxp1;
+ struct cvmx_gmxx_txx_append_s cn56xx;
+ struct cvmx_gmxx_txx_append_s cn56xxp1;
+ struct cvmx_gmxx_txx_append_s cn58xx;
+ struct cvmx_gmxx_txx_append_s cn58xxp1;
+} cvmx_gmxx_txx_append_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_burst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t burst:16;
+#else
+ uint64_t burst:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_burst_s cn30xx;
+ struct cvmx_gmxx_txx_burst_s cn31xx;
+ struct cvmx_gmxx_txx_burst_s cn38xx;
+ struct cvmx_gmxx_txx_burst_s cn38xxp2;
+ struct cvmx_gmxx_txx_burst_s cn50xx;
+ struct cvmx_gmxx_txx_burst_s cn52xx;
+ struct cvmx_gmxx_txx_burst_s cn52xxp1;
+ struct cvmx_gmxx_txx_burst_s cn56xx;
+ struct cvmx_gmxx_txx_burst_s cn56xxp1;
+ struct cvmx_gmxx_txx_burst_s cn58xx;
+ struct cvmx_gmxx_txx_burst_s cn58xxp1;
+} cvmx_gmxx_txx_burst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_cbfc_xoff_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t xoff:16;
+#else
+ uint64_t xoff:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
+} cvmx_gmxx_txx_cbfc_xoff_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_cbfc_xon_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t xon:16;
+#else
+ uint64_t xon:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
+} cvmx_gmxx_txx_cbfc_xon_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_clk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t clk_cnt:6;
+#else
+ uint64_t clk_cnt:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_clk_s cn30xx;
+ struct cvmx_gmxx_txx_clk_s cn31xx;
+ struct cvmx_gmxx_txx_clk_s cn38xx;
+ struct cvmx_gmxx_txx_clk_s cn38xxp2;
+ struct cvmx_gmxx_txx_clk_s cn50xx;
+ struct cvmx_gmxx_txx_clk_s cn58xx;
+ struct cvmx_gmxx_txx_clk_s cn58xxp1;
+} cvmx_gmxx_txx_clk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t xsdef_en:1;
+ uint64_t xscol_en:1;
+#else
+ uint64_t xscol_en:1;
+ uint64_t xsdef_en:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_ctl_s cn30xx;
+ struct cvmx_gmxx_txx_ctl_s cn31xx;
+ struct cvmx_gmxx_txx_ctl_s cn38xx;
+ struct cvmx_gmxx_txx_ctl_s cn38xxp2;
+ struct cvmx_gmxx_txx_ctl_s cn50xx;
+ struct cvmx_gmxx_txx_ctl_s cn52xx;
+ struct cvmx_gmxx_txx_ctl_s cn52xxp1;
+ struct cvmx_gmxx_txx_ctl_s cn56xx;
+ struct cvmx_gmxx_txx_ctl_s cn56xxp1;
+ struct cvmx_gmxx_txx_ctl_s cn58xx;
+ struct cvmx_gmxx_txx_ctl_s cn58xxp1;
+} cvmx_gmxx_txx_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_min_pkt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t min_size:8;
+#else
+ uint64_t min_size:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_min_pkt_s cn30xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn31xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn38xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
+ struct cvmx_gmxx_txx_min_pkt_s cn50xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn52xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
+ struct cvmx_gmxx_txx_min_pkt_s cn56xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
+ struct cvmx_gmxx_txx_min_pkt_s cn58xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
+} cvmx_gmxx_txx_min_pkt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t interval:16;
+#else
+ uint64_t interval:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+} cvmx_gmxx_txx_pause_pkt_interval_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_pause_pkt_time_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+} cvmx_gmxx_txx_pause_pkt_time_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_pause_togo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t msg_time:16;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t msg_time:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
+ struct cvmx_gmxx_txx_pause_togo_s cn52xx;
+ struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
+ struct cvmx_gmxx_txx_pause_togo_s cn56xx;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
+ struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+} cvmx_gmxx_txx_pause_togo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_pause_zero_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t send:1;
+#else
+ uint64_t send:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_pause_zero_s cn30xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn31xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn38xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
+ struct cvmx_gmxx_txx_pause_zero_s cn50xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn52xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
+ struct cvmx_gmxx_txx_pause_zero_s cn56xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
+ struct cvmx_gmxx_txx_pause_zero_s cn58xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
+} cvmx_gmxx_txx_pause_zero_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_sgmii_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t align:1;
+#else
+ uint64_t align:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
+} cvmx_gmxx_txx_sgmii_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_slot_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t slot:10;
+#else
+ uint64_t slot:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_slot_s cn30xx;
+ struct cvmx_gmxx_txx_slot_s cn31xx;
+ struct cvmx_gmxx_txx_slot_s cn38xx;
+ struct cvmx_gmxx_txx_slot_s cn38xxp2;
+ struct cvmx_gmxx_txx_slot_s cn50xx;
+ struct cvmx_gmxx_txx_slot_s cn52xx;
+ struct cvmx_gmxx_txx_slot_s cn52xxp1;
+ struct cvmx_gmxx_txx_slot_s cn56xx;
+ struct cvmx_gmxx_txx_slot_s cn56xxp1;
+ struct cvmx_gmxx_txx_slot_s cn58xx;
+ struct cvmx_gmxx_txx_slot_s cn58xxp1;
+} cvmx_gmxx_txx_slot_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_soft_pause_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t time:16;
+#else
+ uint64_t time:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_soft_pause_s cn30xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn31xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn38xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
+ struct cvmx_gmxx_txx_soft_pause_s cn50xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn52xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
+ struct cvmx_gmxx_txx_soft_pause_s cn56xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
+ struct cvmx_gmxx_txx_soft_pause_s cn58xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
+} cvmx_gmxx_txx_soft_pause_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t xsdef:32;
+ uint64_t xscol:32;
+#else
+ uint64_t xscol:32;
+ uint64_t xsdef:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat0_s cn30xx;
+ struct cvmx_gmxx_txx_stat0_s cn31xx;
+ struct cvmx_gmxx_txx_stat0_s cn38xx;
+ struct cvmx_gmxx_txx_stat0_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat0_s cn50xx;
+ struct cvmx_gmxx_txx_stat0_s cn52xx;
+ struct cvmx_gmxx_txx_stat0_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat0_s cn56xx;
+ struct cvmx_gmxx_txx_stat0_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat0_s cn58xx;
+ struct cvmx_gmxx_txx_stat0_s cn58xxp1;
+} cvmx_gmxx_txx_stat0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t scol:32;
+ uint64_t mcol:32;
+#else
+ uint64_t mcol:32;
+ uint64_t scol:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat1_s cn30xx;
+ struct cvmx_gmxx_txx_stat1_s cn31xx;
+ struct cvmx_gmxx_txx_stat1_s cn38xx;
+ struct cvmx_gmxx_txx_stat1_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat1_s cn50xx;
+ struct cvmx_gmxx_txx_stat1_s cn52xx;
+ struct cvmx_gmxx_txx_stat1_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat1_s cn56xx;
+ struct cvmx_gmxx_txx_stat1_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat1_s cn58xx;
+ struct cvmx_gmxx_txx_stat1_s cn58xxp1;
+} cvmx_gmxx_txx_stat1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t octs:48;
+#else
+ uint64_t octs:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat2_s cn30xx;
+ struct cvmx_gmxx_txx_stat2_s cn31xx;
+ struct cvmx_gmxx_txx_stat2_s cn38xx;
+ struct cvmx_gmxx_txx_stat2_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat2_s cn50xx;
+ struct cvmx_gmxx_txx_stat2_s cn52xx;
+ struct cvmx_gmxx_txx_stat2_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat2_s cn56xx;
+ struct cvmx_gmxx_txx_stat2_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat2_s cn58xx;
+ struct cvmx_gmxx_txx_stat2_s cn58xxp1;
+} cvmx_gmxx_txx_stat2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pkts:32;
+#else
+ uint64_t pkts:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat3_s cn30xx;
+ struct cvmx_gmxx_txx_stat3_s cn31xx;
+ struct cvmx_gmxx_txx_stat3_s cn38xx;
+ struct cvmx_gmxx_txx_stat3_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat3_s cn50xx;
+ struct cvmx_gmxx_txx_stat3_s cn52xx;
+ struct cvmx_gmxx_txx_stat3_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat3_s cn56xx;
+ struct cvmx_gmxx_txx_stat3_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat3_s cn58xx;
+ struct cvmx_gmxx_txx_stat3_s cn58xxp1;
+} cvmx_gmxx_txx_stat3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist1:32;
+ uint64_t hist0:32;
+#else
+ uint64_t hist0:32;
+ uint64_t hist1:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat4_s cn30xx;
+ struct cvmx_gmxx_txx_stat4_s cn31xx;
+ struct cvmx_gmxx_txx_stat4_s cn38xx;
+ struct cvmx_gmxx_txx_stat4_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat4_s cn50xx;
+ struct cvmx_gmxx_txx_stat4_s cn52xx;
+ struct cvmx_gmxx_txx_stat4_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat4_s cn56xx;
+ struct cvmx_gmxx_txx_stat4_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat4_s cn58xx;
+ struct cvmx_gmxx_txx_stat4_s cn58xxp1;
+} cvmx_gmxx_txx_stat4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist3:32;
+ uint64_t hist2:32;
+#else
+ uint64_t hist2:32;
+ uint64_t hist3:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat5_s cn30xx;
+ struct cvmx_gmxx_txx_stat5_s cn31xx;
+ struct cvmx_gmxx_txx_stat5_s cn38xx;
+ struct cvmx_gmxx_txx_stat5_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat5_s cn50xx;
+ struct cvmx_gmxx_txx_stat5_s cn52xx;
+ struct cvmx_gmxx_txx_stat5_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat5_s cn56xx;
+ struct cvmx_gmxx_txx_stat5_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat5_s cn58xx;
+ struct cvmx_gmxx_txx_stat5_s cn58xxp1;
+} cvmx_gmxx_txx_stat5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist5:32;
+ uint64_t hist4:32;
+#else
+ uint64_t hist4:32;
+ uint64_t hist5:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat6_s cn30xx;
+ struct cvmx_gmxx_txx_stat6_s cn31xx;
+ struct cvmx_gmxx_txx_stat6_s cn38xx;
+ struct cvmx_gmxx_txx_stat6_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat6_s cn50xx;
+ struct cvmx_gmxx_txx_stat6_s cn52xx;
+ struct cvmx_gmxx_txx_stat6_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat6_s cn56xx;
+ struct cvmx_gmxx_txx_stat6_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat6_s cn58xx;
+ struct cvmx_gmxx_txx_stat6_s cn58xxp1;
+} cvmx_gmxx_txx_stat6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t hist7:32;
+ uint64_t hist6:32;
+#else
+ uint64_t hist6:32;
+ uint64_t hist7:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat7_s cn30xx;
+ struct cvmx_gmxx_txx_stat7_s cn31xx;
+ struct cvmx_gmxx_txx_stat7_s cn38xx;
+ struct cvmx_gmxx_txx_stat7_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat7_s cn50xx;
+ struct cvmx_gmxx_txx_stat7_s cn52xx;
+ struct cvmx_gmxx_txx_stat7_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat7_s cn56xx;
+ struct cvmx_gmxx_txx_stat7_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat7_s cn58xx;
+ struct cvmx_gmxx_txx_stat7_s cn58xxp1;
+} cvmx_gmxx_txx_stat7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat8_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mcst:32;
+ uint64_t bcst:32;
+#else
+ uint64_t bcst:32;
+ uint64_t mcst:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat8_s cn30xx;
+ struct cvmx_gmxx_txx_stat8_s cn31xx;
+ struct cvmx_gmxx_txx_stat8_s cn38xx;
+ struct cvmx_gmxx_txx_stat8_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat8_s cn50xx;
+ struct cvmx_gmxx_txx_stat8_s cn52xx;
+ struct cvmx_gmxx_txx_stat8_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat8_s cn56xx;
+ struct cvmx_gmxx_txx_stat8_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat8_s cn58xx;
+ struct cvmx_gmxx_txx_stat8_s cn58xxp1;
+} cvmx_gmxx_txx_stat8_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stat9_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t undflw:32;
+ uint64_t ctl:32;
+#else
+ uint64_t ctl:32;
+ uint64_t undflw:32;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stat9_s cn30xx;
+ struct cvmx_gmxx_txx_stat9_s cn31xx;
+ struct cvmx_gmxx_txx_stat9_s cn38xx;
+ struct cvmx_gmxx_txx_stat9_s cn38xxp2;
+ struct cvmx_gmxx_txx_stat9_s cn50xx;
+ struct cvmx_gmxx_txx_stat9_s cn52xx;
+ struct cvmx_gmxx_txx_stat9_s cn52xxp1;
+ struct cvmx_gmxx_txx_stat9_s cn56xx;
+ struct cvmx_gmxx_txx_stat9_s cn56xxp1;
+ struct cvmx_gmxx_txx_stat9_s cn58xx;
+ struct cvmx_gmxx_txx_stat9_s cn58xxp1;
+} cvmx_gmxx_txx_stat9_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_stats_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rd_clr:1;
+#else
+ uint64_t rd_clr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
+ struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
+ struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
+ struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
+} cvmx_gmxx_txx_stats_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_thresh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t cnt:9;
+#else
+ uint64_t cnt:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_thresh_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t cnt:7;
+#else
+ uint64_t cnt:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
+ struct cvmx_gmxx_txx_thresh_s cn38xx;
+ struct cvmx_gmxx_txx_thresh_s cn38xxp2;
+ struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
+ struct cvmx_gmxx_txx_thresh_s cn52xx;
+ struct cvmx_gmxx_txx_thresh_s cn52xxp1;
+ struct cvmx_gmxx_txx_thresh_s cn56xx;
+ struct cvmx_gmxx_txx_thresh_s cn56xxp1;
+ struct cvmx_gmxx_txx_thresh_s cn58xx;
+ struct cvmx_gmxx_txx_thresh_s cn58xxp1;
+} cvmx_gmxx_txx_thresh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t bp:4;
+#else
+ uint64_t bp:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_bp_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t bp:3;
+#else
+ uint64_t bp:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
+ struct cvmx_gmxx_tx_bp_s cn38xx;
+ struct cvmx_gmxx_tx_bp_s cn38xxp2;
+ struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
+ struct cvmx_gmxx_tx_bp_s cn52xx;
+ struct cvmx_gmxx_tx_bp_s cn52xxp1;
+ struct cvmx_gmxx_tx_bp_s cn56xx;
+ struct cvmx_gmxx_tx_bp_s cn56xxp1;
+ struct cvmx_gmxx_tx_bp_s cn58xx;
+ struct cvmx_gmxx_tx_bp_s cn58xxp1;
+} cvmx_gmxx_tx_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_clk_mskx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t msk:1;
+#else
+ uint64_t msk:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
+ struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
+} cvmx_gmxx_tx_clk_mskx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_col_attempt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t limit:5;
+#else
+ uint64_t limit:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_col_attempt_s cn30xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn31xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn38xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
+ struct cvmx_gmxx_tx_col_attempt_s cn50xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn52xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
+ struct cvmx_gmxx_tx_col_attempt_s cn56xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
+ struct cvmx_gmxx_tx_col_attempt_s cn58xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
+} cvmx_gmxx_tx_col_attempt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_corrupt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t corrupt:4;
+#else
+ uint64_t corrupt:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_corrupt_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t corrupt:3;
+#else
+ uint64_t corrupt:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
+ struct cvmx_gmxx_tx_corrupt_s cn38xx;
+ struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
+ struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
+ struct cvmx_gmxx_tx_corrupt_s cn52xx;
+ struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
+ struct cvmx_gmxx_tx_corrupt_s cn56xx;
+ struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
+ struct cvmx_gmxx_tx_corrupt_s cn58xx;
+ struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
+} cvmx_gmxx_tx_corrupt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_hg2_reg1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t tx_xof:16;
+#else
+ uint64_t tx_xof:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
+} cvmx_gmxx_tx_hg2_reg1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_hg2_reg2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t tx_xon:16;
+#else
+ uint64_t tx_xon:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
+} cvmx_gmxx_tx_hg2_reg2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_ifg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ifg2:4;
+ uint64_t ifg1:4;
+#else
+ uint64_t ifg1:4;
+ uint64_t ifg2:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_ifg_s cn30xx;
+ struct cvmx_gmxx_tx_ifg_s cn31xx;
+ struct cvmx_gmxx_tx_ifg_s cn38xx;
+ struct cvmx_gmxx_tx_ifg_s cn38xxp2;
+ struct cvmx_gmxx_tx_ifg_s cn50xx;
+ struct cvmx_gmxx_tx_ifg_s cn52xx;
+ struct cvmx_gmxx_tx_ifg_s cn52xxp1;
+ struct cvmx_gmxx_tx_ifg_s cn56xx;
+ struct cvmx_gmxx_tx_ifg_s cn56xxp1;
+ struct cvmx_gmxx_tx_ifg_s cn58xx;
+ struct cvmx_gmxx_tx_ifg_s cn58xxp1;
+} cvmx_gmxx_tx_ifg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t late_col:4;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t ncb_nxa:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t ncb_nxa:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t late_col:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_int_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t late_col:3;
+ uint64_t reserved_15_15:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xscol:3;
+ uint64_t reserved_5_7:3;
+ uint64_t undflw:3;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:3;
+ uint64_t reserved_5_7:3;
+ uint64_t xscol:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_15_15:1;
+ uint64_t late_col:3;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_tx_int_en_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t xsdef:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xscol:3;
+ uint64_t reserved_5_7:3;
+ uint64_t undflw:3;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:3;
+ uint64_t reserved_5_7:3;
+ uint64_t xscol:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_15_63:49;
+#endif
+ } cn31xx;
+ struct cvmx_gmxx_tx_int_en_s cn38xx;
+ struct cvmx_gmxx_tx_int_en_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t ncb_nxa:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t ncb_nxa:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xxp2;
+ struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
+ struct cvmx_gmxx_tx_int_en_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t late_col:4;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t late_col:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
+ struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
+ struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
+ struct cvmx_gmxx_tx_int_en_s cn58xx;
+ struct cvmx_gmxx_tx_int_en_s cn58xxp1;
+} cvmx_gmxx_tx_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t late_col:4;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t ncb_nxa:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t ncb_nxa:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t late_col:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_int_reg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t late_col:3;
+ uint64_t reserved_15_15:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xscol:3;
+ uint64_t reserved_5_7:3;
+ uint64_t undflw:3;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:3;
+ uint64_t reserved_5_7:3;
+ uint64_t xscol:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_15_15:1;
+ uint64_t late_col:3;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_tx_int_reg_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t xsdef:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xscol:3;
+ uint64_t reserved_5_7:3;
+ uint64_t undflw:3;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:3;
+ uint64_t reserved_5_7:3;
+ uint64_t xscol:3;
+ uint64_t reserved_11_11:1;
+ uint64_t xsdef:3;
+ uint64_t reserved_15_63:49;
+#endif
+ } cn31xx;
+ struct cvmx_gmxx_tx_int_reg_s cn38xx;
+ struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t ncb_nxa:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t ncb_nxa:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xxp2;
+ struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
+ struct cvmx_gmxx_tx_int_reg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t late_col:4;
+ uint64_t xsdef:4;
+ uint64_t xscol:4;
+ uint64_t reserved_6_7:2;
+ uint64_t undflw:4;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+#else
+ uint64_t pko_nxa:1;
+ uint64_t reserved_1_1:1;
+ uint64_t undflw:4;
+ uint64_t reserved_6_7:2;
+ uint64_t xscol:4;
+ uint64_t xsdef:4;
+ uint64_t late_col:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
+ struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
+ struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
+ struct cvmx_gmxx_tx_int_reg_s cn58xx;
+ struct cvmx_gmxx_tx_int_reg_s cn58xxp1;
+} cvmx_gmxx_tx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_jam_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t jam:8;
+#else
+ uint64_t jam:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_jam_s cn30xx;
+ struct cvmx_gmxx_tx_jam_s cn31xx;
+ struct cvmx_gmxx_tx_jam_s cn38xx;
+ struct cvmx_gmxx_tx_jam_s cn38xxp2;
+ struct cvmx_gmxx_tx_jam_s cn50xx;
+ struct cvmx_gmxx_tx_jam_s cn52xx;
+ struct cvmx_gmxx_tx_jam_s cn52xxp1;
+ struct cvmx_gmxx_tx_jam_s cn56xx;
+ struct cvmx_gmxx_tx_jam_s cn56xxp1;
+ struct cvmx_gmxx_tx_jam_s cn58xx;
+ struct cvmx_gmxx_tx_jam_s cn58xxp1;
+} cvmx_gmxx_tx_jam_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_lfsr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t lfsr:16;
+#else
+ uint64_t lfsr:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_lfsr_s cn30xx;
+ struct cvmx_gmxx_tx_lfsr_s cn31xx;
+ struct cvmx_gmxx_tx_lfsr_s cn38xx;
+ struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
+ struct cvmx_gmxx_tx_lfsr_s cn50xx;
+ struct cvmx_gmxx_tx_lfsr_s cn52xx;
+ struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
+ struct cvmx_gmxx_tx_lfsr_s cn56xx;
+ struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
+ struct cvmx_gmxx_tx_lfsr_s cn58xx;
+ struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
+} cvmx_gmxx_tx_lfsr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_ovr_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t tx_prt_bp:16;
+ uint64_t reserved_12_31:20;
+ uint64_t en:4;
+ uint64_t bp:4;
+ uint64_t ign_full:4;
+#else
+ uint64_t ign_full:4;
+ uint64_t bp:4;
+ uint64_t en:4;
+ uint64_t reserved_12_31:20;
+ uint64_t tx_prt_bp:16;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_ovr_bp_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t en:3;
+ uint64_t reserved_7_7:1;
+ uint64_t bp:3;
+ uint64_t reserved_3_3:1;
+ uint64_t ign_full:3;
+#else
+ uint64_t ign_full:3;
+ uint64_t reserved_3_3:1;
+ uint64_t bp:3;
+ uint64_t reserved_7_7:1;
+ uint64_t en:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
+ struct cvmx_gmxx_tx_ovr_bp_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t en:4;
+ uint64_t bp:4;
+ uint64_t ign_full:4;
+#else
+ uint64_t ign_full:4;
+ uint64_t bp:4;
+ uint64_t en:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn38xx;
+ struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
+ struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
+ struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
+ struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
+ struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
+ struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
+ struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
+ struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
+} cvmx_gmxx_tx_ovr_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t dmac:48;
+#else
+ uint64_t dmac:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
+} cvmx_gmxx_tx_pause_pkt_dmac_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_pause_pkt_type_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t type:16;
+#else
+ uint64_t type:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
+} cvmx_gmxx_tx_pause_pkt_type_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_prts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t prts:5;
+#else
+ uint64_t prts:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_prts_s cn30xx;
+ struct cvmx_gmxx_tx_prts_s cn31xx;
+ struct cvmx_gmxx_tx_prts_s cn38xx;
+ struct cvmx_gmxx_tx_prts_s cn38xxp2;
+ struct cvmx_gmxx_tx_prts_s cn50xx;
+ struct cvmx_gmxx_tx_prts_s cn52xx;
+ struct cvmx_gmxx_tx_prts_s cn52xxp1;
+ struct cvmx_gmxx_tx_prts_s cn56xx;
+ struct cvmx_gmxx_tx_prts_s cn56xxp1;
+ struct cvmx_gmxx_tx_prts_s cn58xx;
+ struct cvmx_gmxx_tx_prts_s cn58xxp1;
+} cvmx_gmxx_tx_prts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_spi_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t tpa_clr:1;
+ uint64_t cont_pkt:1;
+#else
+ uint64_t cont_pkt:1;
+ uint64_t tpa_clr:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
+ struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
+ struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
+ struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
+} cvmx_gmxx_tx_spi_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_spi_drain_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t drain:16;
+#else
+ uint64_t drain:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_spi_drain_s cn38xx;
+ struct cvmx_gmxx_tx_spi_drain_s cn58xx;
+ struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
+} cvmx_gmxx_tx_spi_drain_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_spi_max_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t slice:7;
+ uint64_t max2:8;
+ uint64_t max1:8;
+#else
+ uint64_t max1:8;
+ uint64_t max2:8;
+ uint64_t slice:7;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_spi_max_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t max2:8;
+ uint64_t max1:8;
+#else
+ uint64_t max1:8;
+ uint64_t max2:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
+ struct cvmx_gmxx_tx_spi_max_s cn58xx;
+ struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
+} cvmx_gmxx_tx_spi_max_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_spi_roundx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t round:16;
+#else
+ uint64_t round:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
+ struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
+} cvmx_gmxx_tx_spi_roundx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_spi_thresh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t thresh:6;
+#else
+ uint64_t thresh:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
+ struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
+ struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
+ struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
+} cvmx_gmxx_tx_spi_thresh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_tx_xaui_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t hg_pause_hgi:2;
+ uint64_t hg_en:1;
+ uint64_t reserved_7_7:1;
+ uint64_t ls_byp:1;
+ uint64_t ls:2;
+ uint64_t reserved_2_3:2;
+ uint64_t uni_en:1;
+ uint64_t dic_en:1;
+#else
+ uint64_t dic_en:1;
+ uint64_t uni_en:1;
+ uint64_t reserved_2_3:2;
+ uint64_t ls:2;
+ uint64_t ls_byp:1;
+ uint64_t reserved_7_7:1;
+ uint64_t hg_en:1;
+ uint64_t hg_pause_hgi:2;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
+} cvmx_gmxx_tx_xaui_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gmxx_xaui_ext_loopback_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t en:1;
+ uint64_t thresh:4;
+#else
+ uint64_t thresh:4;
+ uint64_t en:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
+} cvmx_gmxx_xaui_ext_loopback_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_bit_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t clk_gen:1;
+ uint64_t clk_sel:2;
+ uint64_t fil_sel:4;
+ uint64_t fil_cnt:4;
+ uint64_t int_type:1;
+ uint64_t int_en:1;
+ uint64_t rx_xor:1;
+ uint64_t tx_oe:1;
+#else
+ uint64_t tx_oe:1;
+ uint64_t rx_xor:1;
+ uint64_t int_en:1;
+ uint64_t int_type:1;
+ uint64_t fil_cnt:4;
+ uint64_t fil_sel:4;
+ uint64_t clk_sel:2;
+ uint64_t clk_gen:1;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_gpio_bit_cfgx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t fil_sel:4;
+ uint64_t fil_cnt:4;
+ uint64_t int_type:1;
+ uint64_t int_en:1;
+ uint64_t rx_xor:1;
+ uint64_t tx_oe:1;
+#else
+ uint64_t tx_oe:1;
+ uint64_t rx_xor:1;
+ uint64_t int_en:1;
+ uint64_t int_type:1;
+ uint64_t fil_cnt:4;
+ uint64_t fil_sel:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn30xx;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
+ struct cvmx_gpio_bit_cfgx_s cn52xx;
+ struct cvmx_gpio_bit_cfgx_s cn52xxp1;
+ struct cvmx_gpio_bit_cfgx_s cn56xx;
+ struct cvmx_gpio_bit_cfgx_s cn56xxp1;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
+ struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
+} cvmx_gpio_bit_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_boot_ena_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t boot_ena:4;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t boot_ena:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_gpio_boot_ena_s cn30xx;
+ struct cvmx_gpio_boot_ena_s cn31xx;
+ struct cvmx_gpio_boot_ena_s cn50xx;
+} cvmx_gpio_boot_ena_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_clk_genx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t n:32;
+#else
+ uint64_t n:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_gpio_clk_genx_s cn52xx;
+ struct cvmx_gpio_clk_genx_s cn52xxp1;
+ struct cvmx_gpio_clk_genx_s cn56xx;
+ struct cvmx_gpio_clk_genx_s cn56xxp1;
+} cvmx_gpio_clk_genx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_dbg_ena_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t dbg_ena:21;
+#else
+ uint64_t dbg_ena:21;
+ uint64_t reserved_21_63:43;
+#endif
+ } s;
+ struct cvmx_gpio_dbg_ena_s cn30xx;
+ struct cvmx_gpio_dbg_ena_s cn31xx;
+ struct cvmx_gpio_dbg_ena_s cn50xx;
+} cvmx_gpio_dbg_ena_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_int_clr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t type:16;
+#else
+ uint64_t type:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_gpio_int_clr_s cn30xx;
+ struct cvmx_gpio_int_clr_s cn31xx;
+ struct cvmx_gpio_int_clr_s cn38xx;
+ struct cvmx_gpio_int_clr_s cn38xxp2;
+ struct cvmx_gpio_int_clr_s cn50xx;
+ struct cvmx_gpio_int_clr_s cn52xx;
+ struct cvmx_gpio_int_clr_s cn52xxp1;
+ struct cvmx_gpio_int_clr_s cn56xx;
+ struct cvmx_gpio_int_clr_s cn56xxp1;
+ struct cvmx_gpio_int_clr_s cn58xx;
+ struct cvmx_gpio_int_clr_s cn58xxp1;
+} cvmx_gpio_int_clr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_rx_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t dat:24;
+#else
+ uint64_t dat:24;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_gpio_rx_dat_s cn30xx;
+ struct cvmx_gpio_rx_dat_s cn31xx;
+ struct cvmx_gpio_rx_dat_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dat:16;
+#else
+ uint64_t dat:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
+ struct cvmx_gpio_rx_dat_s cn50xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn52xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
+ struct cvmx_gpio_rx_dat_cn38xx cn56xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
+ struct cvmx_gpio_rx_dat_cn38xx cn58xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
+} cvmx_gpio_rx_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_tx_clr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t clr:24;
+#else
+ uint64_t clr:24;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_gpio_tx_clr_s cn30xx;
+ struct cvmx_gpio_tx_clr_s cn31xx;
+ struct cvmx_gpio_tx_clr_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t clr:16;
+#else
+ uint64_t clr:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
+ struct cvmx_gpio_tx_clr_s cn50xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn52xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
+ struct cvmx_gpio_tx_clr_cn38xx cn56xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
+ struct cvmx_gpio_tx_clr_cn38xx cn58xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
+} cvmx_gpio_tx_clr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_tx_set_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t set:24;
+#else
+ uint64_t set:24;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_gpio_tx_set_s cn30xx;
+ struct cvmx_gpio_tx_set_s cn31xx;
+ struct cvmx_gpio_tx_set_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t set:16;
+#else
+ uint64_t set:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
+ struct cvmx_gpio_tx_set_s cn50xx;
+ struct cvmx_gpio_tx_set_cn38xx cn52xx;
+ struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
+ struct cvmx_gpio_tx_set_cn38xx cn56xx;
+ struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
+ struct cvmx_gpio_tx_set_cn38xx cn58xx;
+ struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
+} cvmx_gpio_tx_set_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_gpio_xbit_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t fil_sel:4;
+ uint64_t fil_cnt:4;
+ uint64_t reserved_2_3:2;
+ uint64_t rx_xor:1;
+ uint64_t tx_oe:1;
+#else
+ uint64_t tx_oe:1;
+ uint64_t rx_xor:1;
+ uint64_t reserved_2_3:2;
+ uint64_t fil_cnt:4;
+ uint64_t fil_sel:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_gpio_xbit_cfgx_s cn30xx;
+ struct cvmx_gpio_xbit_cfgx_s cn31xx;
+ struct cvmx_gpio_xbit_cfgx_s cn50xx;
+} cvmx_gpio_xbit_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t icnrcb:1;
+ uint64_t icr0:1;
+ uint64_t icr1:1;
+ uint64_t icnr1:1;
+ uint64_t icnr0:1;
+ uint64_t ibdr0:1;
+ uint64_t ibdr1:1;
+ uint64_t ibr0:1;
+ uint64_t ibr1:1;
+ uint64_t icnrt:1;
+ uint64_t ibrq0:1;
+ uint64_t ibrq1:1;
+ uint64_t icrn0:1;
+ uint64_t icrn1:1;
+ uint64_t icrp0:1;
+ uint64_t icrp1:1;
+ uint64_t ibd:1;
+ uint64_t icd:1;
+#else
+ uint64_t icd:1;
+ uint64_t ibd:1;
+ uint64_t icrp1:1;
+ uint64_t icrp0:1;
+ uint64_t icrn1:1;
+ uint64_t icrn0:1;
+ uint64_t ibrq1:1;
+ uint64_t ibrq0:1;
+ uint64_t icnrt:1;
+ uint64_t ibr1:1;
+ uint64_t ibr0:1;
+ uint64_t ibdr1:1;
+ uint64_t ibdr0:1;
+ uint64_t icnr0:1;
+ uint64_t icnr1:1;
+ uint64_t icr1:1;
+ uint64_t icr0:1;
+ uint64_t icnrcb:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_iob_bist_status_s cn30xx;
+ struct cvmx_iob_bist_status_s cn31xx;
+ struct cvmx_iob_bist_status_s cn38xx;
+ struct cvmx_iob_bist_status_s cn38xxp2;
+ struct cvmx_iob_bist_status_s cn50xx;
+ struct cvmx_iob_bist_status_s cn52xx;
+ struct cvmx_iob_bist_status_s cn52xxp1;
+ struct cvmx_iob_bist_status_s cn56xx;
+ struct cvmx_iob_bist_status_s cn56xxp1;
+ struct cvmx_iob_bist_status_s cn58xx;
+ struct cvmx_iob_bist_status_s cn58xxp1;
+} cvmx_iob_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t outb_mat:1;
+ uint64_t inb_mat:1;
+ uint64_t pko_enb:1;
+ uint64_t dwb_enb:1;
+ uint64_t fau_end:1;
+#else
+ uint64_t fau_end:1;
+ uint64_t dwb_enb:1;
+ uint64_t pko_enb:1;
+ uint64_t inb_mat:1;
+ uint64_t outb_mat:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_iob_ctl_status_s cn30xx;
+ struct cvmx_iob_ctl_status_s cn31xx;
+ struct cvmx_iob_ctl_status_s cn38xx;
+ struct cvmx_iob_ctl_status_s cn38xxp2;
+ struct cvmx_iob_ctl_status_s cn50xx;
+ struct cvmx_iob_ctl_status_s cn52xx;
+ struct cvmx_iob_ctl_status_s cn52xxp1;
+ struct cvmx_iob_ctl_status_s cn56xx;
+ struct cvmx_iob_ctl_status_s cn56xxp1;
+ struct cvmx_iob_ctl_status_s cn58xx;
+ struct cvmx_iob_ctl_status_s cn58xxp1;
+} cvmx_iob_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_dwb_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_dwb_pri_cnt_s cn38xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_dwb_pri_cnt_s cn52xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_dwb_pri_cnt_s cn56xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_dwb_pri_cnt_s cn58xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
+} cvmx_iob_dwb_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_fau_timeout_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t tout_enb:1;
+ uint64_t tout_val:12;
+#else
+ uint64_t tout_val:12;
+ uint64_t tout_enb:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_iob_fau_timeout_s cn30xx;
+ struct cvmx_iob_fau_timeout_s cn31xx;
+ struct cvmx_iob_fau_timeout_s cn38xx;
+ struct cvmx_iob_fau_timeout_s cn38xxp2;
+ struct cvmx_iob_fau_timeout_s cn50xx;
+ struct cvmx_iob_fau_timeout_s cn52xx;
+ struct cvmx_iob_fau_timeout_s cn52xxp1;
+ struct cvmx_iob_fau_timeout_s cn56xx;
+ struct cvmx_iob_fau_timeout_s cn56xxp1;
+ struct cvmx_iob_fau_timeout_s cn58xx;
+ struct cvmx_iob_fau_timeout_s cn58xxp1;
+} cvmx_iob_fau_timeout_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_i2c_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_i2c_pri_cnt_s cn38xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_i2c_pri_cnt_s cn52xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_i2c_pri_cnt_s cn56xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_i2c_pri_cnt_s cn58xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
+} cvmx_iob_i2c_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_inb_control_match_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t mask:8;
+ uint64_t opc:4;
+ uint64_t dst:9;
+ uint64_t src:8;
+#else
+ uint64_t src:8;
+ uint64_t dst:9;
+ uint64_t opc:4;
+ uint64_t mask:8;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_iob_inb_control_match_s cn30xx;
+ struct cvmx_iob_inb_control_match_s cn31xx;
+ struct cvmx_iob_inb_control_match_s cn38xx;
+ struct cvmx_iob_inb_control_match_s cn38xxp2;
+ struct cvmx_iob_inb_control_match_s cn50xx;
+ struct cvmx_iob_inb_control_match_s cn52xx;
+ struct cvmx_iob_inb_control_match_s cn52xxp1;
+ struct cvmx_iob_inb_control_match_s cn56xx;
+ struct cvmx_iob_inb_control_match_s cn56xxp1;
+ struct cvmx_iob_inb_control_match_s cn58xx;
+ struct cvmx_iob_inb_control_match_s cn58xxp1;
+} cvmx_iob_inb_control_match_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_inb_control_match_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t mask:8;
+ uint64_t opc:4;
+ uint64_t dst:9;
+ uint64_t src:8;
+#else
+ uint64_t src:8;
+ uint64_t dst:9;
+ uint64_t opc:4;
+ uint64_t mask:8;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_iob_inb_control_match_enb_s cn30xx;
+ struct cvmx_iob_inb_control_match_enb_s cn31xx;
+ struct cvmx_iob_inb_control_match_enb_s cn38xx;
+ struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
+ struct cvmx_iob_inb_control_match_enb_s cn50xx;
+ struct cvmx_iob_inb_control_match_enb_s cn52xx;
+ struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
+ struct cvmx_iob_inb_control_match_enb_s cn56xx;
+ struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
+ struct cvmx_iob_inb_control_match_enb_s cn58xx;
+ struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+} cvmx_iob_inb_control_match_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_inb_data_match_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_iob_inb_data_match_s cn30xx;
+ struct cvmx_iob_inb_data_match_s cn31xx;
+ struct cvmx_iob_inb_data_match_s cn38xx;
+ struct cvmx_iob_inb_data_match_s cn38xxp2;
+ struct cvmx_iob_inb_data_match_s cn50xx;
+ struct cvmx_iob_inb_data_match_s cn52xx;
+ struct cvmx_iob_inb_data_match_s cn52xxp1;
+ struct cvmx_iob_inb_data_match_s cn56xx;
+ struct cvmx_iob_inb_data_match_s cn56xxp1;
+ struct cvmx_iob_inb_data_match_s cn58xx;
+ struct cvmx_iob_inb_data_match_s cn58xxp1;
+} cvmx_iob_inb_data_match_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_inb_data_match_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_iob_inb_data_match_enb_s cn30xx;
+ struct cvmx_iob_inb_data_match_enb_s cn31xx;
+ struct cvmx_iob_inb_data_match_enb_s cn38xx;
+ struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
+ struct cvmx_iob_inb_data_match_enb_s cn50xx;
+ struct cvmx_iob_inb_data_match_enb_s cn52xx;
+ struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
+ struct cvmx_iob_inb_data_match_enb_s cn56xx;
+ struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
+ struct cvmx_iob_inb_data_match_enb_s cn58xx;
+ struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+} cvmx_iob_inb_data_match_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t p_dat:1;
+ uint64_t np_dat:1;
+ uint64_t p_eop:1;
+ uint64_t p_sop:1;
+ uint64_t np_eop:1;
+ uint64_t np_sop:1;
+#else
+ uint64_t np_sop:1;
+ uint64_t np_eop:1;
+ uint64_t p_sop:1;
+ uint64_t p_eop:1;
+ uint64_t np_dat:1;
+ uint64_t p_dat:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_iob_int_enb_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t p_eop:1;
+ uint64_t p_sop:1;
+ uint64_t np_eop:1;
+ uint64_t np_sop:1;
+#else
+ uint64_t np_sop:1;
+ uint64_t np_eop:1;
+ uint64_t p_sop:1;
+ uint64_t p_eop:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_iob_int_enb_cn30xx cn31xx;
+ struct cvmx_iob_int_enb_cn30xx cn38xx;
+ struct cvmx_iob_int_enb_cn30xx cn38xxp2;
+ struct cvmx_iob_int_enb_s cn50xx;
+ struct cvmx_iob_int_enb_s cn52xx;
+ struct cvmx_iob_int_enb_s cn52xxp1;
+ struct cvmx_iob_int_enb_s cn56xx;
+ struct cvmx_iob_int_enb_s cn56xxp1;
+ struct cvmx_iob_int_enb_s cn58xx;
+ struct cvmx_iob_int_enb_s cn58xxp1;
+} cvmx_iob_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t p_dat:1;
+ uint64_t np_dat:1;
+ uint64_t p_eop:1;
+ uint64_t p_sop:1;
+ uint64_t np_eop:1;
+ uint64_t np_sop:1;
+#else
+ uint64_t np_sop:1;
+ uint64_t np_eop:1;
+ uint64_t p_sop:1;
+ uint64_t p_eop:1;
+ uint64_t np_dat:1;
+ uint64_t p_dat:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_iob_int_sum_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t p_eop:1;
+ uint64_t p_sop:1;
+ uint64_t np_eop:1;
+ uint64_t np_sop:1;
+#else
+ uint64_t np_sop:1;
+ uint64_t np_eop:1;
+ uint64_t p_sop:1;
+ uint64_t p_eop:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_iob_int_sum_cn30xx cn31xx;
+ struct cvmx_iob_int_sum_cn30xx cn38xx;
+ struct cvmx_iob_int_sum_cn30xx cn38xxp2;
+ struct cvmx_iob_int_sum_s cn50xx;
+ struct cvmx_iob_int_sum_s cn52xx;
+ struct cvmx_iob_int_sum_s cn52xxp1;
+ struct cvmx_iob_int_sum_s cn56xx;
+ struct cvmx_iob_int_sum_s cn56xxp1;
+ struct cvmx_iob_int_sum_s cn58xx;
+ struct cvmx_iob_int_sum_s cn58xxp1;
+} cvmx_iob_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
+} cvmx_iob_n2c_l2c_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
+} cvmx_iob_n2c_rsp_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_com_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
+} cvmx_iob_outb_com_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_control_match_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_26_63:38;
+ uint64_t mask:8;
+ uint64_t eot:1;
+ uint64_t dst:8;
+ uint64_t src:9;
+#else
+ uint64_t src:9;
+ uint64_t dst:8;
+ uint64_t eot:1;
+ uint64_t mask:8;
+ uint64_t reserved_26_63:38;
+#endif
+ } s;
+ struct cvmx_iob_outb_control_match_s cn30xx;
+ struct cvmx_iob_outb_control_match_s cn31xx;
+ struct cvmx_iob_outb_control_match_s cn38xx;
+ struct cvmx_iob_outb_control_match_s cn38xxp2;
+ struct cvmx_iob_outb_control_match_s cn50xx;
+ struct cvmx_iob_outb_control_match_s cn52xx;
+ struct cvmx_iob_outb_control_match_s cn52xxp1;
+ struct cvmx_iob_outb_control_match_s cn56xx;
+ struct cvmx_iob_outb_control_match_s cn56xxp1;
+ struct cvmx_iob_outb_control_match_s cn58xx;
+ struct cvmx_iob_outb_control_match_s cn58xxp1;
+} cvmx_iob_outb_control_match_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_control_match_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_26_63:38;
+ uint64_t mask:8;
+ uint64_t eot:1;
+ uint64_t dst:8;
+ uint64_t src:9;
+#else
+ uint64_t src:9;
+ uint64_t dst:8;
+ uint64_t eot:1;
+ uint64_t mask:8;
+ uint64_t reserved_26_63:38;
+#endif
+ } s;
+ struct cvmx_iob_outb_control_match_enb_s cn30xx;
+ struct cvmx_iob_outb_control_match_enb_s cn31xx;
+ struct cvmx_iob_outb_control_match_enb_s cn38xx;
+ struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
+ struct cvmx_iob_outb_control_match_enb_s cn50xx;
+ struct cvmx_iob_outb_control_match_enb_s cn52xx;
+ struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
+ struct cvmx_iob_outb_control_match_enb_s cn56xx;
+ struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
+ struct cvmx_iob_outb_control_match_enb_s cn58xx;
+ struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+} cvmx_iob_outb_control_match_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_data_match_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_iob_outb_data_match_s cn30xx;
+ struct cvmx_iob_outb_data_match_s cn31xx;
+ struct cvmx_iob_outb_data_match_s cn38xx;
+ struct cvmx_iob_outb_data_match_s cn38xxp2;
+ struct cvmx_iob_outb_data_match_s cn50xx;
+ struct cvmx_iob_outb_data_match_s cn52xx;
+ struct cvmx_iob_outb_data_match_s cn52xxp1;
+ struct cvmx_iob_outb_data_match_s cn56xx;
+ struct cvmx_iob_outb_data_match_s cn56xxp1;
+ struct cvmx_iob_outb_data_match_s cn58xx;
+ struct cvmx_iob_outb_data_match_s cn58xxp1;
+} cvmx_iob_outb_data_match_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_data_match_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_iob_outb_data_match_enb_s cn30xx;
+ struct cvmx_iob_outb_data_match_enb_s cn31xx;
+ struct cvmx_iob_outb_data_match_enb_s cn38xx;
+ struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
+ struct cvmx_iob_outb_data_match_enb_s cn50xx;
+ struct cvmx_iob_outb_data_match_enb_s cn52xx;
+ struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
+ struct cvmx_iob_outb_data_match_enb_s cn56xx;
+ struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
+ struct cvmx_iob_outb_data_match_enb_s cn58xx;
+ struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+} cvmx_iob_outb_data_match_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_fpa_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
+} cvmx_iob_outb_fpa_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_outb_req_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
+} cvmx_iob_outb_req_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_p2c_req_pri_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt_enb:1;
+ uint64_t cnt_val:15;
+#else
+ uint64_t cnt_val:15;
+ uint64_t cnt_enb:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
+} cvmx_iob_p2c_req_pri_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_iob_pkt_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t port:6;
+#else
+ uint64_t port:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_iob_pkt_err_s cn30xx;
+ struct cvmx_iob_pkt_err_s cn31xx;
+ struct cvmx_iob_pkt_err_s cn38xx;
+ struct cvmx_iob_pkt_err_s cn38xxp2;
+ struct cvmx_iob_pkt_err_s cn50xx;
+ struct cvmx_iob_pkt_err_s cn52xx;
+ struct cvmx_iob_pkt_err_s cn52xxp1;
+ struct cvmx_iob_pkt_err_s cn56xx;
+ struct cvmx_iob_pkt_err_s cn56xxp1;
+ struct cvmx_iob_pkt_err_s cn58xx;
+ struct cvmx_iob_pkt_err_s cn58xxp1;
+} cvmx_iob_pkt_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_1st_mbuff_skip_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t skip_sz:6;
+#else
+ uint64_t skip_sz:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn38xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;
+ struct cvmx_ipd_1st_mbuff_skip_s cn50xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn52xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;
+ struct cvmx_ipd_1st_mbuff_skip_s cn56xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
+ struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
+} cvmx_ipd_1st_mbuff_skip_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_1st_next_ptr_back_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t back:4;
+#else
+ uint64_t back:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn38xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;
+ struct cvmx_ipd_1st_next_ptr_back_s cn50xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn52xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;
+ struct cvmx_ipd_1st_next_ptr_back_s cn56xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
+ struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
+} cvmx_ipd_1st_next_ptr_back_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_2nd_next_ptr_back_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t back:4;
+#else
+ uint64_t back:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn38xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn50xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn52xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn56xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
+} cvmx_ipd_2nd_next_ptr_back_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t csr_mem:1;
+ uint64_t csr_ncmd:1;
+ uint64_t pwq_wqed:1;
+ uint64_t pwq_wp1:1;
+ uint64_t pwq_pow:1;
+ uint64_t ipq_pbe1:1;
+ uint64_t ipq_pbe0:1;
+ uint64_t pbm3:1;
+ uint64_t pbm2:1;
+ uint64_t pbm1:1;
+ uint64_t pbm0:1;
+ uint64_t pbm_word:1;
+ uint64_t pwq1:1;
+ uint64_t pwq0:1;
+ uint64_t prc_off:1;
+ uint64_t ipd_old:1;
+ uint64_t ipd_new:1;
+ uint64_t pwp:1;
+#else
+ uint64_t pwp:1;
+ uint64_t ipd_new:1;
+ uint64_t ipd_old:1;
+ uint64_t prc_off:1;
+ uint64_t pwq0:1;
+ uint64_t pwq1:1;
+ uint64_t pbm_word:1;
+ uint64_t pbm0:1;
+ uint64_t pbm1:1;
+ uint64_t pbm2:1;
+ uint64_t pbm3:1;
+ uint64_t ipq_pbe0:1;
+ uint64_t ipq_pbe1:1;
+ uint64_t pwq_pow:1;
+ uint64_t pwq_wp1:1;
+ uint64_t pwq_wqed:1;
+ uint64_t csr_ncmd:1;
+ uint64_t csr_mem:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_ipd_bist_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t pwq_wqed:1;
+ uint64_t pwq_wp1:1;
+ uint64_t pwq_pow:1;
+ uint64_t ipq_pbe1:1;
+ uint64_t ipq_pbe0:1;
+ uint64_t pbm3:1;
+ uint64_t pbm2:1;
+ uint64_t pbm1:1;
+ uint64_t pbm0:1;
+ uint64_t pbm_word:1;
+ uint64_t pwq1:1;
+ uint64_t pwq0:1;
+ uint64_t prc_off:1;
+ uint64_t ipd_old:1;
+ uint64_t ipd_new:1;
+ uint64_t pwp:1;
+#else
+ uint64_t pwp:1;
+ uint64_t ipd_new:1;
+ uint64_t ipd_old:1;
+ uint64_t prc_off:1;
+ uint64_t pwq0:1;
+ uint64_t pwq1:1;
+ uint64_t pbm_word:1;
+ uint64_t pbm0:1;
+ uint64_t pbm1:1;
+ uint64_t pbm2:1;
+ uint64_t pbm3:1;
+ uint64_t ipq_pbe0:1;
+ uint64_t ipq_pbe1:1;
+ uint64_t pwq_pow:1;
+ uint64_t pwq_wp1:1;
+ uint64_t pwq_wqed:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_bist_status_cn30xx cn31xx;
+ struct cvmx_ipd_bist_status_cn30xx cn38xx;
+ struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
+ struct cvmx_ipd_bist_status_cn30xx cn50xx;
+ struct cvmx_ipd_bist_status_s cn52xx;
+ struct cvmx_ipd_bist_status_s cn52xxp1;
+ struct cvmx_ipd_bist_status_s cn56xx;
+ struct cvmx_ipd_bist_status_s cn56xxp1;
+ struct cvmx_ipd_bist_status_cn30xx cn58xx;
+ struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
+} cvmx_ipd_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_bp_prt_red_end_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t prt_enb:40;
+#else
+ uint64_t prt_enb:40;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t prt_enb:36;
+#else
+ uint64_t prt_enb:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
+ struct cvmx_ipd_bp_prt_red_end_s cn52xx;
+ struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
+ struct cvmx_ipd_bp_prt_red_end_s cn56xx;
+ struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
+ struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+} cvmx_ipd_bp_prt_red_end_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_clk_count_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t clk_cnt:64;
+#else
+ uint64_t clk_cnt:64;
+#endif
+ } s;
+ struct cvmx_ipd_clk_count_s cn30xx;
+ struct cvmx_ipd_clk_count_s cn31xx;
+ struct cvmx_ipd_clk_count_s cn38xx;
+ struct cvmx_ipd_clk_count_s cn38xxp2;
+ struct cvmx_ipd_clk_count_s cn50xx;
+ struct cvmx_ipd_clk_count_s cn52xx;
+ struct cvmx_ipd_clk_count_s cn52xxp1;
+ struct cvmx_ipd_clk_count_s cn56xx;
+ struct cvmx_ipd_clk_count_s cn56xxp1;
+ struct cvmx_ipd_clk_count_s cn58xx;
+ struct cvmx_ipd_clk_count_s cn58xxp1;
+} cvmx_ipd_clk_count_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t no_wptr:1;
+ uint64_t pq_apkt:1;
+ uint64_t pq_nabuf:1;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t ipd_en:1;
+#else
+ uint64_t ipd_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t pbp_en:1;
+ uint64_t wqe_lend:1;
+ uint64_t pkt_lend:1;
+ uint64_t naddbuf:1;
+ uint64_t addpkt:1;
+ uint64_t reset:1;
+ uint64_t len_m8:1;
+ uint64_t pkt_off:1;
+ uint64_t ipd_full:1;
+ uint64_t pq_nabuf:1;
+ uint64_t pq_apkt:1;
+ uint64_t no_wptr:1;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_ipd_ctl_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t ipd_en:1;
+#else
+ uint64_t ipd_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t pbp_en:1;
+ uint64_t wqe_lend:1;
+ uint64_t pkt_lend:1;
+ uint64_t naddbuf:1;
+ uint64_t addpkt:1;
+ uint64_t reset:1;
+ uint64_t len_m8:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_ctl_status_cn30xx cn31xx;
+ struct cvmx_ipd_ctl_status_cn30xx cn38xx;
+ struct cvmx_ipd_ctl_status_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t ipd_en:1;
+#else
+ uint64_t ipd_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t pbp_en:1;
+ uint64_t wqe_lend:1;
+ uint64_t pkt_lend:1;
+ uint64_t naddbuf:1;
+ uint64_t addpkt:1;
+ uint64_t reset:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn38xxp2;
+ struct cvmx_ipd_ctl_status_s cn50xx;
+ struct cvmx_ipd_ctl_status_s cn52xx;
+ struct cvmx_ipd_ctl_status_s cn52xxp1;
+ struct cvmx_ipd_ctl_status_s cn56xx;
+ struct cvmx_ipd_ctl_status_s cn56xxp1;
+ struct cvmx_ipd_ctl_status_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t ipd_en:1;
+#else
+ uint64_t ipd_en:1;
+ cvmx_ipd_mode_t opc_mode:2;
+ uint64_t pbp_en:1;
+ uint64_t wqe_lend:1;
+ uint64_t pkt_lend:1;
+ uint64_t naddbuf:1;
+ uint64_t addpkt:1;
+ uint64_t reset:1;
+ uint64_t len_m8:1;
+ uint64_t pkt_off:1;
+ uint64_t ipd_full:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn58xx;
+ struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
+} cvmx_ipd_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t pq_sub:1;
+ uint64_t pq_add:1;
+ uint64_t bc_ovr:1;
+ uint64_t d_coll:1;
+ uint64_t c_coll:1;
+ uint64_t cc_ovr:1;
+ uint64_t dc_ovr:1;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t dc_ovr:1;
+ uint64_t cc_ovr:1;
+ uint64_t c_coll:1;
+ uint64_t d_coll:1;
+ uint64_t bc_ovr:1;
+ uint64_t pq_add:1;
+ uint64_t pq_sub:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_ipd_int_enb_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_int_enb_cn30xx cn31xx;
+ struct cvmx_ipd_int_enb_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t bc_ovr:1;
+ uint64_t d_coll:1;
+ uint64_t c_coll:1;
+ uint64_t cc_ovr:1;
+ uint64_t dc_ovr:1;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t dc_ovr:1;
+ uint64_t cc_ovr:1;
+ uint64_t c_coll:1;
+ uint64_t d_coll:1;
+ uint64_t bc_ovr:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn38xx;
+ struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
+ struct cvmx_ipd_int_enb_cn38xx cn50xx;
+ struct cvmx_ipd_int_enb_s cn52xx;
+ struct cvmx_ipd_int_enb_s cn52xxp1;
+ struct cvmx_ipd_int_enb_s cn56xx;
+ struct cvmx_ipd_int_enb_s cn56xxp1;
+ struct cvmx_ipd_int_enb_cn38xx cn58xx;
+ struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
+} cvmx_ipd_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t pq_sub:1;
+ uint64_t pq_add:1;
+ uint64_t bc_ovr:1;
+ uint64_t d_coll:1;
+ uint64_t c_coll:1;
+ uint64_t cc_ovr:1;
+ uint64_t dc_ovr:1;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t dc_ovr:1;
+ uint64_t cc_ovr:1;
+ uint64_t c_coll:1;
+ uint64_t d_coll:1;
+ uint64_t bc_ovr:1;
+ uint64_t pq_add:1;
+ uint64_t pq_sub:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_ipd_int_sum_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_int_sum_cn30xx cn31xx;
+ struct cvmx_ipd_int_sum_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t bc_ovr:1;
+ uint64_t d_coll:1;
+ uint64_t c_coll:1;
+ uint64_t cc_ovr:1;
+ uint64_t dc_ovr:1;
+ uint64_t bp_sub:1;
+ uint64_t prc_par3:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par0:1;
+#else
+ uint64_t prc_par0:1;
+ uint64_t prc_par1:1;
+ uint64_t prc_par2:1;
+ uint64_t prc_par3:1;
+ uint64_t bp_sub:1;
+ uint64_t dc_ovr:1;
+ uint64_t cc_ovr:1;
+ uint64_t c_coll:1;
+ uint64_t d_coll:1;
+ uint64_t bc_ovr:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn38xx;
+ struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
+ struct cvmx_ipd_int_sum_cn38xx cn50xx;
+ struct cvmx_ipd_int_sum_s cn52xx;
+ struct cvmx_ipd_int_sum_s cn52xxp1;
+ struct cvmx_ipd_int_sum_s cn56xx;
+ struct cvmx_ipd_int_sum_s cn56xxp1;
+ struct cvmx_ipd_int_sum_cn38xx cn58xx;
+ struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
+} cvmx_ipd_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_not_1st_mbuff_skip_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t skip_sz:6;
+#else
+ uint64_t skip_sz:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+} cvmx_ipd_not_1st_mbuff_skip_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_packet_mbuff_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t mb_size:12;
+#else
+ uint64_t mb_size:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_ipd_packet_mbuff_size_s cn30xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn31xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn38xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn38xxp2;
+ struct cvmx_ipd_packet_mbuff_size_s cn50xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn52xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn52xxp1;
+ struct cvmx_ipd_packet_mbuff_size_s cn56xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
+ struct cvmx_ipd_packet_mbuff_size_s cn58xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
+} cvmx_ipd_packet_mbuff_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_pkt_ptr_valid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t ptr:29;
+#else
+ uint64_t ptr:29;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn38xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn50xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn52xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;
+ struct cvmx_ipd_pkt_ptr_valid_s cn56xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
+ struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
+} cvmx_ipd_pkt_ptr_valid_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_portx_bp_page_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t bp_enb:1;
+ uint64_t page_cnt:17;
+#else
+ uint64_t page_cnt:17;
+ uint64_t bp_enb:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn38xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn50xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn52xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn56xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
+} cvmx_ipd_portx_bp_page_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_portx_bp_page_cnt2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t bp_enb:1;
+ uint64_t page_cnt:17;
+#else
+ uint64_t page_cnt:17;
+ uint64_t bp_enb:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+} cvmx_ipd_portx_bp_page_cnt2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_port_bp_counters2_pairx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_25_63:39;
+ uint64_t cnt_val:25;
+#else
+ uint64_t cnt_val:25;
+ uint64_t reserved_25_63:39;
+#endif
+ } s;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+} cvmx_ipd_port_bp_counters2_pairx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_port_bp_counters_pairx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_25_63:39;
+ uint64_t cnt_val:25;
+#else
+ uint64_t cnt_val:25;
+ uint64_t reserved_25_63:39;
+#endif
+ } s;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+} cvmx_ipd_port_bp_counters_pairx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_port_qos_x_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t wmark:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t wmark:32;
+#endif
+ } s;
+ struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
+ struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
+ struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
+ struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
+} cvmx_ipd_port_qos_x_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_port_qos_intx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t intr:64;
+#else
+ uint64_t intr:64;
+#endif
+ } s;
+ struct cvmx_ipd_port_qos_intx_s cn52xx;
+ struct cvmx_ipd_port_qos_intx_s cn52xxp1;
+ struct cvmx_ipd_port_qos_intx_s cn56xx;
+ struct cvmx_ipd_port_qos_intx_s cn56xxp1;
+} cvmx_ipd_port_qos_intx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_port_qos_int_enbx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t enb:64;
+#else
+ uint64_t enb:64;
+#endif
+ } s;
+ struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
+ struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
+ struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
+ struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
+} cvmx_ipd_port_qos_int_enbx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t max_pkt:3;
+ uint64_t praddr:3;
+ uint64_t ptr:29;
+ uint64_t cena:1;
+ uint64_t raddr:3;
+#else
+ uint64_t raddr:3;
+ uint64_t cena:1;
+ uint64_t ptr:29;
+ uint64_t praddr:3;
+ uint64_t max_pkt:3;
+ uint64_t reserved_39_63:25;
+#endif
+ } s;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+} cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t max_pkt:7;
+ uint64_t ptr:29;
+ uint64_t cena:1;
+ uint64_t raddr:7;
+#else
+ uint64_t raddr:7;
+ uint64_t cena:1;
+ uint64_t ptr:29;
+ uint64_t max_pkt:7;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+} cvmx_ipd_prc_port_ptr_fifo_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_ptr_count_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t pktv_cnt:1;
+ uint64_t wqev_cnt:1;
+ uint64_t pfif_cnt:3;
+ uint64_t pkt_pcnt:7;
+ uint64_t wqe_pcnt:7;
+#else
+ uint64_t wqe_pcnt:7;
+ uint64_t pkt_pcnt:7;
+ uint64_t pfif_cnt:3;
+ uint64_t wqev_cnt:1;
+ uint64_t pktv_cnt:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_ipd_ptr_count_s cn30xx;
+ struct cvmx_ipd_ptr_count_s cn31xx;
+ struct cvmx_ipd_ptr_count_s cn38xx;
+ struct cvmx_ipd_ptr_count_s cn38xxp2;
+ struct cvmx_ipd_ptr_count_s cn50xx;
+ struct cvmx_ipd_ptr_count_s cn52xx;
+ struct cvmx_ipd_ptr_count_s cn52xxp1;
+ struct cvmx_ipd_ptr_count_s cn56xx;
+ struct cvmx_ipd_ptr_count_s cn56xxp1;
+ struct cvmx_ipd_ptr_count_s cn58xx;
+ struct cvmx_ipd_ptr_count_s cn58xxp1;
+} cvmx_ipd_ptr_count_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_61_63:3;
+ uint64_t max_cnts:7;
+ uint64_t wraddr:8;
+ uint64_t praddr:8;
+ uint64_t ptr:29;
+ uint64_t cena:1;
+ uint64_t raddr:8;
+#else
+ uint64_t raddr:8;
+ uint64_t cena:1;
+ uint64_t ptr:29;
+ uint64_t praddr:8;
+ uint64_t wraddr:8;
+ uint64_t max_cnts:7;
+ uint64_t reserved_61_63:3;
+#endif
+ } s;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
+} cvmx_ipd_pwp_ptr_fifo_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_qosx_red_marks_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t drop:32;
+ uint64_t pass:32;
+#else
+ uint64_t pass:32;
+ uint64_t drop:32;
+#endif
+ } s;
+ struct cvmx_ipd_qosx_red_marks_s cn30xx;
+ struct cvmx_ipd_qosx_red_marks_s cn31xx;
+ struct cvmx_ipd_qosx_red_marks_s cn38xx;
+ struct cvmx_ipd_qosx_red_marks_s cn38xxp2;
+ struct cvmx_ipd_qosx_red_marks_s cn50xx;
+ struct cvmx_ipd_qosx_red_marks_s cn52xx;
+ struct cvmx_ipd_qosx_red_marks_s cn52xxp1;
+ struct cvmx_ipd_qosx_red_marks_s cn56xx;
+ struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
+ struct cvmx_ipd_qosx_red_marks_s cn58xx;
+ struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
+} cvmx_ipd_qosx_red_marks_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_que0_free_page_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t q0_pcnt:32;
+#else
+ uint64_t q0_pcnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
+ struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
+ struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
+ struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+} cvmx_ipd_que0_free_page_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_red_port_enable_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t prb_dly:14;
+ uint64_t avg_dly:14;
+ uint64_t prt_enb:36;
+#else
+ uint64_t prt_enb:36;
+ uint64_t avg_dly:14;
+ uint64_t prb_dly:14;
+#endif
+ } s;
+ struct cvmx_ipd_red_port_enable_s cn30xx;
+ struct cvmx_ipd_red_port_enable_s cn31xx;
+ struct cvmx_ipd_red_port_enable_s cn38xx;
+ struct cvmx_ipd_red_port_enable_s cn38xxp2;
+ struct cvmx_ipd_red_port_enable_s cn50xx;
+ struct cvmx_ipd_red_port_enable_s cn52xx;
+ struct cvmx_ipd_red_port_enable_s cn52xxp1;
+ struct cvmx_ipd_red_port_enable_s cn56xx;
+ struct cvmx_ipd_red_port_enable_s cn56xxp1;
+ struct cvmx_ipd_red_port_enable_s cn58xx;
+ struct cvmx_ipd_red_port_enable_s cn58xxp1;
+} cvmx_ipd_red_port_enable_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_red_port_enable2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t prt_enb:4;
+#else
+ uint64_t prt_enb:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_ipd_red_port_enable2_s cn52xx;
+ struct cvmx_ipd_red_port_enable2_s cn52xxp1;
+ struct cvmx_ipd_red_port_enable2_s cn56xx;
+ struct cvmx_ipd_red_port_enable2_s cn56xxp1;
+} cvmx_ipd_red_port_enable2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_red_quex_param_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t use_pcnt:1;
+ uint64_t new_con:8;
+ uint64_t avg_con:8;
+ uint64_t prb_con:32;
+#else
+ uint64_t prb_con:32;
+ uint64_t avg_con:8;
+ uint64_t new_con:8;
+ uint64_t use_pcnt:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_ipd_red_quex_param_s cn30xx;
+ struct cvmx_ipd_red_quex_param_s cn31xx;
+ struct cvmx_ipd_red_quex_param_s cn38xx;
+ struct cvmx_ipd_red_quex_param_s cn38xxp2;
+ struct cvmx_ipd_red_quex_param_s cn50xx;
+ struct cvmx_ipd_red_quex_param_s cn52xx;
+ struct cvmx_ipd_red_quex_param_s cn52xxp1;
+ struct cvmx_ipd_red_quex_param_s cn56xx;
+ struct cvmx_ipd_red_quex_param_s cn56xxp1;
+ struct cvmx_ipd_red_quex_param_s cn58xx;
+ struct cvmx_ipd_red_quex_param_s cn58xxp1;
+} cvmx_ipd_red_quex_param_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t port:6;
+ uint64_t page_cnt:25;
+#else
+ uint64_t page_cnt:25;
+ uint64_t port:6;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+} cvmx_ipd_sub_port_bp_page_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_sub_port_fcs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t port_bit2:4;
+ uint64_t reserved_32_35:4;
+ uint64_t port_bit:32;
+#else
+ uint64_t port_bit:32;
+ uint64_t reserved_32_35:4;
+ uint64_t port_bit2:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_ipd_sub_port_fcs_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t port_bit:3;
+#else
+ uint64_t port_bit:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
+ struct cvmx_ipd_sub_port_fcs_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t port_bit:32;
+#else
+ uint64_t port_bit:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
+ struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
+ struct cvmx_ipd_sub_port_fcs_s cn52xx;
+ struct cvmx_ipd_sub_port_fcs_s cn52xxp1;
+ struct cvmx_ipd_sub_port_fcs_s cn56xx;
+ struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
+ struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
+ struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
+} cvmx_ipd_sub_port_fcs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_sub_port_qos_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_41_63:23;
+ uint64_t port_qos:9;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t port_qos:9;
+ uint64_t reserved_41_63:23;
+#endif
+ } s;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
+} cvmx_ipd_sub_port_qos_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_wqe_fpa_queue_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t wqe_pool:3;
+#else
+ uint64_t wqe_pool:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn38xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;
+ struct cvmx_ipd_wqe_fpa_queue_s cn50xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn52xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;
+ struct cvmx_ipd_wqe_fpa_queue_s cn56xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
+ struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
+} cvmx_ipd_wqe_fpa_queue_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ipd_wqe_ptr_valid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t ptr:29;
+#else
+ uint64_t ptr:29;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn38xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn50xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn52xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;
+ struct cvmx_ipd_wqe_ptr_valid_s cn56xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
+ struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
+} cvmx_ipd_wqe_ptr_valid_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_key_bist_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t rrc:1;
+ uint64_t mem1:1;
+ uint64_t mem0:1;
+#else
+ uint64_t mem0:1;
+ uint64_t mem1:1;
+ uint64_t rrc:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_key_bist_reg_s cn38xx;
+ struct cvmx_key_bist_reg_s cn38xxp2;
+ struct cvmx_key_bist_reg_s cn56xx;
+ struct cvmx_key_bist_reg_s cn56xxp1;
+ struct cvmx_key_bist_reg_s cn58xx;
+ struct cvmx_key_bist_reg_s cn58xxp1;
+} cvmx_key_bist_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_key_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t mem1_err:7;
+ uint64_t mem0_err:7;
+#else
+ uint64_t mem0_err:7;
+ uint64_t mem1_err:7;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_key_ctl_status_s cn38xx;
+ struct cvmx_key_ctl_status_s cn38xxp2;
+ struct cvmx_key_ctl_status_s cn56xx;
+ struct cvmx_key_ctl_status_s cn56xxp1;
+ struct cvmx_key_ctl_status_s cn58xx;
+ struct cvmx_key_ctl_status_s cn58xxp1;
+} cvmx_key_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_key_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ked1_dbe:1;
+ uint64_t ked1_sbe:1;
+ uint64_t ked0_dbe:1;
+ uint64_t ked0_sbe:1;
+#else
+ uint64_t ked0_sbe:1;
+ uint64_t ked0_dbe:1;
+ uint64_t ked1_sbe:1;
+ uint64_t ked1_dbe:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_key_int_enb_s cn38xx;
+ struct cvmx_key_int_enb_s cn38xxp2;
+ struct cvmx_key_int_enb_s cn56xx;
+ struct cvmx_key_int_enb_s cn56xxp1;
+ struct cvmx_key_int_enb_s cn58xx;
+ struct cvmx_key_int_enb_s cn58xxp1;
+} cvmx_key_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_key_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ked1_dbe:1;
+ uint64_t ked1_sbe:1;
+ uint64_t ked0_dbe:1;
+ uint64_t ked0_sbe:1;
+#else
+ uint64_t ked0_sbe:1;
+ uint64_t ked0_dbe:1;
+ uint64_t ked1_sbe:1;
+ uint64_t ked1_dbe:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_key_int_sum_s cn38xx;
+ struct cvmx_key_int_sum_s cn38xxp2;
+ struct cvmx_key_int_sum_s cn56xx;
+ struct cvmx_key_int_sum_s cn56xxp1;
+ struct cvmx_key_int_sum_s cn58xx;
+ struct cvmx_key_int_sum_s cn58xxp1;
+} cvmx_key_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_bst0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t dtbnk:1;
+ uint64_t wlb_msk:4;
+ uint64_t dtcnt:13;
+ uint64_t dt:1;
+ uint64_t stin_msk:1;
+ uint64_t wlb_dat:4;
+#else
+ uint64_t wlb_dat:4;
+ uint64_t stin_msk:1;
+ uint64_t dt:1;
+ uint64_t dtcnt:13;
+ uint64_t wlb_msk:4;
+ uint64_t dtbnk:1;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_l2c_bst0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t wlb_msk:4;
+ uint64_t reserved_15_18:4;
+ uint64_t dtcnt:9;
+ uint64_t dt:1;
+ uint64_t reserved_4_4:1;
+ uint64_t wlb_dat:4;
+#else
+ uint64_t wlb_dat:4;
+ uint64_t reserved_4_4:1;
+ uint64_t dt:1;
+ uint64_t dtcnt:9;
+ uint64_t reserved_15_18:4;
+ uint64_t wlb_msk:4;
+ uint64_t reserved_23_63:41;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_bst0_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t wlb_msk:4;
+ uint64_t reserved_16_18:3;
+ uint64_t dtcnt:10;
+ uint64_t dt:1;
+ uint64_t stin_msk:1;
+ uint64_t wlb_dat:4;
+#else
+ uint64_t wlb_dat:4;
+ uint64_t stin_msk:1;
+ uint64_t dt:1;
+ uint64_t dtcnt:10;
+ uint64_t reserved_16_18:3;
+ uint64_t wlb_msk:4;
+ uint64_t reserved_23_63:41;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_bst0_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t dtcnt:13;
+ uint64_t dt:1;
+ uint64_t stin_msk:1;
+ uint64_t wlb_dat:4;
+#else
+ uint64_t wlb_dat:4;
+ uint64_t stin_msk:1;
+ uint64_t dt:1;
+ uint64_t dtcnt:13;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn38xx;
+ struct cvmx_l2c_bst0_cn38xx cn38xxp2;
+ struct cvmx_l2c_bst0_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t dtbnk:1;
+ uint64_t wlb_msk:4;
+ uint64_t reserved_16_18:3;
+ uint64_t dtcnt:10;
+ uint64_t dt:1;
+ uint64_t stin_msk:1;
+ uint64_t wlb_dat:4;
+#else
+ uint64_t wlb_dat:4;
+ uint64_t stin_msk:1;
+ uint64_t dt:1;
+ uint64_t dtcnt:10;
+ uint64_t reserved_16_18:3;
+ uint64_t wlb_msk:4;
+ uint64_t dtbnk:1;
+ uint64_t reserved_24_63:40;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_bst0_cn50xx cn52xx;
+ struct cvmx_l2c_bst0_cn50xx cn52xxp1;
+ struct cvmx_l2c_bst0_s cn56xx;
+ struct cvmx_l2c_bst0_s cn56xxp1;
+ struct cvmx_l2c_bst0_s cn58xx;
+ struct cvmx_l2c_bst0_s cn58xxp1;
+} cvmx_l2c_bst0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_bst1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t l2t:9;
+#else
+ uint64_t l2t:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_l2c_bst1_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t vwdf:4;
+ uint64_t lrf:2;
+ uint64_t vab_vwcf:1;
+ uint64_t reserved_5_8:4;
+ uint64_t l2t:5;
+#else
+ uint64_t l2t:5;
+ uint64_t reserved_5_8:4;
+ uint64_t vab_vwcf:1;
+ uint64_t lrf:2;
+ uint64_t vwdf:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_bst1_cn30xx cn31xx;
+ struct cvmx_l2c_bst1_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t vwdf:4;
+ uint64_t lrf:2;
+ uint64_t vab_vwcf:1;
+ uint64_t l2t:9;
+#else
+ uint64_t l2t:9;
+ uint64_t vab_vwcf:1;
+ uint64_t lrf:2;
+ uint64_t vwdf:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_l2c_bst1_cn38xx cn38xxp2;
+ struct cvmx_l2c_bst1_cn38xx cn50xx;
+ struct cvmx_l2c_bst1_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t plc2:1;
+ uint64_t plc1:1;
+ uint64_t plc0:1;
+ uint64_t vwdf:4;
+ uint64_t reserved_11_11:1;
+ uint64_t ilc:1;
+ uint64_t vab_vwcf:1;
+ uint64_t l2t:9;
+#else
+ uint64_t l2t:9;
+ uint64_t vab_vwcf:1;
+ uint64_t ilc:1;
+ uint64_t reserved_11_11:1;
+ uint64_t vwdf:4;
+ uint64_t plc0:1;
+ uint64_t plc1:1;
+ uint64_t plc2:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } cn52xx;
+ struct cvmx_l2c_bst1_cn52xx cn52xxp1;
+ struct cvmx_l2c_bst1_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t plc2:1;
+ uint64_t plc1:1;
+ uint64_t plc0:1;
+ uint64_t ilc:1;
+ uint64_t vwdf1:4;
+ uint64_t vwdf0:4;
+ uint64_t vab_vwcf1:1;
+ uint64_t reserved_10_10:1;
+ uint64_t vab_vwcf0:1;
+ uint64_t l2t:9;
+#else
+ uint64_t l2t:9;
+ uint64_t vab_vwcf0:1;
+ uint64_t reserved_10_10:1;
+ uint64_t vab_vwcf1:1;
+ uint64_t vwdf0:4;
+ uint64_t vwdf1:4;
+ uint64_t ilc:1;
+ uint64_t plc0:1;
+ uint64_t plc1:1;
+ uint64_t plc2:1;
+ uint64_t reserved_24_63:40;
+#endif
+ } cn56xx;
+ struct cvmx_l2c_bst1_cn56xx cn56xxp1;
+ struct cvmx_l2c_bst1_cn38xx cn58xx;
+ struct cvmx_l2c_bst1_cn38xx cn58xxp1;
+} cvmx_l2c_bst1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_bst2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mrb:4;
+ uint64_t reserved_4_11:8;
+ uint64_t ipcbst:1;
+ uint64_t picbst:1;
+ uint64_t xrdmsk:1;
+ uint64_t xrddat:1;
+#else
+ uint64_t xrddat:1;
+ uint64_t xrdmsk:1;
+ uint64_t picbst:1;
+ uint64_t ipcbst:1;
+ uint64_t reserved_4_11:8;
+ uint64_t mrb:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_l2c_bst2_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mrb:4;
+ uint64_t rmdf:4;
+ uint64_t reserved_4_7:4;
+ uint64_t ipcbst:1;
+ uint64_t reserved_2_2:1;
+ uint64_t xrdmsk:1;
+ uint64_t xrddat:1;
+#else
+ uint64_t xrddat:1;
+ uint64_t xrdmsk:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ipcbst:1;
+ uint64_t reserved_4_7:4;
+ uint64_t rmdf:4;
+ uint64_t mrb:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_bst2_cn30xx cn31xx;
+ struct cvmx_l2c_bst2_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mrb:4;
+ uint64_t rmdf:4;
+ uint64_t rhdf:4;
+ uint64_t ipcbst:1;
+ uint64_t picbst:1;
+ uint64_t xrdmsk:1;
+ uint64_t xrddat:1;
+#else
+ uint64_t xrddat:1;
+ uint64_t xrdmsk:1;
+ uint64_t picbst:1;
+ uint64_t ipcbst:1;
+ uint64_t rhdf:4;
+ uint64_t rmdf:4;
+ uint64_t mrb:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_l2c_bst2_cn38xx cn38xxp2;
+ struct cvmx_l2c_bst2_cn30xx cn50xx;
+ struct cvmx_l2c_bst2_cn30xx cn52xx;
+ struct cvmx_l2c_bst2_cn30xx cn52xxp1;
+ struct cvmx_l2c_bst2_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mrb:4;
+ uint64_t rmdb:4;
+ uint64_t rhdb:4;
+ uint64_t ipcbst:1;
+ uint64_t picbst:1;
+ uint64_t xrdmsk:1;
+ uint64_t xrddat:1;
+#else
+ uint64_t xrddat:1;
+ uint64_t xrdmsk:1;
+ uint64_t picbst:1;
+ uint64_t ipcbst:1;
+ uint64_t rhdb:4;
+ uint64_t rmdb:4;
+ uint64_t mrb:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn56xx;
+ struct cvmx_l2c_bst2_cn56xx cn56xxp1;
+ struct cvmx_l2c_bst2_cn56xx cn58xx;
+ struct cvmx_l2c_bst2_cn56xx cn58xxp1;
+} cvmx_l2c_bst2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t bstrun:1;
+ uint64_t lbist:1;
+ uint64_t xor_bank:1;
+ uint64_t dpres1:1;
+ uint64_t dpres0:1;
+ uint64_t dfill_dis:1;
+ uint64_t fpexp:4;
+ uint64_t fpempty:1;
+ uint64_t fpen:1;
+ uint64_t idxalias:1;
+ uint64_t mwf_crd:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t lrf_arb_mode:1;
+#else
+ uint64_t lrf_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t rsp_arb_mode:1;
+ uint64_t mwf_crd:4;
+ uint64_t idxalias:1;
+ uint64_t fpen:1;
+ uint64_t fpempty:1;
+ uint64_t fpexp:4;
+ uint64_t dfill_dis:1;
+ uint64_t dpres0:1;
+ uint64_t dpres1:1;
+ uint64_t xor_bank:1;
+ uint64_t lbist:1;
+ uint64_t bstrun:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_l2c_cfg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t fpexp:4;
+ uint64_t fpempty:1;
+ uint64_t fpen:1;
+ uint64_t idxalias:1;
+ uint64_t mwf_crd:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t lrf_arb_mode:1;
+#else
+ uint64_t lrf_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t rsp_arb_mode:1;
+ uint64_t mwf_crd:4;
+ uint64_t idxalias:1;
+ uint64_t fpen:1;
+ uint64_t fpempty:1;
+ uint64_t fpexp:4;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_cfg_cn30xx cn31xx;
+ struct cvmx_l2c_cfg_cn30xx cn38xx;
+ struct cvmx_l2c_cfg_cn30xx cn38xxp2;
+ struct cvmx_l2c_cfg_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t bstrun:1;
+ uint64_t lbist:1;
+ uint64_t reserved_14_17:4;
+ uint64_t fpexp:4;
+ uint64_t fpempty:1;
+ uint64_t fpen:1;
+ uint64_t idxalias:1;
+ uint64_t mwf_crd:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t lrf_arb_mode:1;
+#else
+ uint64_t lrf_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t rsp_arb_mode:1;
+ uint64_t mwf_crd:4;
+ uint64_t idxalias:1;
+ uint64_t fpen:1;
+ uint64_t fpempty:1;
+ uint64_t fpexp:4;
+ uint64_t reserved_14_17:4;
+ uint64_t lbist:1;
+ uint64_t bstrun:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_cfg_cn50xx cn52xx;
+ struct cvmx_l2c_cfg_cn50xx cn52xxp1;
+ struct cvmx_l2c_cfg_s cn56xx;
+ struct cvmx_l2c_cfg_s cn56xxp1;
+ struct cvmx_l2c_cfg_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t bstrun:1;
+ uint64_t lbist:1;
+ uint64_t reserved_15_17:3;
+ uint64_t dfill_dis:1;
+ uint64_t fpexp:4;
+ uint64_t fpempty:1;
+ uint64_t fpen:1;
+ uint64_t idxalias:1;
+ uint64_t mwf_crd:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t lrf_arb_mode:1;
+#else
+ uint64_t lrf_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t rsp_arb_mode:1;
+ uint64_t mwf_crd:4;
+ uint64_t idxalias:1;
+ uint64_t fpen:1;
+ uint64_t fpempty:1;
+ uint64_t fpexp:4;
+ uint64_t dfill_dis:1;
+ uint64_t reserved_15_17:3;
+ uint64_t lbist:1;
+ uint64_t bstrun:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn58xx;
+ struct cvmx_l2c_cfg_cn58xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t dfill_dis:1;
+ uint64_t fpexp:4;
+ uint64_t fpempty:1;
+ uint64_t fpen:1;
+ uint64_t idxalias:1;
+ uint64_t mwf_crd:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t lrf_arb_mode:1;
+#else
+ uint64_t lrf_arb_mode:1;
+ uint64_t rfb_arb_mode:1;
+ uint64_t rsp_arb_mode:1;
+ uint64_t mwf_crd:4;
+ uint64_t idxalias:1;
+ uint64_t fpen:1;
+ uint64_t fpempty:1;
+ uint64_t fpexp:4;
+ uint64_t dfill_dis:1;
+ uint64_t reserved_15_63:49;
+#endif
+ } cn58xxp1;
+} cvmx_l2c_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t lfb_enum:4;
+ uint64_t lfb_dmp:1;
+ uint64_t ppnum:4;
+ uint64_t set:3;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+#else
+ uint64_t l2t:1;
+ uint64_t l2d:1;
+ uint64_t finv:1;
+ uint64_t set:3;
+ uint64_t ppnum:4;
+ uint64_t lfb_dmp:1;
+ uint64_t lfb_enum:4;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_l2c_dbg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t lfb_enum:2;
+ uint64_t lfb_dmp:1;
+ uint64_t reserved_5_9:5;
+ uint64_t set:2;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+#else
+ uint64_t l2t:1;
+ uint64_t l2d:1;
+ uint64_t finv:1;
+ uint64_t set:2;
+ uint64_t reserved_5_9:5;
+ uint64_t lfb_dmp:1;
+ uint64_t lfb_enum:2;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_dbg_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t lfb_enum:3;
+ uint64_t lfb_dmp:1;
+ uint64_t reserved_7_9:3;
+ uint64_t ppnum:1;
+ uint64_t reserved_5_5:1;
+ uint64_t set:2;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+#else
+ uint64_t l2t:1;
+ uint64_t l2d:1;
+ uint64_t finv:1;
+ uint64_t set:2;
+ uint64_t reserved_5_5:1;
+ uint64_t ppnum:1;
+ uint64_t reserved_7_9:3;
+ uint64_t lfb_dmp:1;
+ uint64_t lfb_enum:3;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_dbg_s cn38xx;
+ struct cvmx_l2c_dbg_s cn38xxp2;
+ struct cvmx_l2c_dbg_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t lfb_enum:3;
+ uint64_t lfb_dmp:1;
+ uint64_t reserved_7_9:3;
+ uint64_t ppnum:1;
+ uint64_t set:3;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+#else
+ uint64_t l2t:1;
+ uint64_t l2d:1;
+ uint64_t finv:1;
+ uint64_t set:3;
+ uint64_t ppnum:1;
+ uint64_t reserved_7_9:3;
+ uint64_t lfb_dmp:1;
+ uint64_t lfb_enum:3;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_dbg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t lfb_enum:3;
+ uint64_t lfb_dmp:1;
+ uint64_t reserved_8_9:2;
+ uint64_t ppnum:2;
+ uint64_t set:3;
+ uint64_t finv:1;
+ uint64_t l2d:1;
+ uint64_t l2t:1;
+#else
+ uint64_t l2t:1;
+ uint64_t l2d:1;
+ uint64_t finv:1;
+ uint64_t set:3;
+ uint64_t ppnum:2;
+ uint64_t reserved_8_9:2;
+ uint64_t lfb_dmp:1;
+ uint64_t lfb_enum:3;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn52xx;
+ struct cvmx_l2c_dbg_cn52xx cn52xxp1;
+ struct cvmx_l2c_dbg_s cn56xx;
+ struct cvmx_l2c_dbg_s cn56xxp1;
+ struct cvmx_l2c_dbg_s cn58xx;
+ struct cvmx_l2c_dbg_s cn58xxp1;
+} cvmx_l2c_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_dut_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dtena:1;
+ uint64_t reserved_30_30:1;
+ uint64_t dt_vld:1;
+ uint64_t dt_tag:29;
+#else
+ uint64_t dt_tag:29;
+ uint64_t dt_vld:1;
+ uint64_t reserved_30_30:1;
+ uint64_t dtena:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_dut_s cn30xx;
+ struct cvmx_l2c_dut_s cn31xx;
+ struct cvmx_l2c_dut_s cn38xx;
+ struct cvmx_l2c_dut_s cn38xxp2;
+ struct cvmx_l2c_dut_s cn50xx;
+ struct cvmx_l2c_dut_s cn52xx;
+ struct cvmx_l2c_dut_s cn52xxp1;
+ struct cvmx_l2c_dut_s cn56xx;
+ struct cvmx_l2c_dut_s cn56xxp1;
+ struct cvmx_l2c_dut_s cn58xx;
+ struct cvmx_l2c_dut_s cn58xxp1;
+} cvmx_l2c_dut_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_grpwrr0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t plc1rmsk:32;
+ uint64_t plc0rmsk:32;
+#else
+ uint64_t plc0rmsk:32;
+ uint64_t plc1rmsk:32;
+#endif
+ } s;
+ struct cvmx_l2c_grpwrr0_s cn52xx;
+ struct cvmx_l2c_grpwrr0_s cn52xxp1;
+ struct cvmx_l2c_grpwrr0_s cn56xx;
+ struct cvmx_l2c_grpwrr0_s cn56xxp1;
+} cvmx_l2c_grpwrr0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_grpwrr1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t ilcrmsk:32;
+ uint64_t plc2rmsk:32;
+#else
+ uint64_t plc2rmsk:32;
+ uint64_t ilcrmsk:32;
+#endif
+ } s;
+ struct cvmx_l2c_grpwrr1_s cn52xx;
+ struct cvmx_l2c_grpwrr1_s cn52xxp1;
+ struct cvmx_l2c_grpwrr1_s cn56xx;
+ struct cvmx_l2c_grpwrr1_s cn56xxp1;
+} cvmx_l2c_grpwrr1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t lck2ena:1;
+ uint64_t lckena:1;
+ uint64_t l2ddeden:1;
+ uint64_t l2dsecen:1;
+ uint64_t l2tdeden:1;
+ uint64_t l2tsecen:1;
+ uint64_t oob3en:1;
+ uint64_t oob2en:1;
+ uint64_t oob1en:1;
+#else
+ uint64_t oob1en:1;
+ uint64_t oob2en:1;
+ uint64_t oob3en:1;
+ uint64_t l2tsecen:1;
+ uint64_t l2tdeden:1;
+ uint64_t l2dsecen:1;
+ uint64_t l2ddeden:1;
+ uint64_t lckena:1;
+ uint64_t lck2ena:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_l2c_int_en_s cn52xx;
+ struct cvmx_l2c_int_en_s cn52xxp1;
+ struct cvmx_l2c_int_en_s cn56xx;
+ struct cvmx_l2c_int_en_s cn56xxp1;
+} cvmx_l2c_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_int_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t lck2:1;
+ uint64_t lck:1;
+ uint64_t l2dded:1;
+ uint64_t l2dsec:1;
+ uint64_t l2tded:1;
+ uint64_t l2tsec:1;
+ uint64_t oob3:1;
+ uint64_t oob2:1;
+ uint64_t oob1:1;
+#else
+ uint64_t oob1:1;
+ uint64_t oob2:1;
+ uint64_t oob3:1;
+ uint64_t l2tsec:1;
+ uint64_t l2tded:1;
+ uint64_t l2dsec:1;
+ uint64_t l2dded:1;
+ uint64_t lck:1;
+ uint64_t lck2:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_l2c_int_stat_s cn52xx;
+ struct cvmx_l2c_int_stat_s cn52xxp1;
+ struct cvmx_l2c_int_stat_s cn56xx;
+ struct cvmx_l2c_int_stat_s cn56xxp1;
+} cvmx_l2c_int_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lckbase_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t lck_base:27;
+ uint64_t reserved_1_3:3;
+ uint64_t lck_ena:1;
+#else
+ uint64_t lck_ena:1;
+ uint64_t reserved_1_3:3;
+ uint64_t lck_base:27;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_l2c_lckbase_s cn30xx;
+ struct cvmx_l2c_lckbase_s cn31xx;
+ struct cvmx_l2c_lckbase_s cn38xx;
+ struct cvmx_l2c_lckbase_s cn38xxp2;
+ struct cvmx_l2c_lckbase_s cn50xx;
+ struct cvmx_l2c_lckbase_s cn52xx;
+ struct cvmx_l2c_lckbase_s cn52xxp1;
+ struct cvmx_l2c_lckbase_s cn56xx;
+ struct cvmx_l2c_lckbase_s cn56xxp1;
+ struct cvmx_l2c_lckbase_s cn58xx;
+ struct cvmx_l2c_lckbase_s cn58xxp1;
+} cvmx_l2c_lckbase_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lckoff_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t lck_offset:10;
+#else
+ uint64_t lck_offset:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_l2c_lckoff_s cn30xx;
+ struct cvmx_l2c_lckoff_s cn31xx;
+ struct cvmx_l2c_lckoff_s cn38xx;
+ struct cvmx_l2c_lckoff_s cn38xxp2;
+ struct cvmx_l2c_lckoff_s cn50xx;
+ struct cvmx_l2c_lckoff_s cn52xx;
+ struct cvmx_l2c_lckoff_s cn52xxp1;
+ struct cvmx_l2c_lckoff_s cn56xx;
+ struct cvmx_l2c_lckoff_s cn56xxp1;
+ struct cvmx_l2c_lckoff_s cn58xx;
+ struct cvmx_l2c_lckoff_s cn58xxp1;
+} cvmx_l2c_lckoff_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lfb0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t stcpnd:1;
+ uint64_t stpnd:1;
+ uint64_t stinv:1;
+ uint64_t stcfl:1;
+ uint64_t vam:1;
+ uint64_t inxt:4;
+ uint64_t itl:1;
+ uint64_t ihd:1;
+ uint64_t set:3;
+ uint64_t vabnum:4;
+ uint64_t sid:9;
+ uint64_t cmd:4;
+ uint64_t vld:1;
+#else
+ uint64_t vld:1;
+ uint64_t cmd:4;
+ uint64_t sid:9;
+ uint64_t vabnum:4;
+ uint64_t set:3;
+ uint64_t ihd:1;
+ uint64_t itl:1;
+ uint64_t inxt:4;
+ uint64_t vam:1;
+ uint64_t stcfl:1;
+ uint64_t stinv:1;
+ uint64_t stpnd:1;
+ uint64_t stcpnd:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_lfb0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t stcpnd:1;
+ uint64_t stpnd:1;
+ uint64_t stinv:1;
+ uint64_t stcfl:1;
+ uint64_t vam:1;
+ uint64_t reserved_25_26:2;
+ uint64_t inxt:2;
+ uint64_t itl:1;
+ uint64_t ihd:1;
+ uint64_t reserved_20_20:1;
+ uint64_t set:2;
+ uint64_t reserved_16_17:2;
+ uint64_t vabnum:2;
+ uint64_t sid:9;
+ uint64_t cmd:4;
+ uint64_t vld:1;
+#else
+ uint64_t vld:1;
+ uint64_t cmd:4;
+ uint64_t sid:9;
+ uint64_t vabnum:2;
+ uint64_t reserved_16_17:2;
+ uint64_t set:2;
+ uint64_t reserved_20_20:1;
+ uint64_t ihd:1;
+ uint64_t itl:1;
+ uint64_t inxt:2;
+ uint64_t reserved_25_26:2;
+ uint64_t vam:1;
+ uint64_t stcfl:1;
+ uint64_t stinv:1;
+ uint64_t stpnd:1;
+ uint64_t stcpnd:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_lfb0_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t stcpnd:1;
+ uint64_t stpnd:1;
+ uint64_t stinv:1;
+ uint64_t stcfl:1;
+ uint64_t vam:1;
+ uint64_t reserved_26_26:1;
+ uint64_t inxt:3;
+ uint64_t itl:1;
+ uint64_t ihd:1;
+ uint64_t reserved_20_20:1;
+ uint64_t set:2;
+ uint64_t reserved_17_17:1;
+ uint64_t vabnum:3;
+ uint64_t sid:9;
+ uint64_t cmd:4;
+ uint64_t vld:1;
+#else
+ uint64_t vld:1;
+ uint64_t cmd:4;
+ uint64_t sid:9;
+ uint64_t vabnum:3;
+ uint64_t reserved_17_17:1;
+ uint64_t set:2;
+ uint64_t reserved_20_20:1;
+ uint64_t ihd:1;
+ uint64_t itl:1;
+ uint64_t inxt:3;
+ uint64_t reserved_26_26:1;
+ uint64_t vam:1;
+ uint64_t stcfl:1;
+ uint64_t stinv:1;
+ uint64_t stpnd:1;
+ uint64_t stcpnd:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_lfb0_s cn38xx;
+ struct cvmx_l2c_lfb0_s cn38xxp2;
+ struct cvmx_l2c_lfb0_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t stcpnd:1;
+ uint64_t stpnd:1;
+ uint64_t stinv:1;
+ uint64_t stcfl:1;
+ uint64_t vam:1;
+ uint64_t reserved_26_26:1;
+ uint64_t inxt:3;
+ uint64_t itl:1;
+ uint64_t ihd:1;
+ uint64_t set:3;
+ uint64_t reserved_17_17:1;
+ uint64_t vabnum:3;
+ uint64_t sid:9;
+ uint64_t cmd:4;
+ uint64_t vld:1;
+#else
+ uint64_t vld:1;
+ uint64_t cmd:4;
+ uint64_t sid:9;
+ uint64_t vabnum:3;
+ uint64_t reserved_17_17:1;
+ uint64_t set:3;
+ uint64_t ihd:1;
+ uint64_t itl:1;
+ uint64_t inxt:3;
+ uint64_t reserved_26_26:1;
+ uint64_t vam:1;
+ uint64_t stcfl:1;
+ uint64_t stinv:1;
+ uint64_t stpnd:1;
+ uint64_t stcpnd:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_lfb0_cn50xx cn52xx;
+ struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
+ struct cvmx_l2c_lfb0_s cn56xx;
+ struct cvmx_l2c_lfb0_s cn56xxp1;
+ struct cvmx_l2c_lfb0_s cn58xx;
+ struct cvmx_l2c_lfb0_s cn58xxp1;
+} cvmx_l2c_lfb0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lfb1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t dsgoing:1;
+ uint64_t bid:2;
+ uint64_t wtrsp:1;
+ uint64_t wtdw:1;
+ uint64_t wtdq:1;
+ uint64_t wtwhp:1;
+ uint64_t wtwhf:1;
+ uint64_t wtwrm:1;
+ uint64_t wtstm:1;
+ uint64_t wtrda:1;
+ uint64_t wtstdt:1;
+ uint64_t wtstrsp:1;
+ uint64_t wtstrsc:1;
+ uint64_t wtvtm:1;
+ uint64_t wtmfl:1;
+ uint64_t prbrty:1;
+ uint64_t wtprb:1;
+ uint64_t vld:1;
+#else
+ uint64_t vld:1;
+ uint64_t wtprb:1;
+ uint64_t prbrty:1;
+ uint64_t wtmfl:1;
+ uint64_t wtvtm:1;
+ uint64_t wtstrsc:1;
+ uint64_t wtstrsp:1;
+ uint64_t wtstdt:1;
+ uint64_t wtrda:1;
+ uint64_t wtstm:1;
+ uint64_t wtwrm:1;
+ uint64_t wtwhf:1;
+ uint64_t wtwhp:1;
+ uint64_t wtdq:1;
+ uint64_t wtdw:1;
+ uint64_t wtrsp:1;
+ uint64_t bid:2;
+ uint64_t dsgoing:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_l2c_lfb1_s cn30xx;
+ struct cvmx_l2c_lfb1_s cn31xx;
+ struct cvmx_l2c_lfb1_s cn38xx;
+ struct cvmx_l2c_lfb1_s cn38xxp2;
+ struct cvmx_l2c_lfb1_s cn50xx;
+ struct cvmx_l2c_lfb1_s cn52xx;
+ struct cvmx_l2c_lfb1_s cn52xxp1;
+ struct cvmx_l2c_lfb1_s cn56xx;
+ struct cvmx_l2c_lfb1_s cn56xxp1;
+ struct cvmx_l2c_lfb1_s cn58xx;
+ struct cvmx_l2c_lfb1_s cn58xxp1;
+} cvmx_l2c_lfb1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lfb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_l2c_lfb2_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t lfb_tag:19;
+ uint64_t lfb_idx:8;
+#else
+ uint64_t lfb_idx:8;
+ uint64_t lfb_tag:19;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_lfb2_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t lfb_tag:17;
+ uint64_t lfb_idx:10;
+#else
+ uint64_t lfb_idx:10;
+ uint64_t lfb_tag:17;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_lfb2_cn31xx cn38xx;
+ struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
+ struct cvmx_l2c_lfb2_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t lfb_tag:20;
+ uint64_t lfb_idx:7;
+#else
+ uint64_t lfb_idx:7;
+ uint64_t lfb_tag:20;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_lfb2_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t lfb_tag:18;
+ uint64_t lfb_idx:9;
+#else
+ uint64_t lfb_idx:9;
+ uint64_t lfb_tag:18;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn52xx;
+ struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
+ struct cvmx_l2c_lfb2_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t lfb_tag:16;
+ uint64_t lfb_idx:11;
+#else
+ uint64_t lfb_idx:11;
+ uint64_t lfb_tag:16;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn56xx;
+ struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
+ struct cvmx_l2c_lfb2_cn56xx cn58xx;
+ struct cvmx_l2c_lfb2_cn56xx cn58xxp1;
+} cvmx_l2c_lfb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_lfb3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t stpartdis:1;
+ uint64_t lfb_hwm:4;
+#else
+ uint64_t lfb_hwm:4;
+ uint64_t stpartdis:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_l2c_lfb3_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t stpartdis:1;
+ uint64_t reserved_2_3:2;
+ uint64_t lfb_hwm:2;
+#else
+ uint64_t lfb_hwm:2;
+ uint64_t reserved_2_3:2;
+ uint64_t stpartdis:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_lfb3_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t stpartdis:1;
+ uint64_t reserved_3_3:1;
+ uint64_t lfb_hwm:3;
+#else
+ uint64_t lfb_hwm:3;
+ uint64_t reserved_3_3:1;
+ uint64_t stpartdis:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_lfb3_s cn38xx;
+ struct cvmx_l2c_lfb3_s cn38xxp2;
+ struct cvmx_l2c_lfb3_cn31xx cn50xx;
+ struct cvmx_l2c_lfb3_cn31xx cn52xx;
+ struct cvmx_l2c_lfb3_cn31xx cn52xxp1;
+ struct cvmx_l2c_lfb3_s cn56xx;
+ struct cvmx_l2c_lfb3_s cn56xxp1;
+ struct cvmx_l2c_lfb3_s cn58xx;
+ struct cvmx_l2c_lfb3_s cn58xxp1;
+} cvmx_l2c_lfb3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_oob_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dwbena:1;
+ uint64_t stena:1;
+#else
+ uint64_t stena:1;
+ uint64_t dwbena:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_l2c_oob_s cn52xx;
+ struct cvmx_l2c_oob_s cn52xxp1;
+ struct cvmx_l2c_oob_s cn56xx;
+ struct cvmx_l2c_oob_s cn56xxp1;
+} cvmx_l2c_oob_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_oob1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fadr:27;
+ uint64_t fsrc:1;
+ uint64_t reserved_34_35:2;
+ uint64_t sadr:14;
+ uint64_t reserved_14_19:6;
+ uint64_t size:14;
+#else
+ uint64_t size:14;
+ uint64_t reserved_14_19:6;
+ uint64_t sadr:14;
+ uint64_t reserved_34_35:2;
+ uint64_t fsrc:1;
+ uint64_t fadr:27;
+#endif
+ } s;
+ struct cvmx_l2c_oob1_s cn52xx;
+ struct cvmx_l2c_oob1_s cn52xxp1;
+ struct cvmx_l2c_oob1_s cn56xx;
+ struct cvmx_l2c_oob1_s cn56xxp1;
+} cvmx_l2c_oob1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_oob2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fadr:27;
+ uint64_t fsrc:1;
+ uint64_t reserved_34_35:2;
+ uint64_t sadr:14;
+ uint64_t reserved_14_19:6;
+ uint64_t size:14;
+#else
+ uint64_t size:14;
+ uint64_t reserved_14_19:6;
+ uint64_t sadr:14;
+ uint64_t reserved_34_35:2;
+ uint64_t fsrc:1;
+ uint64_t fadr:27;
+#endif
+ } s;
+ struct cvmx_l2c_oob2_s cn52xx;
+ struct cvmx_l2c_oob2_s cn52xxp1;
+ struct cvmx_l2c_oob2_s cn56xx;
+ struct cvmx_l2c_oob2_s cn56xxp1;
+} cvmx_l2c_oob2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_oob3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fadr:27;
+ uint64_t fsrc:1;
+ uint64_t reserved_34_35:2;
+ uint64_t sadr:14;
+ uint64_t reserved_14_19:6;
+ uint64_t size:14;
+#else
+ uint64_t size:14;
+ uint64_t reserved_14_19:6;
+ uint64_t sadr:14;
+ uint64_t reserved_34_35:2;
+ uint64_t fsrc:1;
+ uint64_t fadr:27;
+#endif
+ } s;
+ struct cvmx_l2c_oob3_s cn52xx;
+ struct cvmx_l2c_oob3_s cn52xxp1;
+ struct cvmx_l2c_oob3_s cn56xx;
+ struct cvmx_l2c_oob3_s cn56xxp1;
+} cvmx_l2c_oob3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_pfcx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t pfcnt0:36;
+#else
+ uint64_t pfcnt0:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_l2c_pfcx_s cn30xx;
+ struct cvmx_l2c_pfcx_s cn31xx;
+ struct cvmx_l2c_pfcx_s cn38xx;
+ struct cvmx_l2c_pfcx_s cn38xxp2;
+ struct cvmx_l2c_pfcx_s cn50xx;
+ struct cvmx_l2c_pfcx_s cn52xx;
+ struct cvmx_l2c_pfcx_s cn52xxp1;
+ struct cvmx_l2c_pfcx_s cn56xx;
+ struct cvmx_l2c_pfcx_s cn56xxp1;
+ struct cvmx_l2c_pfcx_s cn58xx;
+ struct cvmx_l2c_pfcx_s cn58xxp1;
+} cvmx_l2c_pfcx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_pfctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t cnt3rdclr:1;
+ uint64_t cnt2rdclr:1;
+ uint64_t cnt1rdclr:1;
+ uint64_t cnt0rdclr:1;
+ uint64_t cnt3ena:1;
+ uint64_t cnt3clr:1;
+ uint64_t cnt3sel:6;
+ uint64_t cnt2ena:1;
+ uint64_t cnt2clr:1;
+ uint64_t cnt2sel:6;
+ uint64_t cnt1ena:1;
+ uint64_t cnt1clr:1;
+ uint64_t cnt1sel:6;
+ uint64_t cnt0ena:1;
+ uint64_t cnt0clr:1;
+ uint64_t cnt0sel:6;
+#else
+ uint64_t cnt0sel:6;
+ uint64_t cnt0clr:1;
+ uint64_t cnt0ena:1;
+ uint64_t cnt1sel:6;
+ uint64_t cnt1clr:1;
+ uint64_t cnt1ena:1;
+ uint64_t cnt2sel:6;
+ uint64_t cnt2clr:1;
+ uint64_t cnt2ena:1;
+ uint64_t cnt3sel:6;
+ uint64_t cnt3clr:1;
+ uint64_t cnt3ena:1;
+ uint64_t cnt0rdclr:1;
+ uint64_t cnt1rdclr:1;
+ uint64_t cnt2rdclr:1;
+ uint64_t cnt3rdclr:1;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_l2c_pfctl_s cn30xx;
+ struct cvmx_l2c_pfctl_s cn31xx;
+ struct cvmx_l2c_pfctl_s cn38xx;
+ struct cvmx_l2c_pfctl_s cn38xxp2;
+ struct cvmx_l2c_pfctl_s cn50xx;
+ struct cvmx_l2c_pfctl_s cn52xx;
+ struct cvmx_l2c_pfctl_s cn52xxp1;
+ struct cvmx_l2c_pfctl_s cn56xx;
+ struct cvmx_l2c_pfctl_s cn56xxp1;
+ struct cvmx_l2c_pfctl_s cn58xx;
+ struct cvmx_l2c_pfctl_s cn58xxp1;
+} cvmx_l2c_pfctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_ppgrp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t pp11grp:2;
+ uint64_t pp10grp:2;
+ uint64_t pp9grp:2;
+ uint64_t pp8grp:2;
+ uint64_t pp7grp:2;
+ uint64_t pp6grp:2;
+ uint64_t pp5grp:2;
+ uint64_t pp4grp:2;
+ uint64_t pp3grp:2;
+ uint64_t pp2grp:2;
+ uint64_t pp1grp:2;
+ uint64_t pp0grp:2;
+#else
+ uint64_t pp0grp:2;
+ uint64_t pp1grp:2;
+ uint64_t pp2grp:2;
+ uint64_t pp3grp:2;
+ uint64_t pp4grp:2;
+ uint64_t pp5grp:2;
+ uint64_t pp6grp:2;
+ uint64_t pp7grp:2;
+ uint64_t pp8grp:2;
+ uint64_t pp9grp:2;
+ uint64_t pp10grp:2;
+ uint64_t pp11grp:2;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_l2c_ppgrp_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t pp3grp:2;
+ uint64_t pp2grp:2;
+ uint64_t pp1grp:2;
+ uint64_t pp0grp:2;
+#else
+ uint64_t pp0grp:2;
+ uint64_t pp1grp:2;
+ uint64_t pp2grp:2;
+ uint64_t pp3grp:2;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn52xx;
+ struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
+ struct cvmx_l2c_ppgrp_s cn56xx;
+ struct cvmx_l2c_ppgrp_s cn56xxp1;
+} cvmx_l2c_ppgrp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_spar0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t umsk3:8;
+ uint64_t umsk2:8;
+ uint64_t umsk1:8;
+ uint64_t umsk0:8;
+#else
+ uint64_t umsk0:8;
+ uint64_t umsk1:8;
+ uint64_t umsk2:8;
+ uint64_t umsk3:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_spar0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t umsk0:4;
+#else
+ uint64_t umsk0:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_spar0_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t umsk1:4;
+ uint64_t reserved_4_7:4;
+ uint64_t umsk0:4;
+#else
+ uint64_t umsk0:4;
+ uint64_t reserved_4_7:4;
+ uint64_t umsk1:4;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn31xx;
+ struct cvmx_l2c_spar0_s cn38xx;
+ struct cvmx_l2c_spar0_s cn38xxp2;
+ struct cvmx_l2c_spar0_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t umsk1:8;
+ uint64_t umsk0:8;
+#else
+ uint64_t umsk0:8;
+ uint64_t umsk1:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn50xx;
+ struct cvmx_l2c_spar0_s cn52xx;
+ struct cvmx_l2c_spar0_s cn52xxp1;
+ struct cvmx_l2c_spar0_s cn56xx;
+ struct cvmx_l2c_spar0_s cn56xxp1;
+ struct cvmx_l2c_spar0_s cn58xx;
+ struct cvmx_l2c_spar0_s cn58xxp1;
+} cvmx_l2c_spar0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_spar1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t umsk7:8;
+ uint64_t umsk6:8;
+ uint64_t umsk5:8;
+ uint64_t umsk4:8;
+#else
+ uint64_t umsk4:8;
+ uint64_t umsk5:8;
+ uint64_t umsk6:8;
+ uint64_t umsk7:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_spar1_s cn38xx;
+ struct cvmx_l2c_spar1_s cn38xxp2;
+ struct cvmx_l2c_spar1_s cn56xx;
+ struct cvmx_l2c_spar1_s cn56xxp1;
+ struct cvmx_l2c_spar1_s cn58xx;
+ struct cvmx_l2c_spar1_s cn58xxp1;
+} cvmx_l2c_spar1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_spar2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t umsk11:8;
+ uint64_t umsk10:8;
+ uint64_t umsk9:8;
+ uint64_t umsk8:8;
+#else
+ uint64_t umsk8:8;
+ uint64_t umsk9:8;
+ uint64_t umsk10:8;
+ uint64_t umsk11:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_spar2_s cn38xx;
+ struct cvmx_l2c_spar2_s cn38xxp2;
+ struct cvmx_l2c_spar2_s cn56xx;
+ struct cvmx_l2c_spar2_s cn56xxp1;
+ struct cvmx_l2c_spar2_s cn58xx;
+ struct cvmx_l2c_spar2_s cn58xxp1;
+} cvmx_l2c_spar2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_spar3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t umsk15:8;
+ uint64_t umsk14:8;
+ uint64_t umsk13:8;
+ uint64_t umsk12:8;
+#else
+ uint64_t umsk12:8;
+ uint64_t umsk13:8;
+ uint64_t umsk14:8;
+ uint64_t umsk15:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_l2c_spar3_s cn38xx;
+ struct cvmx_l2c_spar3_s cn38xxp2;
+ struct cvmx_l2c_spar3_s cn58xx;
+ struct cvmx_l2c_spar3_s cn58xxp1;
+} cvmx_l2c_spar3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2c_spar4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t umskiob:8;
+#else
+ uint64_t umskiob:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_l2c_spar4_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t umskiob:4;
+#else
+ uint64_t umskiob:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_l2c_spar4_cn30xx cn31xx;
+ struct cvmx_l2c_spar4_s cn38xx;
+ struct cvmx_l2c_spar4_s cn38xxp2;
+ struct cvmx_l2c_spar4_s cn50xx;
+ struct cvmx_l2c_spar4_s cn52xx;
+ struct cvmx_l2c_spar4_s cn52xxp1;
+ struct cvmx_l2c_spar4_s cn56xx;
+ struct cvmx_l2c_spar4_s cn56xxp1;
+ struct cvmx_l2c_spar4_s cn58xx;
+ struct cvmx_l2c_spar4_s cn58xxp1;
+} cvmx_l2c_spar4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_bst0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_35_63:29;
+ uint64_t ftl:1;
+ uint64_t q0stat:34;
+#else
+ uint64_t q0stat:34;
+ uint64_t ftl:1;
+ uint64_t reserved_35_63:29;
+#endif
+ } s;
+ struct cvmx_l2d_bst0_s cn30xx;
+ struct cvmx_l2d_bst0_s cn31xx;
+ struct cvmx_l2d_bst0_s cn38xx;
+ struct cvmx_l2d_bst0_s cn38xxp2;
+ struct cvmx_l2d_bst0_s cn50xx;
+ struct cvmx_l2d_bst0_s cn52xx;
+ struct cvmx_l2d_bst0_s cn52xxp1;
+ struct cvmx_l2d_bst0_s cn56xx;
+ struct cvmx_l2d_bst0_s cn56xxp1;
+ struct cvmx_l2d_bst0_s cn58xx;
+ struct cvmx_l2d_bst0_s cn58xxp1;
+} cvmx_l2d_bst0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_bst1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q1stat:34;
+#else
+ uint64_t q1stat:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_bst1_s cn30xx;
+ struct cvmx_l2d_bst1_s cn31xx;
+ struct cvmx_l2d_bst1_s cn38xx;
+ struct cvmx_l2d_bst1_s cn38xxp2;
+ struct cvmx_l2d_bst1_s cn50xx;
+ struct cvmx_l2d_bst1_s cn52xx;
+ struct cvmx_l2d_bst1_s cn52xxp1;
+ struct cvmx_l2d_bst1_s cn56xx;
+ struct cvmx_l2d_bst1_s cn56xxp1;
+ struct cvmx_l2d_bst1_s cn58xx;
+ struct cvmx_l2d_bst1_s cn58xxp1;
+} cvmx_l2d_bst1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_bst2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q2stat:34;
+#else
+ uint64_t q2stat:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_bst2_s cn30xx;
+ struct cvmx_l2d_bst2_s cn31xx;
+ struct cvmx_l2d_bst2_s cn38xx;
+ struct cvmx_l2d_bst2_s cn38xxp2;
+ struct cvmx_l2d_bst2_s cn50xx;
+ struct cvmx_l2d_bst2_s cn52xx;
+ struct cvmx_l2d_bst2_s cn52xxp1;
+ struct cvmx_l2d_bst2_s cn56xx;
+ struct cvmx_l2d_bst2_s cn56xxp1;
+ struct cvmx_l2d_bst2_s cn58xx;
+ struct cvmx_l2d_bst2_s cn58xxp1;
+} cvmx_l2d_bst2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_bst3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q3stat:34;
+#else
+ uint64_t q3stat:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_bst3_s cn30xx;
+ struct cvmx_l2d_bst3_s cn31xx;
+ struct cvmx_l2d_bst3_s cn38xx;
+ struct cvmx_l2d_bst3_s cn38xxp2;
+ struct cvmx_l2d_bst3_s cn50xx;
+ struct cvmx_l2d_bst3_s cn52xx;
+ struct cvmx_l2d_bst3_s cn52xxp1;
+ struct cvmx_l2d_bst3_s cn56xx;
+ struct cvmx_l2d_bst3_s cn56xxp1;
+ struct cvmx_l2d_bst3_s cn58xx;
+ struct cvmx_l2d_bst3_s cn58xxp1;
+} cvmx_l2d_bst3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t bmhclsel:1;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t bmhclsel:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_l2d_err_s cn30xx;
+ struct cvmx_l2d_err_s cn31xx;
+ struct cvmx_l2d_err_s cn38xx;
+ struct cvmx_l2d_err_s cn38xxp2;
+ struct cvmx_l2d_err_s cn50xx;
+ struct cvmx_l2d_err_s cn52xx;
+ struct cvmx_l2d_err_s cn52xxp1;
+ struct cvmx_l2d_err_s cn56xx;
+ struct cvmx_l2d_err_s cn56xxp1;
+ struct cvmx_l2d_err_s cn58xx;
+ struct cvmx_l2d_err_s cn58xxp1;
+} cvmx_l2d_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fadr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t fadru:1;
+ uint64_t fowmsk:4;
+ uint64_t fset:3;
+ uint64_t fadr:11;
+#else
+ uint64_t fadr:11;
+ uint64_t fset:3;
+ uint64_t fowmsk:4;
+ uint64_t fadru:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_l2d_fadr_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t fowmsk:4;
+ uint64_t reserved_13_13:1;
+ uint64_t fset:2;
+ uint64_t reserved_9_10:2;
+ uint64_t fadr:9;
+#else
+ uint64_t fadr:9;
+ uint64_t reserved_9_10:2;
+ uint64_t fset:2;
+ uint64_t reserved_13_13:1;
+ uint64_t fowmsk:4;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn30xx;
+ struct cvmx_l2d_fadr_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t fowmsk:4;
+ uint64_t reserved_13_13:1;
+ uint64_t fset:2;
+ uint64_t reserved_10_10:1;
+ uint64_t fadr:10;
+#else
+ uint64_t fadr:10;
+ uint64_t reserved_10_10:1;
+ uint64_t fset:2;
+ uint64_t reserved_13_13:1;
+ uint64_t fowmsk:4;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn31xx;
+ struct cvmx_l2d_fadr_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t fowmsk:4;
+ uint64_t fset:3;
+ uint64_t fadr:11;
+#else
+ uint64_t fadr:11;
+ uint64_t fset:3;
+ uint64_t fowmsk:4;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn38xx;
+ struct cvmx_l2d_fadr_cn38xx cn38xxp2;
+ struct cvmx_l2d_fadr_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t fowmsk:4;
+ uint64_t fset:3;
+ uint64_t reserved_8_10:3;
+ uint64_t fadr:8;
+#else
+ uint64_t fadr:8;
+ uint64_t reserved_8_10:3;
+ uint64_t fset:3;
+ uint64_t fowmsk:4;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn50xx;
+ struct cvmx_l2d_fadr_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t fowmsk:4;
+ uint64_t fset:3;
+ uint64_t reserved_10_10:1;
+ uint64_t fadr:10;
+#else
+ uint64_t fadr:10;
+ uint64_t reserved_10_10:1;
+ uint64_t fset:3;
+ uint64_t fowmsk:4;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn52xx;
+ struct cvmx_l2d_fadr_cn52xx cn52xxp1;
+ struct cvmx_l2d_fadr_s cn56xx;
+ struct cvmx_l2d_fadr_s cn56xxp1;
+ struct cvmx_l2d_fadr_s cn58xx;
+ struct cvmx_l2d_fadr_s cn58xxp1;
+} cvmx_l2d_fadr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fsyn0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t fsyn_ow1:10;
+ uint64_t fsyn_ow0:10;
+#else
+ uint64_t fsyn_ow0:10;
+ uint64_t fsyn_ow1:10;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_l2d_fsyn0_s cn30xx;
+ struct cvmx_l2d_fsyn0_s cn31xx;
+ struct cvmx_l2d_fsyn0_s cn38xx;
+ struct cvmx_l2d_fsyn0_s cn38xxp2;
+ struct cvmx_l2d_fsyn0_s cn50xx;
+ struct cvmx_l2d_fsyn0_s cn52xx;
+ struct cvmx_l2d_fsyn0_s cn52xxp1;
+ struct cvmx_l2d_fsyn0_s cn56xx;
+ struct cvmx_l2d_fsyn0_s cn56xxp1;
+ struct cvmx_l2d_fsyn0_s cn58xx;
+ struct cvmx_l2d_fsyn0_s cn58xxp1;
+} cvmx_l2d_fsyn0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fsyn1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t fsyn_ow3:10;
+ uint64_t fsyn_ow2:10;
+#else
+ uint64_t fsyn_ow2:10;
+ uint64_t fsyn_ow3:10;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_l2d_fsyn1_s cn30xx;
+ struct cvmx_l2d_fsyn1_s cn31xx;
+ struct cvmx_l2d_fsyn1_s cn38xx;
+ struct cvmx_l2d_fsyn1_s cn38xxp2;
+ struct cvmx_l2d_fsyn1_s cn50xx;
+ struct cvmx_l2d_fsyn1_s cn52xx;
+ struct cvmx_l2d_fsyn1_s cn52xxp1;
+ struct cvmx_l2d_fsyn1_s cn56xx;
+ struct cvmx_l2d_fsyn1_s cn56xxp1;
+ struct cvmx_l2d_fsyn1_s cn58xx;
+ struct cvmx_l2d_fsyn1_s cn58xxp1;
+} cvmx_l2d_fsyn1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fus0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q0fus:34;
+#else
+ uint64_t q0fus:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_fus0_s cn30xx;
+ struct cvmx_l2d_fus0_s cn31xx;
+ struct cvmx_l2d_fus0_s cn38xx;
+ struct cvmx_l2d_fus0_s cn38xxp2;
+ struct cvmx_l2d_fus0_s cn50xx;
+ struct cvmx_l2d_fus0_s cn52xx;
+ struct cvmx_l2d_fus0_s cn52xxp1;
+ struct cvmx_l2d_fus0_s cn56xx;
+ struct cvmx_l2d_fus0_s cn56xxp1;
+ struct cvmx_l2d_fus0_s cn58xx;
+ struct cvmx_l2d_fus0_s cn58xxp1;
+} cvmx_l2d_fus0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fus1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q1fus:34;
+#else
+ uint64_t q1fus:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_fus1_s cn30xx;
+ struct cvmx_l2d_fus1_s cn31xx;
+ struct cvmx_l2d_fus1_s cn38xx;
+ struct cvmx_l2d_fus1_s cn38xxp2;
+ struct cvmx_l2d_fus1_s cn50xx;
+ struct cvmx_l2d_fus1_s cn52xx;
+ struct cvmx_l2d_fus1_s cn52xxp1;
+ struct cvmx_l2d_fus1_s cn56xx;
+ struct cvmx_l2d_fus1_s cn56xxp1;
+ struct cvmx_l2d_fus1_s cn58xx;
+ struct cvmx_l2d_fus1_s cn58xxp1;
+} cvmx_l2d_fus1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fus2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t q2fus:34;
+#else
+ uint64_t q2fus:34;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_l2d_fus2_s cn30xx;
+ struct cvmx_l2d_fus2_s cn31xx;
+ struct cvmx_l2d_fus2_s cn38xx;
+ struct cvmx_l2d_fus2_s cn38xxp2;
+ struct cvmx_l2d_fus2_s cn50xx;
+ struct cvmx_l2d_fus2_s cn52xx;
+ struct cvmx_l2d_fus2_s cn52xxp1;
+ struct cvmx_l2d_fus2_s cn56xx;
+ struct cvmx_l2d_fus2_s cn56xxp1;
+ struct cvmx_l2d_fus2_s cn58xx;
+ struct cvmx_l2d_fus2_s cn58xxp1;
+} cvmx_l2d_fus2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2d_fus3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_34_36:3;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t reserved_34_36:3;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_l2d_fus3_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_35_63:29;
+ uint64_t crip_64k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_64k:1;
+ uint64_t reserved_35_63:29;
+#endif
+ } cn30xx;
+ struct cvmx_l2d_fus3_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_35_63:29;
+ uint64_t crip_128k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_128k:1;
+ uint64_t reserved_35_63:29;
+#endif
+ } cn31xx;
+ struct cvmx_l2d_fus3_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t crip_256k:1;
+ uint64_t crip_512k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_512k:1;
+ uint64_t crip_256k:1;
+ uint64_t reserved_36_63:28;
+#endif
+ } cn38xx;
+ struct cvmx_l2d_fus3_cn38xx cn38xxp2;
+ struct cvmx_l2d_fus3_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_36_36:1;
+ uint64_t crip_32k:1;
+ uint64_t crip_64k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_64k:1;
+ uint64_t crip_32k:1;
+ uint64_t reserved_36_36:1;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_40_63:24;
+#endif
+ } cn50xx;
+ struct cvmx_l2d_fus3_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_36_36:1;
+ uint64_t crip_128k:1;
+ uint64_t crip_256k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_256k:1;
+ uint64_t crip_128k:1;
+ uint64_t reserved_36_36:1;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_40_63:24;
+#endif
+ } cn52xx;
+ struct cvmx_l2d_fus3_cn52xx cn52xxp1;
+ struct cvmx_l2d_fus3_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_36_36:1;
+ uint64_t crip_512k:1;
+ uint64_t crip_1024k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_1024k:1;
+ uint64_t crip_512k:1;
+ uint64_t reserved_36_36:1;
+ uint64_t ema_ctl:3;
+ uint64_t reserved_40_63:24;
+#endif
+ } cn56xx;
+ struct cvmx_l2d_fus3_cn56xx cn56xxp1;
+ struct cvmx_l2d_fus3_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t ema_ctl:2;
+ uint64_t reserved_36_36:1;
+ uint64_t crip_512k:1;
+ uint64_t crip_1024k:1;
+ uint64_t q3fus:34;
+#else
+ uint64_t q3fus:34;
+ uint64_t crip_1024k:1;
+ uint64_t crip_512k:1;
+ uint64_t reserved_36_36:1;
+ uint64_t ema_ctl:2;
+ uint64_t reserved_39_63:25;
+#endif
+ } cn58xx;
+ struct cvmx_l2d_fus3_cn58xx cn58xxp1;
+} cvmx_l2d_fus3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_l2t_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t fadru:1;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t fset:3;
+ uint64_t fadr:10;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:10;
+ uint64_t fset:3;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t fadru:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_l2t_err_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t reserved_23_23:1;
+ uint64_t fset:2;
+ uint64_t reserved_19_20:2;
+ uint64_t fadr:8;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:8;
+ uint64_t reserved_19_20:2;
+ uint64_t fset:2;
+ uint64_t reserved_23_23:1;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn30xx;
+ struct cvmx_l2t_err_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t reserved_23_23:1;
+ uint64_t fset:2;
+ uint64_t reserved_20_20:1;
+ uint64_t fadr:9;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:9;
+ uint64_t reserved_20_20:1;
+ uint64_t fset:2;
+ uint64_t reserved_23_23:1;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn31xx;
+ struct cvmx_l2t_err_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t fset:3;
+ uint64_t fadr:10;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:10;
+ uint64_t fset:3;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn38xx;
+ struct cvmx_l2t_err_cn38xx cn38xxp2;
+ struct cvmx_l2t_err_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t fset:3;
+ uint64_t reserved_18_20:3;
+ uint64_t fadr:7;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:7;
+ uint64_t reserved_18_20:3;
+ uint64_t fset:3;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn50xx;
+ struct cvmx_l2t_err_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t lck_intena2:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr:1;
+ uint64_t fset:3;
+ uint64_t reserved_20_20:1;
+ uint64_t fadr:9;
+ uint64_t fsyn:6;
+ uint64_t ded_err:1;
+ uint64_t sec_err:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_intena:1;
+ uint64_t ecc_ena:1;
+#else
+ uint64_t ecc_ena:1;
+ uint64_t sec_intena:1;
+ uint64_t ded_intena:1;
+ uint64_t sec_err:1;
+ uint64_t ded_err:1;
+ uint64_t fsyn:6;
+ uint64_t fadr:9;
+ uint64_t reserved_20_20:1;
+ uint64_t fset:3;
+ uint64_t lckerr:1;
+ uint64_t lck_intena:1;
+ uint64_t lckerr2:1;
+ uint64_t lck_intena2:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn52xx;
+ struct cvmx_l2t_err_cn52xx cn52xxp1;
+ struct cvmx_l2t_err_s cn56xx;
+ struct cvmx_l2t_err_s cn56xxp1;
+ struct cvmx_l2t_err_s cn58xx;
+ struct cvmx_l2t_err_s cn58xxp1;
+} cvmx_l2t_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_blink_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rate:8;
+#else
+ uint64_t rate:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_led_blink_s cn38xx;
+ struct cvmx_led_blink_s cn38xxp2;
+ struct cvmx_led_blink_s cn56xx;
+ struct cvmx_led_blink_s cn56xxp1;
+ struct cvmx_led_blink_s cn58xx;
+ struct cvmx_led_blink_s cn58xxp1;
+} cvmx_led_blink_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_clk_phase_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t phase:7;
+#else
+ uint64_t phase:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_led_clk_phase_s cn38xx;
+ struct cvmx_led_clk_phase_s cn38xxp2;
+ struct cvmx_led_clk_phase_s cn56xx;
+ struct cvmx_led_clk_phase_s cn56xxp1;
+ struct cvmx_led_clk_phase_s cn58xx;
+ struct cvmx_led_clk_phase_s cn58xxp1;
+} cvmx_led_clk_phase_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_cylon_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t rate:16;
+#else
+ uint64_t rate:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_led_cylon_s cn38xx;
+ struct cvmx_led_cylon_s cn38xxp2;
+ struct cvmx_led_cylon_s cn56xx;
+ struct cvmx_led_cylon_s cn56xxp1;
+ struct cvmx_led_cylon_s cn58xx;
+ struct cvmx_led_cylon_s cn58xxp1;
+} cvmx_led_cylon_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t dbg_en:1;
+#else
+ uint64_t dbg_en:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_led_dbg_s cn38xx;
+ struct cvmx_led_dbg_s cn38xxp2;
+ struct cvmx_led_dbg_s cn56xx;
+ struct cvmx_led_dbg_s cn56xxp1;
+ struct cvmx_led_dbg_s cn58xx;
+ struct cvmx_led_dbg_s cn58xxp1;
+} cvmx_led_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_led_en_s cn38xx;
+ struct cvmx_led_en_s cn38xxp2;
+ struct cvmx_led_en_s cn56xx;
+ struct cvmx_led_en_s cn56xxp1;
+ struct cvmx_led_en_s cn58xx;
+ struct cvmx_led_en_s cn58xxp1;
+} cvmx_led_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_polarity_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t polarity:1;
+#else
+ uint64_t polarity:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_led_polarity_s cn38xx;
+ struct cvmx_led_polarity_s cn38xxp2;
+ struct cvmx_led_polarity_s cn56xx;
+ struct cvmx_led_polarity_s cn56xxp1;
+ struct cvmx_led_polarity_s cn58xx;
+ struct cvmx_led_polarity_s cn58xxp1;
+} cvmx_led_polarity_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_prt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t prt_en:8;
+#else
+ uint64_t prt_en:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_led_prt_s cn38xx;
+ struct cvmx_led_prt_s cn38xxp2;
+ struct cvmx_led_prt_s cn56xx;
+ struct cvmx_led_prt_s cn56xxp1;
+ struct cvmx_led_prt_s cn58xx;
+ struct cvmx_led_prt_s cn58xxp1;
+} cvmx_led_prt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_prt_fmt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t format:4;
+#else
+ uint64_t format:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_led_prt_fmt_s cn38xx;
+ struct cvmx_led_prt_fmt_s cn38xxp2;
+ struct cvmx_led_prt_fmt_s cn56xx;
+ struct cvmx_led_prt_fmt_s cn56xxp1;
+ struct cvmx_led_prt_fmt_s cn58xx;
+ struct cvmx_led_prt_fmt_s cn58xxp1;
+} cvmx_led_prt_fmt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_prt_statusx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t status:6;
+#else
+ uint64_t status:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_led_prt_statusx_s cn38xx;
+ struct cvmx_led_prt_statusx_s cn38xxp2;
+ struct cvmx_led_prt_statusx_s cn56xx;
+ struct cvmx_led_prt_statusx_s cn56xxp1;
+ struct cvmx_led_prt_statusx_s cn58xx;
+ struct cvmx_led_prt_statusx_s cn58xxp1;
+} cvmx_led_prt_statusx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_udd_cntx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t cnt:6;
+#else
+ uint64_t cnt:6;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_led_udd_cntx_s cn38xx;
+ struct cvmx_led_udd_cntx_s cn38xxp2;
+ struct cvmx_led_udd_cntx_s cn56xx;
+ struct cvmx_led_udd_cntx_s cn56xxp1;
+ struct cvmx_led_udd_cntx_s cn58xx;
+ struct cvmx_led_udd_cntx_s cn58xxp1;
+} cvmx_led_udd_cntx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_udd_datx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dat:32;
+#else
+ uint64_t dat:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_led_udd_datx_s cn38xx;
+ struct cvmx_led_udd_datx_s cn38xxp2;
+ struct cvmx_led_udd_datx_s cn56xx;
+ struct cvmx_led_udd_datx_s cn56xxp1;
+ struct cvmx_led_udd_datx_s cn58xx;
+ struct cvmx_led_udd_datx_s cn58xxp1;
+} cvmx_led_udd_datx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_udd_dat_clrx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t clr:32;
+#else
+ uint64_t clr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_led_udd_dat_clrx_s cn38xx;
+ struct cvmx_led_udd_dat_clrx_s cn38xxp2;
+ struct cvmx_led_udd_dat_clrx_s cn56xx;
+ struct cvmx_led_udd_dat_clrx_s cn56xxp1;
+ struct cvmx_led_udd_dat_clrx_s cn58xx;
+ struct cvmx_led_udd_dat_clrx_s cn58xxp1;
+} cvmx_led_udd_dat_clrx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_led_udd_dat_setx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t set:32;
+#else
+ uint64_t set:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_led_udd_dat_setx_s cn38xx;
+ struct cvmx_led_udd_dat_setx_s cn38xxp2;
+ struct cvmx_led_udd_dat_setx_s cn56xx;
+ struct cvmx_led_udd_dat_setx_s cn56xxp1;
+ struct cvmx_led_udd_dat_setx_s cn58xx;
+ struct cvmx_led_udd_dat_setx_s cn58xxp1;
+} cvmx_led_udd_dat_setx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_bist_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t start:1;
+#else
+ uint64_t start:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_lmcx_bist_ctl_s cn50xx;
+ struct cvmx_lmcx_bist_ctl_s cn52xx;
+ struct cvmx_lmcx_bist_ctl_s cn52xxp1;
+ struct cvmx_lmcx_bist_ctl_s cn56xx;
+ struct cvmx_lmcx_bist_ctl_s cn56xxp1;
+} cvmx_lmcx_bist_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_bist_result_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t csrd2e:1;
+ uint64_t csre2d:1;
+ uint64_t mwf:1;
+ uint64_t mwd:3;
+ uint64_t mwc:1;
+ uint64_t mrf:1;
+ uint64_t mrd:3;
+#else
+ uint64_t mrd:3;
+ uint64_t mrf:1;
+ uint64_t mwc:1;
+ uint64_t mwd:3;
+ uint64_t mwf:1;
+ uint64_t csre2d:1;
+ uint64_t csrd2e:1;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_lmcx_bist_result_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t mwf:1;
+ uint64_t mwd:3;
+ uint64_t mwc:1;
+ uint64_t mrf:1;
+ uint64_t mrd:3;
+#else
+ uint64_t mrd:3;
+ uint64_t mrf:1;
+ uint64_t mwc:1;
+ uint64_t mwd:3;
+ uint64_t mwf:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn50xx;
+ struct cvmx_lmcx_bist_result_s cn52xx;
+ struct cvmx_lmcx_bist_result_s cn52xxp1;
+ struct cvmx_lmcx_bist_result_s cn56xx;
+ struct cvmx_lmcx_bist_result_s cn56xxp1;
+} cvmx_lmcx_bist_result_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_comp_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nctl_csr:4;
+ uint64_t nctl_clk:4;
+ uint64_t nctl_cmd:4;
+ uint64_t nctl_dat:4;
+ uint64_t pctl_csr:4;
+ uint64_t pctl_clk:4;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t pctl_clk:4;
+ uint64_t pctl_csr:4;
+ uint64_t nctl_dat:4;
+ uint64_t nctl_cmd:4;
+ uint64_t nctl_clk:4;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_comp_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nctl_csr:4;
+ uint64_t nctl_clk:4;
+ uint64_t nctl_cmd:4;
+ uint64_t nctl_dat:4;
+ uint64_t pctl_csr:4;
+ uint64_t pctl_clk:4;
+ uint64_t pctl_cmd:4;
+ uint64_t pctl_dat:4;
+#else
+ uint64_t pctl_dat:4;
+ uint64_t pctl_cmd:4;
+ uint64_t pctl_clk:4;
+ uint64_t pctl_csr:4;
+ uint64_t nctl_dat:4;
+ uint64_t nctl_cmd:4;
+ uint64_t nctl_clk:4;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_lmcx_comp_ctl_cn30xx cn31xx;
+ struct cvmx_lmcx_comp_ctl_cn30xx cn38xx;
+ struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2;
+ struct cvmx_lmcx_comp_ctl_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_20_27:8;
+ uint64_t nctl_dat:4;
+ uint64_t pctl_csr:4;
+ uint64_t reserved_5_11:7;
+ uint64_t pctl_dat:5;
+#else
+ uint64_t pctl_dat:5;
+ uint64_t reserved_5_11:7;
+ uint64_t pctl_csr:4;
+ uint64_t nctl_dat:4;
+ uint64_t reserved_20_27:8;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn50xx;
+ struct cvmx_lmcx_comp_ctl_cn50xx cn52xx;
+ struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1;
+ struct cvmx_lmcx_comp_ctl_cn50xx cn56xx;
+ struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1;
+ struct cvmx_lmcx_comp_ctl_cn50xx cn58xx;
+ struct cvmx_lmcx_comp_ctl_cn58xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_20_27:8;
+ uint64_t nctl_dat:4;
+ uint64_t pctl_csr:4;
+ uint64_t reserved_4_11:8;
+ uint64_t pctl_dat:4;
+#else
+ uint64_t pctl_dat:4;
+ uint64_t reserved_4_11:8;
+ uint64_t pctl_csr:4;
+ uint64_t nctl_dat:4;
+ uint64_t reserved_20_27:8;
+ uint64_t nctl_csr:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn58xxp1;
+} cvmx_lmcx_comp_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t pll_div2:1;
+ uint64_t pll_bypass:1;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t inorder_mwf:1;
+ uint64_t inorder_mrf:1;
+ uint64_t reserved_10_11:2;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t reserved_10_11:2;
+ uint64_t inorder_mrf:1;
+ uint64_t inorder_mwf:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t pll_bypass:1;
+ uint64_t pll_div2:1;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t pll_div2:1;
+ uint64_t pll_bypass:1;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t reserved_13_13:1;
+ uint64_t inorder_mrf:1;
+ uint64_t dreset:1;
+ uint64_t mode32b:1;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t mode32b:1;
+ uint64_t dreset:1;
+ uint64_t inorder_mrf:1;
+ uint64_t reserved_13_13:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t pll_bypass:1;
+ uint64_t pll_div2:1;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_lmcx_ctl_cn30xx cn31xx;
+ struct cvmx_lmcx_ctl_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t reserved_16_17:2;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t inorder_mwf:1;
+ uint64_t inorder_mrf:1;
+ uint64_t set_zero:1;
+ uint64_t mode128b:1;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t mode128b:1;
+ uint64_t set_zero:1;
+ uint64_t inorder_mrf:1;
+ uint64_t inorder_mwf:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t reserved_16_17:2;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_lmcx_ctl_cn38xx cn38xxp2;
+ struct cvmx_lmcx_ctl_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t reserved_17_17:1;
+ uint64_t pll_bypass:1;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t reserved_13_13:1;
+ uint64_t inorder_mrf:1;
+ uint64_t dreset:1;
+ uint64_t mode32b:1;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t mode32b:1;
+ uint64_t dreset:1;
+ uint64_t inorder_mrf:1;
+ uint64_t reserved_13_13:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t pll_bypass:1;
+ uint64_t reserved_17_17:1;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn50xx;
+ struct cvmx_lmcx_ctl_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t reserved_16_17:2;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t reserved_13_13:1;
+ uint64_t inorder_mrf:1;
+ uint64_t dreset:1;
+ uint64_t mode32b:1;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t mode32b:1;
+ uint64_t dreset:1;
+ uint64_t inorder_mrf:1;
+ uint64_t reserved_13_13:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t reserved_16_17:2;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn52xx;
+ struct cvmx_lmcx_ctl_cn52xx cn52xxp1;
+ struct cvmx_lmcx_ctl_cn52xx cn56xx;
+ struct cvmx_lmcx_ctl_cn52xx cn56xxp1;
+ struct cvmx_lmcx_ctl_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:4;
+ uint64_t ddr__pctl:4;
+ uint64_t slow_scf:1;
+ uint64_t xor_bank:1;
+ uint64_t max_write_batch:4;
+ uint64_t reserved_16_17:2;
+ uint64_t rdimm_ena:1;
+ uint64_t r2r_slot:1;
+ uint64_t reserved_13_13:1;
+ uint64_t inorder_mrf:1;
+ uint64_t dreset:1;
+ uint64_t mode128b:1;
+ uint64_t fprch2:1;
+ uint64_t bprch:1;
+ uint64_t sil_lat:2;
+ uint64_t tskw:2;
+ uint64_t qs_dic:2;
+ uint64_t dic:2;
+#else
+ uint64_t dic:2;
+ uint64_t qs_dic:2;
+ uint64_t tskw:2;
+ uint64_t sil_lat:2;
+ uint64_t bprch:1;
+ uint64_t fprch2:1;
+ uint64_t mode128b:1;
+ uint64_t dreset:1;
+ uint64_t inorder_mrf:1;
+ uint64_t reserved_13_13:1;
+ uint64_t r2r_slot:1;
+ uint64_t rdimm_ena:1;
+ uint64_t reserved_16_17:2;
+ uint64_t max_write_batch:4;
+ uint64_t xor_bank:1;
+ uint64_t slow_scf:1;
+ uint64_t ddr__pctl:4;
+ uint64_t ddr__nctl:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn58xx;
+ struct cvmx_lmcx_ctl_cn58xx cn58xxp1;
+} cvmx_lmcx_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ctl1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t ecc_adr:1;
+ uint64_t forcewrite:4;
+ uint64_t idlepower:3;
+ uint64_t sequence:3;
+ uint64_t sil_mode:1;
+ uint64_t dcc_enable:1;
+ uint64_t reserved_2_7:6;
+ uint64_t data_layout:2;
+#else
+ uint64_t data_layout:2;
+ uint64_t reserved_2_7:6;
+ uint64_t dcc_enable:1;
+ uint64_t sil_mode:1;
+ uint64_t sequence:3;
+ uint64_t idlepower:3;
+ uint64_t forcewrite:4;
+ uint64_t ecc_adr:1;
+ uint64_t reserved_21_63:43;
+#endif
+ } s;
+ struct cvmx_lmcx_ctl1_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t data_layout:2;
+#else
+ uint64_t data_layout:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn30xx;
+ struct cvmx_lmcx_ctl1_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t sil_mode:1;
+ uint64_t dcc_enable:1;
+ uint64_t reserved_2_7:6;
+ uint64_t data_layout:2;
+#else
+ uint64_t data_layout:2;
+ uint64_t reserved_2_7:6;
+ uint64_t dcc_enable:1;
+ uint64_t sil_mode:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn50xx;
+ struct cvmx_lmcx_ctl1_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t ecc_adr:1;
+ uint64_t forcewrite:4;
+ uint64_t idlepower:3;
+ uint64_t sequence:3;
+ uint64_t sil_mode:1;
+ uint64_t dcc_enable:1;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t dcc_enable:1;
+ uint64_t sil_mode:1;
+ uint64_t sequence:3;
+ uint64_t idlepower:3;
+ uint64_t forcewrite:4;
+ uint64_t ecc_adr:1;
+ uint64_t reserved_21_63:43;
+#endif
+ } cn52xx;
+ struct cvmx_lmcx_ctl1_cn52xx cn52xxp1;
+ struct cvmx_lmcx_ctl1_cn52xx cn56xx;
+ struct cvmx_lmcx_ctl1_cn52xx cn56xxp1;
+ struct cvmx_lmcx_ctl1_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t sil_mode:1;
+ uint64_t dcc_enable:1;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t dcc_enable:1;
+ uint64_t sil_mode:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn58xx;
+ struct cvmx_lmcx_ctl1_cn58xx cn58xxp1;
+} cvmx_lmcx_ctl1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_dclk_cnt_hi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dclkcnt_hi:32;
+#else
+ uint64_t dclkcnt_hi:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn30xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn31xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn38xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn50xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn52xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn56xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn58xx;
+ struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1;
+} cvmx_lmcx_dclk_cnt_hi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_dclk_cnt_lo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dclkcnt_lo:32;
+#else
+ uint64_t dclkcnt_lo:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn30xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn31xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn38xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn50xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn52xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn56xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn58xx;
+ struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1;
+} cvmx_lmcx_dclk_cnt_lo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_dclk_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t off90_ena:1;
+ uint64_t dclk90_byp:1;
+ uint64_t dclk90_ld:1;
+ uint64_t dclk90_vlu:5;
+#else
+ uint64_t dclk90_vlu:5;
+ uint64_t dclk90_ld:1;
+ uint64_t dclk90_byp:1;
+ uint64_t off90_ena:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_lmcx_dclk_ctl_s cn56xx;
+ struct cvmx_lmcx_dclk_ctl_s cn56xxp1;
+} cvmx_lmcx_dclk_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ddr2_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bank8:1;
+ uint64_t burst8:1;
+ uint64_t addlat:3;
+ uint64_t pocas:1;
+ uint64_t bwcnt:1;
+ uint64_t twr:3;
+ uint64_t silo_hc:1;
+ uint64_t ddr_eof:4;
+ uint64_t tfaw:5;
+ uint64_t crip_mode:1;
+ uint64_t ddr2t:1;
+ uint64_t odt_ena:1;
+ uint64_t qdll_ena:1;
+ uint64_t dll90_vlu:5;
+ uint64_t dll90_byp:1;
+ uint64_t rdqs:1;
+ uint64_t ddr2:1;
+#else
+ uint64_t ddr2:1;
+ uint64_t rdqs:1;
+ uint64_t dll90_byp:1;
+ uint64_t dll90_vlu:5;
+ uint64_t qdll_ena:1;
+ uint64_t odt_ena:1;
+ uint64_t ddr2t:1;
+ uint64_t crip_mode:1;
+ uint64_t tfaw:5;
+ uint64_t ddr_eof:4;
+ uint64_t silo_hc:1;
+ uint64_t twr:3;
+ uint64_t bwcnt:1;
+ uint64_t pocas:1;
+ uint64_t addlat:3;
+ uint64_t burst8:1;
+ uint64_t bank8:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ddr2_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bank8:1;
+ uint64_t burst8:1;
+ uint64_t addlat:3;
+ uint64_t pocas:1;
+ uint64_t bwcnt:1;
+ uint64_t twr:3;
+ uint64_t silo_hc:1;
+ uint64_t ddr_eof:4;
+ uint64_t tfaw:5;
+ uint64_t crip_mode:1;
+ uint64_t ddr2t:1;
+ uint64_t odt_ena:1;
+ uint64_t qdll_ena:1;
+ uint64_t dll90_vlu:5;
+ uint64_t dll90_byp:1;
+ uint64_t reserved_1_1:1;
+ uint64_t ddr2:1;
+#else
+ uint64_t ddr2:1;
+ uint64_t reserved_1_1:1;
+ uint64_t dll90_byp:1;
+ uint64_t dll90_vlu:5;
+ uint64_t qdll_ena:1;
+ uint64_t odt_ena:1;
+ uint64_t ddr2t:1;
+ uint64_t crip_mode:1;
+ uint64_t tfaw:5;
+ uint64_t ddr_eof:4;
+ uint64_t silo_hc:1;
+ uint64_t twr:3;
+ uint64_t bwcnt:1;
+ uint64_t pocas:1;
+ uint64_t addlat:3;
+ uint64_t burst8:1;
+ uint64_t bank8:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn38xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn38xxp2;
+ struct cvmx_lmcx_ddr2_ctl_s cn50xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn52xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn52xxp1;
+ struct cvmx_lmcx_ddr2_ctl_s cn56xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn56xxp1;
+ struct cvmx_lmcx_ddr2_ctl_s cn58xx;
+ struct cvmx_lmcx_ddr2_ctl_s cn58xxp1;
+} cvmx_lmcx_ddr2_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_delay_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t dq:5;
+ uint64_t cmd:5;
+ uint64_t clk:5;
+#else
+ uint64_t clk:5;
+ uint64_t cmd:5;
+ uint64_t dq:5;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_lmcx_delay_cfg_s cn30xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t dq:4;
+ uint64_t reserved_9_9:1;
+ uint64_t cmd:4;
+ uint64_t reserved_4_4:1;
+ uint64_t clk:4;
+#else
+ uint64_t clk:4;
+ uint64_t reserved_4_4:1;
+ uint64_t cmd:4;
+ uint64_t reserved_9_9:1;
+ uint64_t dq:4;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn38xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn50xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn52xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn56xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn58xx;
+ struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1;
+} cvmx_lmcx_delay_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_dll_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dreset:1;
+ uint64_t dll90_byp:1;
+ uint64_t dll90_ena:1;
+ uint64_t dll90_vlu:5;
+#else
+ uint64_t dll90_vlu:5;
+ uint64_t dll90_ena:1;
+ uint64_t dll90_byp:1;
+ uint64_t dreset:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_lmcx_dll_ctl_s cn52xx;
+ struct cvmx_lmcx_dll_ctl_s cn52xxp1;
+ struct cvmx_lmcx_dll_ctl_s cn56xx;
+ struct cvmx_lmcx_dll_ctl_s cn56xxp1;
+} cvmx_lmcx_dll_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_dual_memcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t bank8:1;
+ uint64_t row_lsb:3;
+ uint64_t reserved_8_15:8;
+ uint64_t cs_mask:8;
+#else
+ uint64_t cs_mask:8;
+ uint64_t reserved_8_15:8;
+ uint64_t row_lsb:3;
+ uint64_t bank8:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_lmcx_dual_memcfg_s cn50xx;
+ struct cvmx_lmcx_dual_memcfg_s cn52xx;
+ struct cvmx_lmcx_dual_memcfg_s cn52xxp1;
+ struct cvmx_lmcx_dual_memcfg_s cn56xx;
+ struct cvmx_lmcx_dual_memcfg_s cn56xxp1;
+ struct cvmx_lmcx_dual_memcfg_s cn58xx;
+ struct cvmx_lmcx_dual_memcfg_s cn58xxp1;
+} cvmx_lmcx_dual_memcfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ecc_synd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t mrdsyn3:8;
+ uint64_t mrdsyn2:8;
+ uint64_t mrdsyn1:8;
+ uint64_t mrdsyn0:8;
+#else
+ uint64_t mrdsyn0:8;
+ uint64_t mrdsyn1:8;
+ uint64_t mrdsyn2:8;
+ uint64_t mrdsyn3:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ecc_synd_s cn30xx;
+ struct cvmx_lmcx_ecc_synd_s cn31xx;
+ struct cvmx_lmcx_ecc_synd_s cn38xx;
+ struct cvmx_lmcx_ecc_synd_s cn38xxp2;
+ struct cvmx_lmcx_ecc_synd_s cn50xx;
+ struct cvmx_lmcx_ecc_synd_s cn52xx;
+ struct cvmx_lmcx_ecc_synd_s cn52xxp1;
+ struct cvmx_lmcx_ecc_synd_s cn56xx;
+ struct cvmx_lmcx_ecc_synd_s cn56xxp1;
+ struct cvmx_lmcx_ecc_synd_s cn58xx;
+ struct cvmx_lmcx_ecc_synd_s cn58xxp1;
+} cvmx_lmcx_ecc_synd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_fadr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t fdimm:2;
+ uint64_t fbunk:1;
+ uint64_t fbank:3;
+ uint64_t frow:14;
+ uint64_t fcol:12;
+#else
+ uint64_t fcol:12;
+ uint64_t frow:14;
+ uint64_t fbank:3;
+ uint64_t fbunk:1;
+ uint64_t fdimm:2;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_fadr_s cn30xx;
+ struct cvmx_lmcx_fadr_s cn31xx;
+ struct cvmx_lmcx_fadr_s cn38xx;
+ struct cvmx_lmcx_fadr_s cn38xxp2;
+ struct cvmx_lmcx_fadr_s cn50xx;
+ struct cvmx_lmcx_fadr_s cn52xx;
+ struct cvmx_lmcx_fadr_s cn52xxp1;
+ struct cvmx_lmcx_fadr_s cn56xx;
+ struct cvmx_lmcx_fadr_s cn56xxp1;
+ struct cvmx_lmcx_fadr_s cn58xx;
+ struct cvmx_lmcx_fadr_s cn58xxp1;
+} cvmx_lmcx_fadr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ifb_cnt_hi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ifbcnt_hi:32;
+#else
+ uint64_t ifbcnt_hi:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn30xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn31xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn38xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn50xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn52xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn56xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn58xx;
+ struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1;
+} cvmx_lmcx_ifb_cnt_hi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ifb_cnt_lo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ifbcnt_lo:32;
+#else
+ uint64_t ifbcnt_lo:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn30xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn31xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn38xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn50xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn52xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn56xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn58xx;
+ struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1;
+} cvmx_lmcx_ifb_cnt_lo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_mem_cfg0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t reset:1;
+ uint64_t silo_qc:1;
+ uint64_t bunk_ena:1;
+ uint64_t ded_err:4;
+ uint64_t sec_err:4;
+ uint64_t intr_ded_ena:1;
+ uint64_t intr_sec_ena:1;
+ uint64_t tcl:4;
+ uint64_t ref_int:6;
+ uint64_t pbank_lsb:4;
+ uint64_t row_lsb:3;
+ uint64_t ecc_ena:1;
+ uint64_t init_start:1;
+#else
+ uint64_t init_start:1;
+ uint64_t ecc_ena:1;
+ uint64_t row_lsb:3;
+ uint64_t pbank_lsb:4;
+ uint64_t ref_int:6;
+ uint64_t tcl:4;
+ uint64_t intr_sec_ena:1;
+ uint64_t intr_ded_ena:1;
+ uint64_t sec_err:4;
+ uint64_t ded_err:4;
+ uint64_t bunk_ena:1;
+ uint64_t silo_qc:1;
+ uint64_t reset:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_mem_cfg0_s cn30xx;
+ struct cvmx_lmcx_mem_cfg0_s cn31xx;
+ struct cvmx_lmcx_mem_cfg0_s cn38xx;
+ struct cvmx_lmcx_mem_cfg0_s cn38xxp2;
+ struct cvmx_lmcx_mem_cfg0_s cn50xx;
+ struct cvmx_lmcx_mem_cfg0_s cn52xx;
+ struct cvmx_lmcx_mem_cfg0_s cn52xxp1;
+ struct cvmx_lmcx_mem_cfg0_s cn56xx;
+ struct cvmx_lmcx_mem_cfg0_s cn56xxp1;
+ struct cvmx_lmcx_mem_cfg0_s cn58xx;
+ struct cvmx_lmcx_mem_cfg0_s cn58xxp1;
+} cvmx_lmcx_mem_cfg0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_mem_cfg1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t comp_bypass:1;
+ uint64_t trrd:3;
+ uint64_t caslat:3;
+ uint64_t tmrd:3;
+ uint64_t trfc:5;
+ uint64_t trp:4;
+ uint64_t twtr:4;
+ uint64_t trcd:4;
+ uint64_t tras:5;
+#else
+ uint64_t tras:5;
+ uint64_t trcd:4;
+ uint64_t twtr:4;
+ uint64_t trp:4;
+ uint64_t trfc:5;
+ uint64_t tmrd:3;
+ uint64_t caslat:3;
+ uint64_t trrd:3;
+ uint64_t comp_bypass:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_mem_cfg1_s cn30xx;
+ struct cvmx_lmcx_mem_cfg1_s cn31xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t trrd:3;
+ uint64_t caslat:3;
+ uint64_t tmrd:3;
+ uint64_t trfc:5;
+ uint64_t trp:4;
+ uint64_t twtr:4;
+ uint64_t trcd:4;
+ uint64_t tras:5;
+#else
+ uint64_t tras:5;
+ uint64_t trcd:4;
+ uint64_t twtr:4;
+ uint64_t trp:4;
+ uint64_t trfc:5;
+ uint64_t tmrd:3;
+ uint64_t caslat:3;
+ uint64_t trrd:3;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn38xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2;
+ struct cvmx_lmcx_mem_cfg1_s cn50xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx;
+ struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1;
+} cvmx_lmcx_mem_cfg1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_nxm_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t cs_mask:8;
+#else
+ uint64_t cs_mask:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_lmcx_nxm_s cn52xx;
+ struct cvmx_lmcx_nxm_s cn56xx;
+ struct cvmx_lmcx_nxm_s cn58xx;
+} cvmx_lmcx_nxm_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ops_cnt_hi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t opscnt_hi:32;
+#else
+ uint64_t opscnt_hi:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ops_cnt_hi_s cn30xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn31xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn38xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2;
+ struct cvmx_lmcx_ops_cnt_hi_s cn50xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn52xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1;
+ struct cvmx_lmcx_ops_cnt_hi_s cn56xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1;
+ struct cvmx_lmcx_ops_cnt_hi_s cn58xx;
+ struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1;
+} cvmx_lmcx_ops_cnt_hi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_ops_cnt_lo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t opscnt_lo:32;
+#else
+ uint64_t opscnt_lo:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_ops_cnt_lo_s cn30xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn31xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn38xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2;
+ struct cvmx_lmcx_ops_cnt_lo_s cn50xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn52xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1;
+ struct cvmx_lmcx_ops_cnt_lo_s cn56xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1;
+ struct cvmx_lmcx_ops_cnt_lo_s cn58xx;
+ struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1;
+} cvmx_lmcx_ops_cnt_lo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_pll_bwctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t bwupd:1;
+ uint64_t bwctl:4;
+#else
+ uint64_t bwctl:4;
+ uint64_t bwupd:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_lmcx_pll_bwctl_s cn30xx;
+ struct cvmx_lmcx_pll_bwctl_s cn31xx;
+ struct cvmx_lmcx_pll_bwctl_s cn38xx;
+ struct cvmx_lmcx_pll_bwctl_s cn38xxp2;
+} cvmx_lmcx_pll_bwctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_pll_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_30_63:34;
+ uint64_t bypass:1;
+ uint64_t fasten_n:1;
+ uint64_t div_reset:1;
+ uint64_t reset_n:1;
+ uint64_t clkf:12;
+ uint64_t clkr:6;
+ uint64_t reserved_6_7:2;
+ uint64_t en16:1;
+ uint64_t en12:1;
+ uint64_t en8:1;
+ uint64_t en6:1;
+ uint64_t en4:1;
+ uint64_t en2:1;
+#else
+ uint64_t en2:1;
+ uint64_t en4:1;
+ uint64_t en6:1;
+ uint64_t en8:1;
+ uint64_t en12:1;
+ uint64_t en16:1;
+ uint64_t reserved_6_7:2;
+ uint64_t clkr:6;
+ uint64_t clkf:12;
+ uint64_t reset_n:1;
+ uint64_t div_reset:1;
+ uint64_t fasten_n:1;
+ uint64_t bypass:1;
+ uint64_t reserved_30_63:34;
+#endif
+ } s;
+ struct cvmx_lmcx_pll_ctl_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t fasten_n:1;
+ uint64_t div_reset:1;
+ uint64_t reset_n:1;
+ uint64_t clkf:12;
+ uint64_t clkr:6;
+ uint64_t reserved_6_7:2;
+ uint64_t en16:1;
+ uint64_t en12:1;
+ uint64_t en8:1;
+ uint64_t en6:1;
+ uint64_t en4:1;
+ uint64_t en2:1;
+#else
+ uint64_t en2:1;
+ uint64_t en4:1;
+ uint64_t en6:1;
+ uint64_t en8:1;
+ uint64_t en12:1;
+ uint64_t en16:1;
+ uint64_t reserved_6_7:2;
+ uint64_t clkr:6;
+ uint64_t clkf:12;
+ uint64_t reset_n:1;
+ uint64_t div_reset:1;
+ uint64_t fasten_n:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn50xx;
+ struct cvmx_lmcx_pll_ctl_s cn52xx;
+ struct cvmx_lmcx_pll_ctl_s cn52xxp1;
+ struct cvmx_lmcx_pll_ctl_cn50xx cn56xx;
+ struct cvmx_lmcx_pll_ctl_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t div_reset:1;
+ uint64_t reset_n:1;
+ uint64_t clkf:12;
+ uint64_t clkr:6;
+ uint64_t reserved_6_7:2;
+ uint64_t en16:1;
+ uint64_t en12:1;
+ uint64_t en8:1;
+ uint64_t en6:1;
+ uint64_t en4:1;
+ uint64_t en2:1;
+#else
+ uint64_t en2:1;
+ uint64_t en4:1;
+ uint64_t en6:1;
+ uint64_t en8:1;
+ uint64_t en12:1;
+ uint64_t en16:1;
+ uint64_t reserved_6_7:2;
+ uint64_t clkr:6;
+ uint64_t clkf:12;
+ uint64_t reset_n:1;
+ uint64_t div_reset:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn56xxp1;
+ struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx;
+ struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1;
+} cvmx_lmcx_pll_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_pll_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ddr__nctl:5;
+ uint64_t ddr__pctl:5;
+ uint64_t reserved_2_21:20;
+ uint64_t rfslip:1;
+ uint64_t fbslip:1;
+#else
+ uint64_t fbslip:1;
+ uint64_t rfslip:1;
+ uint64_t reserved_2_21:20;
+ uint64_t ddr__pctl:5;
+ uint64_t ddr__nctl:5;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_pll_status_s cn50xx;
+ struct cvmx_lmcx_pll_status_s cn52xx;
+ struct cvmx_lmcx_pll_status_s cn52xxp1;
+ struct cvmx_lmcx_pll_status_s cn56xx;
+ struct cvmx_lmcx_pll_status_s cn56xxp1;
+ struct cvmx_lmcx_pll_status_s cn58xx;
+ struct cvmx_lmcx_pll_status_cn58xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t rfslip:1;
+ uint64_t fbslip:1;
+#else
+ uint64_t fbslip:1;
+ uint64_t rfslip:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn58xxp1;
+} cvmx_lmcx_pll_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_read_level_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t rankmask:4;
+ uint64_t pattern:8;
+ uint64_t row:16;
+ uint64_t col:12;
+ uint64_t reserved_3_3:1;
+ uint64_t bnk:3;
+#else
+ uint64_t bnk:3;
+ uint64_t reserved_3_3:1;
+ uint64_t col:12;
+ uint64_t row:16;
+ uint64_t pattern:8;
+ uint64_t rankmask:4;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_lmcx_read_level_ctl_s cn52xx;
+ struct cvmx_lmcx_read_level_ctl_s cn52xxp1;
+ struct cvmx_lmcx_read_level_ctl_s cn56xx;
+ struct cvmx_lmcx_read_level_ctl_s cn56xxp1;
+} cvmx_lmcx_read_level_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_read_level_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bitmask:16;
+ uint64_t reserved_4_15:12;
+ uint64_t byte:4;
+#else
+ uint64_t byte:4;
+ uint64_t reserved_4_15:12;
+ uint64_t bitmask:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_read_level_dbg_s cn52xx;
+ struct cvmx_lmcx_read_level_dbg_s cn52xxp1;
+ struct cvmx_lmcx_read_level_dbg_s cn56xx;
+ struct cvmx_lmcx_read_level_dbg_s cn56xxp1;
+} cvmx_lmcx_read_level_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_read_level_rankx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t status:2;
+ uint64_t byte8:4;
+ uint64_t byte7:4;
+ uint64_t byte6:4;
+ uint64_t byte5:4;
+ uint64_t byte4:4;
+ uint64_t byte3:4;
+ uint64_t byte2:4;
+ uint64_t byte1:4;
+ uint64_t byte0:4;
+#else
+ uint64_t byte0:4;
+ uint64_t byte1:4;
+ uint64_t byte2:4;
+ uint64_t byte3:4;
+ uint64_t byte4:4;
+ uint64_t byte5:4;
+ uint64_t byte6:4;
+ uint64_t byte7:4;
+ uint64_t byte8:4;
+ uint64_t status:2;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_lmcx_read_level_rankx_s cn52xx;
+ struct cvmx_lmcx_read_level_rankx_s cn52xxp1;
+ struct cvmx_lmcx_read_level_rankx_s cn56xx;
+ struct cvmx_lmcx_read_level_rankx_s cn56xxp1;
+} cvmx_lmcx_read_level_rankx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_rodt_comp_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t enable:1;
+ uint64_t reserved_12_15:4;
+ uint64_t nctl:4;
+ uint64_t reserved_5_7:3;
+ uint64_t pctl:5;
+#else
+ uint64_t pctl:5;
+ uint64_t reserved_5_7:3;
+ uint64_t nctl:4;
+ uint64_t reserved_12_15:4;
+ uint64_t enable:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn50xx;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn52xx;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn56xx;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn58xx;
+ struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1;
+} cvmx_lmcx_rodt_comp_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_rodt_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rodt_hi3:4;
+ uint64_t rodt_hi2:4;
+ uint64_t rodt_hi1:4;
+ uint64_t rodt_hi0:4;
+ uint64_t rodt_lo3:4;
+ uint64_t rodt_lo2:4;
+ uint64_t rodt_lo1:4;
+ uint64_t rodt_lo0:4;
+#else
+ uint64_t rodt_lo0:4;
+ uint64_t rodt_lo1:4;
+ uint64_t rodt_lo2:4;
+ uint64_t rodt_lo3:4;
+ uint64_t rodt_hi0:4;
+ uint64_t rodt_hi1:4;
+ uint64_t rodt_hi2:4;
+ uint64_t rodt_hi3:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_rodt_ctl_s cn30xx;
+ struct cvmx_lmcx_rodt_ctl_s cn31xx;
+ struct cvmx_lmcx_rodt_ctl_s cn38xx;
+ struct cvmx_lmcx_rodt_ctl_s cn38xxp2;
+ struct cvmx_lmcx_rodt_ctl_s cn50xx;
+ struct cvmx_lmcx_rodt_ctl_s cn52xx;
+ struct cvmx_lmcx_rodt_ctl_s cn52xxp1;
+ struct cvmx_lmcx_rodt_ctl_s cn56xx;
+ struct cvmx_lmcx_rodt_ctl_s cn56xxp1;
+ struct cvmx_lmcx_rodt_ctl_s cn58xx;
+ struct cvmx_lmcx_rodt_ctl_s cn58xxp1;
+} cvmx_lmcx_rodt_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_wodt_ctl0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wodt_d1_r1:8;
+ uint64_t wodt_d1_r0:8;
+ uint64_t wodt_d0_r1:8;
+ uint64_t wodt_d0_r0:8;
+#else
+ uint64_t wodt_d0_r0:8;
+ uint64_t wodt_d0_r1:8;
+ uint64_t wodt_d1_r0:8;
+ uint64_t wodt_d1_r1:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx;
+ struct cvmx_lmcx_wodt_ctl0_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wodt_hi3:4;
+ uint64_t wodt_hi2:4;
+ uint64_t wodt_hi1:4;
+ uint64_t wodt_hi0:4;
+ uint64_t wodt_lo3:4;
+ uint64_t wodt_lo2:4;
+ uint64_t wodt_lo1:4;
+ uint64_t wodt_lo0:4;
+#else
+ uint64_t wodt_lo0:4;
+ uint64_t wodt_lo1:4;
+ uint64_t wodt_lo2:4;
+ uint64_t wodt_lo3:4;
+ uint64_t wodt_hi0:4;
+ uint64_t wodt_hi1:4;
+ uint64_t wodt_hi2:4;
+ uint64_t wodt_hi3:4;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2;
+ struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx;
+ struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1;
+ struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx;
+ struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1;
+} cvmx_lmcx_wodt_ctl0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_lmcx_wodt_ctl1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wodt_d3_r1:8;
+ uint64_t wodt_d3_r0:8;
+ uint64_t wodt_d2_r1:8;
+ uint64_t wodt_d2_r0:8;
+#else
+ uint64_t wodt_d2_r0:8;
+ uint64_t wodt_d2_r1:8;
+ uint64_t wodt_d3_r0:8;
+ uint64_t wodt_d3_r1:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_lmcx_wodt_ctl1_s cn30xx;
+ struct cvmx_lmcx_wodt_ctl1_s cn31xx;
+ struct cvmx_lmcx_wodt_ctl1_s cn52xx;
+ struct cvmx_lmcx_wodt_ctl1_s cn52xxp1;
+ struct cvmx_lmcx_wodt_ctl1_s cn56xx;
+ struct cvmx_lmcx_wodt_ctl1_s cn56xxp1;
+} cvmx_lmcx_wodt_ctl1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_bist_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_boot_bist_stat_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ncbo_1:1;
+ uint64_t ncbo_0:1;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t ncbo_0:1;
+ uint64_t ncbo_1:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
+ struct cvmx_mio_boot_bist_stat_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t ncbo_0:1;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t ncbo_0:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn38xx;
+ struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
+ struct cvmx_mio_boot_bist_stat_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t pcm_1:1;
+ uint64_t pcm_0:1;
+ uint64_t ncbo_1:1;
+ uint64_t ncbo_0:1;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t ncbo_0:1;
+ uint64_t ncbo_1:1;
+ uint64_t pcm_0:1;
+ uint64_t pcm_1:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } cn50xx;
+ struct cvmx_mio_boot_bist_stat_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t ndf:2;
+ uint64_t ncbo_0:1;
+ uint64_t dma:1;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t dma:1;
+ uint64_t ncbo_0:1;
+ uint64_t ndf:2;
+ uint64_t reserved_6_63:58;
+#endif
+ } cn52xx;
+ struct cvmx_mio_boot_bist_stat_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t ncbo_0:1;
+ uint64_t dma:1;
+ uint64_t loc:1;
+ uint64_t ncbi:1;
+#else
+ uint64_t ncbi:1;
+ uint64_t loc:1;
+ uint64_t dma:1;
+ uint64_t ncbo_0:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn52xxp1;
+ struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
+ struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
+ struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
+ struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+} cvmx_mio_boot_bist_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_comp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pctl:5;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t pctl:5;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_mio_boot_comp_s cn50xx;
+ struct cvmx_mio_boot_comp_s cn52xx;
+ struct cvmx_mio_boot_comp_s cn52xxp1;
+ struct cvmx_mio_boot_comp_s cn56xx;
+ struct cvmx_mio_boot_comp_s cn56xxp1;
+} cvmx_mio_boot_comp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_dma_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t en:1;
+ uint64_t rw:1;
+ uint64_t clr:1;
+ uint64_t reserved_60_60:1;
+ uint64_t swap32:1;
+ uint64_t swap16:1;
+ uint64_t swap8:1;
+ uint64_t endian:1;
+ uint64_t size:20;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t size:20;
+ uint64_t endian:1;
+ uint64_t swap8:1;
+ uint64_t swap16:1;
+ uint64_t swap32:1;
+ uint64_t reserved_60_60:1;
+ uint64_t clr:1;
+ uint64_t rw:1;
+ uint64_t en:1;
+#endif
+ } s;
+ struct cvmx_mio_boot_dma_cfgx_s cn52xx;
+ struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
+ struct cvmx_mio_boot_dma_cfgx_s cn56xx;
+ struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+} cvmx_mio_boot_dma_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_dma_intx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dmarq:1;
+ uint64_t done:1;
+#else
+ uint64_t done:1;
+ uint64_t dmarq:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_boot_dma_intx_s cn52xx;
+ struct cvmx_mio_boot_dma_intx_s cn52xxp1;
+ struct cvmx_mio_boot_dma_intx_s cn56xx;
+ struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+} cvmx_mio_boot_dma_intx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_dma_int_enx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dmarq:1;
+ uint64_t done:1;
+#else
+ uint64_t done:1;
+ uint64_t dmarq:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_boot_dma_int_enx_s cn52xx;
+ struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
+ struct cvmx_mio_boot_dma_int_enx_s cn56xx;
+ struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+} cvmx_mio_boot_dma_int_enx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_dma_timx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dmack_pi:1;
+ uint64_t dmarq_pi:1;
+ uint64_t tim_mult:2;
+ uint64_t rd_dly:3;
+ uint64_t ddr:1;
+ uint64_t width:1;
+ uint64_t reserved_48_54:7;
+ uint64_t pause:6;
+ uint64_t dmack_h:6;
+ uint64_t we_n:6;
+ uint64_t we_a:6;
+ uint64_t oe_n:6;
+ uint64_t oe_a:6;
+ uint64_t dmack_s:6;
+ uint64_t dmarq:6;
+#else
+ uint64_t dmarq:6;
+ uint64_t dmack_s:6;
+ uint64_t oe_a:6;
+ uint64_t oe_n:6;
+ uint64_t we_a:6;
+ uint64_t we_n:6;
+ uint64_t dmack_h:6;
+ uint64_t pause:6;
+ uint64_t reserved_48_54:7;
+ uint64_t width:1;
+ uint64_t ddr:1;
+ uint64_t rd_dly:3;
+ uint64_t tim_mult:2;
+ uint64_t dmarq_pi:1;
+ uint64_t dmack_pi:1;
+#endif
+ } s;
+ struct cvmx_mio_boot_dma_timx_s cn52xx;
+ struct cvmx_mio_boot_dma_timx_s cn52xxp1;
+ struct cvmx_mio_boot_dma_timx_s cn56xx;
+ struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+} cvmx_mio_boot_dma_timx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t wait_err:1;
+ uint64_t adr_err:1;
+#else
+ uint64_t adr_err:1;
+ uint64_t wait_err:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_boot_err_s cn30xx;
+ struct cvmx_mio_boot_err_s cn31xx;
+ struct cvmx_mio_boot_err_s cn38xx;
+ struct cvmx_mio_boot_err_s cn38xxp2;
+ struct cvmx_mio_boot_err_s cn50xx;
+ struct cvmx_mio_boot_err_s cn52xx;
+ struct cvmx_mio_boot_err_s cn52xxp1;
+ struct cvmx_mio_boot_err_s cn56xx;
+ struct cvmx_mio_boot_err_s cn56xxp1;
+ struct cvmx_mio_boot_err_s cn58xx;
+ struct cvmx_mio_boot_err_s cn58xxp1;
+} cvmx_mio_boot_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t wait_int:1;
+ uint64_t adr_int:1;
+#else
+ uint64_t adr_int:1;
+ uint64_t wait_int:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_boot_int_s cn30xx;
+ struct cvmx_mio_boot_int_s cn31xx;
+ struct cvmx_mio_boot_int_s cn38xx;
+ struct cvmx_mio_boot_int_s cn38xxp2;
+ struct cvmx_mio_boot_int_s cn50xx;
+ struct cvmx_mio_boot_int_s cn52xx;
+ struct cvmx_mio_boot_int_s cn52xxp1;
+ struct cvmx_mio_boot_int_s cn56xx;
+ struct cvmx_mio_boot_int_s cn56xxp1;
+ struct cvmx_mio_boot_int_s cn58xx;
+ struct cvmx_mio_boot_int_s cn58xxp1;
+} cvmx_mio_boot_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_loc_adr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t adr:5;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t adr:5;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_boot_loc_adr_s cn30xx;
+ struct cvmx_mio_boot_loc_adr_s cn31xx;
+ struct cvmx_mio_boot_loc_adr_s cn38xx;
+ struct cvmx_mio_boot_loc_adr_s cn38xxp2;
+ struct cvmx_mio_boot_loc_adr_s cn50xx;
+ struct cvmx_mio_boot_loc_adr_s cn52xx;
+ struct cvmx_mio_boot_loc_adr_s cn52xxp1;
+ struct cvmx_mio_boot_loc_adr_s cn56xx;
+ struct cvmx_mio_boot_loc_adr_s cn56xxp1;
+ struct cvmx_mio_boot_loc_adr_s cn58xx;
+ struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+} cvmx_mio_boot_loc_adr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_loc_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t en:1;
+ uint64_t reserved_28_30:3;
+ uint64_t base:25;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t base:25;
+ uint64_t reserved_28_30:3;
+ uint64_t en:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_mio_boot_loc_cfgx_s cn30xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn31xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn38xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
+ struct cvmx_mio_boot_loc_cfgx_s cn50xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn52xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
+ struct cvmx_mio_boot_loc_cfgx_s cn56xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
+ struct cvmx_mio_boot_loc_cfgx_s cn58xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+} cvmx_mio_boot_loc_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_loc_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_mio_boot_loc_dat_s cn30xx;
+ struct cvmx_mio_boot_loc_dat_s cn31xx;
+ struct cvmx_mio_boot_loc_dat_s cn38xx;
+ struct cvmx_mio_boot_loc_dat_s cn38xxp2;
+ struct cvmx_mio_boot_loc_dat_s cn50xx;
+ struct cvmx_mio_boot_loc_dat_s cn52xx;
+ struct cvmx_mio_boot_loc_dat_s cn52xxp1;
+ struct cvmx_mio_boot_loc_dat_s cn56xx;
+ struct cvmx_mio_boot_loc_dat_s cn56xxp1;
+ struct cvmx_mio_boot_loc_dat_s cn58xx;
+ struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+} cvmx_mio_boot_loc_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_pin_defs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t dmack_p2:1;
+ uint64_t dmack_p1:1;
+ uint64_t dmack_p0:1;
+ uint64_t term:2;
+ uint64_t nand:1;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t nand:1;
+ uint64_t term:2;
+ uint64_t dmack_p0:1;
+ uint64_t dmack_p1:1;
+ uint64_t dmack_p2:1;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_mio_boot_pin_defs_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t reserved_13_13:1;
+ uint64_t dmack_p1:1;
+ uint64_t dmack_p0:1;
+ uint64_t term:2;
+ uint64_t nand:1;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t nand:1;
+ uint64_t term:2;
+ uint64_t dmack_p0:1;
+ uint64_t dmack_p1:1;
+ uint64_t reserved_13_13:1;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn52xx;
+ struct cvmx_mio_boot_pin_defs_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t dmack_p2:1;
+ uint64_t dmack_p1:1;
+ uint64_t dmack_p0:1;
+ uint64_t term:2;
+ uint64_t reserved_0_8:9;
+#else
+ uint64_t reserved_0_8:9;
+ uint64_t term:2;
+ uint64_t dmack_p0:1;
+ uint64_t dmack_p1:1;
+ uint64_t dmack_p2:1;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn56xx;
+} cvmx_mio_boot_pin_defs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_reg_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t dmack:2;
+ uint64_t tim_mult:2;
+ uint64_t rd_dly:3;
+ uint64_t sam:1;
+ uint64_t we_ext:2;
+ uint64_t oe_ext:2;
+ uint64_t en:1;
+ uint64_t orbit:1;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t size:12;
+ uint64_t base:16;
+#else
+ uint64_t base:16;
+ uint64_t size:12;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t orbit:1;
+ uint64_t en:1;
+ uint64_t oe_ext:2;
+ uint64_t we_ext:2;
+ uint64_t sam:1;
+ uint64_t rd_dly:3;
+ uint64_t tim_mult:2;
+ uint64_t dmack:2;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_mio_boot_reg_cfgx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t sam:1;
+ uint64_t we_ext:2;
+ uint64_t oe_ext:2;
+ uint64_t en:1;
+ uint64_t orbit:1;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t size:12;
+ uint64_t base:16;
+#else
+ uint64_t base:16;
+ uint64_t size:12;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t orbit:1;
+ uint64_t en:1;
+ uint64_t oe_ext:2;
+ uint64_t we_ext:2;
+ uint64_t sam:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } cn30xx;
+ struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
+ struct cvmx_mio_boot_reg_cfgx_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t en:1;
+ uint64_t orbit:1;
+ uint64_t reserved_28_29:2;
+ uint64_t size:12;
+ uint64_t base:16;
+#else
+ uint64_t base:16;
+ uint64_t size:12;
+ uint64_t reserved_28_29:2;
+ uint64_t orbit:1;
+ uint64_t en:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
+ struct cvmx_mio_boot_reg_cfgx_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_42_63:22;
+ uint64_t tim_mult:2;
+ uint64_t rd_dly:3;
+ uint64_t sam:1;
+ uint64_t we_ext:2;
+ uint64_t oe_ext:2;
+ uint64_t en:1;
+ uint64_t orbit:1;
+ uint64_t ale:1;
+ uint64_t width:1;
+ uint64_t size:12;
+ uint64_t base:16;
+#else
+ uint64_t base:16;
+ uint64_t size:12;
+ uint64_t width:1;
+ uint64_t ale:1;
+ uint64_t orbit:1;
+ uint64_t en:1;
+ uint64_t oe_ext:2;
+ uint64_t we_ext:2;
+ uint64_t sam:1;
+ uint64_t rd_dly:3;
+ uint64_t tim_mult:2;
+ uint64_t reserved_42_63:22;
+#endif
+ } cn50xx;
+ struct cvmx_mio_boot_reg_cfgx_s cn52xx;
+ struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
+ struct cvmx_mio_boot_reg_cfgx_s cn56xx;
+ struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
+ struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
+ struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+} cvmx_mio_boot_reg_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_reg_timx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pagem:1;
+ uint64_t waitm:1;
+ uint64_t pages:2;
+ uint64_t ale:6;
+ uint64_t page:6;
+ uint64_t wait:6;
+ uint64_t pause:6;
+ uint64_t wr_hld:6;
+ uint64_t rd_hld:6;
+ uint64_t we:6;
+ uint64_t oe:6;
+ uint64_t ce:6;
+ uint64_t adr:6;
+#else
+ uint64_t adr:6;
+ uint64_t ce:6;
+ uint64_t oe:6;
+ uint64_t we:6;
+ uint64_t rd_hld:6;
+ uint64_t wr_hld:6;
+ uint64_t pause:6;
+ uint64_t wait:6;
+ uint64_t page:6;
+ uint64_t ale:6;
+ uint64_t pages:2;
+ uint64_t waitm:1;
+ uint64_t pagem:1;
+#endif
+ } s;
+ struct cvmx_mio_boot_reg_timx_s cn30xx;
+ struct cvmx_mio_boot_reg_timx_s cn31xx;
+ struct cvmx_mio_boot_reg_timx_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pagem:1;
+ uint64_t waitm:1;
+ uint64_t pages:2;
+ uint64_t reserved_54_59:6;
+ uint64_t page:6;
+ uint64_t wait:6;
+ uint64_t pause:6;
+ uint64_t wr_hld:6;
+ uint64_t rd_hld:6;
+ uint64_t we:6;
+ uint64_t oe:6;
+ uint64_t ce:6;
+ uint64_t adr:6;
+#else
+ uint64_t adr:6;
+ uint64_t ce:6;
+ uint64_t oe:6;
+ uint64_t we:6;
+ uint64_t rd_hld:6;
+ uint64_t wr_hld:6;
+ uint64_t pause:6;
+ uint64_t wait:6;
+ uint64_t page:6;
+ uint64_t reserved_54_59:6;
+ uint64_t pages:2;
+ uint64_t waitm:1;
+ uint64_t pagem:1;
+#endif
+ } cn38xx;
+ struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
+ struct cvmx_mio_boot_reg_timx_s cn50xx;
+ struct cvmx_mio_boot_reg_timx_s cn52xx;
+ struct cvmx_mio_boot_reg_timx_s cn52xxp1;
+ struct cvmx_mio_boot_reg_timx_s cn56xx;
+ struct cvmx_mio_boot_reg_timx_s cn56xxp1;
+ struct cvmx_mio_boot_reg_timx_s cn58xx;
+ struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+} cvmx_mio_boot_reg_timx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_boot_thr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_22_63:42;
+ uint64_t dma_thr:6;
+ uint64_t reserved_14_15:2;
+ uint64_t fif_cnt:6;
+ uint64_t reserved_6_7:2;
+ uint64_t fif_thr:6;
+#else
+ uint64_t fif_thr:6;
+ uint64_t reserved_6_7:2;
+ uint64_t fif_cnt:6;
+ uint64_t reserved_14_15:2;
+ uint64_t dma_thr:6;
+ uint64_t reserved_22_63:42;
+#endif
+ } s;
+ struct cvmx_mio_boot_thr_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t fif_cnt:6;
+ uint64_t reserved_6_7:2;
+ uint64_t fif_thr:6;
+#else
+ uint64_t fif_thr:6;
+ uint64_t reserved_6_7:2;
+ uint64_t fif_cnt:6;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn30xx;
+ struct cvmx_mio_boot_thr_cn30xx cn31xx;
+ struct cvmx_mio_boot_thr_cn30xx cn38xx;
+ struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
+ struct cvmx_mio_boot_thr_cn30xx cn50xx;
+ struct cvmx_mio_boot_thr_s cn52xx;
+ struct cvmx_mio_boot_thr_s cn52xxp1;
+ struct cvmx_mio_boot_thr_s cn56xx;
+ struct cvmx_mio_boot_thr_s cn56xxp1;
+ struct cvmx_mio_boot_thr_cn30xx cn58xx;
+ struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+} cvmx_mio_boot_thr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_bnk_datx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dat:64;
+#else
+ uint64_t dat:64;
+#endif
+ } s;
+ struct cvmx_mio_fus_bnk_datx_s cn50xx;
+ struct cvmx_mio_fus_bnk_datx_s cn52xx;
+ struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
+ struct cvmx_mio_fus_bnk_datx_s cn56xx;
+ struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
+ struct cvmx_mio_fus_bnk_datx_s cn58xx;
+ struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+} cvmx_mio_fus_bnk_datx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_dat0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t man_info:32;
+#else
+ uint64_t man_info:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_mio_fus_dat0_s cn30xx;
+ struct cvmx_mio_fus_dat0_s cn31xx;
+ struct cvmx_mio_fus_dat0_s cn38xx;
+ struct cvmx_mio_fus_dat0_s cn38xxp2;
+ struct cvmx_mio_fus_dat0_s cn50xx;
+ struct cvmx_mio_fus_dat0_s cn52xx;
+ struct cvmx_mio_fus_dat0_s cn52xxp1;
+ struct cvmx_mio_fus_dat0_s cn56xx;
+ struct cvmx_mio_fus_dat0_s cn56xxp1;
+ struct cvmx_mio_fus_dat0_s cn58xx;
+ struct cvmx_mio_fus_dat0_s cn58xxp1;
+} cvmx_mio_fus_dat0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_dat1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t man_info:32;
+#else
+ uint64_t man_info:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_mio_fus_dat1_s cn30xx;
+ struct cvmx_mio_fus_dat1_s cn31xx;
+ struct cvmx_mio_fus_dat1_s cn38xx;
+ struct cvmx_mio_fus_dat1_s cn38xxp2;
+ struct cvmx_mio_fus_dat1_s cn50xx;
+ struct cvmx_mio_fus_dat1_s cn52xx;
+ struct cvmx_mio_fus_dat1_s cn52xxp1;
+ struct cvmx_mio_fus_dat1_s cn56xx;
+ struct cvmx_mio_fus_dat1_s cn56xxp1;
+ struct cvmx_mio_fus_dat1_s cn58xx;
+ struct cvmx_mio_fus_dat1_s cn58xxp1;
+} cvmx_mio_fus_dat1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_dat2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_30_31:2;
+ uint64_t nokasu:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t reserved_0_15:16;
+#else
+ uint64_t reserved_0_15:16;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nokasu:1;
+ uint64_t reserved_30_31:2;
+ uint64_t raid_en:1;
+ uint64_t fus318:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_mio_fus_dat2_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t pll_off:4;
+ uint64_t reserved_1_11:11;
+ uint64_t pp_dis:1;
+#else
+ uint64_t pp_dis:1;
+ uint64_t reserved_1_11:11;
+ uint64_t pll_off:4;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn30xx;
+ struct cvmx_mio_fus_dat2_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t pll_off:4;
+ uint64_t reserved_2_11:10;
+ uint64_t pp_dis:2;
+#else
+ uint64_t pp_dis:2;
+ uint64_t reserved_2_11:10;
+ uint64_t pll_off:4;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn31xx;
+ struct cvmx_mio_fus_dat2_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t pp_dis:16;
+#else
+ uint64_t pp_dis:16;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn38xx;
+ struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
+ struct cvmx_mio_fus_dat2_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_30_31:2;
+ uint64_t nokasu:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t reserved_2_15:14;
+ uint64_t pp_dis:2;
+#else
+ uint64_t pp_dis:2;
+ uint64_t reserved_2_15:14;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nokasu:1;
+ uint64_t reserved_30_31:2;
+ uint64_t raid_en:1;
+ uint64_t fus318:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn50xx;
+ struct cvmx_mio_fus_dat2_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_30_31:2;
+ uint64_t nokasu:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t reserved_4_15:12;
+ uint64_t pp_dis:4;
+#else
+ uint64_t pp_dis:4;
+ uint64_t reserved_4_15:12;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nokasu:1;
+ uint64_t reserved_30_31:2;
+ uint64_t raid_en:1;
+ uint64_t fus318:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn52xx;
+ struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
+ struct cvmx_mio_fus_dat2_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_30_31:2;
+ uint64_t nokasu:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t reserved_12_15:4;
+ uint64_t pp_dis:12;
+#else
+ uint64_t pp_dis:12;
+ uint64_t reserved_12_15:4;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nokasu:1;
+ uint64_t reserved_30_31:2;
+ uint64_t raid_en:1;
+ uint64_t fus318:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn56xx;
+ struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
+ struct cvmx_mio_fus_dat2_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_30_63:34;
+ uint64_t nokasu:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t rst_sht:1;
+ uint64_t bist_dis:1;
+ uint64_t chip_id:8;
+ uint64_t pp_dis:16;
+#else
+ uint64_t pp_dis:16;
+ uint64_t chip_id:8;
+ uint64_t bist_dis:1;
+ uint64_t rst_sht:1;
+ uint64_t nocrypto:1;
+ uint64_t nomul:1;
+ uint64_t nodfa_cp2:1;
+ uint64_t nokasu:1;
+ uint64_t reserved_30_63:34;
+#endif
+ } cn58xx;
+ struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+} cvmx_mio_fus_dat2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_dat3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pll_div4:1;
+ uint64_t zip_crip:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+#else
+ uint64_t icache:24;
+ uint64_t nodfa_dte:1;
+ uint64_t nozip:1;
+ uint64_t efus_ign:1;
+ uint64_t efus_lck:1;
+ uint64_t bar2_en:1;
+ uint64_t zip_crip:2;
+ uint64_t pll_div4:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_mio_fus_dat3_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pll_div4:1;
+ uint64_t reserved_29_30:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+#else
+ uint64_t icache:24;
+ uint64_t nodfa_dte:1;
+ uint64_t nozip:1;
+ uint64_t efus_ign:1;
+ uint64_t efus_lck:1;
+ uint64_t bar2_en:1;
+ uint64_t reserved_29_30:2;
+ uint64_t pll_div4:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_mio_fus_dat3_s cn31xx;
+ struct cvmx_mio_fus_dat3_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t zip_crip:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+#else
+ uint64_t icache:24;
+ uint64_t nodfa_dte:1;
+ uint64_t nozip:1;
+ uint64_t efus_ign:1;
+ uint64_t efus_lck:1;
+ uint64_t bar2_en:1;
+ uint64_t zip_crip:2;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn38xx;
+ struct cvmx_mio_fus_dat3_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+#else
+ uint64_t icache:24;
+ uint64_t nodfa_dte:1;
+ uint64_t nozip:1;
+ uint64_t efus_ign:1;
+ uint64_t efus_lck:1;
+ uint64_t bar2_en:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn38xxp2;
+ struct cvmx_mio_fus_dat3_cn38xx cn50xx;
+ struct cvmx_mio_fus_dat3_cn38xx cn52xx;
+ struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
+ struct cvmx_mio_fus_dat3_cn38xx cn56xx;
+ struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
+ struct cvmx_mio_fus_dat3_cn38xx cn58xx;
+ struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
+} cvmx_mio_fus_dat3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_ema_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t eff_ema:3;
+ uint64_t reserved_3_3:1;
+ uint64_t ema:3;
+#else
+ uint64_t ema:3;
+ uint64_t reserved_3_3:1;
+ uint64_t eff_ema:3;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mio_fus_ema_s cn50xx;
+ struct cvmx_mio_fus_ema_s cn52xx;
+ struct cvmx_mio_fus_ema_s cn52xxp1;
+ struct cvmx_mio_fus_ema_s cn56xx;
+ struct cvmx_mio_fus_ema_s cn56xxp1;
+ struct cvmx_mio_fus_ema_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t ema:2;
+#else
+ uint64_t ema:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn58xx;
+ struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+} cvmx_mio_fus_ema_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_pdf_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pdf:64;
+#else
+ uint64_t pdf:64;
+#endif
+ } s;
+ struct cvmx_mio_fus_pdf_s cn50xx;
+ struct cvmx_mio_fus_pdf_s cn52xx;
+ struct cvmx_mio_fus_pdf_s cn52xxp1;
+ struct cvmx_mio_fus_pdf_s cn56xx;
+ struct cvmx_mio_fus_pdf_s cn56xxp1;
+ struct cvmx_mio_fus_pdf_s cn58xx;
+} cvmx_mio_fus_pdf_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_pll_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t rfslip:1;
+ uint64_t fbslip:1;
+#else
+ uint64_t fbslip:1;
+ uint64_t rfslip:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_fus_pll_s cn50xx;
+ struct cvmx_mio_fus_pll_s cn52xx;
+ struct cvmx_mio_fus_pll_s cn52xxp1;
+ struct cvmx_mio_fus_pll_s cn56xx;
+ struct cvmx_mio_fus_pll_s cn56xxp1;
+ struct cvmx_mio_fus_pll_s cn58xx;
+ struct cvmx_mio_fus_pll_s cn58xxp1;
+} cvmx_mio_fus_pll_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_prog_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t prog:1;
+#else
+ uint64_t prog:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_fus_prog_s cn30xx;
+ struct cvmx_mio_fus_prog_s cn31xx;
+ struct cvmx_mio_fus_prog_s cn38xx;
+ struct cvmx_mio_fus_prog_s cn38xxp2;
+ struct cvmx_mio_fus_prog_s cn50xx;
+ struct cvmx_mio_fus_prog_s cn52xx;
+ struct cvmx_mio_fus_prog_s cn52xxp1;
+ struct cvmx_mio_fus_prog_s cn56xx;
+ struct cvmx_mio_fus_prog_s cn56xxp1;
+ struct cvmx_mio_fus_prog_s cn58xx;
+ struct cvmx_mio_fus_prog_s cn58xxp1;
+} cvmx_mio_fus_prog_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_prog_times_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_33_63:31;
+ uint64_t prog_pin:1;
+ uint64_t out:8;
+ uint64_t sclk_lo:4;
+ uint64_t sclk_hi:12;
+ uint64_t setup:8;
+#else
+ uint64_t setup:8;
+ uint64_t sclk_hi:12;
+ uint64_t sclk_lo:4;
+ uint64_t out:8;
+ uint64_t prog_pin:1;
+ uint64_t reserved_33_63:31;
+#endif
+ } s;
+ struct cvmx_mio_fus_prog_times_s cn50xx;
+ struct cvmx_mio_fus_prog_times_s cn52xx;
+ struct cvmx_mio_fus_prog_times_s cn52xxp1;
+ struct cvmx_mio_fus_prog_times_s cn56xx;
+ struct cvmx_mio_fus_prog_times_s cn56xxp1;
+ struct cvmx_mio_fus_prog_times_s cn58xx;
+ struct cvmx_mio_fus_prog_times_s cn58xxp1;
+} cvmx_mio_fus_prog_times_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_rcmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t dat:8;
+ uint64_t reserved_13_15:3;
+ uint64_t pend:1;
+ uint64_t reserved_9_11:3;
+ uint64_t efuse:1;
+ uint64_t addr:8;
+#else
+ uint64_t addr:8;
+ uint64_t efuse:1;
+ uint64_t reserved_9_11:3;
+ uint64_t pend:1;
+ uint64_t reserved_13_15:3;
+ uint64_t dat:8;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_mio_fus_rcmd_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t dat:8;
+ uint64_t reserved_13_15:3;
+ uint64_t pend:1;
+ uint64_t reserved_9_11:3;
+ uint64_t efuse:1;
+ uint64_t reserved_7_7:1;
+ uint64_t addr:7;
+#else
+ uint64_t addr:7;
+ uint64_t reserved_7_7:1;
+ uint64_t efuse:1;
+ uint64_t reserved_9_11:3;
+ uint64_t pend:1;
+ uint64_t reserved_13_15:3;
+ uint64_t dat:8;
+ uint64_t reserved_24_63:40;
+#endif
+ } cn30xx;
+ struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
+ struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
+ struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
+ struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
+ struct cvmx_mio_fus_rcmd_s cn52xx;
+ struct cvmx_mio_fus_rcmd_s cn52xxp1;
+ struct cvmx_mio_fus_rcmd_s cn56xx;
+ struct cvmx_mio_fus_rcmd_s cn56xxp1;
+ struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
+ struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+} cvmx_mio_fus_rcmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_spr_repair_res_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_42_63:22;
+ uint64_t repair2:14;
+ uint64_t repair1:14;
+ uint64_t repair0:14;
+#else
+ uint64_t repair0:14;
+ uint64_t repair1:14;
+ uint64_t repair2:14;
+ uint64_t reserved_42_63:22;
+#endif
+ } s;
+ struct cvmx_mio_fus_spr_repair_res_s cn30xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn31xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn38xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn50xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn52xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
+ struct cvmx_mio_fus_spr_repair_res_s cn56xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
+ struct cvmx_mio_fus_spr_repair_res_s cn58xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+} cvmx_mio_fus_spr_repair_res_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_spr_repair_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t too_many:1;
+#else
+ uint64_t too_many:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
+ struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
+ struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+} cvmx_mio_fus_spr_repair_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_unlock_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t key:24;
+#else
+ uint64_t key:24;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_mio_fus_unlock_s cn30xx;
+ struct cvmx_mio_fus_unlock_s cn31xx;
+} cvmx_mio_fus_unlock_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_fus_wadr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t addr:10;
+#else
+ uint64_t addr:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_mio_fus_wadr_s cn30xx;
+ struct cvmx_mio_fus_wadr_s cn31xx;
+ struct cvmx_mio_fus_wadr_s cn38xx;
+ struct cvmx_mio_fus_wadr_s cn38xxp2;
+ struct cvmx_mio_fus_wadr_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t addr:2;
+#else
+ uint64_t addr:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn50xx;
+ struct cvmx_mio_fus_wadr_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t addr:3;
+#else
+ uint64_t addr:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn52xx;
+ struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
+ struct cvmx_mio_fus_wadr_cn52xx cn56xx;
+ struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
+ struct cvmx_mio_fus_wadr_cn50xx cn58xx;
+ struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
+} cvmx_mio_fus_wadr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_ndf_dma_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t en:1;
+ uint64_t rw:1;
+ uint64_t clr:1;
+ uint64_t reserved_60_60:1;
+ uint64_t swap32:1;
+ uint64_t swap16:1;
+ uint64_t swap8:1;
+ uint64_t endian:1;
+ uint64_t size:20;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t size:20;
+ uint64_t endian:1;
+ uint64_t swap8:1;
+ uint64_t swap16:1;
+ uint64_t swap32:1;
+ uint64_t reserved_60_60:1;
+ uint64_t clr:1;
+ uint64_t rw:1;
+ uint64_t en:1;
+#endif
+ } s;
+ struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+} cvmx_mio_ndf_dma_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_ndf_dma_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t done:1;
+#else
+ uint64_t done:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_ndf_dma_int_s cn52xx;
+} cvmx_mio_ndf_dma_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_ndf_dma_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t done:1;
+#else
+ uint64_t done:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+} cvmx_mio_ndf_dma_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_pll_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t bw_ctl:5;
+#else
+ uint64_t bw_ctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_mio_pll_ctl_s cn30xx;
+ struct cvmx_mio_pll_ctl_s cn31xx;
+} cvmx_mio_pll_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_pll_setting_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t setting:17;
+#else
+ uint64_t setting:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_mio_pll_setting_s cn30xx;
+ struct cvmx_mio_pll_setting_s cn31xx;
+} cvmx_mio_pll_setting_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_twsx_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t scl:1;
+ uint64_t sda:1;
+ uint64_t scl_ovr:1;
+ uint64_t sda_ovr:1;
+ uint64_t reserved_7_7:1;
+ uint64_t core_en:1;
+ uint64_t ts_en:1;
+ uint64_t st_en:1;
+ uint64_t reserved_3_3:1;
+ uint64_t core_int:1;
+ uint64_t ts_int:1;
+ uint64_t st_int:1;
+#else
+ uint64_t st_int:1;
+ uint64_t ts_int:1;
+ uint64_t core_int:1;
+ uint64_t reserved_3_3:1;
+ uint64_t st_en:1;
+ uint64_t ts_en:1;
+ uint64_t core_en:1;
+ uint64_t reserved_7_7:1;
+ uint64_t sda_ovr:1;
+ uint64_t scl_ovr:1;
+ uint64_t sda:1;
+ uint64_t scl:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_mio_twsx_int_s cn30xx;
+ struct cvmx_mio_twsx_int_s cn31xx;
+ struct cvmx_mio_twsx_int_s cn38xx;
+ struct cvmx_mio_twsx_int_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t core_en:1;
+ uint64_t ts_en:1;
+ uint64_t st_en:1;
+ uint64_t reserved_3_3:1;
+ uint64_t core_int:1;
+ uint64_t ts_int:1;
+ uint64_t st_int:1;
+#else
+ uint64_t st_int:1;
+ uint64_t ts_int:1;
+ uint64_t core_int:1;
+ uint64_t reserved_3_3:1;
+ uint64_t st_en:1;
+ uint64_t ts_en:1;
+ uint64_t core_en:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } cn38xxp2;
+ struct cvmx_mio_twsx_int_s cn50xx;
+ struct cvmx_mio_twsx_int_s cn52xx;
+ struct cvmx_mio_twsx_int_s cn52xxp1;
+ struct cvmx_mio_twsx_int_s cn56xx;
+ struct cvmx_mio_twsx_int_s cn56xxp1;
+ struct cvmx_mio_twsx_int_s cn58xx;
+ struct cvmx_mio_twsx_int_s cn58xxp1;
+} cvmx_mio_twsx_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_twsx_sw_twsi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t v:1;
+ uint64_t slonly:1;
+ uint64_t eia:1;
+ uint64_t op:4;
+ uint64_t r:1;
+ uint64_t sovr:1;
+ uint64_t size:3;
+ uint64_t scr:2;
+ uint64_t a:10;
+ uint64_t ia:5;
+ uint64_t eop_ia:3;
+ uint64_t d:32;
+#else
+ uint64_t d:32;
+ uint64_t eop_ia:3;
+ uint64_t ia:5;
+ uint64_t a:10;
+ uint64_t scr:2;
+ uint64_t size:3;
+ uint64_t sovr:1;
+ uint64_t r:1;
+ uint64_t op:4;
+ uint64_t eia:1;
+ uint64_t slonly:1;
+ uint64_t v:1;
+#endif
+ } s;
+ struct cvmx_mio_twsx_sw_twsi_s cn30xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn31xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn38xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
+ struct cvmx_mio_twsx_sw_twsi_s cn50xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn52xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
+ struct cvmx_mio_twsx_sw_twsi_s cn56xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
+ struct cvmx_mio_twsx_sw_twsi_s cn58xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+} cvmx_mio_twsx_sw_twsi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_twsx_sw_twsi_ext_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ia:8;
+ uint64_t d:32;
+#else
+ uint64_t d:32;
+ uint64_t ia:8;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+} cvmx_mio_twsx_sw_twsi_ext_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_twsx_twsi_sw_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t v:2;
+ uint64_t reserved_32_61:30;
+ uint64_t d:32;
+#else
+ uint64_t d:32;
+ uint64_t reserved_32_61:30;
+ uint64_t v:2;
+#endif
+ } s;
+ struct cvmx_mio_twsx_twsi_sw_s cn30xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn31xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn38xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
+ struct cvmx_mio_twsx_twsi_sw_s cn50xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn52xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
+ struct cvmx_mio_twsx_twsi_sw_s cn56xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
+ struct cvmx_mio_twsx_twsi_sw_s cn58xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+} cvmx_mio_twsx_twsi_sw_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_dlh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dlh:8;
+#else
+ uint64_t dlh:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_dlh_s cn30xx;
+ struct cvmx_mio_uartx_dlh_s cn31xx;
+ struct cvmx_mio_uartx_dlh_s cn38xx;
+ struct cvmx_mio_uartx_dlh_s cn38xxp2;
+ struct cvmx_mio_uartx_dlh_s cn50xx;
+ struct cvmx_mio_uartx_dlh_s cn52xx;
+ struct cvmx_mio_uartx_dlh_s cn52xxp1;
+ struct cvmx_mio_uartx_dlh_s cn56xx;
+ struct cvmx_mio_uartx_dlh_s cn56xxp1;
+ struct cvmx_mio_uartx_dlh_s cn58xx;
+ struct cvmx_mio_uartx_dlh_s cn58xxp1;
+} cvmx_mio_uartx_dlh_t;
+typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_dll_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dll:8;
+#else
+ uint64_t dll:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_dll_s cn30xx;
+ struct cvmx_mio_uartx_dll_s cn31xx;
+ struct cvmx_mio_uartx_dll_s cn38xx;
+ struct cvmx_mio_uartx_dll_s cn38xxp2;
+ struct cvmx_mio_uartx_dll_s cn50xx;
+ struct cvmx_mio_uartx_dll_s cn52xx;
+ struct cvmx_mio_uartx_dll_s cn52xxp1;
+ struct cvmx_mio_uartx_dll_s cn56xx;
+ struct cvmx_mio_uartx_dll_s cn56xxp1;
+ struct cvmx_mio_uartx_dll_s cn58xx;
+ struct cvmx_mio_uartx_dll_s cn58xxp1;
+} cvmx_mio_uartx_dll_t;
+typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_far_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t far:1;
+#else
+ uint64_t far:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uartx_far_s cn30xx;
+ struct cvmx_mio_uartx_far_s cn31xx;
+ struct cvmx_mio_uartx_far_s cn38xx;
+ struct cvmx_mio_uartx_far_s cn38xxp2;
+ struct cvmx_mio_uartx_far_s cn50xx;
+ struct cvmx_mio_uartx_far_s cn52xx;
+ struct cvmx_mio_uartx_far_s cn52xxp1;
+ struct cvmx_mio_uartx_far_s cn56xx;
+ struct cvmx_mio_uartx_far_s cn56xxp1;
+ struct cvmx_mio_uartx_far_s cn58xx;
+ struct cvmx_mio_uartx_far_s cn58xxp1;
+} cvmx_mio_uartx_far_t;
+typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_fcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rxtrig:2;
+ uint64_t txtrig:2;
+ uint64_t reserved_3_3:1;
+ uint64_t txfr:1;
+ uint64_t rxfr:1;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t rxfr:1;
+ uint64_t txfr:1;
+ uint64_t reserved_3_3:1;
+ uint64_t txtrig:2;
+ uint64_t rxtrig:2;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_fcr_s cn30xx;
+ struct cvmx_mio_uartx_fcr_s cn31xx;
+ struct cvmx_mio_uartx_fcr_s cn38xx;
+ struct cvmx_mio_uartx_fcr_s cn38xxp2;
+ struct cvmx_mio_uartx_fcr_s cn50xx;
+ struct cvmx_mio_uartx_fcr_s cn52xx;
+ struct cvmx_mio_uartx_fcr_s cn52xxp1;
+ struct cvmx_mio_uartx_fcr_s cn56xx;
+ struct cvmx_mio_uartx_fcr_s cn56xxp1;
+ struct cvmx_mio_uartx_fcr_s cn58xx;
+ struct cvmx_mio_uartx_fcr_s cn58xxp1;
+} cvmx_mio_uartx_fcr_t;
+typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_htx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t htx:1;
+#else
+ uint64_t htx:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uartx_htx_s cn30xx;
+ struct cvmx_mio_uartx_htx_s cn31xx;
+ struct cvmx_mio_uartx_htx_s cn38xx;
+ struct cvmx_mio_uartx_htx_s cn38xxp2;
+ struct cvmx_mio_uartx_htx_s cn50xx;
+ struct cvmx_mio_uartx_htx_s cn52xx;
+ struct cvmx_mio_uartx_htx_s cn52xxp1;
+ struct cvmx_mio_uartx_htx_s cn56xx;
+ struct cvmx_mio_uartx_htx_s cn56xxp1;
+ struct cvmx_mio_uartx_htx_s cn58xx;
+ struct cvmx_mio_uartx_htx_s cn58xxp1;
+} cvmx_mio_uartx_htx_t;
+typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_ier_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ptime:1;
+ uint64_t reserved_4_6:3;
+ uint64_t edssi:1;
+ uint64_t elsi:1;
+ uint64_t etbei:1;
+ uint64_t erbfi:1;
+#else
+ uint64_t erbfi:1;
+ uint64_t etbei:1;
+ uint64_t elsi:1;
+ uint64_t edssi:1;
+ uint64_t reserved_4_6:3;
+ uint64_t ptime:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_ier_s cn30xx;
+ struct cvmx_mio_uartx_ier_s cn31xx;
+ struct cvmx_mio_uartx_ier_s cn38xx;
+ struct cvmx_mio_uartx_ier_s cn38xxp2;
+ struct cvmx_mio_uartx_ier_s cn50xx;
+ struct cvmx_mio_uartx_ier_s cn52xx;
+ struct cvmx_mio_uartx_ier_s cn52xxp1;
+ struct cvmx_mio_uartx_ier_s cn56xx;
+ struct cvmx_mio_uartx_ier_s cn56xxp1;
+ struct cvmx_mio_uartx_ier_s cn58xx;
+ struct cvmx_mio_uartx_ier_s cn58xxp1;
+} cvmx_mio_uartx_ier_t;
+typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_iir_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t fen:2;
+ uint64_t reserved_4_5:2;
+ cvmx_uart_iid_t iid:4;
+#else
+ cvmx_uart_iid_t iid:4;
+ uint64_t reserved_4_5:2;
+ uint64_t fen:2;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_iir_s cn30xx;
+ struct cvmx_mio_uartx_iir_s cn31xx;
+ struct cvmx_mio_uartx_iir_s cn38xx;
+ struct cvmx_mio_uartx_iir_s cn38xxp2;
+ struct cvmx_mio_uartx_iir_s cn50xx;
+ struct cvmx_mio_uartx_iir_s cn52xx;
+ struct cvmx_mio_uartx_iir_s cn52xxp1;
+ struct cvmx_mio_uartx_iir_s cn56xx;
+ struct cvmx_mio_uartx_iir_s cn56xxp1;
+ struct cvmx_mio_uartx_iir_s cn58xx;
+ struct cvmx_mio_uartx_iir_s cn58xxp1;
+} cvmx_mio_uartx_iir_t;
+typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_lcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dlab:1;
+ uint64_t brk:1;
+ uint64_t reserved_5_5:1;
+ uint64_t eps:1;
+ uint64_t pen:1;
+ uint64_t stop:1;
+ cvmx_uart_bits_t cls:2;
+#else
+ cvmx_uart_bits_t cls:2;
+ uint64_t stop:1;
+ uint64_t pen:1;
+ uint64_t eps:1;
+ uint64_t reserved_5_5:1;
+ uint64_t brk:1;
+ uint64_t dlab:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_lcr_s cn30xx;
+ struct cvmx_mio_uartx_lcr_s cn31xx;
+ struct cvmx_mio_uartx_lcr_s cn38xx;
+ struct cvmx_mio_uartx_lcr_s cn38xxp2;
+ struct cvmx_mio_uartx_lcr_s cn50xx;
+ struct cvmx_mio_uartx_lcr_s cn52xx;
+ struct cvmx_mio_uartx_lcr_s cn52xxp1;
+ struct cvmx_mio_uartx_lcr_s cn56xx;
+ struct cvmx_mio_uartx_lcr_s cn56xxp1;
+ struct cvmx_mio_uartx_lcr_s cn58xx;
+ struct cvmx_mio_uartx_lcr_s cn58xxp1;
+} cvmx_mio_uartx_lcr_t;
+typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_lsr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ferr:1;
+ uint64_t temt:1;
+ uint64_t thre:1;
+ uint64_t bi:1;
+ uint64_t fe:1;
+ uint64_t pe:1;
+ uint64_t oe:1;
+ uint64_t dr:1;
+#else
+ uint64_t dr:1;
+ uint64_t oe:1;
+ uint64_t pe:1;
+ uint64_t fe:1;
+ uint64_t bi:1;
+ uint64_t thre:1;
+ uint64_t temt:1;
+ uint64_t ferr:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_lsr_s cn30xx;
+ struct cvmx_mio_uartx_lsr_s cn31xx;
+ struct cvmx_mio_uartx_lsr_s cn38xx;
+ struct cvmx_mio_uartx_lsr_s cn38xxp2;
+ struct cvmx_mio_uartx_lsr_s cn50xx;
+ struct cvmx_mio_uartx_lsr_s cn52xx;
+ struct cvmx_mio_uartx_lsr_s cn52xxp1;
+ struct cvmx_mio_uartx_lsr_s cn56xx;
+ struct cvmx_mio_uartx_lsr_s cn56xxp1;
+ struct cvmx_mio_uartx_lsr_s cn58xx;
+ struct cvmx_mio_uartx_lsr_s cn58xxp1;
+} cvmx_mio_uartx_lsr_t;
+typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_mcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t afce:1;
+ uint64_t loop:1;
+ uint64_t out2:1;
+ uint64_t out1:1;
+ uint64_t rts:1;
+ uint64_t dtr:1;
+#else
+ uint64_t dtr:1;
+ uint64_t rts:1;
+ uint64_t out1:1;
+ uint64_t out2:1;
+ uint64_t loop:1;
+ uint64_t afce:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_mio_uartx_mcr_s cn30xx;
+ struct cvmx_mio_uartx_mcr_s cn31xx;
+ struct cvmx_mio_uartx_mcr_s cn38xx;
+ struct cvmx_mio_uartx_mcr_s cn38xxp2;
+ struct cvmx_mio_uartx_mcr_s cn50xx;
+ struct cvmx_mio_uartx_mcr_s cn52xx;
+ struct cvmx_mio_uartx_mcr_s cn52xxp1;
+ struct cvmx_mio_uartx_mcr_s cn56xx;
+ struct cvmx_mio_uartx_mcr_s cn56xxp1;
+ struct cvmx_mio_uartx_mcr_s cn58xx;
+ struct cvmx_mio_uartx_mcr_s cn58xxp1;
+} cvmx_mio_uartx_mcr_t;
+typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_msr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dcd:1;
+ uint64_t ri:1;
+ uint64_t dsr:1;
+ uint64_t cts:1;
+ uint64_t ddcd:1;
+ uint64_t teri:1;
+ uint64_t ddsr:1;
+ uint64_t dcts:1;
+#else
+ uint64_t dcts:1;
+ uint64_t ddsr:1;
+ uint64_t teri:1;
+ uint64_t ddcd:1;
+ uint64_t cts:1;
+ uint64_t dsr:1;
+ uint64_t ri:1;
+ uint64_t dcd:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_msr_s cn30xx;
+ struct cvmx_mio_uartx_msr_s cn31xx;
+ struct cvmx_mio_uartx_msr_s cn38xx;
+ struct cvmx_mio_uartx_msr_s cn38xxp2;
+ struct cvmx_mio_uartx_msr_s cn50xx;
+ struct cvmx_mio_uartx_msr_s cn52xx;
+ struct cvmx_mio_uartx_msr_s cn52xxp1;
+ struct cvmx_mio_uartx_msr_s cn56xx;
+ struct cvmx_mio_uartx_msr_s cn56xxp1;
+ struct cvmx_mio_uartx_msr_s cn58xx;
+ struct cvmx_mio_uartx_msr_s cn58xxp1;
+} cvmx_mio_uartx_msr_t;
+typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_rbr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rbr:8;
+#else
+ uint64_t rbr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_rbr_s cn30xx;
+ struct cvmx_mio_uartx_rbr_s cn31xx;
+ struct cvmx_mio_uartx_rbr_s cn38xx;
+ struct cvmx_mio_uartx_rbr_s cn38xxp2;
+ struct cvmx_mio_uartx_rbr_s cn50xx;
+ struct cvmx_mio_uartx_rbr_s cn52xx;
+ struct cvmx_mio_uartx_rbr_s cn52xxp1;
+ struct cvmx_mio_uartx_rbr_s cn56xx;
+ struct cvmx_mio_uartx_rbr_s cn56xxp1;
+ struct cvmx_mio_uartx_rbr_s cn58xx;
+ struct cvmx_mio_uartx_rbr_s cn58xxp1;
+} cvmx_mio_uartx_rbr_t;
+typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_rfl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t rfl:7;
+#else
+ uint64_t rfl:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mio_uartx_rfl_s cn30xx;
+ struct cvmx_mio_uartx_rfl_s cn31xx;
+ struct cvmx_mio_uartx_rfl_s cn38xx;
+ struct cvmx_mio_uartx_rfl_s cn38xxp2;
+ struct cvmx_mio_uartx_rfl_s cn50xx;
+ struct cvmx_mio_uartx_rfl_s cn52xx;
+ struct cvmx_mio_uartx_rfl_s cn52xxp1;
+ struct cvmx_mio_uartx_rfl_s cn56xx;
+ struct cvmx_mio_uartx_rfl_s cn56xxp1;
+ struct cvmx_mio_uartx_rfl_s cn58xx;
+ struct cvmx_mio_uartx_rfl_s cn58xxp1;
+} cvmx_mio_uartx_rfl_t;
+typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_rfw_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t rffe:1;
+ uint64_t rfpe:1;
+ uint64_t rfwd:8;
+#else
+ uint64_t rfwd:8;
+ uint64_t rfpe:1;
+ uint64_t rffe:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_mio_uartx_rfw_s cn30xx;
+ struct cvmx_mio_uartx_rfw_s cn31xx;
+ struct cvmx_mio_uartx_rfw_s cn38xx;
+ struct cvmx_mio_uartx_rfw_s cn38xxp2;
+ struct cvmx_mio_uartx_rfw_s cn50xx;
+ struct cvmx_mio_uartx_rfw_s cn52xx;
+ struct cvmx_mio_uartx_rfw_s cn52xxp1;
+ struct cvmx_mio_uartx_rfw_s cn56xx;
+ struct cvmx_mio_uartx_rfw_s cn56xxp1;
+ struct cvmx_mio_uartx_rfw_s cn58xx;
+ struct cvmx_mio_uartx_rfw_s cn58xxp1;
+} cvmx_mio_uartx_rfw_t;
+typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_sbcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t sbcr:1;
+#else
+ uint64_t sbcr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uartx_sbcr_s cn30xx;
+ struct cvmx_mio_uartx_sbcr_s cn31xx;
+ struct cvmx_mio_uartx_sbcr_s cn38xx;
+ struct cvmx_mio_uartx_sbcr_s cn38xxp2;
+ struct cvmx_mio_uartx_sbcr_s cn50xx;
+ struct cvmx_mio_uartx_sbcr_s cn52xx;
+ struct cvmx_mio_uartx_sbcr_s cn52xxp1;
+ struct cvmx_mio_uartx_sbcr_s cn56xx;
+ struct cvmx_mio_uartx_sbcr_s cn56xxp1;
+ struct cvmx_mio_uartx_sbcr_s cn58xx;
+ struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+} cvmx_mio_uartx_sbcr_t;
+typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_scr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t scr:8;
+#else
+ uint64_t scr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_scr_s cn30xx;
+ struct cvmx_mio_uartx_scr_s cn31xx;
+ struct cvmx_mio_uartx_scr_s cn38xx;
+ struct cvmx_mio_uartx_scr_s cn38xxp2;
+ struct cvmx_mio_uartx_scr_s cn50xx;
+ struct cvmx_mio_uartx_scr_s cn52xx;
+ struct cvmx_mio_uartx_scr_s cn52xxp1;
+ struct cvmx_mio_uartx_scr_s cn56xx;
+ struct cvmx_mio_uartx_scr_s cn56xxp1;
+ struct cvmx_mio_uartx_scr_s cn58xx;
+ struct cvmx_mio_uartx_scr_s cn58xxp1;
+} cvmx_mio_uartx_scr_t;
+typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_sfe_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t sfe:1;
+#else
+ uint64_t sfe:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uartx_sfe_s cn30xx;
+ struct cvmx_mio_uartx_sfe_s cn31xx;
+ struct cvmx_mio_uartx_sfe_s cn38xx;
+ struct cvmx_mio_uartx_sfe_s cn38xxp2;
+ struct cvmx_mio_uartx_sfe_s cn50xx;
+ struct cvmx_mio_uartx_sfe_s cn52xx;
+ struct cvmx_mio_uartx_sfe_s cn52xxp1;
+ struct cvmx_mio_uartx_sfe_s cn56xx;
+ struct cvmx_mio_uartx_sfe_s cn56xxp1;
+ struct cvmx_mio_uartx_sfe_s cn58xx;
+ struct cvmx_mio_uartx_sfe_s cn58xxp1;
+} cvmx_mio_uartx_sfe_t;
+typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_srr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t stfr:1;
+ uint64_t srfr:1;
+ uint64_t usr:1;
+#else
+ uint64_t usr:1;
+ uint64_t srfr:1;
+ uint64_t stfr:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_mio_uartx_srr_s cn30xx;
+ struct cvmx_mio_uartx_srr_s cn31xx;
+ struct cvmx_mio_uartx_srr_s cn38xx;
+ struct cvmx_mio_uartx_srr_s cn38xxp2;
+ struct cvmx_mio_uartx_srr_s cn50xx;
+ struct cvmx_mio_uartx_srr_s cn52xx;
+ struct cvmx_mio_uartx_srr_s cn52xxp1;
+ struct cvmx_mio_uartx_srr_s cn56xx;
+ struct cvmx_mio_uartx_srr_s cn56xxp1;
+ struct cvmx_mio_uartx_srr_s cn58xx;
+ struct cvmx_mio_uartx_srr_s cn58xxp1;
+} cvmx_mio_uartx_srr_t;
+typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_srt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t srt:2;
+#else
+ uint64_t srt:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_uartx_srt_s cn30xx;
+ struct cvmx_mio_uartx_srt_s cn31xx;
+ struct cvmx_mio_uartx_srt_s cn38xx;
+ struct cvmx_mio_uartx_srt_s cn38xxp2;
+ struct cvmx_mio_uartx_srt_s cn50xx;
+ struct cvmx_mio_uartx_srt_s cn52xx;
+ struct cvmx_mio_uartx_srt_s cn52xxp1;
+ struct cvmx_mio_uartx_srt_s cn56xx;
+ struct cvmx_mio_uartx_srt_s cn56xxp1;
+ struct cvmx_mio_uartx_srt_s cn58xx;
+ struct cvmx_mio_uartx_srt_s cn58xxp1;
+} cvmx_mio_uartx_srt_t;
+typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_srts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t srts:1;
+#else
+ uint64_t srts:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uartx_srts_s cn30xx;
+ struct cvmx_mio_uartx_srts_s cn31xx;
+ struct cvmx_mio_uartx_srts_s cn38xx;
+ struct cvmx_mio_uartx_srts_s cn38xxp2;
+ struct cvmx_mio_uartx_srts_s cn50xx;
+ struct cvmx_mio_uartx_srts_s cn52xx;
+ struct cvmx_mio_uartx_srts_s cn52xxp1;
+ struct cvmx_mio_uartx_srts_s cn56xx;
+ struct cvmx_mio_uartx_srts_s cn56xxp1;
+ struct cvmx_mio_uartx_srts_s cn58xx;
+ struct cvmx_mio_uartx_srts_s cn58xxp1;
+} cvmx_mio_uartx_srts_t;
+typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_stt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t stt:2;
+#else
+ uint64_t stt:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_uartx_stt_s cn30xx;
+ struct cvmx_mio_uartx_stt_s cn31xx;
+ struct cvmx_mio_uartx_stt_s cn38xx;
+ struct cvmx_mio_uartx_stt_s cn38xxp2;
+ struct cvmx_mio_uartx_stt_s cn50xx;
+ struct cvmx_mio_uartx_stt_s cn52xx;
+ struct cvmx_mio_uartx_stt_s cn52xxp1;
+ struct cvmx_mio_uartx_stt_s cn56xx;
+ struct cvmx_mio_uartx_stt_s cn56xxp1;
+ struct cvmx_mio_uartx_stt_s cn58xx;
+ struct cvmx_mio_uartx_stt_s cn58xxp1;
+} cvmx_mio_uartx_stt_t;
+typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_tfl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t tfl:7;
+#else
+ uint64_t tfl:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mio_uartx_tfl_s cn30xx;
+ struct cvmx_mio_uartx_tfl_s cn31xx;
+ struct cvmx_mio_uartx_tfl_s cn38xx;
+ struct cvmx_mio_uartx_tfl_s cn38xxp2;
+ struct cvmx_mio_uartx_tfl_s cn50xx;
+ struct cvmx_mio_uartx_tfl_s cn52xx;
+ struct cvmx_mio_uartx_tfl_s cn52xxp1;
+ struct cvmx_mio_uartx_tfl_s cn56xx;
+ struct cvmx_mio_uartx_tfl_s cn56xxp1;
+ struct cvmx_mio_uartx_tfl_s cn58xx;
+ struct cvmx_mio_uartx_tfl_s cn58xxp1;
+} cvmx_mio_uartx_tfl_t;
+typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_tfr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t tfr:8;
+#else
+ uint64_t tfr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_tfr_s cn30xx;
+ struct cvmx_mio_uartx_tfr_s cn31xx;
+ struct cvmx_mio_uartx_tfr_s cn38xx;
+ struct cvmx_mio_uartx_tfr_s cn38xxp2;
+ struct cvmx_mio_uartx_tfr_s cn50xx;
+ struct cvmx_mio_uartx_tfr_s cn52xx;
+ struct cvmx_mio_uartx_tfr_s cn52xxp1;
+ struct cvmx_mio_uartx_tfr_s cn56xx;
+ struct cvmx_mio_uartx_tfr_s cn56xxp1;
+ struct cvmx_mio_uartx_tfr_s cn58xx;
+ struct cvmx_mio_uartx_tfr_s cn58xxp1;
+} cvmx_mio_uartx_tfr_t;
+typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_thr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t thr:8;
+#else
+ uint64_t thr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uartx_thr_s cn30xx;
+ struct cvmx_mio_uartx_thr_s cn31xx;
+ struct cvmx_mio_uartx_thr_s cn38xx;
+ struct cvmx_mio_uartx_thr_s cn38xxp2;
+ struct cvmx_mio_uartx_thr_s cn50xx;
+ struct cvmx_mio_uartx_thr_s cn52xx;
+ struct cvmx_mio_uartx_thr_s cn52xxp1;
+ struct cvmx_mio_uartx_thr_s cn56xx;
+ struct cvmx_mio_uartx_thr_s cn56xxp1;
+ struct cvmx_mio_uartx_thr_s cn58xx;
+ struct cvmx_mio_uartx_thr_s cn58xxp1;
+} cvmx_mio_uartx_thr_t;
+typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uartx_usr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t rff:1;
+ uint64_t rfne:1;
+ uint64_t tfe:1;
+ uint64_t tfnf:1;
+ uint64_t busy:1;
+#else
+ uint64_t busy:1;
+ uint64_t tfnf:1;
+ uint64_t tfe:1;
+ uint64_t rfne:1;
+ uint64_t rff:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_mio_uartx_usr_s cn30xx;
+ struct cvmx_mio_uartx_usr_s cn31xx;
+ struct cvmx_mio_uartx_usr_s cn38xx;
+ struct cvmx_mio_uartx_usr_s cn38xxp2;
+ struct cvmx_mio_uartx_usr_s cn50xx;
+ struct cvmx_mio_uartx_usr_s cn52xx;
+ struct cvmx_mio_uartx_usr_s cn52xxp1;
+ struct cvmx_mio_uartx_usr_s cn56xx;
+ struct cvmx_mio_uartx_usr_s cn56xxp1;
+ struct cvmx_mio_uartx_usr_s cn58xx;
+ struct cvmx_mio_uartx_usr_s cn58xxp1;
+} cvmx_mio_uartx_usr_t;
+typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_dlh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dlh:8;
+#else
+ uint64_t dlh:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_dlh_s cn52xx;
+ struct cvmx_mio_uart2_dlh_s cn52xxp1;
+} cvmx_mio_uart2_dlh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_dll_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dll:8;
+#else
+ uint64_t dll:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_dll_s cn52xx;
+ struct cvmx_mio_uart2_dll_s cn52xxp1;
+} cvmx_mio_uart2_dll_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_far_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t far:1;
+#else
+ uint64_t far:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uart2_far_s cn52xx;
+ struct cvmx_mio_uart2_far_s cn52xxp1;
+} cvmx_mio_uart2_far_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_fcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rxtrig:2;
+ uint64_t txtrig:2;
+ uint64_t reserved_3_3:1;
+ uint64_t txfr:1;
+ uint64_t rxfr:1;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t rxfr:1;
+ uint64_t txfr:1;
+ uint64_t reserved_3_3:1;
+ uint64_t txtrig:2;
+ uint64_t rxtrig:2;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_fcr_s cn52xx;
+ struct cvmx_mio_uart2_fcr_s cn52xxp1;
+} cvmx_mio_uart2_fcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_htx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t htx:1;
+#else
+ uint64_t htx:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uart2_htx_s cn52xx;
+ struct cvmx_mio_uart2_htx_s cn52xxp1;
+} cvmx_mio_uart2_htx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_ier_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ptime:1;
+ uint64_t reserved_4_6:3;
+ uint64_t edssi:1;
+ uint64_t elsi:1;
+ uint64_t etbei:1;
+ uint64_t erbfi:1;
+#else
+ uint64_t erbfi:1;
+ uint64_t etbei:1;
+ uint64_t elsi:1;
+ uint64_t edssi:1;
+ uint64_t reserved_4_6:3;
+ uint64_t ptime:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_ier_s cn52xx;
+ struct cvmx_mio_uart2_ier_s cn52xxp1;
+} cvmx_mio_uart2_ier_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_iir_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t fen:2;
+ uint64_t reserved_4_5:2;
+ uint64_t iid:4;
+#else
+ uint64_t iid:4;
+ uint64_t reserved_4_5:2;
+ uint64_t fen:2;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_iir_s cn52xx;
+ struct cvmx_mio_uart2_iir_s cn52xxp1;
+} cvmx_mio_uart2_iir_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_lcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dlab:1;
+ uint64_t brk:1;
+ uint64_t reserved_5_5:1;
+ uint64_t eps:1;
+ uint64_t pen:1;
+ uint64_t stop:1;
+ uint64_t cls:2;
+#else
+ uint64_t cls:2;
+ uint64_t stop:1;
+ uint64_t pen:1;
+ uint64_t eps:1;
+ uint64_t reserved_5_5:1;
+ uint64_t brk:1;
+ uint64_t dlab:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_lcr_s cn52xx;
+ struct cvmx_mio_uart2_lcr_s cn52xxp1;
+} cvmx_mio_uart2_lcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_lsr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t ferr:1;
+ uint64_t temt:1;
+ uint64_t thre:1;
+ uint64_t bi:1;
+ uint64_t fe:1;
+ uint64_t pe:1;
+ uint64_t oe:1;
+ uint64_t dr:1;
+#else
+ uint64_t dr:1;
+ uint64_t oe:1;
+ uint64_t pe:1;
+ uint64_t fe:1;
+ uint64_t bi:1;
+ uint64_t thre:1;
+ uint64_t temt:1;
+ uint64_t ferr:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_lsr_s cn52xx;
+ struct cvmx_mio_uart2_lsr_s cn52xxp1;
+} cvmx_mio_uart2_lsr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_mcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t afce:1;
+ uint64_t loop:1;
+ uint64_t out2:1;
+ uint64_t out1:1;
+ uint64_t rts:1;
+ uint64_t dtr:1;
+#else
+ uint64_t dtr:1;
+ uint64_t rts:1;
+ uint64_t out1:1;
+ uint64_t out2:1;
+ uint64_t loop:1;
+ uint64_t afce:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_mio_uart2_mcr_s cn52xx;
+ struct cvmx_mio_uart2_mcr_s cn52xxp1;
+} cvmx_mio_uart2_mcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_msr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t dcd:1;
+ uint64_t ri:1;
+ uint64_t dsr:1;
+ uint64_t cts:1;
+ uint64_t ddcd:1;
+ uint64_t teri:1;
+ uint64_t ddsr:1;
+ uint64_t dcts:1;
+#else
+ uint64_t dcts:1;
+ uint64_t ddsr:1;
+ uint64_t teri:1;
+ uint64_t ddcd:1;
+ uint64_t cts:1;
+ uint64_t dsr:1;
+ uint64_t ri:1;
+ uint64_t dcd:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_msr_s cn52xx;
+ struct cvmx_mio_uart2_msr_s cn52xxp1;
+} cvmx_mio_uart2_msr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_rbr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rbr:8;
+#else
+ uint64_t rbr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_rbr_s cn52xx;
+ struct cvmx_mio_uart2_rbr_s cn52xxp1;
+} cvmx_mio_uart2_rbr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_rfl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t rfl:7;
+#else
+ uint64_t rfl:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mio_uart2_rfl_s cn52xx;
+ struct cvmx_mio_uart2_rfl_s cn52xxp1;
+} cvmx_mio_uart2_rfl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_rfw_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t rffe:1;
+ uint64_t rfpe:1;
+ uint64_t rfwd:8;
+#else
+ uint64_t rfwd:8;
+ uint64_t rfpe:1;
+ uint64_t rffe:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_mio_uart2_rfw_s cn52xx;
+ struct cvmx_mio_uart2_rfw_s cn52xxp1;
+} cvmx_mio_uart2_rfw_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_sbcr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t sbcr:1;
+#else
+ uint64_t sbcr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uart2_sbcr_s cn52xx;
+ struct cvmx_mio_uart2_sbcr_s cn52xxp1;
+} cvmx_mio_uart2_sbcr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_scr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t scr:8;
+#else
+ uint64_t scr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_scr_s cn52xx;
+ struct cvmx_mio_uart2_scr_s cn52xxp1;
+} cvmx_mio_uart2_scr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_sfe_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t sfe:1;
+#else
+ uint64_t sfe:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uart2_sfe_s cn52xx;
+ struct cvmx_mio_uart2_sfe_s cn52xxp1;
+} cvmx_mio_uart2_sfe_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_srr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t stfr:1;
+ uint64_t srfr:1;
+ uint64_t usr:1;
+#else
+ uint64_t usr:1;
+ uint64_t srfr:1;
+ uint64_t stfr:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_mio_uart2_srr_s cn52xx;
+ struct cvmx_mio_uart2_srr_s cn52xxp1;
+} cvmx_mio_uart2_srr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_srt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t srt:2;
+#else
+ uint64_t srt:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_uart2_srt_s cn52xx;
+ struct cvmx_mio_uart2_srt_s cn52xxp1;
+} cvmx_mio_uart2_srt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_srts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t srts:1;
+#else
+ uint64_t srts:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_mio_uart2_srts_s cn52xx;
+ struct cvmx_mio_uart2_srts_s cn52xxp1;
+} cvmx_mio_uart2_srts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_stt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t stt:2;
+#else
+ uint64_t stt:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_mio_uart2_stt_s cn52xx;
+ struct cvmx_mio_uart2_stt_s cn52xxp1;
+} cvmx_mio_uart2_stt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_tfl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t tfl:7;
+#else
+ uint64_t tfl:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mio_uart2_tfl_s cn52xx;
+ struct cvmx_mio_uart2_tfl_s cn52xxp1;
+} cvmx_mio_uart2_tfl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_tfr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t tfr:8;
+#else
+ uint64_t tfr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_tfr_s cn52xx;
+ struct cvmx_mio_uart2_tfr_s cn52xxp1;
+} cvmx_mio_uart2_tfr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_thr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t thr:8;
+#else
+ uint64_t thr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mio_uart2_thr_s cn52xx;
+ struct cvmx_mio_uart2_thr_s cn52xxp1;
+} cvmx_mio_uart2_thr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mio_uart2_usr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t rff:1;
+ uint64_t rfne:1;
+ uint64_t tfe:1;
+ uint64_t tfnf:1;
+ uint64_t busy:1;
+#else
+ uint64_t busy:1;
+ uint64_t tfnf:1;
+ uint64_t tfe:1;
+ uint64_t rfne:1;
+ uint64_t rff:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_mio_uart2_usr_s cn52xx;
+ struct cvmx_mio_uart2_usr_s cn52xxp1;
+} cvmx_mio_uart2_usr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_bist_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t mrqdat:1;
+ uint64_t ipfdat:1;
+ uint64_t irfdat:1;
+ uint64_t orfdat:1;
+#else
+ uint64_t orfdat:1;
+ uint64_t irfdat:1;
+ uint64_t ipfdat:1;
+ uint64_t mrqdat:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_mixx_bist_s cn52xx;
+ struct cvmx_mixx_bist_s cn52xxp1;
+ struct cvmx_mixx_bist_s cn56xx;
+ struct cvmx_mixx_bist_s cn56xxp1;
+} cvmx_mixx_bist_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t crc_strip:1;
+ uint64_t busy:1;
+ uint64_t en:1;
+ uint64_t reset:1;
+ uint64_t lendian:1;
+ uint64_t nbtarb:1;
+ uint64_t mrq_hwm:2;
+#else
+ uint64_t mrq_hwm:2;
+ uint64_t nbtarb:1;
+ uint64_t lendian:1;
+ uint64_t reset:1;
+ uint64_t en:1;
+ uint64_t busy:1;
+ uint64_t crc_strip:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mixx_ctl_s cn52xx;
+ struct cvmx_mixx_ctl_s cn52xxp1;
+ struct cvmx_mixx_ctl_s cn56xx;
+ struct cvmx_mixx_ctl_s cn56xxp1;
+} cvmx_mixx_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_intena_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t orunena:1;
+ uint64_t irunena:1;
+ uint64_t data_drpena:1;
+ uint64_t ithena:1;
+ uint64_t othena:1;
+ uint64_t ivfena:1;
+ uint64_t ovfena:1;
+#else
+ uint64_t ovfena:1;
+ uint64_t ivfena:1;
+ uint64_t othena:1;
+ uint64_t ithena:1;
+ uint64_t data_drpena:1;
+ uint64_t irunena:1;
+ uint64_t orunena:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mixx_intena_s cn52xx;
+ struct cvmx_mixx_intena_s cn52xxp1;
+ struct cvmx_mixx_intena_s cn56xx;
+ struct cvmx_mixx_intena_s cn56xxp1;
+} cvmx_mixx_intena_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_ircnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t ircnt:20;
+#else
+ uint64_t ircnt:20;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_mixx_ircnt_s cn52xx;
+ struct cvmx_mixx_ircnt_s cn52xxp1;
+ struct cvmx_mixx_ircnt_s cn56xx;
+ struct cvmx_mixx_ircnt_s cn56xxp1;
+} cvmx_mixx_ircnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_irhwm_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t ibplwm:20;
+ uint64_t irhwm:20;
+#else
+ uint64_t irhwm:20;
+ uint64_t ibplwm:20;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_mixx_irhwm_s cn52xx;
+ struct cvmx_mixx_irhwm_s cn52xxp1;
+ struct cvmx_mixx_irhwm_s cn56xx;
+ struct cvmx_mixx_irhwm_s cn56xxp1;
+} cvmx_mixx_irhwm_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_iring1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_60_63:4;
+ uint64_t isize:20;
+ uint64_t reserved_36_39:4;
+ uint64_t ibase:33;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t ibase:33;
+ uint64_t reserved_36_39:4;
+ uint64_t isize:20;
+ uint64_t reserved_60_63:4;
+#endif
+ } s;
+ struct cvmx_mixx_iring1_s cn52xx;
+ struct cvmx_mixx_iring1_s cn52xxp1;
+ struct cvmx_mixx_iring1_s cn56xx;
+ struct cvmx_mixx_iring1_s cn56xxp1;
+} cvmx_mixx_iring1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_iring2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_52_63:12;
+ uint64_t itlptr:20;
+ uint64_t reserved_20_31:12;
+ uint64_t idbell:20;
+#else
+ uint64_t idbell:20;
+ uint64_t reserved_20_31:12;
+ uint64_t itlptr:20;
+ uint64_t reserved_52_63:12;
+#endif
+ } s;
+ struct cvmx_mixx_iring2_s cn52xx;
+ struct cvmx_mixx_iring2_s cn52xxp1;
+ struct cvmx_mixx_iring2_s cn56xx;
+ struct cvmx_mixx_iring2_s cn56xxp1;
+} cvmx_mixx_iring2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_isr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t orun:1;
+ uint64_t irun:1;
+ uint64_t data_drp:1;
+ uint64_t irthresh:1;
+ uint64_t orthresh:1;
+ uint64_t idblovf:1;
+ uint64_t odblovf:1;
+#else
+ uint64_t odblovf:1;
+ uint64_t idblovf:1;
+ uint64_t orthresh:1;
+ uint64_t irthresh:1;
+ uint64_t data_drp:1;
+ uint64_t irun:1;
+ uint64_t orun:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_mixx_isr_s cn52xx;
+ struct cvmx_mixx_isr_s cn52xxp1;
+ struct cvmx_mixx_isr_s cn56xx;
+ struct cvmx_mixx_isr_s cn56xxp1;
+} cvmx_mixx_isr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_orcnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t orcnt:20;
+#else
+ uint64_t orcnt:20;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_mixx_orcnt_s cn52xx;
+ struct cvmx_mixx_orcnt_s cn52xxp1;
+ struct cvmx_mixx_orcnt_s cn56xx;
+ struct cvmx_mixx_orcnt_s cn56xxp1;
+} cvmx_mixx_orcnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_orhwm_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t orhwm:20;
+#else
+ uint64_t orhwm:20;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_mixx_orhwm_s cn52xx;
+ struct cvmx_mixx_orhwm_s cn52xxp1;
+ struct cvmx_mixx_orhwm_s cn56xx;
+ struct cvmx_mixx_orhwm_s cn56xxp1;
+} cvmx_mixx_orhwm_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_oring1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_60_63:4;
+ uint64_t osize:20;
+ uint64_t reserved_36_39:4;
+ uint64_t obase:33;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t obase:33;
+ uint64_t reserved_36_39:4;
+ uint64_t osize:20;
+ uint64_t reserved_60_63:4;
+#endif
+ } s;
+ struct cvmx_mixx_oring1_s cn52xx;
+ struct cvmx_mixx_oring1_s cn52xxp1;
+ struct cvmx_mixx_oring1_s cn56xx;
+ struct cvmx_mixx_oring1_s cn56xxp1;
+} cvmx_mixx_oring1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_oring2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_52_63:12;
+ uint64_t otlptr:20;
+ uint64_t reserved_20_31:12;
+ uint64_t odbell:20;
+#else
+ uint64_t odbell:20;
+ uint64_t reserved_20_31:12;
+ uint64_t otlptr:20;
+ uint64_t reserved_52_63:12;
+#endif
+ } s;
+ struct cvmx_mixx_oring2_s cn52xx;
+ struct cvmx_mixx_oring2_s cn52xxp1;
+ struct cvmx_mixx_oring2_s cn56xx;
+ struct cvmx_mixx_oring2_s cn56xxp1;
+} cvmx_mixx_oring2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mixx_remcnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_52_63:12;
+ uint64_t iremcnt:20;
+ uint64_t reserved_20_31:12;
+ uint64_t oremcnt:20;
+#else
+ uint64_t oremcnt:20;
+ uint64_t reserved_20_31:12;
+ uint64_t iremcnt:20;
+ uint64_t reserved_52_63:12;
+#endif
+ } s;
+ struct cvmx_mixx_remcnt_s cn52xx;
+ struct cvmx_mixx_remcnt_s cn52xxp1;
+ struct cvmx_mixx_remcnt_s cn56xx;
+ struct cvmx_mixx_remcnt_s cn56xxp1;
+} cvmx_mixx_remcnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mpi_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t clkdiv:13;
+ uint64_t reserved_12_15:4;
+ uint64_t cslate:1;
+ uint64_t tritx:1;
+ uint64_t idleclks:2;
+ uint64_t cshi:1;
+ uint64_t csena:1;
+ uint64_t int_ena:1;
+ uint64_t lsbfirst:1;
+ uint64_t wireor:1;
+ uint64_t clk_cont:1;
+ uint64_t idlelo:1;
+ uint64_t enable:1;
+#else
+ uint64_t enable:1;
+ uint64_t idlelo:1;
+ uint64_t clk_cont:1;
+ uint64_t wireor:1;
+ uint64_t lsbfirst:1;
+ uint64_t int_ena:1;
+ uint64_t csena:1;
+ uint64_t cshi:1;
+ uint64_t idleclks:2;
+ uint64_t tritx:1;
+ uint64_t cslate:1;
+ uint64_t reserved_12_15:4;
+ uint64_t clkdiv:13;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_mpi_cfg_s cn30xx;
+ struct cvmx_mpi_cfg_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t clkdiv:13;
+ uint64_t reserved_11_15:5;
+ uint64_t tritx:1;
+ uint64_t idleclks:2;
+ uint64_t cshi:1;
+ uint64_t csena:1;
+ uint64_t int_ena:1;
+ uint64_t lsbfirst:1;
+ uint64_t wireor:1;
+ uint64_t clk_cont:1;
+ uint64_t idlelo:1;
+ uint64_t enable:1;
+#else
+ uint64_t enable:1;
+ uint64_t idlelo:1;
+ uint64_t clk_cont:1;
+ uint64_t wireor:1;
+ uint64_t lsbfirst:1;
+ uint64_t int_ena:1;
+ uint64_t csena:1;
+ uint64_t cshi:1;
+ uint64_t idleclks:2;
+ uint64_t tritx:1;
+ uint64_t reserved_11_15:5;
+ uint64_t clkdiv:13;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn31xx;
+ struct cvmx_mpi_cfg_s cn50xx;
+} cvmx_mpi_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mpi_datx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t data:8;
+#else
+ uint64_t data:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_mpi_datx_s cn30xx;
+ struct cvmx_mpi_datx_s cn31xx;
+ struct cvmx_mpi_datx_s cn50xx;
+} cvmx_mpi_datx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mpi_sts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t rxnum:5;
+ uint64_t reserved_1_7:7;
+ uint64_t busy:1;
+#else
+ uint64_t busy:1;
+ uint64_t reserved_1_7:7;
+ uint64_t rxnum:5;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_mpi_sts_s cn30xx;
+ struct cvmx_mpi_sts_s cn31xx;
+ struct cvmx_mpi_sts_s cn50xx;
+} cvmx_mpi_sts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_mpi_tx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t leavecs:1;
+ uint64_t reserved_13_15:3;
+ uint64_t txnum:5;
+ uint64_t reserved_5_7:3;
+ uint64_t totnum:5;
+#else
+ uint64_t totnum:5;
+ uint64_t reserved_5_7:3;
+ uint64_t txnum:5;
+ uint64_t reserved_13_15:3;
+ uint64_t leavecs:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_mpi_tx_s cn30xx;
+ struct cvmx_mpi_tx_s cn31xx;
+ struct cvmx_mpi_tx_s cn50xx;
+} cvmx_mpi_tx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_bt_pg_info_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t t_mult:4;
+ uint64_t adr_cyc:4;
+ uint64_t size:3;
+#else
+ uint64_t size:3;
+ uint64_t adr_cyc:4;
+ uint64_t t_mult:4;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_ndf_bt_pg_info_s cn52xx;
+} cvmx_ndf_bt_pg_info_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t nf_cmd:64;
+#else
+ uint64_t nf_cmd:64;
+#endif
+ } s;
+ struct cvmx_ndf_cmd_s cn52xx;
+} cvmx_ndf_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_drbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t cnt:8;
+#else
+ uint64_t cnt:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_ndf_drbell_s cn52xx;
+} cvmx_ndf_drbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_ecc_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t xor_ecc:24;
+ uint64_t ecc_err:8;
+#else
+ uint64_t ecc_err:8;
+ uint64_t xor_ecc:24;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_ndf_ecc_cnt_s cn52xx;
+} cvmx_ndf_ecc_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t ovrf:1;
+ uint64_t ecc_mult:1;
+ uint64_t ecc_1bit:1;
+ uint64_t sm_bad:1;
+ uint64_t wdog:1;
+ uint64_t full:1;
+ uint64_t empty:1;
+#else
+ uint64_t empty:1;
+ uint64_t full:1;
+ uint64_t wdog:1;
+ uint64_t sm_bad:1;
+ uint64_t ecc_1bit:1;
+ uint64_t ecc_mult:1;
+ uint64_t ovrf:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_ndf_int_s cn52xx;
+} cvmx_ndf_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t ovrf:1;
+ uint64_t ecc_mult:1;
+ uint64_t ecc_1bit:1;
+ uint64_t sm_bad:1;
+ uint64_t wdog:1;
+ uint64_t full:1;
+ uint64_t empty:1;
+#else
+ uint64_t empty:1;
+ uint64_t full:1;
+ uint64_t wdog:1;
+ uint64_t sm_bad:1;
+ uint64_t ecc_1bit:1;
+ uint64_t ecc_mult:1;
+ uint64_t ovrf:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_ndf_int_en_s cn52xx;
+} cvmx_ndf_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_misc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t nbr_hwm:3;
+ uint64_t wait_cnt:6;
+ uint64_t fr_byt:11;
+ uint64_t rd_done:1;
+ uint64_t rd_val:1;
+ uint64_t rd_cmd:1;
+ uint64_t bt_dma:1;
+ uint64_t bt_dis:1;
+ uint64_t ex_dis:1;
+ uint64_t rst_ff:1;
+#else
+ uint64_t rst_ff:1;
+ uint64_t ex_dis:1;
+ uint64_t bt_dis:1;
+ uint64_t bt_dma:1;
+ uint64_t rd_cmd:1;
+ uint64_t rd_val:1;
+ uint64_t rd_done:1;
+ uint64_t fr_byt:11;
+ uint64_t wait_cnt:6;
+ uint64_t nbr_hwm:3;
+ uint64_t reserved_27_63:37;
+#endif
+ } s;
+ struct cvmx_ndf_misc_s cn52xx;
+} cvmx_ndf_misc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_ndf_st_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t exe_idle:1;
+ uint64_t exe_sm:4;
+ uint64_t bt_sm:4;
+ uint64_t rd_ff_bad:1;
+ uint64_t rd_ff:2;
+ uint64_t main_bad:1;
+ uint64_t main_sm:3;
+#else
+ uint64_t main_sm:3;
+ uint64_t main_bad:1;
+ uint64_t rd_ff:2;
+ uint64_t rd_ff_bad:1;
+ uint64_t bt_sm:4;
+ uint64_t exe_sm:4;
+ uint64_t exe_idle:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_ndf_st_reg_s cn52xx;
+} cvmx_ndf_st_reg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_npei_bar1_indexx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_18_31:14;
+ uint32_t addr_idx:14;
+ uint32_t ca:1;
+ uint32_t end_swp:2;
+ uint32_t addr_v:1;
+#else
+ uint32_t addr_v:1;
+ uint32_t end_swp:2;
+ uint32_t ca:1;
+ uint32_t addr_idx:14;
+ uint32_t reserved_18_31:14;
+#endif
+ } s;
+ struct cvmx_npei_bar1_indexx_s cn52xx;
+ struct cvmx_npei_bar1_indexx_s cn52xxp1;
+ struct cvmx_npei_bar1_indexx_s cn56xx;
+ struct cvmx_npei_bar1_indexx_s cn56xxp1;
+} cvmx_npei_bar1_indexx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pkt_rdf:1;
+ uint64_t pkt_pmem:1;
+ uint64_t pkt_p1:1;
+ uint64_t reserved_60_60:1;
+ uint64_t pcr_gim:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcsr_int:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_sl:1;
+ uint64_t reserved_50_52:3;
+ uint64_t pkt_ind:1;
+ uint64_t pkt_slm:1;
+ uint64_t reserved_36_47:12;
+ uint64_t d0_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t reserved_31_31:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t p2n1_po:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t csm0:1;
+ uint64_t csm1:1;
+ uint64_t dif0:1;
+ uint64_t dif1:1;
+ uint64_t dif2:1;
+ uint64_t dif3:1;
+ uint64_t reserved_2_2:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+#else
+ uint64_t ncb_cmd:1;
+ uint64_t msi:1;
+ uint64_t reserved_2_2:1;
+ uint64_t dif3:1;
+ uint64_t dif2:1;
+ uint64_t dif1:1;
+ uint64_t dif0:1;
+ uint64_t csm1:1;
+ uint64_t csm0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_po:1;
+ uint64_t cpl_p1:1;
+ uint64_t cpl_p0:1;
+ uint64_t n2p1_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p0_c:1;
+ uint64_t reserved_31_31:1;
+ uint64_t d3_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d0_pst:1;
+ uint64_t reserved_36_47:12;
+ uint64_t pkt_slm:1;
+ uint64_t pkt_ind:1;
+ uint64_t reserved_50_52:3;
+ uint64_t pcsr_sl:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_int:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcr_gim:1;
+ uint64_t reserved_60_60:1;
+ uint64_t pkt_p1:1;
+ uint64_t pkt_pmem:1;
+ uint64_t pkt_rdf:1;
+#endif
+ } s;
+ struct cvmx_npei_bist_status_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pkt_rdf:1;
+ uint64_t pkt_pmem:1;
+ uint64_t pkt_p1:1;
+ uint64_t reserved_60_60:1;
+ uint64_t pcr_gim:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcsr_int:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pkt_imem:1;
+ uint64_t pkt_pfm:1;
+ uint64_t pkt_pof:1;
+ uint64_t reserved_48_49:2;
+ uint64_t pkt_pop0:1;
+ uint64_t pkt_pop1:1;
+ uint64_t d0_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d4_mem:1;
+ uint64_t ds_mem:1;
+ uint64_t reserved_36_39:4;
+ uint64_t d0_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d4_pst:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t p2n1_po:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t csm0:1;
+ uint64_t csm1:1;
+ uint64_t dif0:1;
+ uint64_t dif1:1;
+ uint64_t dif2:1;
+ uint64_t dif3:1;
+ uint64_t dif4:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+#else
+ uint64_t ncb_cmd:1;
+ uint64_t msi:1;
+ uint64_t dif4:1;
+ uint64_t dif3:1;
+ uint64_t dif2:1;
+ uint64_t dif1:1;
+ uint64_t dif0:1;
+ uint64_t csm1:1;
+ uint64_t csm0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_po:1;
+ uint64_t cpl_p1:1;
+ uint64_t cpl_p0:1;
+ uint64_t n2p1_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p0_c:1;
+ uint64_t d4_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d0_pst:1;
+ uint64_t reserved_36_39:4;
+ uint64_t ds_mem:1;
+ uint64_t d4_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d0_mem:1;
+ uint64_t pkt_pop1:1;
+ uint64_t pkt_pop0:1;
+ uint64_t reserved_48_49:2;
+ uint64_t pkt_pof:1;
+ uint64_t pkt_pfm:1;
+ uint64_t pkt_imem:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_int:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcr_gim:1;
+ uint64_t reserved_60_60:1;
+ uint64_t pkt_p1:1;
+ uint64_t pkt_pmem:1;
+ uint64_t pkt_rdf:1;
+#endif
+ } cn52xx;
+ struct cvmx_npei_bist_status_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_46_63:18;
+ uint64_t d0_mem0:1;
+ uint64_t d1_mem1:1;
+ uint64_t d2_mem2:1;
+ uint64_t d3_mem3:1;
+ uint64_t dr0_mem:1;
+ uint64_t d0_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t dr1_mem:1;
+ uint64_t d0_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t dr2_mem:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t p2n1_po:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t csm0:1;
+ uint64_t csm1:1;
+ uint64_t dif0:1;
+ uint64_t dif1:1;
+ uint64_t dif2:1;
+ uint64_t dif3:1;
+ uint64_t dr3_mem:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+#else
+ uint64_t ncb_cmd:1;
+ uint64_t msi:1;
+ uint64_t dr3_mem:1;
+ uint64_t dif3:1;
+ uint64_t dif2:1;
+ uint64_t dif1:1;
+ uint64_t dif0:1;
+ uint64_t csm1:1;
+ uint64_t csm0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_po:1;
+ uint64_t cpl_p1:1;
+ uint64_t cpl_p0:1;
+ uint64_t n2p1_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p0_c:1;
+ uint64_t dr2_mem:1;
+ uint64_t d3_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d0_pst:1;
+ uint64_t dr1_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d0_mem:1;
+ uint64_t dr0_mem:1;
+ uint64_t d3_mem3:1;
+ uint64_t d2_mem2:1;
+ uint64_t d1_mem1:1;
+ uint64_t d0_mem0:1;
+ uint64_t reserved_46_63:18;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_bist_status_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pkt_rdf:1;
+ uint64_t reserved_60_62:3;
+ uint64_t pcr_gim:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcsr_int:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pkt_imem:1;
+ uint64_t pkt_pfm:1;
+ uint64_t pkt_pof:1;
+ uint64_t reserved_48_49:2;
+ uint64_t pkt_pop0:1;
+ uint64_t pkt_pop1:1;
+ uint64_t d0_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d4_mem:1;
+ uint64_t ds_mem:1;
+ uint64_t reserved_36_39:4;
+ uint64_t d0_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d4_pst:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t p2n1_po:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t csm0:1;
+ uint64_t csm1:1;
+ uint64_t dif0:1;
+ uint64_t dif1:1;
+ uint64_t dif2:1;
+ uint64_t dif3:1;
+ uint64_t dif4:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+#else
+ uint64_t ncb_cmd:1;
+ uint64_t msi:1;
+ uint64_t dif4:1;
+ uint64_t dif3:1;
+ uint64_t dif2:1;
+ uint64_t dif1:1;
+ uint64_t dif0:1;
+ uint64_t csm1:1;
+ uint64_t csm0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_po:1;
+ uint64_t cpl_p1:1;
+ uint64_t cpl_p0:1;
+ uint64_t n2p1_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p0_c:1;
+ uint64_t d4_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d0_pst:1;
+ uint64_t reserved_36_39:4;
+ uint64_t ds_mem:1;
+ uint64_t d4_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d0_mem:1;
+ uint64_t pkt_pop1:1;
+ uint64_t pkt_pop0:1;
+ uint64_t reserved_48_49:2;
+ uint64_t pkt_pof:1;
+ uint64_t pkt_pfm:1;
+ uint64_t pkt_imem:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_int:1;
+ uint64_t pkt_pif:1;
+ uint64_t pcr_gim:1;
+ uint64_t reserved_60_62:3;
+ uint64_t pkt_rdf:1;
+#endif
+ } cn56xx;
+ struct cvmx_npei_bist_status_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_58_63:6;
+ uint64_t pcsr_int:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pkt_pout:1;
+ uint64_t pkt_imem:1;
+ uint64_t pkt_cntm:1;
+ uint64_t pkt_ind:1;
+ uint64_t pkt_slm:1;
+ uint64_t pkt_odf:1;
+ uint64_t pkt_oif:1;
+ uint64_t pkt_out:1;
+ uint64_t pkt_i0:1;
+ uint64_t pkt_i1:1;
+ uint64_t pkt_s0:1;
+ uint64_t pkt_s1:1;
+ uint64_t d0_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d4_mem:1;
+ uint64_t d0_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d4_pst:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t p2n1_po:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t csm0:1;
+ uint64_t csm1:1;
+ uint64_t dif0:1;
+ uint64_t dif1:1;
+ uint64_t dif2:1;
+ uint64_t dif3:1;
+ uint64_t dif4:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+#else
+ uint64_t ncb_cmd:1;
+ uint64_t msi:1;
+ uint64_t dif4:1;
+ uint64_t dif3:1;
+ uint64_t dif2:1;
+ uint64_t dif1:1;
+ uint64_t dif0:1;
+ uint64_t csm1:1;
+ uint64_t csm0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_co:1;
+ uint64_t p2n0_no:1;
+ uint64_t p2n0_po:1;
+ uint64_t p2n1_co:1;
+ uint64_t p2n1_no:1;
+ uint64_t p2n1_po:1;
+ uint64_t cpl_p1:1;
+ uint64_t cpl_p0:1;
+ uint64_t n2p1_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p0_c:1;
+ uint64_t d4_pst:1;
+ uint64_t d3_pst:1;
+ uint64_t d2_pst:1;
+ uint64_t d1_pst:1;
+ uint64_t d0_pst:1;
+ uint64_t d4_mem:1;
+ uint64_t d3_mem:1;
+ uint64_t d2_mem:1;
+ uint64_t d1_mem:1;
+ uint64_t d0_mem:1;
+ uint64_t pkt_s1:1;
+ uint64_t pkt_s0:1;
+ uint64_t pkt_i1:1;
+ uint64_t pkt_i0:1;
+ uint64_t pkt_out:1;
+ uint64_t pkt_oif:1;
+ uint64_t pkt_odf:1;
+ uint64_t pkt_slm:1;
+ uint64_t pkt_ind:1;
+ uint64_t pkt_cntm:1;
+ uint64_t pkt_imem:1;
+ uint64_t pkt_pout:1;
+ uint64_t pcsr_sl:1;
+ uint64_t pcsr_id:1;
+ uint64_t pcsr_cnt:1;
+ uint64_t pcsr_im:1;
+ uint64_t pcsr_int:1;
+ uint64_t reserved_58_63:6;
+#endif
+ } cn56xxp1;
+} cvmx_npei_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_bist_status2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t psc_p0:1;
+ uint64_t psc_p1:1;
+ uint64_t pkt_gd:1;
+ uint64_t pkt_gl:1;
+ uint64_t pkt_blk:1;
+#else
+ uint64_t pkt_blk:1;
+ uint64_t pkt_gl:1;
+ uint64_t pkt_gd:1;
+ uint64_t psc_p1:1;
+ uint64_t psc_p0:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_npei_bist_status2_s cn52xx;
+ struct cvmx_npei_bist_status2_s cn56xx;
+} cvmx_npei_bist_status2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_ctl_port0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t waitl_com:1;
+ uint64_t intd:1;
+ uint64_t intc:1;
+ uint64_t intb:1;
+ uint64_t inta:1;
+ uint64_t intd_map:2;
+ uint64_t intc_map:2;
+ uint64_t intb_map:2;
+ uint64_t inta_map:2;
+ uint64_t ctlp_ro:1;
+ uint64_t reserved_6_6:1;
+ uint64_t ptlp_ro:1;
+ uint64_t bar2_enb:1;
+ uint64_t bar2_esx:2;
+ uint64_t bar2_cax:1;
+ uint64_t wait_com:1;
+#else
+ uint64_t wait_com:1;
+ uint64_t bar2_cax:1;
+ uint64_t bar2_esx:2;
+ uint64_t bar2_enb:1;
+ uint64_t ptlp_ro:1;
+ uint64_t reserved_6_6:1;
+ uint64_t ctlp_ro:1;
+ uint64_t inta_map:2;
+ uint64_t intb_map:2;
+ uint64_t intc_map:2;
+ uint64_t intd_map:2;
+ uint64_t inta:1;
+ uint64_t intb:1;
+ uint64_t intc:1;
+ uint64_t intd:1;
+ uint64_t waitl_com:1;
+ uint64_t reserved_21_63:43;
+#endif
+ } s;
+ struct cvmx_npei_ctl_port0_s cn52xx;
+ struct cvmx_npei_ctl_port0_s cn52xxp1;
+ struct cvmx_npei_ctl_port0_s cn56xx;
+ struct cvmx_npei_ctl_port0_s cn56xxp1;
+} cvmx_npei_ctl_port0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_ctl_port1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t waitl_com:1;
+ uint64_t intd:1;
+ uint64_t intc:1;
+ uint64_t intb:1;
+ uint64_t inta:1;
+ uint64_t intd_map:2;
+ uint64_t intc_map:2;
+ uint64_t intb_map:2;
+ uint64_t inta_map:2;
+ uint64_t ctlp_ro:1;
+ uint64_t reserved_6_6:1;
+ uint64_t ptlp_ro:1;
+ uint64_t bar2_enb:1;
+ uint64_t bar2_esx:2;
+ uint64_t bar2_cax:1;
+ uint64_t wait_com:1;
+#else
+ uint64_t wait_com:1;
+ uint64_t bar2_cax:1;
+ uint64_t bar2_esx:2;
+ uint64_t bar2_enb:1;
+ uint64_t ptlp_ro:1;
+ uint64_t reserved_6_6:1;
+ uint64_t ctlp_ro:1;
+ uint64_t inta_map:2;
+ uint64_t intb_map:2;
+ uint64_t intc_map:2;
+ uint64_t intd_map:2;
+ uint64_t inta:1;
+ uint64_t intb:1;
+ uint64_t intc:1;
+ uint64_t intd:1;
+ uint64_t waitl_com:1;
+ uint64_t reserved_21_63:43;
+#endif
+ } s;
+ struct cvmx_npei_ctl_port1_s cn52xx;
+ struct cvmx_npei_ctl_port1_s cn52xxp1;
+ struct cvmx_npei_ctl_port1_s cn56xx;
+ struct cvmx_npei_ctl_port1_s cn56xxp1;
+} cvmx_npei_ctl_port1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t p1_ntags:6;
+ uint64_t p0_ntags:6;
+ uint64_t cfg_rtry:16;
+ uint64_t ring_en:1;
+ uint64_t lnk_rst:1;
+ uint64_t arb:1;
+ uint64_t pkt_bp:4;
+ uint64_t host_mode:1;
+ uint64_t chip_rev:8;
+#else
+ uint64_t chip_rev:8;
+ uint64_t host_mode:1;
+ uint64_t pkt_bp:4;
+ uint64_t arb:1;
+ uint64_t lnk_rst:1;
+ uint64_t ring_en:1;
+ uint64_t cfg_rtry:16;
+ uint64_t p0_ntags:6;
+ uint64_t p1_ntags:6;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npei_ctl_status_s cn52xx;
+ struct cvmx_npei_ctl_status_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t p1_ntags:6;
+ uint64_t p0_ntags:6;
+ uint64_t cfg_rtry:16;
+ uint64_t reserved_15_15:1;
+ uint64_t lnk_rst:1;
+ uint64_t arb:1;
+ uint64_t reserved_9_12:4;
+ uint64_t host_mode:1;
+ uint64_t chip_rev:8;
+#else
+ uint64_t chip_rev:8;
+ uint64_t host_mode:1;
+ uint64_t reserved_9_12:4;
+ uint64_t arb:1;
+ uint64_t lnk_rst:1;
+ uint64_t reserved_15_15:1;
+ uint64_t cfg_rtry:16;
+ uint64_t p0_ntags:6;
+ uint64_t p1_ntags:6;
+ uint64_t reserved_44_63:20;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_ctl_status_s cn56xx;
+ struct cvmx_npei_ctl_status_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ring_en:1;
+ uint64_t lnk_rst:1;
+ uint64_t arb:1;
+ uint64_t pkt_bp:4;
+ uint64_t host_mode:1;
+ uint64_t chip_rev:8;
+#else
+ uint64_t chip_rev:8;
+ uint64_t host_mode:1;
+ uint64_t pkt_bp:4;
+ uint64_t arb:1;
+ uint64_t lnk_rst:1;
+ uint64_t ring_en:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn56xxp1;
+} cvmx_npei_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_ctl_status2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mps:1;
+ uint64_t mrrs:3;
+ uint64_t c1_w_flt:1;
+ uint64_t c0_w_flt:1;
+ uint64_t c1_b1_s:3;
+ uint64_t c0_b1_s:3;
+ uint64_t c1_wi_d:1;
+ uint64_t c1_b0_d:1;
+ uint64_t c0_wi_d:1;
+ uint64_t c0_b0_d:1;
+#else
+ uint64_t c0_b0_d:1;
+ uint64_t c0_wi_d:1;
+ uint64_t c1_b0_d:1;
+ uint64_t c1_wi_d:1;
+ uint64_t c0_b1_s:3;
+ uint64_t c1_b1_s:3;
+ uint64_t c0_w_flt:1;
+ uint64_t c1_w_flt:1;
+ uint64_t mrrs:3;
+ uint64_t mps:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npei_ctl_status2_s cn52xx;
+ struct cvmx_npei_ctl_status2_s cn52xxp1;
+ struct cvmx_npei_ctl_status2_s cn56xx;
+ struct cvmx_npei_ctl_status2_s cn56xxp1;
+} cvmx_npei_ctl_status2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_data_out_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t p1_ucnt:16;
+ uint64_t p1_fcnt:6;
+ uint64_t p0_ucnt:16;
+ uint64_t p0_fcnt:6;
+#else
+ uint64_t p0_fcnt:6;
+ uint64_t p0_ucnt:16;
+ uint64_t p1_fcnt:6;
+ uint64_t p1_ucnt:16;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npei_data_out_cnt_s cn52xx;
+ struct cvmx_npei_data_out_cnt_s cn52xxp1;
+ struct cvmx_npei_data_out_cnt_s cn56xx;
+ struct cvmx_npei_data_out_cnt_s cn56xxp1;
+} cvmx_npei_data_out_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dbg_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t reserved_25_26:2;
+ uint64_t qlm1_spd:2;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t qlm1_spd:2;
+ uint64_t reserved_25_26:2;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t reserved_28_63:36;
+#endif
+ } s;
+ struct cvmx_npei_dbg_data_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t qlm0_link_width:1;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t qlm1_mode:2;
+ uint64_t qlm1_spd:2;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t qlm1_spd:2;
+ uint64_t qlm1_mode:2;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t qlm0_link_width:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn52xx;
+ struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
+ struct cvmx_npei_dbg_data_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t qlm2_rev_lanes:1;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t qlm3_spd:2;
+ uint64_t qlm1_spd:2;
+ uint64_t c_mul:5;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+#else
+ uint64_t data:17;
+ uint64_t dsel_ext:1;
+ uint64_t c_mul:5;
+ uint64_t qlm1_spd:2;
+ uint64_t qlm3_spd:2;
+ uint64_t qlm0_rev_lanes:1;
+ uint64_t qlm2_rev_lanes:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn56xx;
+ struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
+} cvmx_npei_dbg_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dbg_select_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dbg_sel:16;
+#else
+ uint64_t dbg_sel:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npei_dbg_select_s cn52xx;
+ struct cvmx_npei_dbg_select_s cn52xxp1;
+ struct cvmx_npei_dbg_select_s cn56xx;
+ struct cvmx_npei_dbg_select_s cn56xxp1;
+} cvmx_npei_dbg_select_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dmax_counts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t fcnt:7;
+ uint64_t dbell:32;
+#else
+ uint64_t dbell:32;
+ uint64_t fcnt:7;
+ uint64_t reserved_39_63:25;
+#endif
+ } s;
+ struct cvmx_npei_dmax_counts_s cn52xx;
+ struct cvmx_npei_dmax_counts_s cn52xxp1;
+ struct cvmx_npei_dmax_counts_s cn56xx;
+ struct cvmx_npei_dmax_counts_s cn56xxp1;
+} cvmx_npei_dmax_counts_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_npei_dmax_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t dbell:16;
+#else
+ uint32_t dbell:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_npei_dmax_dbell_s cn52xx;
+ struct cvmx_npei_dmax_dbell_s cn52xxp1;
+ struct cvmx_npei_dmax_dbell_s cn56xx;
+ struct cvmx_npei_dmax_dbell_s cn56xxp1;
+} cvmx_npei_dmax_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dmax_ibuff_saddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t idle:1;
+ uint64_t saddr:29;
+ uint64_t reserved_0_6:7;
+#else
+ uint64_t reserved_0_6:7;
+ uint64_t saddr:29;
+ uint64_t idle:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } s;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t saddr:29;
+ uint64_t reserved_0_6:7;
+#else
+ uint64_t reserved_0_6:7;
+ uint64_t saddr:29;
+ uint64_t reserved_36_63:28;
+#endif
+ } cn52xx;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+ struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+} cvmx_npei_dmax_ibuff_saddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dmax_naddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_npei_dmax_naddr_s cn52xx;
+ struct cvmx_npei_dmax_naddr_s cn52xxp1;
+ struct cvmx_npei_dmax_naddr_s cn56xx;
+ struct cvmx_npei_dmax_naddr_s cn56xxp1;
+} cvmx_npei_dmax_naddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dma0_int_level_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t time:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t time:32;
+#endif
+ } s;
+ struct cvmx_npei_dma0_int_level_s cn52xx;
+ struct cvmx_npei_dma0_int_level_s cn52xxp1;
+ struct cvmx_npei_dma0_int_level_s cn56xx;
+ struct cvmx_npei_dma0_int_level_s cn56xxp1;
+} cvmx_npei_dma0_int_level_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dma1_int_level_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t time:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t time:32;
+#endif
+ } s;
+ struct cvmx_npei_dma1_int_level_s cn52xx;
+ struct cvmx_npei_dma1_int_level_s cn52xxp1;
+ struct cvmx_npei_dma1_int_level_s cn56xx;
+ struct cvmx_npei_dma1_int_level_s cn56xxp1;
+} cvmx_npei_dma1_int_level_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dma_cnts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dma1:32;
+ uint64_t dma0:32;
+#else
+ uint64_t dma0:32;
+ uint64_t dma1:32;
+#endif
+ } s;
+ struct cvmx_npei_dma_cnts_s cn52xx;
+ struct cvmx_npei_dma_cnts_s cn52xxp1;
+ struct cvmx_npei_dma_cnts_s cn56xx;
+ struct cvmx_npei_dma_cnts_s cn56xxp1;
+} cvmx_npei_dma_cnts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_dma_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t dma4_enb:1;
+ uint64_t dma3_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma0_enb:1;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t csize:14;
+#else
+ uint64_t csize:14;
+ uint64_t o_mode:1;
+ uint64_t o_es:2;
+ uint64_t o_ns:1;
+ uint64_t o_ro:1;
+ uint64_t o_add1:1;
+ uint64_t fpa_que:3;
+ uint64_t dwb_ichk:9;
+ uint64_t dwb_denb:1;
+ uint64_t b0_lend:1;
+ uint64_t dma0_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma3_enb:1;
+ uint64_t dma4_enb:1;
+ uint64_t reserved_39_63:25;
+#endif
+ } s;
+ struct cvmx_npei_dma_control_s cn52xx;
+ struct cvmx_npei_dma_control_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t dma3_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma0_enb:1;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t csize:14;
+#else
+ uint64_t csize:14;
+ uint64_t o_mode:1;
+ uint64_t o_es:2;
+ uint64_t o_ns:1;
+ uint64_t o_ro:1;
+ uint64_t o_add1:1;
+ uint64_t fpa_que:3;
+ uint64_t dwb_ichk:9;
+ uint64_t dwb_denb:1;
+ uint64_t b0_lend:1;
+ uint64_t dma0_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma3_enb:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_dma_control_s cn56xx;
+ struct cvmx_npei_dma_control_s cn56xxp1;
+} cvmx_npei_dma_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_a_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pout_err:1;
+ uint64_t pin_bp:1;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_npei_int_a_enb_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn52xx;
+ struct cvmx_npei_int_a_enb_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_a_enb_s cn56xx;
+} cvmx_npei_int_a_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_a_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pout_err:1;
+ uint64_t pin_bp:1;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_npei_int_a_enb2_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn52xx;
+ struct cvmx_npei_int_a_enb2_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_a_enb2_s cn56xx;
+} cvmx_npei_int_a_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_a_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pout_err:1;
+ uint64_t pin_bp:1;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_npei_int_a_sum_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t p1_rdlk:1;
+ uint64_t p0_rdlk:1;
+ uint64_t pgl_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pop_err:1;
+ uint64_t pins_err:1;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t p0_rdlk:1;
+ uint64_t p1_rdlk:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } cn52xx;
+ struct cvmx_npei_int_a_sum_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t dma1_cpl:1;
+ uint64_t dma0_cpl:1;
+#else
+ uint64_t dma0_cpl:1;
+ uint64_t dma1_cpl:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_a_sum_s cn56xx;
+} cvmx_npei_int_a_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_62_62:1;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_62:1;
+ uint64_t mio_inta:1;
+#endif
+ } s;
+ struct cvmx_npei_int_enb_s cn52xx;
+ struct cvmx_npei_int_enb_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_62_62:1;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_62:1;
+ uint64_t mio_inta:1;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_enb_s cn56xx;
+ struct cvmx_npei_int_enb_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_61_62:2;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t reserved_61_62:2;
+ uint64_t mio_inta:1;
+#endif
+ } cn56xxp1;
+} cvmx_npei_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } s;
+ struct cvmx_npei_int_enb2_s cn52xx;
+ struct cvmx_npei_int_enb2_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_enb2_s cn56xx;
+ struct cvmx_npei_int_enb2_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_61_63:3;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t reserved_61_63:3;
+#endif
+ } cn56xxp1;
+} cvmx_npei_int_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_info_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t pidbof:6;
+ uint64_t psldbof:6;
+#else
+ uint64_t psldbof:6;
+ uint64_t pidbof:6;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_npei_int_info_s cn52xx;
+ struct cvmx_npei_int_info_s cn56xx;
+ struct cvmx_npei_int_info_s cn56xxp1;
+} cvmx_npei_int_info_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_62_62:1;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_62:1;
+ uint64_t mio_inta:1;
+#endif
+ } s;
+ struct cvmx_npei_int_sum_s cn52xx;
+ struct cvmx_npei_int_sum_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_62_62:1;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t reserved_15_18:4;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t reserved_15_18:4;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_62:1;
+ uint64_t mio_inta:1;
+#endif
+ } cn52xxp1;
+ struct cvmx_npei_int_sum_s cn56xx;
+ struct cvmx_npei_int_sum_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_61_62:2;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_aeri:1;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t pidbof:1;
+ uint64_t psldbof:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma4dbo:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t pcnt:1;
+ uint64_t ptime:1;
+ uint64_t c0_aeri:1;
+ uint64_t reserved_20_20:1;
+ uint64_t c0_se:1;
+ uint64_t reserved_22_22:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t reserved_27_27:1;
+ uint64_t c1_se:1;
+ uint64_t reserved_29_29:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t reserved_61_62:2;
+ uint64_t mio_inta:1;
+#endif
+ } cn56xxp1;
+} cvmx_npei_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_int_sum2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mio_inta:1;
+ uint64_t reserved_62_62:1;
+ uint64_t int_a:1;
+ uint64_t c1_ldwn:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c1_hpint:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_wake:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_aeri:1;
+ uint64_t c0_hpint:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_wake:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_aeri:1;
+ uint64_t reserved_15_18:4;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t dma1fi:1;
+ uint64_t dma0fi:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma3dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma0dbo:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t bar0_to:1;
+ uint64_t iob2big:1;
+ uint64_t dma0dbo:1;
+ uint64_t dma1dbo:1;
+ uint64_t dma2dbo:1;
+ uint64_t dma3dbo:1;
+ uint64_t reserved_8_8:1;
+ uint64_t dma0fi:1;
+ uint64_t dma1fi:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t reserved_15_18:4;
+ uint64_t c0_aeri:1;
+ uint64_t crs0_er:1;
+ uint64_t c0_se:1;
+ uint64_t crs0_dr:1;
+ uint64_t c0_wake:1;
+ uint64_t c0_pmei:1;
+ uint64_t c0_hpint:1;
+ uint64_t c1_aeri:1;
+ uint64_t crs1_er:1;
+ uint64_t c1_se:1;
+ uint64_t crs1_dr:1;
+ uint64_t c1_wake:1;
+ uint64_t c1_pmei:1;
+ uint64_t c1_hpint:1;
+ uint64_t c0_up_b0:1;
+ uint64_t c0_up_b1:1;
+ uint64_t c0_up_b2:1;
+ uint64_t c0_up_wi:1;
+ uint64_t c0_up_bx:1;
+ uint64_t c0_un_b0:1;
+ uint64_t c0_un_b1:1;
+ uint64_t c0_un_b2:1;
+ uint64_t c0_un_wi:1;
+ uint64_t c0_un_bx:1;
+ uint64_t c1_up_b0:1;
+ uint64_t c1_up_b1:1;
+ uint64_t c1_up_b2:1;
+ uint64_t c1_up_wi:1;
+ uint64_t c1_up_bx:1;
+ uint64_t c1_un_b0:1;
+ uint64_t c1_un_b1:1;
+ uint64_t c1_un_b2:1;
+ uint64_t c1_un_wi:1;
+ uint64_t c1_un_bx:1;
+ uint64_t c0_un_wf:1;
+ uint64_t c1_un_wf:1;
+ uint64_t c0_up_wf:1;
+ uint64_t c1_up_wf:1;
+ uint64_t c0_exc:1;
+ uint64_t c1_exc:1;
+ uint64_t c0_ldwn:1;
+ uint64_t c1_ldwn:1;
+ uint64_t int_a:1;
+ uint64_t reserved_62_62:1;
+ uint64_t mio_inta:1;
+#endif
+ } s;
+ struct cvmx_npei_int_sum2_s cn52xx;
+ struct cvmx_npei_int_sum2_s cn52xxp1;
+ struct cvmx_npei_int_sum2_s cn56xx;
+} cvmx_npei_int_sum2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_last_win_rdata0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_npei_last_win_rdata0_s cn52xx;
+ struct cvmx_npei_last_win_rdata0_s cn52xxp1;
+ struct cvmx_npei_last_win_rdata0_s cn56xx;
+ struct cvmx_npei_last_win_rdata0_s cn56xxp1;
+} cvmx_npei_last_win_rdata0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_last_win_rdata1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_npei_last_win_rdata1_s cn52xx;
+ struct cvmx_npei_last_win_rdata1_s cn52xxp1;
+ struct cvmx_npei_last_win_rdata1_s cn56xx;
+ struct cvmx_npei_last_win_rdata1_s cn56xxp1;
+} cvmx_npei_last_win_rdata1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_mem_access_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t max_word:4;
+ uint64_t timer:10;
+#else
+ uint64_t timer:10;
+ uint64_t max_word:4;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_npei_mem_access_ctl_s cn52xx;
+ struct cvmx_npei_mem_access_ctl_s cn52xxp1;
+ struct cvmx_npei_mem_access_ctl_s cn56xx;
+ struct cvmx_npei_mem_access_ctl_s cn56xxp1;
+} cvmx_npei_mem_access_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_mem_access_subidx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_42_63:22;
+ uint64_t zero:1;
+ uint64_t port:2;
+ uint64_t nmerge:1;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t nsr:1;
+ uint64_t nsw:1;
+ uint64_t ror:1;
+ uint64_t row:1;
+ uint64_t ba:30;
+#else
+ uint64_t ba:30;
+ uint64_t row:1;
+ uint64_t ror:1;
+ uint64_t nsw:1;
+ uint64_t nsr:1;
+ uint64_t esw:2;
+ uint64_t esr:2;
+ uint64_t nmerge:1;
+ uint64_t port:2;
+ uint64_t zero:1;
+ uint64_t reserved_42_63:22;
+#endif
+ } s;
+ struct cvmx_npei_mem_access_subidx_s cn52xx;
+ struct cvmx_npei_mem_access_subidx_s cn52xxp1;
+ struct cvmx_npei_mem_access_subidx_s cn56xx;
+ struct cvmx_npei_mem_access_subidx_s cn56xxp1;
+} cvmx_npei_mem_access_subidx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_enb0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t enb:64;
+#else
+ uint64_t enb:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_enb0_s cn52xx;
+ struct cvmx_npei_msi_enb0_s cn52xxp1;
+ struct cvmx_npei_msi_enb0_s cn56xx;
+ struct cvmx_npei_msi_enb0_s cn56xxp1;
+} cvmx_npei_msi_enb0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_enb1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t enb:64;
+#else
+ uint64_t enb:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_enb1_s cn52xx;
+ struct cvmx_npei_msi_enb1_s cn52xxp1;
+ struct cvmx_npei_msi_enb1_s cn56xx;
+ struct cvmx_npei_msi_enb1_s cn56xxp1;
+} cvmx_npei_msi_enb1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t enb:64;
+#else
+ uint64_t enb:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_enb2_s cn52xx;
+ struct cvmx_npei_msi_enb2_s cn52xxp1;
+ struct cvmx_npei_msi_enb2_s cn56xx;
+ struct cvmx_npei_msi_enb2_s cn56xxp1;
+} cvmx_npei_msi_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_enb3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t enb:64;
+#else
+ uint64_t enb:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_enb3_s cn52xx;
+ struct cvmx_npei_msi_enb3_s cn52xxp1;
+ struct cvmx_npei_msi_enb3_s cn56xx;
+ struct cvmx_npei_msi_enb3_s cn56xxp1;
+} cvmx_npei_msi_enb3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_rcv0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t intr:64;
+#else
+ uint64_t intr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_rcv0_s cn52xx;
+ struct cvmx_npei_msi_rcv0_s cn52xxp1;
+ struct cvmx_npei_msi_rcv0_s cn56xx;
+ struct cvmx_npei_msi_rcv0_s cn56xxp1;
+} cvmx_npei_msi_rcv0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_rcv1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t intr:64;
+#else
+ uint64_t intr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_rcv1_s cn52xx;
+ struct cvmx_npei_msi_rcv1_s cn52xxp1;
+ struct cvmx_npei_msi_rcv1_s cn56xx;
+ struct cvmx_npei_msi_rcv1_s cn56xxp1;
+} cvmx_npei_msi_rcv1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_rcv2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t intr:64;
+#else
+ uint64_t intr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_rcv2_s cn52xx;
+ struct cvmx_npei_msi_rcv2_s cn52xxp1;
+ struct cvmx_npei_msi_rcv2_s cn56xx;
+ struct cvmx_npei_msi_rcv2_s cn56xxp1;
+} cvmx_npei_msi_rcv2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_rcv3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t intr:64;
+#else
+ uint64_t intr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_rcv3_s cn52xx;
+ struct cvmx_npei_msi_rcv3_s cn52xxp1;
+ struct cvmx_npei_msi_rcv3_s cn56xx;
+ struct cvmx_npei_msi_rcv3_s cn56xxp1;
+} cvmx_npei_msi_rcv3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_rd_map_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t rd_int:8;
+ uint64_t msi_int:8;
+#else
+ uint64_t msi_int:8;
+ uint64_t rd_int:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npei_msi_rd_map_s cn52xx;
+ struct cvmx_npei_msi_rd_map_s cn52xxp1;
+ struct cvmx_npei_msi_rd_map_s cn56xx;
+ struct cvmx_npei_msi_rd_map_s cn56xxp1;
+} cvmx_npei_msi_rd_map_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1c_enb0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t clr:64;
+#else
+ uint64_t clr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1c_enb0_s cn52xx;
+ struct cvmx_npei_msi_w1c_enb0_s cn56xx;
+} cvmx_npei_msi_w1c_enb0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1c_enb1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t clr:64;
+#else
+ uint64_t clr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1c_enb1_s cn52xx;
+ struct cvmx_npei_msi_w1c_enb1_s cn56xx;
+} cvmx_npei_msi_w1c_enb1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1c_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t clr:64;
+#else
+ uint64_t clr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1c_enb2_s cn52xx;
+ struct cvmx_npei_msi_w1c_enb2_s cn56xx;
+} cvmx_npei_msi_w1c_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1c_enb3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t clr:64;
+#else
+ uint64_t clr:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1c_enb3_s cn52xx;
+ struct cvmx_npei_msi_w1c_enb3_s cn56xx;
+} cvmx_npei_msi_w1c_enb3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1s_enb0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t set:64;
+#else
+ uint64_t set:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1s_enb0_s cn52xx;
+ struct cvmx_npei_msi_w1s_enb0_s cn56xx;
+} cvmx_npei_msi_w1s_enb0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1s_enb1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t set:64;
+#else
+ uint64_t set:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1s_enb1_s cn52xx;
+ struct cvmx_npei_msi_w1s_enb1_s cn56xx;
+} cvmx_npei_msi_w1s_enb1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1s_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t set:64;
+#else
+ uint64_t set:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1s_enb2_s cn52xx;
+ struct cvmx_npei_msi_w1s_enb2_s cn56xx;
+} cvmx_npei_msi_w1s_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_w1s_enb3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t set:64;
+#else
+ uint64_t set:64;
+#endif
+ } s;
+ struct cvmx_npei_msi_w1s_enb3_s cn52xx;
+ struct cvmx_npei_msi_w1s_enb3_s cn56xx;
+} cvmx_npei_msi_w1s_enb3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_msi_wr_map_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ciu_int:8;
+ uint64_t msi_int:8;
+#else
+ uint64_t msi_int:8;
+ uint64_t ciu_int:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npei_msi_wr_map_s cn52xx;
+ struct cvmx_npei_msi_wr_map_s cn52xxp1;
+ struct cvmx_npei_msi_wr_map_s cn56xx;
+ struct cvmx_npei_msi_wr_map_s cn56xxp1;
+} cvmx_npei_msi_wr_map_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pcie_credit_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t p1_ccnt:8;
+ uint64_t p1_ncnt:8;
+ uint64_t p1_pcnt:8;
+ uint64_t p0_ccnt:8;
+ uint64_t p0_ncnt:8;
+ uint64_t p0_pcnt:8;
+#else
+ uint64_t p0_pcnt:8;
+ uint64_t p0_ncnt:8;
+ uint64_t p0_ccnt:8;
+ uint64_t p1_pcnt:8;
+ uint64_t p1_ncnt:8;
+ uint64_t p1_ccnt:8;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_npei_pcie_credit_cnt_s cn52xx;
+ struct cvmx_npei_pcie_credit_cnt_s cn56xx;
+} cvmx_npei_pcie_credit_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pcie_msi_rcv_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t intr:8;
+#else
+ uint64_t intr:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_npei_pcie_msi_rcv_s cn52xx;
+ struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
+ struct cvmx_npei_pcie_msi_rcv_s cn56xx;
+ struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pcie_msi_rcv_b1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t intr:8;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t intr:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
+ struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
+ struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
+ struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pcie_msi_rcv_b2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t intr:8;
+ uint64_t reserved_0_15:16;
+#else
+ uint64_t reserved_0_15:16;
+ uint64_t intr:8;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
+ struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
+ struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
+ struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pcie_msi_rcv_b3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t intr:8;
+ uint64_t reserved_0_23:24;
+#else
+ uint64_t reserved_0_23:24;
+ uint64_t intr:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
+ struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
+ struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
+ struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_cnts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_54_63:10;
+ uint64_t timer:22;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t timer:22;
+ uint64_t reserved_54_63:10;
+#endif
+ } s;
+ struct cvmx_npei_pktx_cnts_s cn52xx;
+ struct cvmx_npei_pktx_cnts_s cn56xx;
+ struct cvmx_npei_pktx_cnts_s cn56xxp1;
+} cvmx_npei_pktx_cnts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_in_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t wmark:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t wmark:32;
+#endif
+ } s;
+ struct cvmx_npei_pktx_in_bp_s cn52xx;
+ struct cvmx_npei_pktx_in_bp_s cn56xx;
+ struct cvmx_npei_pktx_in_bp_s cn56xxp1;
+} cvmx_npei_pktx_in_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_instr_baddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:61;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t addr:61;
+#endif
+ } s;
+ struct cvmx_npei_pktx_instr_baddr_s cn52xx;
+ struct cvmx_npei_pktx_instr_baddr_s cn56xx;
+ struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
+} cvmx_npei_pktx_instr_baddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_instr_baoff_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t aoff:32;
+ uint64_t dbell:32;
+#else
+ uint64_t dbell:32;
+ uint64_t aoff:32;
+#endif
+ } s;
+ struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
+ struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
+ struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
+} cvmx_npei_pktx_instr_baoff_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_instr_fifo_rsize_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t max:9;
+ uint64_t rrp:9;
+ uint64_t wrp:9;
+ uint64_t fcnt:5;
+ uint64_t rsize:32;
+#else
+ uint64_t rsize:32;
+ uint64_t fcnt:5;
+ uint64_t wrp:9;
+ uint64_t rrp:9;
+ uint64_t max:9;
+#endif
+ } s;
+ struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
+ struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
+ struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
+} cvmx_npei_pktx_instr_fifo_rsize_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_instr_header_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t rsv_f:5;
+ uint64_t rparmode:2;
+ uint64_t rsv_e:1;
+ uint64_t rskp_len:7;
+ uint64_t rsv_d:6;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_c:5;
+ uint64_t par_mode:2;
+ uint64_t rsv_b:1;
+ uint64_t skp_len:7;
+ uint64_t rsv_a:6;
+#else
+ uint64_t rsv_a:6;
+ uint64_t skp_len:7;
+ uint64_t rsv_b:1;
+ uint64_t par_mode:2;
+ uint64_t rsv_c:5;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_d:6;
+ uint64_t rskp_len:7;
+ uint64_t rsv_e:1;
+ uint64_t rparmode:2;
+ uint64_t rsv_f:5;
+ uint64_t pbp:1;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npei_pktx_instr_header_s cn52xx;
+ struct cvmx_npei_pktx_instr_header_s cn56xx;
+ struct cvmx_npei_pktx_instr_header_s cn56xxp1;
+} cvmx_npei_pktx_instr_header_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_slist_baddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:60;
+ uint64_t reserved_0_3:4;
+#else
+ uint64_t reserved_0_3:4;
+ uint64_t addr:60;
+#endif
+ } s;
+ struct cvmx_npei_pktx_slist_baddr_s cn52xx;
+ struct cvmx_npei_pktx_slist_baddr_s cn56xx;
+ struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
+} cvmx_npei_pktx_slist_baddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_slist_baoff_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t aoff:32;
+ uint64_t dbell:32;
+#else
+ uint64_t dbell:32;
+ uint64_t aoff:32;
+#endif
+ } s;
+ struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
+ struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
+ struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
+} cvmx_npei_pktx_slist_baoff_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pktx_slist_fifo_rsize_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rsize:32;
+#else
+ uint64_t rsize:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
+ struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
+ struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
+} cvmx_npei_pktx_slist_fifo_rsize_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_cnt_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+#else
+ uint64_t port:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_cnt_int_s cn52xx;
+ struct cvmx_npei_pkt_cnt_int_s cn56xx;
+ struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
+} cvmx_npei_pkt_cnt_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_cnt_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+#else
+ uint64_t port:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
+ struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
+ struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
+} cvmx_npei_pkt_cnt_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_data_out_es_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t es:64;
+#else
+ uint64_t es:64;
+#endif
+ } s;
+ struct cvmx_npei_pkt_data_out_es_s cn52xx;
+ struct cvmx_npei_pkt_data_out_es_s cn56xx;
+ struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
+} cvmx_npei_pkt_data_out_es_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_data_out_ns_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nsr:32;
+#else
+ uint64_t nsr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_data_out_ns_s cn52xx;
+ struct cvmx_npei_pkt_data_out_ns_s cn56xx;
+ struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
+} cvmx_npei_pkt_data_out_ns_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_data_out_ror_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ror:32;
+#else
+ uint64_t ror:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_data_out_ror_s cn52xx;
+ struct cvmx_npei_pkt_data_out_ror_s cn56xx;
+ struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
+} cvmx_npei_pkt_data_out_ror_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_dpaddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dptr:32;
+#else
+ uint64_t dptr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_dpaddr_s cn52xx;
+ struct cvmx_npei_pkt_dpaddr_s cn56xx;
+ struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
+} cvmx_npei_pkt_dpaddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_in_bp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bp:32;
+#else
+ uint64_t bp:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_in_bp_s cn56xx;
+} cvmx_npei_pkt_in_bp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_in_donex_cnts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
+ struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
+ struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
+} cvmx_npei_pkt_in_donex_cnts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_in_instr_counts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t wr_cnt:32;
+ uint64_t rd_cnt:32;
+#else
+ uint64_t rd_cnt:32;
+ uint64_t wr_cnt:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
+ struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
+} cvmx_npei_pkt_in_instr_counts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_in_pcie_port_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pp:64;
+#else
+ uint64_t pp:64;
+#endif
+ } s;
+ struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
+ struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
+} cvmx_npei_pkt_in_pcie_port_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_input_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t pkt_rr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t d_nsr:1;
+ uint64_t d_esr:2;
+ uint64_t d_ror:1;
+ uint64_t use_csr:1;
+ uint64_t nsr:1;
+ uint64_t esr:2;
+ uint64_t ror:1;
+#else
+ uint64_t ror:1;
+ uint64_t esr:2;
+ uint64_t nsr:1;
+ uint64_t use_csr:1;
+ uint64_t d_ror:1;
+ uint64_t d_esr:2;
+ uint64_t d_nsr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t pkt_rr:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_npei_pkt_input_control_s cn52xx;
+ struct cvmx_npei_pkt_input_control_s cn56xx;
+ struct cvmx_npei_pkt_input_control_s cn56xxp1;
+} cvmx_npei_pkt_input_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_instr_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t enb:32;
+#else
+ uint64_t enb:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_instr_enb_s cn52xx;
+ struct cvmx_npei_pkt_instr_enb_s cn56xx;
+ struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
+} cvmx_npei_pkt_instr_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_instr_rd_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t rdsize:64;
+#else
+ uint64_t rdsize:64;
+#endif
+ } s;
+ struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
+ struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
+} cvmx_npei_pkt_instr_rd_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_instr_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t is_64b:32;
+#else
+ uint64_t is_64b:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_instr_size_s cn52xx;
+ struct cvmx_npei_pkt_instr_size_s cn56xx;
+ struct cvmx_npei_pkt_instr_size_s cn56xxp1;
+} cvmx_npei_pkt_instr_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_int_levels_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_54_63:10;
+ uint64_t time:22;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t time:22;
+ uint64_t reserved_54_63:10;
+#endif
+ } s;
+ struct cvmx_npei_pkt_int_levels_s cn52xx;
+ struct cvmx_npei_pkt_int_levels_s cn56xx;
+ struct cvmx_npei_pkt_int_levels_s cn56xxp1;
+} cvmx_npei_pkt_int_levels_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_iptr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iptr:32;
+#else
+ uint64_t iptr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_iptr_s cn52xx;
+ struct cvmx_npei_pkt_iptr_s cn56xx;
+ struct cvmx_npei_pkt_iptr_s cn56xxp1;
+} cvmx_npei_pkt_iptr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_out_bmode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t bmode:32;
+#else
+ uint64_t bmode:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_out_bmode_s cn52xx;
+ struct cvmx_npei_pkt_out_bmode_s cn56xx;
+ struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
+} cvmx_npei_pkt_out_bmode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_out_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t enb:32;
+#else
+ uint64_t enb:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_out_enb_s cn52xx;
+ struct cvmx_npei_pkt_out_enb_s cn56xx;
+ struct cvmx_npei_pkt_out_enb_s cn56xxp1;
+} cvmx_npei_pkt_out_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_output_wmark_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wmark:32;
+#else
+ uint64_t wmark:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_output_wmark_s cn52xx;
+ struct cvmx_npei_pkt_output_wmark_s cn56xx;
+} cvmx_npei_pkt_output_wmark_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_pcie_port_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pp:64;
+#else
+ uint64_t pp:64;
+#endif
+ } s;
+ struct cvmx_npei_pkt_pcie_port_s cn52xx;
+ struct cvmx_npei_pkt_pcie_port_s cn56xx;
+ struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
+} cvmx_npei_pkt_pcie_port_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_port_in_rst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t in_rst:32;
+ uint64_t out_rst:32;
+#else
+ uint64_t out_rst:32;
+ uint64_t in_rst:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_port_in_rst_s cn52xx;
+ struct cvmx_npei_pkt_port_in_rst_s cn56xx;
+} cvmx_npei_pkt_port_in_rst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_slist_es_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t es:64;
+#else
+ uint64_t es:64;
+#endif
+ } s;
+ struct cvmx_npei_pkt_slist_es_s cn52xx;
+ struct cvmx_npei_pkt_slist_es_s cn56xx;
+ struct cvmx_npei_pkt_slist_es_s cn56xxp1;
+} cvmx_npei_pkt_slist_es_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_slist_id_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t isize:7;
+ uint64_t bsize:16;
+#else
+ uint64_t bsize:16;
+ uint64_t isize:7;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_npei_pkt_slist_id_size_s cn52xx;
+ struct cvmx_npei_pkt_slist_id_size_s cn56xx;
+ struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
+} cvmx_npei_pkt_slist_id_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_slist_ns_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t nsr:32;
+#else
+ uint64_t nsr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_slist_ns_s cn52xx;
+ struct cvmx_npei_pkt_slist_ns_s cn56xx;
+ struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
+} cvmx_npei_pkt_slist_ns_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_slist_ror_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ror:32;
+#else
+ uint64_t ror:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_slist_ror_s cn52xx;
+ struct cvmx_npei_pkt_slist_ror_s cn56xx;
+ struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
+} cvmx_npei_pkt_slist_ror_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_time_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+#else
+ uint64_t port:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_time_int_s cn52xx;
+ struct cvmx_npei_pkt_time_int_s cn56xx;
+ struct cvmx_npei_pkt_time_int_s cn56xxp1;
+} cvmx_npei_pkt_time_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_pkt_time_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+#else
+ uint64_t port:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_pkt_time_int_enb_s cn52xx;
+ struct cvmx_npei_pkt_time_int_enb_s cn56xx;
+ struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
+} cvmx_npei_pkt_time_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_rsl_int_blocks_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t iob:1;
+ uint64_t lmc1:1;
+ uint64_t agl:1;
+ uint64_t reserved_24_27:4;
+ uint64_t asxpcs1:1;
+ uint64_t asxpcs0:1;
+ uint64_t reserved_21_21:1;
+ uint64_t pip:1;
+ uint64_t reserved_18_19:2;
+ uint64_t lmc0:1;
+ uint64_t l2c:1;
+ uint64_t usb1:1;
+ uint64_t rad:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t reserved_8_8:1;
+ uint64_t zip:1;
+ uint64_t reserved_6_6:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npei:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npei:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t reserved_6_6:1;
+ uint64_t zip:1;
+ uint64_t reserved_8_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t usb:1;
+ uint64_t rad:1;
+ uint64_t usb1:1;
+ uint64_t l2c:1;
+ uint64_t lmc0:1;
+ uint64_t reserved_18_19:2;
+ uint64_t pip:1;
+ uint64_t reserved_21_21:1;
+ uint64_t asxpcs0:1;
+ uint64_t asxpcs1:1;
+ uint64_t reserved_24_27:4;
+ uint64_t agl:1;
+ uint64_t lmc1:1;
+ uint64_t iob:1;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_npei_rsl_int_blocks_s cn52xx;
+ struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
+ struct cvmx_npei_rsl_int_blocks_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t iob:1;
+ uint64_t lmc1:1;
+ uint64_t agl:1;
+ uint64_t reserved_24_27:4;
+ uint64_t asxpcs1:1;
+ uint64_t asxpcs0:1;
+ uint64_t reserved_21_21:1;
+ uint64_t pip:1;
+ uint64_t reserved_18_19:2;
+ uint64_t lmc0:1;
+ uint64_t l2c:1;
+ uint64_t reserved_15_15:1;
+ uint64_t rad:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t reserved_8_8:1;
+ uint64_t zip:1;
+ uint64_t reserved_6_6:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npei:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npei:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t reserved_6_6:1;
+ uint64_t zip:1;
+ uint64_t reserved_8_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t usb:1;
+ uint64_t rad:1;
+ uint64_t reserved_15_15:1;
+ uint64_t l2c:1;
+ uint64_t lmc0:1;
+ uint64_t reserved_18_19:2;
+ uint64_t pip:1;
+ uint64_t reserved_21_21:1;
+ uint64_t asxpcs0:1;
+ uint64_t asxpcs1:1;
+ uint64_t reserved_24_27:4;
+ uint64_t agl:1;
+ uint64_t lmc1:1;
+ uint64_t iob:1;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn56xx;
+ struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+} cvmx_npei_rsl_int_blocks_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_scratch_1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_npei_scratch_1_s cn52xx;
+ struct cvmx_npei_scratch_1_s cn52xxp1;
+ struct cvmx_npei_scratch_1_s cn56xx;
+ struct cvmx_npei_scratch_1_s cn56xxp1;
+} cvmx_npei_scratch_1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_state1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cpl1:12;
+ uint64_t cpl0:12;
+ uint64_t arb:1;
+ uint64_t csr:39;
+#else
+ uint64_t csr:39;
+ uint64_t arb:1;
+ uint64_t cpl0:12;
+ uint64_t cpl1:12;
+#endif
+ } s;
+ struct cvmx_npei_state1_s cn52xx;
+ struct cvmx_npei_state1_s cn52xxp1;
+ struct cvmx_npei_state1_s cn56xx;
+ struct cvmx_npei_state1_s cn56xxp1;
+} cvmx_npei_state1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_state2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t npei:1;
+ uint64_t rac:1;
+ uint64_t csm1:15;
+ uint64_t csm0:15;
+ uint64_t nnp0:8;
+ uint64_t nnd:8;
+#else
+ uint64_t nnd:8;
+ uint64_t nnp0:8;
+ uint64_t csm0:15;
+ uint64_t csm1:15;
+ uint64_t rac:1;
+ uint64_t npei:1;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_npei_state2_s cn52xx;
+ struct cvmx_npei_state2_s cn52xxp1;
+ struct cvmx_npei_state2_s cn56xx;
+ struct cvmx_npei_state2_s cn56xxp1;
+} cvmx_npei_state2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_state3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t psm1:15;
+ uint64_t psm0:15;
+ uint64_t nsm1:13;
+ uint64_t nsm0:13;
+#else
+ uint64_t nsm0:13;
+ uint64_t nsm1:13;
+ uint64_t psm0:15;
+ uint64_t psm1:15;
+ uint64_t reserved_56_63:8;
+#endif
+ } s;
+ struct cvmx_npei_state3_s cn52xx;
+ struct cvmx_npei_state3_s cn52xxp1;
+ struct cvmx_npei_state3_s cn56xx;
+ struct cvmx_npei_state3_s cn56xxp1;
+} cvmx_npei_state3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_win_rd_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_51_63:13;
+ uint64_t ld_cmd:2;
+ uint64_t iobit:1;
+ uint64_t rd_addr:48;
+#else
+ uint64_t rd_addr:48;
+ uint64_t iobit:1;
+ uint64_t ld_cmd:2;
+ uint64_t reserved_51_63:13;
+#endif
+ } s;
+ struct cvmx_npei_win_rd_addr_s cn52xx;
+ struct cvmx_npei_win_rd_addr_s cn52xxp1;
+ struct cvmx_npei_win_rd_addr_s cn56xx;
+ struct cvmx_npei_win_rd_addr_s cn56xxp1;
+} cvmx_npei_win_rd_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_win_rd_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t rd_data:64;
+#else
+ uint64_t rd_data:64;
+#endif
+ } s;
+ struct cvmx_npei_win_rd_data_s cn52xx;
+ struct cvmx_npei_win_rd_data_s cn52xxp1;
+ struct cvmx_npei_win_rd_data_s cn56xx;
+ struct cvmx_npei_win_rd_data_s cn56xxp1;
+} cvmx_npei_win_rd_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_win_wr_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t wr_addr:46;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t wr_addr:46;
+ uint64_t iobit:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_npei_win_wr_addr_s cn52xx;
+ struct cvmx_npei_win_wr_addr_s cn52xxp1;
+ struct cvmx_npei_win_wr_addr_s cn56xx;
+ struct cvmx_npei_win_wr_addr_s cn56xxp1;
+} cvmx_npei_win_wr_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_win_wr_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t wr_data:64;
+#else
+ uint64_t wr_data:64;
+#endif
+ } s;
+ struct cvmx_npei_win_wr_data_s cn52xx;
+ struct cvmx_npei_win_wr_data_s cn52xxp1;
+ struct cvmx_npei_win_wr_data_s cn56xx;
+ struct cvmx_npei_win_wr_data_s cn56xxp1;
+} cvmx_npei_win_wr_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_win_wr_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t wr_mask:8;
+#else
+ uint64_t wr_mask:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_npei_win_wr_mask_s cn52xx;
+ struct cvmx_npei_win_wr_mask_s cn52xxp1;
+ struct cvmx_npei_win_wr_mask_s cn56xx;
+ struct cvmx_npei_win_wr_mask_s cn56xxp1;
+} cvmx_npei_win_wr_mask_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npei_window_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t time:32;
+#else
+ uint64_t time:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npei_window_ctl_s cn52xx;
+ struct cvmx_npei_window_ctl_s cn52xxp1;
+ struct cvmx_npei_window_ctl_s cn56xx;
+ struct cvmx_npei_window_ctl_s cn56xxp1;
+} cvmx_npei_window_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_base_addr_inputx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t baddr:61;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t baddr:61;
+#endif
+ } s;
+ struct cvmx_npi_base_addr_inputx_s cn30xx;
+ struct cvmx_npi_base_addr_inputx_s cn31xx;
+ struct cvmx_npi_base_addr_inputx_s cn38xx;
+ struct cvmx_npi_base_addr_inputx_s cn38xxp2;
+ struct cvmx_npi_base_addr_inputx_s cn50xx;
+ struct cvmx_npi_base_addr_inputx_s cn58xx;
+ struct cvmx_npi_base_addr_inputx_s cn58xxp1;
+} cvmx_npi_base_addr_inputx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_base_addr_outputx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t baddr:61;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t baddr:61;
+#endif
+ } s;
+ struct cvmx_npi_base_addr_outputx_s cn30xx;
+ struct cvmx_npi_base_addr_outputx_s cn31xx;
+ struct cvmx_npi_base_addr_outputx_s cn38xx;
+ struct cvmx_npi_base_addr_outputx_s cn38xxp2;
+ struct cvmx_npi_base_addr_outputx_s cn50xx;
+ struct cvmx_npi_base_addr_outputx_s cn58xx;
+ struct cvmx_npi_base_addr_outputx_s cn58xxp1;
+} cvmx_npi_base_addr_outputx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t csr_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pof0_bs:1;
+ uint64_t pof1_bs:1;
+ uint64_t pof2_bs:1;
+ uint64_t pof3_bs:1;
+ uint64_t pos_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dpi_bs:1;
+#else
+ uint64_t dpi_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t pos_bs:1;
+ uint64_t pof3_bs:1;
+ uint64_t pof2_bs:1;
+ uint64_t pof1_bs:1;
+ uint64_t pof0_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t csr_bs:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_npi_bist_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t csr_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pof0_bs:1;
+ uint64_t reserved_5_7:3;
+ uint64_t pos_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dpi_bs:1;
+#else
+ uint64_t dpi_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t pos_bs:1;
+ uint64_t reserved_5_7:3;
+ uint64_t pof0_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t csr_bs:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn30xx;
+ struct cvmx_npi_bist_status_s cn31xx;
+ struct cvmx_npi_bist_status_s cn38xx;
+ struct cvmx_npi_bist_status_s cn38xxp2;
+ struct cvmx_npi_bist_status_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t csr_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pof0_bs:1;
+ uint64_t pof1_bs:1;
+ uint64_t reserved_5_6:2;
+ uint64_t pos_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dpi_bs:1;
+#else
+ uint64_t dpi_bs:1;
+ uint64_t pdf_bs:1;
+ uint64_t dob_bs:1;
+ uint64_t nus_bs:1;
+ uint64_t pos_bs:1;
+ uint64_t reserved_5_6:2;
+ uint64_t pof1_bs:1;
+ uint64_t pof0_bs:1;
+ uint64_t pig_bs:1;
+ uint64_t pgf_bs:1;
+ uint64_t rdnl_bs:1;
+ uint64_t pcad_bs:1;
+ uint64_t pcac_bs:1;
+ uint64_t rdn_bs:1;
+ uint64_t pcn_bs:1;
+ uint64_t pcnc_bs:1;
+ uint64_t rdp_bs:1;
+ uint64_t dif_bs:1;
+ uint64_t csr_bs:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn50xx;
+ struct cvmx_npi_bist_status_s cn58xx;
+ struct cvmx_npi_bist_status_s cn58xxp1;
+} cvmx_npi_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_buff_size_outputx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t isize:7;
+ uint64_t bsize:16;
+#else
+ uint64_t bsize:16;
+ uint64_t isize:7;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_npi_buff_size_outputx_s cn30xx;
+ struct cvmx_npi_buff_size_outputx_s cn31xx;
+ struct cvmx_npi_buff_size_outputx_s cn38xx;
+ struct cvmx_npi_buff_size_outputx_s cn38xxp2;
+ struct cvmx_npi_buff_size_outputx_s cn50xx;
+ struct cvmx_npi_buff_size_outputx_s cn58xx;
+ struct cvmx_npi_buff_size_outputx_s cn58xxp1;
+} cvmx_npi_buff_size_outputx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_comp_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t pctl:5;
+ uint64_t nctl:5;
+#else
+ uint64_t nctl:5;
+ uint64_t pctl:5;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_npi_comp_ctl_s cn50xx;
+ struct cvmx_npi_comp_ctl_s cn58xx;
+ struct cvmx_npi_comp_ctl_s cn58xxp1;
+} cvmx_npi_comp_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_63_63:1;
+ uint64_t chip_rev:8;
+ uint64_t dis_pniw:1;
+ uint64_t out3_enb:1;
+ uint64_t out2_enb:1;
+ uint64_t out1_enb:1;
+ uint64_t out0_enb:1;
+ uint64_t ins3_enb:1;
+ uint64_t ins2_enb:1;
+ uint64_t ins1_enb:1;
+ uint64_t ins0_enb:1;
+ uint64_t ins3_64b:1;
+ uint64_t ins2_64b:1;
+ uint64_t ins1_64b:1;
+ uint64_t ins0_64b:1;
+ uint64_t pci_wdis:1;
+ uint64_t wait_com:1;
+ uint64_t reserved_37_39:3;
+ uint64_t max_word:5;
+ uint64_t reserved_10_31:22;
+ uint64_t timer:10;
+#else
+ uint64_t timer:10;
+ uint64_t reserved_10_31:22;
+ uint64_t max_word:5;
+ uint64_t reserved_37_39:3;
+ uint64_t wait_com:1;
+ uint64_t pci_wdis:1;
+ uint64_t ins0_64b:1;
+ uint64_t ins1_64b:1;
+ uint64_t ins2_64b:1;
+ uint64_t ins3_64b:1;
+ uint64_t ins0_enb:1;
+ uint64_t ins1_enb:1;
+ uint64_t ins2_enb:1;
+ uint64_t ins3_enb:1;
+ uint64_t out0_enb:1;
+ uint64_t out1_enb:1;
+ uint64_t out2_enb:1;
+ uint64_t out3_enb:1;
+ uint64_t dis_pniw:1;
+ uint64_t chip_rev:8;
+ uint64_t reserved_63_63:1;
+#endif
+ } s;
+ struct cvmx_npi_ctl_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_63_63:1;
+ uint64_t chip_rev:8;
+ uint64_t dis_pniw:1;
+ uint64_t reserved_51_53:3;
+ uint64_t out0_enb:1;
+ uint64_t reserved_47_49:3;
+ uint64_t ins0_enb:1;
+ uint64_t reserved_43_45:3;
+ uint64_t ins0_64b:1;
+ uint64_t pci_wdis:1;
+ uint64_t wait_com:1;
+ uint64_t reserved_37_39:3;
+ uint64_t max_word:5;
+ uint64_t reserved_10_31:22;
+ uint64_t timer:10;
+#else
+ uint64_t timer:10;
+ uint64_t reserved_10_31:22;
+ uint64_t max_word:5;
+ uint64_t reserved_37_39:3;
+ uint64_t wait_com:1;
+ uint64_t pci_wdis:1;
+ uint64_t ins0_64b:1;
+ uint64_t reserved_43_45:3;
+ uint64_t ins0_enb:1;
+ uint64_t reserved_47_49:3;
+ uint64_t out0_enb:1;
+ uint64_t reserved_51_53:3;
+ uint64_t dis_pniw:1;
+ uint64_t chip_rev:8;
+ uint64_t reserved_63_63:1;
+#endif
+ } cn30xx;
+ struct cvmx_npi_ctl_status_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_63_63:1;
+ uint64_t chip_rev:8;
+ uint64_t dis_pniw:1;
+ uint64_t reserved_52_53:2;
+ uint64_t out1_enb:1;
+ uint64_t out0_enb:1;
+ uint64_t reserved_48_49:2;
+ uint64_t ins1_enb:1;
+ uint64_t ins0_enb:1;
+ uint64_t reserved_44_45:2;
+ uint64_t ins1_64b:1;
+ uint64_t ins0_64b:1;
+ uint64_t pci_wdis:1;
+ uint64_t wait_com:1;
+ uint64_t reserved_37_39:3;
+ uint64_t max_word:5;
+ uint64_t reserved_10_31:22;
+ uint64_t timer:10;
+#else
+ uint64_t timer:10;
+ uint64_t reserved_10_31:22;
+ uint64_t max_word:5;
+ uint64_t reserved_37_39:3;
+ uint64_t wait_com:1;
+ uint64_t pci_wdis:1;
+ uint64_t ins0_64b:1;
+ uint64_t ins1_64b:1;
+ uint64_t reserved_44_45:2;
+ uint64_t ins0_enb:1;
+ uint64_t ins1_enb:1;
+ uint64_t reserved_48_49:2;
+ uint64_t out0_enb:1;
+ uint64_t out1_enb:1;
+ uint64_t reserved_52_53:2;
+ uint64_t dis_pniw:1;
+ uint64_t chip_rev:8;
+ uint64_t reserved_63_63:1;
+#endif
+ } cn31xx;
+ struct cvmx_npi_ctl_status_s cn38xx;
+ struct cvmx_npi_ctl_status_s cn38xxp2;
+ struct cvmx_npi_ctl_status_cn31xx cn50xx;
+ struct cvmx_npi_ctl_status_s cn58xx;
+ struct cvmx_npi_ctl_status_s cn58xxp1;
+} cvmx_npi_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dbg_select_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dbg_sel:16;
+#else
+ uint64_t dbg_sel:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npi_dbg_select_s cn30xx;
+ struct cvmx_npi_dbg_select_s cn31xx;
+ struct cvmx_npi_dbg_select_s cn38xx;
+ struct cvmx_npi_dbg_select_s cn38xxp2;
+ struct cvmx_npi_dbg_select_s cn50xx;
+ struct cvmx_npi_dbg_select_s cn58xx;
+ struct cvmx_npi_dbg_select_s cn58xxp1;
+} cvmx_npi_dbg_select_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dma_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t hp_enb:1;
+ uint64_t lp_enb:1;
+ uint64_t csize:14;
+#else
+ uint64_t csize:14;
+ uint64_t lp_enb:1;
+ uint64_t hp_enb:1;
+ uint64_t o_mode:1;
+ uint64_t o_es:2;
+ uint64_t o_ns:1;
+ uint64_t o_ro:1;
+ uint64_t o_add1:1;
+ uint64_t fpa_que:3;
+ uint64_t dwb_ichk:9;
+ uint64_t dwb_denb:1;
+ uint64_t b0_lend:1;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_npi_dma_control_s cn30xx;
+ struct cvmx_npi_dma_control_s cn31xx;
+ struct cvmx_npi_dma_control_s cn38xx;
+ struct cvmx_npi_dma_control_s cn38xxp2;
+ struct cvmx_npi_dma_control_s cn50xx;
+ struct cvmx_npi_dma_control_s cn58xx;
+ struct cvmx_npi_dma_control_s cn58xxp1;
+} cvmx_npi_dma_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dma_highp_counts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t fcnt:7;
+ uint64_t dbell:32;
+#else
+ uint64_t dbell:32;
+ uint64_t fcnt:7;
+ uint64_t reserved_39_63:25;
+#endif
+ } s;
+ struct cvmx_npi_dma_highp_counts_s cn30xx;
+ struct cvmx_npi_dma_highp_counts_s cn31xx;
+ struct cvmx_npi_dma_highp_counts_s cn38xx;
+ struct cvmx_npi_dma_highp_counts_s cn38xxp2;
+ struct cvmx_npi_dma_highp_counts_s cn50xx;
+ struct cvmx_npi_dma_highp_counts_s cn58xx;
+ struct cvmx_npi_dma_highp_counts_s cn58xxp1;
+} cvmx_npi_dma_highp_counts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dma_highp_naddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t state:4;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t state:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_npi_dma_highp_naddr_s cn30xx;
+ struct cvmx_npi_dma_highp_naddr_s cn31xx;
+ struct cvmx_npi_dma_highp_naddr_s cn38xx;
+ struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
+ struct cvmx_npi_dma_highp_naddr_s cn50xx;
+ struct cvmx_npi_dma_highp_naddr_s cn58xx;
+ struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
+} cvmx_npi_dma_highp_naddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dma_lowp_counts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_39_63:25;
+ uint64_t fcnt:7;
+ uint64_t dbell:32;
+#else
+ uint64_t dbell:32;
+ uint64_t fcnt:7;
+ uint64_t reserved_39_63:25;
+#endif
+ } s;
+ struct cvmx_npi_dma_lowp_counts_s cn30xx;
+ struct cvmx_npi_dma_lowp_counts_s cn31xx;
+ struct cvmx_npi_dma_lowp_counts_s cn38xx;
+ struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
+ struct cvmx_npi_dma_lowp_counts_s cn50xx;
+ struct cvmx_npi_dma_lowp_counts_s cn58xx;
+ struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
+} cvmx_npi_dma_lowp_counts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_dma_lowp_naddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t state:4;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t state:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_npi_dma_lowp_naddr_s cn30xx;
+ struct cvmx_npi_dma_lowp_naddr_s cn31xx;
+ struct cvmx_npi_dma_lowp_naddr_s cn38xx;
+ struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
+ struct cvmx_npi_dma_lowp_naddr_s cn50xx;
+ struct cvmx_npi_dma_lowp_naddr_s cn58xx;
+ struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
+} cvmx_npi_dma_lowp_naddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_highp_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dbell:16;
+#else
+ uint64_t dbell:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npi_highp_dbell_s cn30xx;
+ struct cvmx_npi_highp_dbell_s cn31xx;
+ struct cvmx_npi_highp_dbell_s cn38xx;
+ struct cvmx_npi_highp_dbell_s cn38xxp2;
+ struct cvmx_npi_highp_dbell_s cn50xx;
+ struct cvmx_npi_highp_dbell_s cn58xx;
+ struct cvmx_npi_highp_dbell_s cn58xxp1;
+} cvmx_npi_highp_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_highp_ibuff_saddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t saddr:36;
+#else
+ uint64_t saddr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
+ struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
+ struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
+ struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
+ struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
+ struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
+ struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
+} cvmx_npi_highp_ibuff_saddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_input_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t pkt_rr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t d_nsr:1;
+ uint64_t d_esr:2;
+ uint64_t d_ror:1;
+ uint64_t use_csr:1;
+ uint64_t nsr:1;
+ uint64_t esr:2;
+ uint64_t ror:1;
+#else
+ uint64_t ror:1;
+ uint64_t esr:2;
+ uint64_t nsr:1;
+ uint64_t use_csr:1;
+ uint64_t d_ror:1;
+ uint64_t d_esr:2;
+ uint64_t d_nsr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t pkt_rr:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_npi_input_control_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_22_63:42;
+ uint64_t pbp_dhi:13;
+ uint64_t d_nsr:1;
+ uint64_t d_esr:2;
+ uint64_t d_ror:1;
+ uint64_t use_csr:1;
+ uint64_t nsr:1;
+ uint64_t esr:2;
+ uint64_t ror:1;
+#else
+ uint64_t ror:1;
+ uint64_t esr:2;
+ uint64_t nsr:1;
+ uint64_t use_csr:1;
+ uint64_t d_ror:1;
+ uint64_t d_esr:2;
+ uint64_t d_nsr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t reserved_22_63:42;
+#endif
+ } cn30xx;
+ struct cvmx_npi_input_control_cn30xx cn31xx;
+ struct cvmx_npi_input_control_s cn38xx;
+ struct cvmx_npi_input_control_cn30xx cn38xxp2;
+ struct cvmx_npi_input_control_s cn50xx;
+ struct cvmx_npi_input_control_s cn58xx;
+ struct cvmx_npi_input_control_s cn58xxp1;
+} cvmx_npi_input_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t i3_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t p3_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t p3_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t g3_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t p3_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t p3_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t i3_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t i3_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t po3_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po3_2sml:1;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i3_rtout:1;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i3_overf:1;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p3_rtout:1;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p3_perr:1;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g3_rtout:1;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p3_pperr:1;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p3_ptout:1;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i3_pperr:1;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } s;
+ struct cvmx_npi_int_enb_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t reserved_36_38:3;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_32_34:3;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_28_30:3;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_24_26:3;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_20_22:3;
+ uint64_t p0_perr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_12_14:3;
+ uint64_t i0_overf:1;
+ uint64_t reserved_8_10:3;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_4_6:3;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t reserved_4_6:3;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_8_10:3;
+ uint64_t i0_overf:1;
+ uint64_t reserved_12_14:3;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_16_18:3;
+ uint64_t p0_perr:1;
+ uint64_t reserved_20_22:3;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_24_26:3;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_28_30:3;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_32_34:3;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_36_38:3;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } cn30xx;
+ struct cvmx_npi_int_enb_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t reserved_37_38:2;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_33_34:2;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_29_30:2;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_25_26:2;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_21_22:2;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t reserved_17_18:2;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_13_14:2;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t reserved_9_10:2;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_5_6:2;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t reserved_5_6:2;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t reserved_9_10:2;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t reserved_13_14:2;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t reserved_17_18:2;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t reserved_21_22:2;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t reserved_25_26:2;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t reserved_29_30:2;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t reserved_33_34:2;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t reserved_37_38:2;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } cn31xx;
+ struct cvmx_npi_int_enb_s cn38xx;
+ struct cvmx_npi_int_enb_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_42_63:22;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t i3_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t p3_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t p3_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t g3_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t p3_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t p3_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t i3_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t i3_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t po3_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po3_2sml:1;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i3_rtout:1;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i3_overf:1;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p3_rtout:1;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p3_perr:1;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g3_rtout:1;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p3_pperr:1;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p3_ptout:1;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i3_pperr:1;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t reserved_42_63:22;
+#endif
+ } cn38xxp2;
+ struct cvmx_npi_int_enb_cn31xx cn50xx;
+ struct cvmx_npi_int_enb_s cn58xx;
+ struct cvmx_npi_int_enb_s cn58xxp1;
+} cvmx_npi_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t i3_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t p3_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t p3_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t g3_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t p3_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t p3_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t i3_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t i3_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t po3_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po3_2sml:1;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i3_rtout:1;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i3_overf:1;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p3_rtout:1;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p3_perr:1;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g3_rtout:1;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p3_pperr:1;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p3_ptout:1;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i3_pperr:1;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } s;
+ struct cvmx_npi_int_sum_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t reserved_36_38:3;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_32_34:3;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_28_30:3;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_24_26:3;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_20_22:3;
+ uint64_t p0_perr:1;
+ uint64_t reserved_16_18:3;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_12_14:3;
+ uint64_t i0_overf:1;
+ uint64_t reserved_8_10:3;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_4_6:3;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t reserved_4_6:3;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_8_10:3;
+ uint64_t i0_overf:1;
+ uint64_t reserved_12_14:3;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_16_18:3;
+ uint64_t p0_perr:1;
+ uint64_t reserved_20_22:3;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_24_26:3;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_28_30:3;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_32_34:3;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_36_38:3;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } cn30xx;
+ struct cvmx_npi_int_sum_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t q1_a_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pcf_p_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t rwx_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t fcr_s_e:1;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t reserved_37_38:2;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t reserved_33_34:2;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t reserved_29_30:2;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t reserved_25_26:2;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t reserved_21_22:2;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t reserved_17_18:2;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t reserved_13_14:2;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t reserved_9_10:2;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t reserved_5_6:2;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t reserved_5_6:2;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t reserved_9_10:2;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t reserved_13_14:2;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t reserved_17_18:2;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t reserved_21_22:2;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t reserved_25_26:2;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t reserved_29_30:2;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t reserved_33_34:2;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t reserved_37_38:2;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t fcr_s_e:1;
+ uint64_t fcr_a_f:1;
+ uint64_t pcr_s_e:1;
+ uint64_t pcr_a_f:1;
+ uint64_t q2_s_e:1;
+ uint64_t q2_a_f:1;
+ uint64_t q3_s_e:1;
+ uint64_t q3_a_f:1;
+ uint64_t com_s_e:1;
+ uint64_t com_a_f:1;
+ uint64_t pnc_s_e:1;
+ uint64_t pnc_a_f:1;
+ uint64_t rwx_s_e:1;
+ uint64_t rdx_s_e:1;
+ uint64_t pcf_p_e:1;
+ uint64_t pcf_p_f:1;
+ uint64_t pdf_p_e:1;
+ uint64_t pdf_p_f:1;
+ uint64_t q1_s_e:1;
+ uint64_t q1_a_f:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } cn31xx;
+ struct cvmx_npi_int_sum_s cn38xx;
+ struct cvmx_npi_int_sum_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_42_63:22;
+ uint64_t iobdma:1;
+ uint64_t p_dperr:1;
+ uint64_t win_rto:1;
+ uint64_t i3_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i0_pperr:1;
+ uint64_t p3_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p0_ptout:1;
+ uint64_t p3_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p0_pperr:1;
+ uint64_t g3_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g0_rtout:1;
+ uint64_t p3_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p0_perr:1;
+ uint64_t p3_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p0_rtout:1;
+ uint64_t i3_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i0_overf:1;
+ uint64_t i3_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i0_rtout:1;
+ uint64_t po3_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po0_2sml:1;
+ uint64_t pci_rsl:1;
+ uint64_t rml_wto:1;
+ uint64_t rml_rto:1;
+#else
+ uint64_t rml_rto:1;
+ uint64_t rml_wto:1;
+ uint64_t pci_rsl:1;
+ uint64_t po0_2sml:1;
+ uint64_t po1_2sml:1;
+ uint64_t po2_2sml:1;
+ uint64_t po3_2sml:1;
+ uint64_t i0_rtout:1;
+ uint64_t i1_rtout:1;
+ uint64_t i2_rtout:1;
+ uint64_t i3_rtout:1;
+ uint64_t i0_overf:1;
+ uint64_t i1_overf:1;
+ uint64_t i2_overf:1;
+ uint64_t i3_overf:1;
+ uint64_t p0_rtout:1;
+ uint64_t p1_rtout:1;
+ uint64_t p2_rtout:1;
+ uint64_t p3_rtout:1;
+ uint64_t p0_perr:1;
+ uint64_t p1_perr:1;
+ uint64_t p2_perr:1;
+ uint64_t p3_perr:1;
+ uint64_t g0_rtout:1;
+ uint64_t g1_rtout:1;
+ uint64_t g2_rtout:1;
+ uint64_t g3_rtout:1;
+ uint64_t p0_pperr:1;
+ uint64_t p1_pperr:1;
+ uint64_t p2_pperr:1;
+ uint64_t p3_pperr:1;
+ uint64_t p0_ptout:1;
+ uint64_t p1_ptout:1;
+ uint64_t p2_ptout:1;
+ uint64_t p3_ptout:1;
+ uint64_t i0_pperr:1;
+ uint64_t i1_pperr:1;
+ uint64_t i2_pperr:1;
+ uint64_t i3_pperr:1;
+ uint64_t win_rto:1;
+ uint64_t p_dperr:1;
+ uint64_t iobdma:1;
+ uint64_t reserved_42_63:22;
+#endif
+ } cn38xxp2;
+ struct cvmx_npi_int_sum_cn31xx cn50xx;
+ struct cvmx_npi_int_sum_s cn58xx;
+ struct cvmx_npi_int_sum_s cn58xxp1;
+} cvmx_npi_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_lowp_dbell_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dbell:16;
+#else
+ uint64_t dbell:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_npi_lowp_dbell_s cn30xx;
+ struct cvmx_npi_lowp_dbell_s cn31xx;
+ struct cvmx_npi_lowp_dbell_s cn38xx;
+ struct cvmx_npi_lowp_dbell_s cn38xxp2;
+ struct cvmx_npi_lowp_dbell_s cn50xx;
+ struct cvmx_npi_lowp_dbell_s cn58xx;
+ struct cvmx_npi_lowp_dbell_s cn58xxp1;
+} cvmx_npi_lowp_dbell_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_lowp_ibuff_saddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t saddr:36;
+#else
+ uint64_t saddr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
+ struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
+} cvmx_npi_lowp_ibuff_saddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_mem_access_subidx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t shortl:1;
+ uint64_t nmerge:1;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t nsr:1;
+ uint64_t nsw:1;
+ uint64_t ror:1;
+ uint64_t row:1;
+ uint64_t ba:28;
+#else
+ uint64_t ba:28;
+ uint64_t row:1;
+ uint64_t ror:1;
+ uint64_t nsw:1;
+ uint64_t nsr:1;
+ uint64_t esw:2;
+ uint64_t esr:2;
+ uint64_t nmerge:1;
+ uint64_t shortl:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_npi_mem_access_subidx_s cn30xx;
+ struct cvmx_npi_mem_access_subidx_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t nsr:1;
+ uint64_t nsw:1;
+ uint64_t ror:1;
+ uint64_t row:1;
+ uint64_t ba:28;
+#else
+ uint64_t ba:28;
+ uint64_t row:1;
+ uint64_t ror:1;
+ uint64_t nsw:1;
+ uint64_t nsr:1;
+ uint64_t esw:2;
+ uint64_t esr:2;
+ uint64_t reserved_36_63:28;
+#endif
+ } cn31xx;
+ struct cvmx_npi_mem_access_subidx_s cn38xx;
+ struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
+ struct cvmx_npi_mem_access_subidx_s cn50xx;
+ struct cvmx_npi_mem_access_subidx_s cn58xx;
+ struct cvmx_npi_mem_access_subidx_s cn58xxp1;
+} cvmx_npi_mem_access_subidx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_msi_rcv_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t int_vec:64;
+#else
+ uint64_t int_vec:64;
+#endif
+ } s;
+ struct cvmx_npi_msi_rcv_s cn30xx;
+ struct cvmx_npi_msi_rcv_s cn31xx;
+ struct cvmx_npi_msi_rcv_s cn38xx;
+ struct cvmx_npi_msi_rcv_s cn38xxp2;
+ struct cvmx_npi_msi_rcv_s cn50xx;
+ struct cvmx_npi_msi_rcv_s cn58xx;
+ struct cvmx_npi_msi_rcv_s cn58xxp1;
+} cvmx_npi_msi_rcv_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_num_desc_outputx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t size:32;
+#else
+ uint64_t size:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npi_num_desc_outputx_s cn30xx;
+ struct cvmx_npi_num_desc_outputx_s cn31xx;
+ struct cvmx_npi_num_desc_outputx_s cn38xx;
+ struct cvmx_npi_num_desc_outputx_s cn38xxp2;
+ struct cvmx_npi_num_desc_outputx_s cn50xx;
+ struct cvmx_npi_num_desc_outputx_s cn58xx;
+ struct cvmx_npi_num_desc_outputx_s cn58xxp1;
+} cvmx_npi_num_desc_outputx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_output_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t pkt_rr:1;
+ uint64_t p3_bmode:1;
+ uint64_t p2_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t p0_bmode:1;
+ uint64_t o3_es:2;
+ uint64_t o3_ns:1;
+ uint64_t o3_ro:1;
+ uint64_t o2_es:2;
+ uint64_t o2_ns:1;
+ uint64_t o2_ro:1;
+ uint64_t o1_es:2;
+ uint64_t o1_ns:1;
+ uint64_t o1_ro:1;
+ uint64_t o0_es:2;
+ uint64_t o0_ns:1;
+ uint64_t o0_ro:1;
+ uint64_t o3_csrm:1;
+ uint64_t o2_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_20_23:4;
+ uint64_t iptr_o3:1;
+ uint64_t iptr_o2:1;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o0:1;
+ uint64_t esr_sl3:2;
+ uint64_t nsr_sl3:1;
+ uint64_t ror_sl3:1;
+ uint64_t esr_sl2:2;
+ uint64_t nsr_sl2:1;
+ uint64_t ror_sl2:1;
+ uint64_t esr_sl1:2;
+ uint64_t nsr_sl1:1;
+ uint64_t ror_sl1:1;
+ uint64_t esr_sl0:2;
+ uint64_t nsr_sl0:1;
+ uint64_t ror_sl0:1;
+#else
+ uint64_t ror_sl0:1;
+ uint64_t nsr_sl0:1;
+ uint64_t esr_sl0:2;
+ uint64_t ror_sl1:1;
+ uint64_t nsr_sl1:1;
+ uint64_t esr_sl1:2;
+ uint64_t ror_sl2:1;
+ uint64_t nsr_sl2:1;
+ uint64_t esr_sl2:2;
+ uint64_t ror_sl3:1;
+ uint64_t nsr_sl3:1;
+ uint64_t esr_sl3:2;
+ uint64_t iptr_o0:1;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o2:1;
+ uint64_t iptr_o3:1;
+ uint64_t reserved_20_23:4;
+ uint64_t o0_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t o2_csrm:1;
+ uint64_t o3_csrm:1;
+ uint64_t o0_ro:1;
+ uint64_t o0_ns:1;
+ uint64_t o0_es:2;
+ uint64_t o1_ro:1;
+ uint64_t o1_ns:1;
+ uint64_t o1_es:2;
+ uint64_t o2_ro:1;
+ uint64_t o2_ns:1;
+ uint64_t o2_es:2;
+ uint64_t o3_ro:1;
+ uint64_t o3_ns:1;
+ uint64_t o3_es:2;
+ uint64_t p0_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t p2_bmode:1;
+ uint64_t p3_bmode:1;
+ uint64_t pkt_rr:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_npi_output_control_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_45_63:19;
+ uint64_t p0_bmode:1;
+ uint64_t reserved_32_43:12;
+ uint64_t o0_es:2;
+ uint64_t o0_ns:1;
+ uint64_t o0_ro:1;
+ uint64_t reserved_25_27:3;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_17_23:7;
+ uint64_t iptr_o0:1;
+ uint64_t reserved_4_15:12;
+ uint64_t esr_sl0:2;
+ uint64_t nsr_sl0:1;
+ uint64_t ror_sl0:1;
+#else
+ uint64_t ror_sl0:1;
+ uint64_t nsr_sl0:1;
+ uint64_t esr_sl0:2;
+ uint64_t reserved_4_15:12;
+ uint64_t iptr_o0:1;
+ uint64_t reserved_17_23:7;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_25_27:3;
+ uint64_t o0_ro:1;
+ uint64_t o0_ns:1;
+ uint64_t o0_es:2;
+ uint64_t reserved_32_43:12;
+ uint64_t p0_bmode:1;
+ uint64_t reserved_45_63:19;
+#endif
+ } cn30xx;
+ struct cvmx_npi_output_control_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_46_63:18;
+ uint64_t p1_bmode:1;
+ uint64_t p0_bmode:1;
+ uint64_t reserved_36_43:8;
+ uint64_t o1_es:2;
+ uint64_t o1_ns:1;
+ uint64_t o1_ro:1;
+ uint64_t o0_es:2;
+ uint64_t o0_ns:1;
+ uint64_t o0_ro:1;
+ uint64_t reserved_26_27:2;
+ uint64_t o1_csrm:1;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_18_23:6;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o0:1;
+ uint64_t reserved_8_15:8;
+ uint64_t esr_sl1:2;
+ uint64_t nsr_sl1:1;
+ uint64_t ror_sl1:1;
+ uint64_t esr_sl0:2;
+ uint64_t nsr_sl0:1;
+ uint64_t ror_sl0:1;
+#else
+ uint64_t ror_sl0:1;
+ uint64_t nsr_sl0:1;
+ uint64_t esr_sl0:2;
+ uint64_t ror_sl1:1;
+ uint64_t nsr_sl1:1;
+ uint64_t esr_sl1:2;
+ uint64_t reserved_8_15:8;
+ uint64_t iptr_o0:1;
+ uint64_t iptr_o1:1;
+ uint64_t reserved_18_23:6;
+ uint64_t o0_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t reserved_26_27:2;
+ uint64_t o0_ro:1;
+ uint64_t o0_ns:1;
+ uint64_t o0_es:2;
+ uint64_t o1_ro:1;
+ uint64_t o1_ns:1;
+ uint64_t o1_es:2;
+ uint64_t reserved_36_43:8;
+ uint64_t p0_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t reserved_46_63:18;
+#endif
+ } cn31xx;
+ struct cvmx_npi_output_control_s cn38xx;
+ struct cvmx_npi_output_control_cn38xxp2 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t p3_bmode:1;
+ uint64_t p2_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t p0_bmode:1;
+ uint64_t o3_es:2;
+ uint64_t o3_ns:1;
+ uint64_t o3_ro:1;
+ uint64_t o2_es:2;
+ uint64_t o2_ns:1;
+ uint64_t o2_ro:1;
+ uint64_t o1_es:2;
+ uint64_t o1_ns:1;
+ uint64_t o1_ro:1;
+ uint64_t o0_es:2;
+ uint64_t o0_ns:1;
+ uint64_t o0_ro:1;
+ uint64_t o3_csrm:1;
+ uint64_t o2_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_20_23:4;
+ uint64_t iptr_o3:1;
+ uint64_t iptr_o2:1;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o0:1;
+ uint64_t esr_sl3:2;
+ uint64_t nsr_sl3:1;
+ uint64_t ror_sl3:1;
+ uint64_t esr_sl2:2;
+ uint64_t nsr_sl2:1;
+ uint64_t ror_sl2:1;
+ uint64_t esr_sl1:2;
+ uint64_t nsr_sl1:1;
+ uint64_t ror_sl1:1;
+ uint64_t esr_sl0:2;
+ uint64_t nsr_sl0:1;
+ uint64_t ror_sl0:1;
+#else
+ uint64_t ror_sl0:1;
+ uint64_t nsr_sl0:1;
+ uint64_t esr_sl0:2;
+ uint64_t ror_sl1:1;
+ uint64_t nsr_sl1:1;
+ uint64_t esr_sl1:2;
+ uint64_t ror_sl2:1;
+ uint64_t nsr_sl2:1;
+ uint64_t esr_sl2:2;
+ uint64_t ror_sl3:1;
+ uint64_t nsr_sl3:1;
+ uint64_t esr_sl3:2;
+ uint64_t iptr_o0:1;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o2:1;
+ uint64_t iptr_o3:1;
+ uint64_t reserved_20_23:4;
+ uint64_t o0_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t o2_csrm:1;
+ uint64_t o3_csrm:1;
+ uint64_t o0_ro:1;
+ uint64_t o0_ns:1;
+ uint64_t o0_es:2;
+ uint64_t o1_ro:1;
+ uint64_t o1_ns:1;
+ uint64_t o1_es:2;
+ uint64_t o2_ro:1;
+ uint64_t o2_ns:1;
+ uint64_t o2_es:2;
+ uint64_t o3_ro:1;
+ uint64_t o3_ns:1;
+ uint64_t o3_es:2;
+ uint64_t p0_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t p2_bmode:1;
+ uint64_t p3_bmode:1;
+ uint64_t reserved_48_63:16;
+#endif
+ } cn38xxp2;
+ struct cvmx_npi_output_control_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t pkt_rr:1;
+ uint64_t reserved_46_47:2;
+ uint64_t p1_bmode:1;
+ uint64_t p0_bmode:1;
+ uint64_t reserved_36_43:8;
+ uint64_t o1_es:2;
+ uint64_t o1_ns:1;
+ uint64_t o1_ro:1;
+ uint64_t o0_es:2;
+ uint64_t o0_ns:1;
+ uint64_t o0_ro:1;
+ uint64_t reserved_26_27:2;
+ uint64_t o1_csrm:1;
+ uint64_t o0_csrm:1;
+ uint64_t reserved_18_23:6;
+ uint64_t iptr_o1:1;
+ uint64_t iptr_o0:1;
+ uint64_t reserved_8_15:8;
+ uint64_t esr_sl1:2;
+ uint64_t nsr_sl1:1;
+ uint64_t ror_sl1:1;
+ uint64_t esr_sl0:2;
+ uint64_t nsr_sl0:1;
+ uint64_t ror_sl0:1;
+#else
+ uint64_t ror_sl0:1;
+ uint64_t nsr_sl0:1;
+ uint64_t esr_sl0:2;
+ uint64_t ror_sl1:1;
+ uint64_t nsr_sl1:1;
+ uint64_t esr_sl1:2;
+ uint64_t reserved_8_15:8;
+ uint64_t iptr_o0:1;
+ uint64_t iptr_o1:1;
+ uint64_t reserved_18_23:6;
+ uint64_t o0_csrm:1;
+ uint64_t o1_csrm:1;
+ uint64_t reserved_26_27:2;
+ uint64_t o0_ro:1;
+ uint64_t o0_ns:1;
+ uint64_t o0_es:2;
+ uint64_t o1_ro:1;
+ uint64_t o1_ns:1;
+ uint64_t o1_es:2;
+ uint64_t reserved_36_43:8;
+ uint64_t p0_bmode:1;
+ uint64_t p1_bmode:1;
+ uint64_t reserved_46_47:2;
+ uint64_t pkt_rr:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } cn50xx;
+ struct cvmx_npi_output_control_s cn58xx;
+ struct cvmx_npi_output_control_s cn58xxp1;
+} cvmx_npi_output_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_px_dbpair_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_63_63:1;
+ uint64_t state:2;
+ uint64_t naddr:61;
+#else
+ uint64_t naddr:61;
+ uint64_t state:2;
+ uint64_t reserved_63_63:1;
+#endif
+ } s;
+ struct cvmx_npi_px_dbpair_addr_s cn30xx;
+ struct cvmx_npi_px_dbpair_addr_s cn31xx;
+ struct cvmx_npi_px_dbpair_addr_s cn38xx;
+ struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
+ struct cvmx_npi_px_dbpair_addr_s cn50xx;
+ struct cvmx_npi_px_dbpair_addr_s cn58xx;
+ struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
+} cvmx_npi_px_dbpair_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_px_instr_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t state:3;
+ uint64_t naddr:61;
+#else
+ uint64_t naddr:61;
+ uint64_t state:3;
+#endif
+ } s;
+ struct cvmx_npi_px_instr_addr_s cn30xx;
+ struct cvmx_npi_px_instr_addr_s cn31xx;
+ struct cvmx_npi_px_instr_addr_s cn38xx;
+ struct cvmx_npi_px_instr_addr_s cn38xxp2;
+ struct cvmx_npi_px_instr_addr_s cn50xx;
+ struct cvmx_npi_px_instr_addr_s cn58xx;
+ struct cvmx_npi_px_instr_addr_s cn58xxp1;
+} cvmx_npi_px_instr_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_px_instr_cnts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t fcnt:6;
+ uint64_t avail:32;
+#else
+ uint64_t avail:32;
+ uint64_t fcnt:6;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_npi_px_instr_cnts_s cn30xx;
+ struct cvmx_npi_px_instr_cnts_s cn31xx;
+ struct cvmx_npi_px_instr_cnts_s cn38xx;
+ struct cvmx_npi_px_instr_cnts_s cn38xxp2;
+ struct cvmx_npi_px_instr_cnts_s cn50xx;
+ struct cvmx_npi_px_instr_cnts_s cn58xx;
+ struct cvmx_npi_px_instr_cnts_s cn58xxp1;
+} cvmx_npi_px_instr_cnts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_px_pair_cnts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t fcnt:5;
+ uint64_t avail:32;
+#else
+ uint64_t avail:32;
+ uint64_t fcnt:5;
+ uint64_t reserved_37_63:27;
+#endif
+ } s;
+ struct cvmx_npi_px_pair_cnts_s cn30xx;
+ struct cvmx_npi_px_pair_cnts_s cn31xx;
+ struct cvmx_npi_px_pair_cnts_s cn38xx;
+ struct cvmx_npi_px_pair_cnts_s cn38xxp2;
+ struct cvmx_npi_px_pair_cnts_s cn50xx;
+ struct cvmx_npi_px_pair_cnts_s cn58xx;
+ struct cvmx_npi_px_pair_cnts_s cn58xxp1;
+} cvmx_npi_px_pair_cnts_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_pci_burst_size_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t wr_brst:7;
+ uint64_t rd_brst:7;
+#else
+ uint64_t rd_brst:7;
+ uint64_t wr_brst:7;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_npi_pci_burst_size_s cn30xx;
+ struct cvmx_npi_pci_burst_size_s cn31xx;
+ struct cvmx_npi_pci_burst_size_s cn38xx;
+ struct cvmx_npi_pci_burst_size_s cn38xxp2;
+ struct cvmx_npi_pci_burst_size_s cn50xx;
+ struct cvmx_npi_pci_burst_size_s cn58xx;
+ struct cvmx_npi_pci_burst_size_s cn58xxp1;
+} cvmx_npi_pci_burst_size_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_pci_int_arb_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t hostmode:1;
+ uint64_t pci_ovr:4;
+ uint64_t reserved_5_7:3;
+ uint64_t en:1;
+ uint64_t park_mod:1;
+ uint64_t park_dev:3;
+#else
+ uint64_t park_dev:3;
+ uint64_t park_mod:1;
+ uint64_t en:1;
+ uint64_t reserved_5_7:3;
+ uint64_t pci_ovr:4;
+ uint64_t hostmode:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_npi_pci_int_arb_cfg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t en:1;
+ uint64_t park_mod:1;
+ uint64_t park_dev:3;
+#else
+ uint64_t park_dev:3;
+ uint64_t park_mod:1;
+ uint64_t en:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } cn30xx;
+ struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
+ struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
+ struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
+ struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
+ struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
+ struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
+} cvmx_npi_pci_int_arb_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_pci_read_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t cmd_size:11;
+#else
+ uint64_t cmd_size:11;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_npi_pci_read_cmd_s cn30xx;
+ struct cvmx_npi_pci_read_cmd_s cn31xx;
+ struct cvmx_npi_pci_read_cmd_s cn38xx;
+ struct cvmx_npi_pci_read_cmd_s cn38xxp2;
+ struct cvmx_npi_pci_read_cmd_s cn50xx;
+ struct cvmx_npi_pci_read_cmd_s cn58xx;
+ struct cvmx_npi_pci_read_cmd_s cn58xxp1;
+} cvmx_npi_pci_read_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_port32_instr_hdr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t rsv_f:5;
+ uint64_t rparmode:2;
+ uint64_t rsv_e:1;
+ uint64_t rskp_len:7;
+ uint64_t rsv_d:6;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_c:5;
+ uint64_t par_mode:2;
+ uint64_t rsv_b:1;
+ uint64_t skp_len:7;
+ uint64_t rsv_a:6;
+#else
+ uint64_t rsv_a:6;
+ uint64_t skp_len:7;
+ uint64_t rsv_b:1;
+ uint64_t par_mode:2;
+ uint64_t rsv_c:5;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_d:6;
+ uint64_t rskp_len:7;
+ uint64_t rsv_e:1;
+ uint64_t rparmode:2;
+ uint64_t rsv_f:5;
+ uint64_t pbp:1;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npi_port32_instr_hdr_s cn30xx;
+ struct cvmx_npi_port32_instr_hdr_s cn31xx;
+ struct cvmx_npi_port32_instr_hdr_s cn38xx;
+ struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
+ struct cvmx_npi_port32_instr_hdr_s cn50xx;
+ struct cvmx_npi_port32_instr_hdr_s cn58xx;
+ struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
+} cvmx_npi_port32_instr_hdr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_port33_instr_hdr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t rsv_f:5;
+ uint64_t rparmode:2;
+ uint64_t rsv_e:1;
+ uint64_t rskp_len:7;
+ uint64_t rsv_d:6;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_c:5;
+ uint64_t par_mode:2;
+ uint64_t rsv_b:1;
+ uint64_t skp_len:7;
+ uint64_t rsv_a:6;
+#else
+ uint64_t rsv_a:6;
+ uint64_t skp_len:7;
+ uint64_t rsv_b:1;
+ uint64_t par_mode:2;
+ uint64_t rsv_c:5;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_d:6;
+ uint64_t rskp_len:7;
+ uint64_t rsv_e:1;
+ uint64_t rparmode:2;
+ uint64_t rsv_f:5;
+ uint64_t pbp:1;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npi_port33_instr_hdr_s cn31xx;
+ struct cvmx_npi_port33_instr_hdr_s cn38xx;
+ struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
+ struct cvmx_npi_port33_instr_hdr_s cn50xx;
+ struct cvmx_npi_port33_instr_hdr_s cn58xx;
+ struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
+} cvmx_npi_port33_instr_hdr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_port34_instr_hdr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t rsv_f:5;
+ uint64_t rparmode:2;
+ uint64_t rsv_e:1;
+ uint64_t rskp_len:7;
+ uint64_t rsv_d:6;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_c:5;
+ uint64_t par_mode:2;
+ uint64_t rsv_b:1;
+ uint64_t skp_len:7;
+ uint64_t rsv_a:6;
+#else
+ uint64_t rsv_a:6;
+ uint64_t skp_len:7;
+ uint64_t rsv_b:1;
+ uint64_t par_mode:2;
+ uint64_t rsv_c:5;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_d:6;
+ uint64_t rskp_len:7;
+ uint64_t rsv_e:1;
+ uint64_t rparmode:2;
+ uint64_t rsv_f:5;
+ uint64_t pbp:1;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npi_port34_instr_hdr_s cn38xx;
+ struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
+ struct cvmx_npi_port34_instr_hdr_s cn58xx;
+ struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
+} cvmx_npi_port34_instr_hdr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_port35_instr_hdr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t rsv_f:5;
+ uint64_t rparmode:2;
+ uint64_t rsv_e:1;
+ uint64_t rskp_len:7;
+ uint64_t rsv_d:6;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_c:5;
+ uint64_t par_mode:2;
+ uint64_t rsv_b:1;
+ uint64_t skp_len:7;
+ uint64_t rsv_a:6;
+#else
+ uint64_t rsv_a:6;
+ uint64_t skp_len:7;
+ uint64_t rsv_b:1;
+ uint64_t par_mode:2;
+ uint64_t rsv_c:5;
+ uint64_t use_ihdr:1;
+ uint64_t rsv_d:6;
+ uint64_t rskp_len:7;
+ uint64_t rsv_e:1;
+ uint64_t rparmode:2;
+ uint64_t rsv_f:5;
+ uint64_t pbp:1;
+ uint64_t reserved_44_63:20;
+#endif
+ } s;
+ struct cvmx_npi_port35_instr_hdr_s cn38xx;
+ struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
+ struct cvmx_npi_port35_instr_hdr_s cn58xx;
+ struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
+} cvmx_npi_port35_instr_hdr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_port_bp_control_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t bp_on:4;
+ uint64_t enb:4;
+#else
+ uint64_t enb:4;
+ uint64_t bp_on:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_npi_port_bp_control_s cn30xx;
+ struct cvmx_npi_port_bp_control_s cn31xx;
+ struct cvmx_npi_port_bp_control_s cn38xx;
+ struct cvmx_npi_port_bp_control_s cn38xxp2;
+ struct cvmx_npi_port_bp_control_s cn50xx;
+ struct cvmx_npi_port_bp_control_s cn58xx;
+ struct cvmx_npi_port_bp_control_s cn58xxp1;
+} cvmx_npi_port_bp_control_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_rsl_int_blocks_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rint_31:1;
+ uint64_t iob:1;
+ uint64_t reserved_28_29:2;
+ uint64_t rint_27:1;
+ uint64_t rint_26:1;
+ uint64_t rint_25:1;
+ uint64_t rint_24:1;
+ uint64_t asx1:1;
+ uint64_t asx0:1;
+ uint64_t rint_21:1;
+ uint64_t pip:1;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
+ uint64_t lmc:1;
+ uint64_t l2c:1;
+ uint64_t rint_15:1;
+ uint64_t reserved_13_14:2;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t rint_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npi:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npi:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rint_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t reserved_13_14:2;
+ uint64_t rint_15:1;
+ uint64_t l2c:1;
+ uint64_t lmc:1;
+ uint64_t spx0:1;
+ uint64_t spx1:1;
+ uint64_t pip:1;
+ uint64_t rint_21:1;
+ uint64_t asx0:1;
+ uint64_t asx1:1;
+ uint64_t rint_24:1;
+ uint64_t rint_25:1;
+ uint64_t rint_26:1;
+ uint64_t rint_27:1;
+ uint64_t reserved_28_29:2;
+ uint64_t iob:1;
+ uint64_t rint_31:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npi_rsl_int_blocks_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rint_31:1;
+ uint64_t iob:1;
+ uint64_t rint_29:1;
+ uint64_t rint_28:1;
+ uint64_t rint_27:1;
+ uint64_t rint_26:1;
+ uint64_t rint_25:1;
+ uint64_t rint_24:1;
+ uint64_t asx1:1;
+ uint64_t asx0:1;
+ uint64_t rint_21:1;
+ uint64_t pip:1;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
+ uint64_t lmc:1;
+ uint64_t l2c:1;
+ uint64_t rint_15:1;
+ uint64_t rint_14:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t rint_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npi:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npi:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rint_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t usb:1;
+ uint64_t rint_14:1;
+ uint64_t rint_15:1;
+ uint64_t l2c:1;
+ uint64_t lmc:1;
+ uint64_t spx0:1;
+ uint64_t spx1:1;
+ uint64_t pip:1;
+ uint64_t rint_21:1;
+ uint64_t asx0:1;
+ uint64_t asx1:1;
+ uint64_t rint_24:1;
+ uint64_t rint_25:1;
+ uint64_t rint_26:1;
+ uint64_t rint_27:1;
+ uint64_t rint_28:1;
+ uint64_t rint_29:1;
+ uint64_t iob:1;
+ uint64_t rint_31:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn30xx;
+ struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
+ struct cvmx_npi_rsl_int_blocks_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rint_31:1;
+ uint64_t iob:1;
+ uint64_t rint_29:1;
+ uint64_t rint_28:1;
+ uint64_t rint_27:1;
+ uint64_t rint_26:1;
+ uint64_t rint_25:1;
+ uint64_t rint_24:1;
+ uint64_t asx1:1;
+ uint64_t asx0:1;
+ uint64_t rint_21:1;
+ uint64_t pip:1;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
+ uint64_t lmc:1;
+ uint64_t l2c:1;
+ uint64_t rint_15:1;
+ uint64_t rint_14:1;
+ uint64_t rint_13:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t rint_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npi:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npi:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rint_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t rint_13:1;
+ uint64_t rint_14:1;
+ uint64_t rint_15:1;
+ uint64_t l2c:1;
+ uint64_t lmc:1;
+ uint64_t spx0:1;
+ uint64_t spx1:1;
+ uint64_t pip:1;
+ uint64_t rint_21:1;
+ uint64_t asx0:1;
+ uint64_t asx1:1;
+ uint64_t rint_24:1;
+ uint64_t rint_25:1;
+ uint64_t rint_26:1;
+ uint64_t rint_27:1;
+ uint64_t rint_28:1;
+ uint64_t rint_29:1;
+ uint64_t iob:1;
+ uint64_t rint_31:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
+ struct cvmx_npi_rsl_int_blocks_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t iob:1;
+ uint64_t lmc1:1;
+ uint64_t agl:1;
+ uint64_t reserved_24_27:4;
+ uint64_t asx1:1;
+ uint64_t asx0:1;
+ uint64_t reserved_21_21:1;
+ uint64_t pip:1;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
+ uint64_t lmc:1;
+ uint64_t l2c:1;
+ uint64_t reserved_15_15:1;
+ uint64_t rad:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t reserved_8_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t npi:1;
+ uint64_t gmx1:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t gmx0:1;
+ uint64_t gmx1:1;
+ uint64_t npi:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t reserved_8_8:1;
+ uint64_t ipd:1;
+ uint64_t pko:1;
+ uint64_t tim:1;
+ uint64_t pow:1;
+ uint64_t usb:1;
+ uint64_t rad:1;
+ uint64_t reserved_15_15:1;
+ uint64_t l2c:1;
+ uint64_t lmc:1;
+ uint64_t spx0:1;
+ uint64_t spx1:1;
+ uint64_t pip:1;
+ uint64_t reserved_21_21:1;
+ uint64_t asx0:1;
+ uint64_t asx1:1;
+ uint64_t reserved_24_27:4;
+ uint64_t agl:1;
+ uint64_t lmc1:1;
+ uint64_t iob:1;
+ uint64_t reserved_31_63:33;
+#endif
+ } cn50xx;
+ struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
+ struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
+} cvmx_npi_rsl_int_blocks_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_size_inputx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t size:32;
+#else
+ uint64_t size:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npi_size_inputx_s cn30xx;
+ struct cvmx_npi_size_inputx_s cn31xx;
+ struct cvmx_npi_size_inputx_s cn38xx;
+ struct cvmx_npi_size_inputx_s cn38xxp2;
+ struct cvmx_npi_size_inputx_s cn50xx;
+ struct cvmx_npi_size_inputx_s cn58xx;
+ struct cvmx_npi_size_inputx_s cn58xxp1;
+} cvmx_npi_size_inputx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_npi_win_read_to_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t time:32;
+#else
+ uint64_t time:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_npi_win_read_to_s cn30xx;
+ struct cvmx_npi_win_read_to_s cn31xx;
+ struct cvmx_npi_win_read_to_s cn38xx;
+ struct cvmx_npi_win_read_to_s cn38xxp2;
+ struct cvmx_npi_win_read_to_s cn50xx;
+ struct cvmx_npi_win_read_to_s cn58xx;
+ struct cvmx_npi_win_read_to_s cn58xxp1;
+} cvmx_npi_win_read_to_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_bar1_indexx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_18_31:14;
+ uint32_t addr_idx:14;
+ uint32_t ca:1;
+ uint32_t end_swp:2;
+ uint32_t addr_v:1;
+#else
+ uint32_t addr_v:1;
+ uint32_t end_swp:2;
+ uint32_t ca:1;
+ uint32_t addr_idx:14;
+ uint32_t reserved_18_31:14;
+#endif
+ } s;
+ struct cvmx_pci_bar1_indexx_s cn30xx;
+ struct cvmx_pci_bar1_indexx_s cn31xx;
+ struct cvmx_pci_bar1_indexx_s cn38xx;
+ struct cvmx_pci_bar1_indexx_s cn38xxp2;
+ struct cvmx_pci_bar1_indexx_s cn50xx;
+ struct cvmx_pci_bar1_indexx_s cn58xx;
+ struct cvmx_pci_bar1_indexx_s cn58xxp1;
+} cvmx_pci_bar1_indexx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_bist_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t rsp_bs:1;
+ uint64_t dma0_bs:1;
+ uint64_t cmd0_bs:1;
+ uint64_t cmd_bs:1;
+ uint64_t csr2p_bs:1;
+ uint64_t csrr_bs:1;
+ uint64_t rsp2p_bs:1;
+ uint64_t csr2n_bs:1;
+ uint64_t dat2n_bs:1;
+ uint64_t dbg2n_bs:1;
+#else
+ uint64_t dbg2n_bs:1;
+ uint64_t dat2n_bs:1;
+ uint64_t csr2n_bs:1;
+ uint64_t rsp2p_bs:1;
+ uint64_t csrr_bs:1;
+ uint64_t csr2p_bs:1;
+ uint64_t cmd_bs:1;
+ uint64_t cmd0_bs:1;
+ uint64_t dma0_bs:1;
+ uint64_t rsp_bs:1;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_pci_bist_reg_s cn50xx;
+} cvmx_pci_bist_reg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg00_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t devid:16;
+ uint32_t vendid:16;
+#else
+ uint32_t vendid:16;
+ uint32_t devid:16;
+#endif
+ } s;
+ struct cvmx_pci_cfg00_s cn30xx;
+ struct cvmx_pci_cfg00_s cn31xx;
+ struct cvmx_pci_cfg00_s cn38xx;
+ struct cvmx_pci_cfg00_s cn38xxp2;
+ struct cvmx_pci_cfg00_s cn50xx;
+ struct cvmx_pci_cfg00_s cn58xx;
+ struct cvmx_pci_cfg00_s cn58xxp1;
+} cvmx_pci_cfg00_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg01_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dpe:1;
+ uint32_t sse:1;
+ uint32_t rma:1;
+ uint32_t rta:1;
+ uint32_t sta:1;
+ uint32_t devt:2;
+ uint32_t mdpe:1;
+ uint32_t fbb:1;
+ uint32_t reserved_22_22:1;
+ uint32_t m66:1;
+ uint32_t cle:1;
+ uint32_t i_stat:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_dis:1;
+ uint32_t fbbe:1;
+ uint32_t see:1;
+ uint32_t ads:1;
+ uint32_t pee:1;
+ uint32_t vps:1;
+ uint32_t mwice:1;
+ uint32_t scse:1;
+ uint32_t me:1;
+ uint32_t msae:1;
+ uint32_t isae:1;
+#else
+ uint32_t isae:1;
+ uint32_t msae:1;
+ uint32_t me:1;
+ uint32_t scse:1;
+ uint32_t mwice:1;
+ uint32_t vps:1;
+ uint32_t pee:1;
+ uint32_t ads:1;
+ uint32_t see:1;
+ uint32_t fbbe:1;
+ uint32_t i_dis:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_stat:1;
+ uint32_t cle:1;
+ uint32_t m66:1;
+ uint32_t reserved_22_22:1;
+ uint32_t fbb:1;
+ uint32_t mdpe:1;
+ uint32_t devt:2;
+ uint32_t sta:1;
+ uint32_t rta:1;
+ uint32_t rma:1;
+ uint32_t sse:1;
+ uint32_t dpe:1;
+#endif
+ } s;
+ struct cvmx_pci_cfg01_s cn30xx;
+ struct cvmx_pci_cfg01_s cn31xx;
+ struct cvmx_pci_cfg01_s cn38xx;
+ struct cvmx_pci_cfg01_s cn38xxp2;
+ struct cvmx_pci_cfg01_s cn50xx;
+ struct cvmx_pci_cfg01_s cn58xx;
+ struct cvmx_pci_cfg01_s cn58xxp1;
+} cvmx_pci_cfg01_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg02_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t cc:24;
+ uint32_t rid:8;
+#else
+ uint32_t rid:8;
+ uint32_t cc:24;
+#endif
+ } s;
+ struct cvmx_pci_cfg02_s cn30xx;
+ struct cvmx_pci_cfg02_s cn31xx;
+ struct cvmx_pci_cfg02_s cn38xx;
+ struct cvmx_pci_cfg02_s cn38xxp2;
+ struct cvmx_pci_cfg02_s cn50xx;
+ struct cvmx_pci_cfg02_s cn58xx;
+ struct cvmx_pci_cfg02_s cn58xxp1;
+} cvmx_pci_cfg02_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg03_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t bcap:1;
+ uint32_t brb:1;
+ uint32_t reserved_28_29:2;
+ uint32_t bcod:4;
+ uint32_t ht:8;
+ uint32_t lt:8;
+ uint32_t cls:8;
+#else
+ uint32_t cls:8;
+ uint32_t lt:8;
+ uint32_t ht:8;
+ uint32_t bcod:4;
+ uint32_t reserved_28_29:2;
+ uint32_t brb:1;
+ uint32_t bcap:1;
+#endif
+ } s;
+ struct cvmx_pci_cfg03_s cn30xx;
+ struct cvmx_pci_cfg03_s cn31xx;
+ struct cvmx_pci_cfg03_s cn38xx;
+ struct cvmx_pci_cfg03_s cn38xxp2;
+ struct cvmx_pci_cfg03_s cn50xx;
+ struct cvmx_pci_cfg03_s cn58xx;
+ struct cvmx_pci_cfg03_s cn58xxp1;
+} cvmx_pci_cfg03_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg04_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lbase:20;
+ uint32_t lbasez:8;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t lbasez:8;
+ uint32_t lbase:20;
+#endif
+ } s;
+ struct cvmx_pci_cfg04_s cn30xx;
+ struct cvmx_pci_cfg04_s cn31xx;
+ struct cvmx_pci_cfg04_s cn38xx;
+ struct cvmx_pci_cfg04_s cn38xxp2;
+ struct cvmx_pci_cfg04_s cn50xx;
+ struct cvmx_pci_cfg04_s cn58xx;
+ struct cvmx_pci_cfg04_s cn58xxp1;
+} cvmx_pci_cfg04_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg05_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t hbase:32;
+#else
+ uint32_t hbase:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg05_s cn30xx;
+ struct cvmx_pci_cfg05_s cn31xx;
+ struct cvmx_pci_cfg05_s cn38xx;
+ struct cvmx_pci_cfg05_s cn38xxp2;
+ struct cvmx_pci_cfg05_s cn50xx;
+ struct cvmx_pci_cfg05_s cn58xx;
+ struct cvmx_pci_cfg05_s cn58xxp1;
+} cvmx_pci_cfg05_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg06_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lbase:5;
+ uint32_t lbasez:23;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t lbasez:23;
+ uint32_t lbase:5;
+#endif
+ } s;
+ struct cvmx_pci_cfg06_s cn30xx;
+ struct cvmx_pci_cfg06_s cn31xx;
+ struct cvmx_pci_cfg06_s cn38xx;
+ struct cvmx_pci_cfg06_s cn38xxp2;
+ struct cvmx_pci_cfg06_s cn50xx;
+ struct cvmx_pci_cfg06_s cn58xx;
+ struct cvmx_pci_cfg06_s cn58xxp1;
+} cvmx_pci_cfg06_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg07_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t hbase:32;
+#else
+ uint32_t hbase:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg07_s cn30xx;
+ struct cvmx_pci_cfg07_s cn31xx;
+ struct cvmx_pci_cfg07_s cn38xx;
+ struct cvmx_pci_cfg07_s cn38xxp2;
+ struct cvmx_pci_cfg07_s cn50xx;
+ struct cvmx_pci_cfg07_s cn58xx;
+ struct cvmx_pci_cfg07_s cn58xxp1;
+} cvmx_pci_cfg07_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg08_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lbasez:28;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t lbasez:28;
+#endif
+ } s;
+ struct cvmx_pci_cfg08_s cn30xx;
+ struct cvmx_pci_cfg08_s cn31xx;
+ struct cvmx_pci_cfg08_s cn38xx;
+ struct cvmx_pci_cfg08_s cn38xxp2;
+ struct cvmx_pci_cfg08_s cn50xx;
+ struct cvmx_pci_cfg08_s cn58xx;
+ struct cvmx_pci_cfg08_s cn58xxp1;
+} cvmx_pci_cfg08_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg09_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t hbase:25;
+ uint32_t hbasez:7;
+#else
+ uint32_t hbasez:7;
+ uint32_t hbase:25;
+#endif
+ } s;
+ struct cvmx_pci_cfg09_s cn30xx;
+ struct cvmx_pci_cfg09_s cn31xx;
+ struct cvmx_pci_cfg09_s cn38xx;
+ struct cvmx_pci_cfg09_s cn38xxp2;
+ struct cvmx_pci_cfg09_s cn50xx;
+ struct cvmx_pci_cfg09_s cn58xx;
+ struct cvmx_pci_cfg09_s cn58xxp1;
+} cvmx_pci_cfg09_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg10_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t cisp:32;
+#else
+ uint32_t cisp:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg10_s cn30xx;
+ struct cvmx_pci_cfg10_s cn31xx;
+ struct cvmx_pci_cfg10_s cn38xx;
+ struct cvmx_pci_cfg10_s cn38xxp2;
+ struct cvmx_pci_cfg10_s cn50xx;
+ struct cvmx_pci_cfg10_s cn58xx;
+ struct cvmx_pci_cfg10_s cn58xxp1;
+} cvmx_pci_cfg10_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg11_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ssid:16;
+ uint32_t ssvid:16;
+#else
+ uint32_t ssvid:16;
+ uint32_t ssid:16;
+#endif
+ } s;
+ struct cvmx_pci_cfg11_s cn30xx;
+ struct cvmx_pci_cfg11_s cn31xx;
+ struct cvmx_pci_cfg11_s cn38xx;
+ struct cvmx_pci_cfg11_s cn38xxp2;
+ struct cvmx_pci_cfg11_s cn50xx;
+ struct cvmx_pci_cfg11_s cn58xx;
+ struct cvmx_pci_cfg11_s cn58xxp1;
+} cvmx_pci_cfg11_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg12_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t erbar:16;
+ uint32_t erbarz:5;
+ uint32_t reserved_1_10:10;
+ uint32_t erbar_en:1;
+#else
+ uint32_t erbar_en:1;
+ uint32_t reserved_1_10:10;
+ uint32_t erbarz:5;
+ uint32_t erbar:16;
+#endif
+ } s;
+ struct cvmx_pci_cfg12_s cn30xx;
+ struct cvmx_pci_cfg12_s cn31xx;
+ struct cvmx_pci_cfg12_s cn38xx;
+ struct cvmx_pci_cfg12_s cn38xxp2;
+ struct cvmx_pci_cfg12_s cn50xx;
+ struct cvmx_pci_cfg12_s cn58xx;
+ struct cvmx_pci_cfg12_s cn58xxp1;
+} cvmx_pci_cfg12_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg13_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_8_31:24;
+ uint32_t cp:8;
+#else
+ uint32_t cp:8;
+ uint32_t reserved_8_31:24;
+#endif
+ } s;
+ struct cvmx_pci_cfg13_s cn30xx;
+ struct cvmx_pci_cfg13_s cn31xx;
+ struct cvmx_pci_cfg13_s cn38xx;
+ struct cvmx_pci_cfg13_s cn38xxp2;
+ struct cvmx_pci_cfg13_s cn50xx;
+ struct cvmx_pci_cfg13_s cn58xx;
+ struct cvmx_pci_cfg13_s cn58xxp1;
+} cvmx_pci_cfg13_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg15_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ml:8;
+ uint32_t mg:8;
+ uint32_t inta:8;
+ uint32_t il:8;
+#else
+ uint32_t il:8;
+ uint32_t inta:8;
+ uint32_t mg:8;
+ uint32_t ml:8;
+#endif
+ } s;
+ struct cvmx_pci_cfg15_s cn30xx;
+ struct cvmx_pci_cfg15_s cn31xx;
+ struct cvmx_pci_cfg15_s cn38xx;
+ struct cvmx_pci_cfg15_s cn38xxp2;
+ struct cvmx_pci_cfg15_s cn50xx;
+ struct cvmx_pci_cfg15_s cn58xx;
+ struct cvmx_pci_cfg15_s cn58xxp1;
+} cvmx_pci_cfg15_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg16_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t trdnpr:1;
+ uint32_t trdard:1;
+ uint32_t rdsati:1;
+ uint32_t trdrs:1;
+ uint32_t trtae:1;
+ uint32_t twsei:1;
+ uint32_t twsen:1;
+ uint32_t twtae:1;
+ uint32_t tmae:1;
+ uint32_t tslte:3;
+ uint32_t tilt:4;
+ uint32_t pbe:12;
+ uint32_t dppmr:1;
+ uint32_t reserved_2_2:1;
+ uint32_t tswc:1;
+ uint32_t mltd:1;
+#else
+ uint32_t mltd:1;
+ uint32_t tswc:1;
+ uint32_t reserved_2_2:1;
+ uint32_t dppmr:1;
+ uint32_t pbe:12;
+ uint32_t tilt:4;
+ uint32_t tslte:3;
+ uint32_t tmae:1;
+ uint32_t twtae:1;
+ uint32_t twsen:1;
+ uint32_t twsei:1;
+ uint32_t trtae:1;
+ uint32_t trdrs:1;
+ uint32_t rdsati:1;
+ uint32_t trdard:1;
+ uint32_t trdnpr:1;
+#endif
+ } s;
+ struct cvmx_pci_cfg16_s cn30xx;
+ struct cvmx_pci_cfg16_s cn31xx;
+ struct cvmx_pci_cfg16_s cn38xx;
+ struct cvmx_pci_cfg16_s cn38xxp2;
+ struct cvmx_pci_cfg16_s cn50xx;
+ struct cvmx_pci_cfg16_s cn58xx;
+ struct cvmx_pci_cfg16_s cn58xxp1;
+} cvmx_pci_cfg16_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg17_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t tscme:32;
+#else
+ uint32_t tscme:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg17_s cn30xx;
+ struct cvmx_pci_cfg17_s cn31xx;
+ struct cvmx_pci_cfg17_s cn38xx;
+ struct cvmx_pci_cfg17_s cn38xxp2;
+ struct cvmx_pci_cfg17_s cn50xx;
+ struct cvmx_pci_cfg17_s cn58xx;
+ struct cvmx_pci_cfg17_s cn58xxp1;
+} cvmx_pci_cfg17_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg18_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t tdsrps:32;
+#else
+ uint32_t tdsrps:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg18_s cn30xx;
+ struct cvmx_pci_cfg18_s cn31xx;
+ struct cvmx_pci_cfg18_s cn38xx;
+ struct cvmx_pci_cfg18_s cn38xxp2;
+ struct cvmx_pci_cfg18_s cn50xx;
+ struct cvmx_pci_cfg18_s cn58xx;
+ struct cvmx_pci_cfg18_s cn58xxp1;
+} cvmx_pci_cfg18_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg19_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t mrbcm:1;
+ uint32_t mrbci:1;
+ uint32_t mdwe:1;
+ uint32_t mdre:1;
+ uint32_t mdrimc:1;
+ uint32_t mdrrmc:3;
+ uint32_t tmes:8;
+ uint32_t teci:1;
+ uint32_t tmei:1;
+ uint32_t tmse:1;
+ uint32_t tmdpes:1;
+ uint32_t tmapes:1;
+ uint32_t reserved_9_10:2;
+ uint32_t tibcd:1;
+ uint32_t tibde:1;
+ uint32_t reserved_6_6:1;
+ uint32_t tidomc:1;
+ uint32_t tdomc:5;
+#else
+ uint32_t tdomc:5;
+ uint32_t tidomc:1;
+ uint32_t reserved_6_6:1;
+ uint32_t tibde:1;
+ uint32_t tibcd:1;
+ uint32_t reserved_9_10:2;
+ uint32_t tmapes:1;
+ uint32_t tmdpes:1;
+ uint32_t tmse:1;
+ uint32_t tmei:1;
+ uint32_t teci:1;
+ uint32_t tmes:8;
+ uint32_t mdrrmc:3;
+ uint32_t mdrimc:1;
+ uint32_t mdre:1;
+ uint32_t mdwe:1;
+ uint32_t mrbci:1;
+ uint32_t mrbcm:1;
+#endif
+ } s;
+ struct cvmx_pci_cfg19_s cn30xx;
+ struct cvmx_pci_cfg19_s cn31xx;
+ struct cvmx_pci_cfg19_s cn38xx;
+ struct cvmx_pci_cfg19_s cn38xxp2;
+ struct cvmx_pci_cfg19_s cn50xx;
+ struct cvmx_pci_cfg19_s cn58xx;
+ struct cvmx_pci_cfg19_s cn58xxp1;
+} cvmx_pci_cfg19_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg20_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t mdsp:32;
+#else
+ uint32_t mdsp:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg20_s cn30xx;
+ struct cvmx_pci_cfg20_s cn31xx;
+ struct cvmx_pci_cfg20_s cn38xx;
+ struct cvmx_pci_cfg20_s cn38xxp2;
+ struct cvmx_pci_cfg20_s cn50xx;
+ struct cvmx_pci_cfg20_s cn58xx;
+ struct cvmx_pci_cfg20_s cn58xxp1;
+} cvmx_pci_cfg20_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg21_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t scmre:32;
+#else
+ uint32_t scmre:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg21_s cn30xx;
+ struct cvmx_pci_cfg21_s cn31xx;
+ struct cvmx_pci_cfg21_s cn38xx;
+ struct cvmx_pci_cfg21_s cn38xxp2;
+ struct cvmx_pci_cfg21_s cn50xx;
+ struct cvmx_pci_cfg21_s cn58xx;
+ struct cvmx_pci_cfg21_s cn58xxp1;
+} cvmx_pci_cfg21_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg22_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t mac:7;
+ uint32_t reserved_19_24:6;
+ uint32_t flush:1;
+ uint32_t mra:1;
+ uint32_t mtta:1;
+ uint32_t mrv:8;
+ uint32_t mttv:8;
+#else
+ uint32_t mttv:8;
+ uint32_t mrv:8;
+ uint32_t mtta:1;
+ uint32_t mra:1;
+ uint32_t flush:1;
+ uint32_t reserved_19_24:6;
+ uint32_t mac:7;
+#endif
+ } s;
+ struct cvmx_pci_cfg22_s cn30xx;
+ struct cvmx_pci_cfg22_s cn31xx;
+ struct cvmx_pci_cfg22_s cn38xx;
+ struct cvmx_pci_cfg22_s cn38xxp2;
+ struct cvmx_pci_cfg22_s cn50xx;
+ struct cvmx_pci_cfg22_s cn58xx;
+ struct cvmx_pci_cfg22_s cn58xxp1;
+} cvmx_pci_cfg22_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg56_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_23_31:9;
+ uint32_t most:3;
+ uint32_t mmbc:2;
+ uint32_t roe:1;
+ uint32_t dpere:1;
+ uint32_t ncp:8;
+ uint32_t pxcid:8;
+#else
+ uint32_t pxcid:8;
+ uint32_t ncp:8;
+ uint32_t dpere:1;
+ uint32_t roe:1;
+ uint32_t mmbc:2;
+ uint32_t most:3;
+ uint32_t reserved_23_31:9;
+#endif
+ } s;
+ struct cvmx_pci_cfg56_s cn30xx;
+ struct cvmx_pci_cfg56_s cn31xx;
+ struct cvmx_pci_cfg56_s cn38xx;
+ struct cvmx_pci_cfg56_s cn38xxp2;
+ struct cvmx_pci_cfg56_s cn50xx;
+ struct cvmx_pci_cfg56_s cn58xx;
+ struct cvmx_pci_cfg56_s cn58xxp1;
+} cvmx_pci_cfg56_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg57_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t scemr:1;
+ uint32_t mcrsd:3;
+ uint32_t mostd:3;
+ uint32_t mmrbcd:2;
+ uint32_t dc:1;
+ uint32_t usc:1;
+ uint32_t scd:1;
+ uint32_t m133:1;
+ uint32_t w64:1;
+ uint32_t bn:8;
+ uint32_t dn:5;
+ uint32_t fn:3;
+#else
+ uint32_t fn:3;
+ uint32_t dn:5;
+ uint32_t bn:8;
+ uint32_t w64:1;
+ uint32_t m133:1;
+ uint32_t scd:1;
+ uint32_t usc:1;
+ uint32_t dc:1;
+ uint32_t mmrbcd:2;
+ uint32_t mostd:3;
+ uint32_t mcrsd:3;
+ uint32_t scemr:1;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pci_cfg57_s cn30xx;
+ struct cvmx_pci_cfg57_s cn31xx;
+ struct cvmx_pci_cfg57_s cn38xx;
+ struct cvmx_pci_cfg57_s cn38xxp2;
+ struct cvmx_pci_cfg57_s cn50xx;
+ struct cvmx_pci_cfg57_s cn58xx;
+ struct cvmx_pci_cfg57_s cn58xxp1;
+} cvmx_pci_cfg57_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg58_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmes:5;
+ uint32_t d2s:1;
+ uint32_t d1s:1;
+ uint32_t auxc:3;
+ uint32_t dsi:1;
+ uint32_t reserved_20_20:1;
+ uint32_t pmec:1;
+ uint32_t pcimiv:3;
+ uint32_t ncp:8;
+ uint32_t pmcid:8;
+#else
+ uint32_t pmcid:8;
+ uint32_t ncp:8;
+ uint32_t pcimiv:3;
+ uint32_t pmec:1;
+ uint32_t reserved_20_20:1;
+ uint32_t dsi:1;
+ uint32_t auxc:3;
+ uint32_t d1s:1;
+ uint32_t d2s:1;
+ uint32_t pmes:5;
+#endif
+ } s;
+ struct cvmx_pci_cfg58_s cn30xx;
+ struct cvmx_pci_cfg58_s cn31xx;
+ struct cvmx_pci_cfg58_s cn38xx;
+ struct cvmx_pci_cfg58_s cn38xxp2;
+ struct cvmx_pci_cfg58_s cn50xx;
+ struct cvmx_pci_cfg58_s cn58xx;
+ struct cvmx_pci_cfg58_s cn58xxp1;
+} cvmx_pci_cfg58_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg59_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmdia:8;
+ uint32_t bpccen:1;
+ uint32_t bd3h:1;
+ uint32_t reserved_16_21:6;
+ uint32_t pmess:1;
+ uint32_t pmedsia:2;
+ uint32_t pmds:4;
+ uint32_t pmeens:1;
+ uint32_t reserved_2_7:6;
+ uint32_t ps:2;
+#else
+ uint32_t ps:2;
+ uint32_t reserved_2_7:6;
+ uint32_t pmeens:1;
+ uint32_t pmds:4;
+ uint32_t pmedsia:2;
+ uint32_t pmess:1;
+ uint32_t reserved_16_21:6;
+ uint32_t bd3h:1;
+ uint32_t bpccen:1;
+ uint32_t pmdia:8;
+#endif
+ } s;
+ struct cvmx_pci_cfg59_s cn30xx;
+ struct cvmx_pci_cfg59_s cn31xx;
+ struct cvmx_pci_cfg59_s cn38xx;
+ struct cvmx_pci_cfg59_s cn38xxp2;
+ struct cvmx_pci_cfg59_s cn50xx;
+ struct cvmx_pci_cfg59_s cn58xx;
+ struct cvmx_pci_cfg59_s cn58xxp1;
+} cvmx_pci_cfg59_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg60_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t m64:1;
+ uint32_t mme:3;
+ uint32_t mmc:3;
+ uint32_t msien:1;
+ uint32_t ncp:8;
+ uint32_t msicid:8;
+#else
+ uint32_t msicid:8;
+ uint32_t ncp:8;
+ uint32_t msien:1;
+ uint32_t mmc:3;
+ uint32_t mme:3;
+ uint32_t m64:1;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pci_cfg60_s cn30xx;
+ struct cvmx_pci_cfg60_s cn31xx;
+ struct cvmx_pci_cfg60_s cn38xx;
+ struct cvmx_pci_cfg60_s cn38xxp2;
+ struct cvmx_pci_cfg60_s cn50xx;
+ struct cvmx_pci_cfg60_s cn58xx;
+ struct cvmx_pci_cfg60_s cn58xxp1;
+} cvmx_pci_cfg60_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg61_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t msi31t2:30;
+ uint32_t reserved_0_1:2;
+#else
+ uint32_t reserved_0_1:2;
+ uint32_t msi31t2:30;
+#endif
+ } s;
+ struct cvmx_pci_cfg61_s cn30xx;
+ struct cvmx_pci_cfg61_s cn31xx;
+ struct cvmx_pci_cfg61_s cn38xx;
+ struct cvmx_pci_cfg61_s cn38xxp2;
+ struct cvmx_pci_cfg61_s cn50xx;
+ struct cvmx_pci_cfg61_s cn58xx;
+ struct cvmx_pci_cfg61_s cn58xxp1;
+} cvmx_pci_cfg61_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg62_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t msi:32;
+#else
+ uint32_t msi:32;
+#endif
+ } s;
+ struct cvmx_pci_cfg62_s cn30xx;
+ struct cvmx_pci_cfg62_s cn31xx;
+ struct cvmx_pci_cfg62_s cn38xx;
+ struct cvmx_pci_cfg62_s cn38xxp2;
+ struct cvmx_pci_cfg62_s cn50xx;
+ struct cvmx_pci_cfg62_s cn58xx;
+ struct cvmx_pci_cfg62_s cn58xxp1;
+} cvmx_pci_cfg62_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_cfg63_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t msimd:16;
+#else
+ uint32_t msimd:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_pci_cfg63_s cn30xx;
+ struct cvmx_pci_cfg63_s cn31xx;
+ struct cvmx_pci_cfg63_s cn38xx;
+ struct cvmx_pci_cfg63_s cn38xxp2;
+ struct cvmx_pci_cfg63_s cn50xx;
+ struct cvmx_pci_cfg63_s cn58xx;
+ struct cvmx_pci_cfg63_s cn58xxp1;
+} cvmx_pci_cfg63_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_cnt_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t hm_pcix:1;
+ uint64_t hm_speed:2;
+ uint64_t ap_pcix:1;
+ uint64_t ap_speed:2;
+ uint64_t pcicnt:32;
+#else
+ uint64_t pcicnt:32;
+ uint64_t ap_speed:2;
+ uint64_t ap_pcix:1;
+ uint64_t hm_speed:2;
+ uint64_t hm_pcix:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_pci_cnt_reg_s cn50xx;
+ struct cvmx_pci_cnt_reg_s cn58xx;
+ struct cvmx_pci_cnt_reg_s cn58xxp1;
+} cvmx_pci_cnt_reg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_ctl_status_2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_29_31:3;
+ uint32_t bb1_hole:3;
+ uint32_t bb1_siz:1;
+ uint32_t bb_ca:1;
+ uint32_t bb_es:2;
+ uint32_t bb1:1;
+ uint32_t bb0:1;
+ uint32_t erst_n:1;
+ uint32_t bar2pres:1;
+ uint32_t scmtyp:1;
+ uint32_t scm:1;
+ uint32_t en_wfilt:1;
+ uint32_t reserved_14_14:1;
+ uint32_t ap_pcix:1;
+ uint32_t ap_64ad:1;
+ uint32_t b12_bist:1;
+ uint32_t pmo_amod:1;
+ uint32_t pmo_fpc:3;
+ uint32_t tsr_hwm:3;
+ uint32_t bar2_enb:1;
+ uint32_t bar2_esx:2;
+ uint32_t bar2_cax:1;
+#else
+ uint32_t bar2_cax:1;
+ uint32_t bar2_esx:2;
+ uint32_t bar2_enb:1;
+ uint32_t tsr_hwm:3;
+ uint32_t pmo_fpc:3;
+ uint32_t pmo_amod:1;
+ uint32_t b12_bist:1;
+ uint32_t ap_64ad:1;
+ uint32_t ap_pcix:1;
+ uint32_t reserved_14_14:1;
+ uint32_t en_wfilt:1;
+ uint32_t scm:1;
+ uint32_t scmtyp:1;
+ uint32_t bar2pres:1;
+ uint32_t erst_n:1;
+ uint32_t bb0:1;
+ uint32_t bb1:1;
+ uint32_t bb_es:2;
+ uint32_t bb_ca:1;
+ uint32_t bb1_siz:1;
+ uint32_t bb1_hole:3;
+ uint32_t reserved_29_31:3;
+#endif
+ } s;
+ struct cvmx_pci_ctl_status_2_s cn30xx;
+ struct cvmx_pci_ctl_status_2_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t erst_n:1;
+ uint32_t bar2pres:1;
+ uint32_t scmtyp:1;
+ uint32_t scm:1;
+ uint32_t en_wfilt:1;
+ uint32_t reserved_14_14:1;
+ uint32_t ap_pcix:1;
+ uint32_t ap_64ad:1;
+ uint32_t b12_bist:1;
+ uint32_t pmo_amod:1;
+ uint32_t pmo_fpc:3;
+ uint32_t tsr_hwm:3;
+ uint32_t bar2_enb:1;
+ uint32_t bar2_esx:2;
+ uint32_t bar2_cax:1;
+#else
+ uint32_t bar2_cax:1;
+ uint32_t bar2_esx:2;
+ uint32_t bar2_enb:1;
+ uint32_t tsr_hwm:3;
+ uint32_t pmo_fpc:3;
+ uint32_t pmo_amod:1;
+ uint32_t b12_bist:1;
+ uint32_t ap_64ad:1;
+ uint32_t ap_pcix:1;
+ uint32_t reserved_14_14:1;
+ uint32_t en_wfilt:1;
+ uint32_t scm:1;
+ uint32_t scmtyp:1;
+ uint32_t bar2pres:1;
+ uint32_t erst_n:1;
+ uint32_t reserved_20_31:12;
+#endif
+ } cn31xx;
+ struct cvmx_pci_ctl_status_2_s cn38xx;
+ struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
+ struct cvmx_pci_ctl_status_2_s cn50xx;
+ struct cvmx_pci_ctl_status_2_s cn58xx;
+ struct cvmx_pci_ctl_status_2_s cn58xxp1;
+} cvmx_pci_ctl_status_2_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_dbellx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t inc_val:16;
+#else
+ uint32_t inc_val:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_pci_dbellx_s cn30xx;
+ struct cvmx_pci_dbellx_s cn31xx;
+ struct cvmx_pci_dbellx_s cn38xx;
+ struct cvmx_pci_dbellx_s cn38xxp2;
+ struct cvmx_pci_dbellx_s cn50xx;
+ struct cvmx_pci_dbellx_s cn58xx;
+ struct cvmx_pci_dbellx_s cn58xxp1;
+} cvmx_pci_dbellx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_dma_cntx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dma_cnt:32;
+#else
+ uint32_t dma_cnt:32;
+#endif
+ } s;
+ struct cvmx_pci_dma_cntx_s cn30xx;
+ struct cvmx_pci_dma_cntx_s cn31xx;
+ struct cvmx_pci_dma_cntx_s cn38xx;
+ struct cvmx_pci_dma_cntx_s cn38xxp2;
+ struct cvmx_pci_dma_cntx_s cn50xx;
+ struct cvmx_pci_dma_cntx_s cn58xx;
+ struct cvmx_pci_dma_cntx_s cn58xxp1;
+} cvmx_pci_dma_cntx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_dma_int_levx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pkt_cnt:32;
+#else
+ uint32_t pkt_cnt:32;
+#endif
+ } s;
+ struct cvmx_pci_dma_int_levx_s cn30xx;
+ struct cvmx_pci_dma_int_levx_s cn31xx;
+ struct cvmx_pci_dma_int_levx_s cn38xx;
+ struct cvmx_pci_dma_int_levx_s cn38xxp2;
+ struct cvmx_pci_dma_int_levx_s cn50xx;
+ struct cvmx_pci_dma_int_levx_s cn58xx;
+ struct cvmx_pci_dma_int_levx_s cn58xxp1;
+} cvmx_pci_dma_int_levx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_dma_timex_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dma_time:32;
+#else
+ uint32_t dma_time:32;
+#endif
+ } s;
+ struct cvmx_pci_dma_timex_s cn30xx;
+ struct cvmx_pci_dma_timex_s cn31xx;
+ struct cvmx_pci_dma_timex_s cn38xx;
+ struct cvmx_pci_dma_timex_s cn38xxp2;
+ struct cvmx_pci_dma_timex_s cn50xx;
+ struct cvmx_pci_dma_timex_s cn58xx;
+ struct cvmx_pci_dma_timex_s cn58xxp1;
+} cvmx_pci_dma_timex_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_instr_countx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t icnt:32;
+#else
+ uint32_t icnt:32;
+#endif
+ } s;
+ struct cvmx_pci_instr_countx_s cn30xx;
+ struct cvmx_pci_instr_countx_s cn31xx;
+ struct cvmx_pci_instr_countx_s cn38xx;
+ struct cvmx_pci_instr_countx_s cn38xxp2;
+ struct cvmx_pci_instr_countx_s cn50xx;
+ struct cvmx_pci_instr_countx_s cn58xx;
+ struct cvmx_pci_instr_countx_s cn58xxp1;
+} cvmx_pci_instr_countx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t idtime1:1;
+ uint64_t idtime0:1;
+ uint64_t idcnt1:1;
+ uint64_t idcnt0:1;
+ uint64_t iptime3:1;
+ uint64_t iptime2:1;
+ uint64_t iptime1:1;
+ uint64_t iptime0:1;
+ uint64_t ipcnt3:1;
+ uint64_t ipcnt2:1;
+ uint64_t ipcnt1:1;
+ uint64_t ipcnt0:1;
+ uint64_t irsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t idperr:1;
+ uint64_t iaperr:1;
+ uint64_t iserr:1;
+ uint64_t itsr_abt:1;
+ uint64_t imsc_msg:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_per:1;
+ uint64_t imr_tto:1;
+ uint64_t imr_abt:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_wtto:1;
+ uint64_t imr_wabt:1;
+ uint64_t itr_wabt:1;
+#else
+ uint64_t itr_wabt:1;
+ uint64_t imr_wabt:1;
+ uint64_t imr_wtto:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_abt:1;
+ uint64_t imr_tto:1;
+ uint64_t imsi_per:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsc_msg:1;
+ uint64_t itsr_abt:1;
+ uint64_t iserr:1;
+ uint64_t iaperr:1;
+ uint64_t idperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t irsl_int:1;
+ uint64_t ipcnt0:1;
+ uint64_t ipcnt1:1;
+ uint64_t ipcnt2:1;
+ uint64_t ipcnt3:1;
+ uint64_t iptime0:1;
+ uint64_t iptime1:1;
+ uint64_t iptime2:1;
+ uint64_t iptime3:1;
+ uint64_t idcnt0:1;
+ uint64_t idcnt1:1;
+ uint64_t idtime0:1;
+ uint64_t idtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_pci_int_enb_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t idtime1:1;
+ uint64_t idtime0:1;
+ uint64_t idcnt1:1;
+ uint64_t idcnt0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t iptime0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t ipcnt0:1;
+ uint64_t irsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t idperr:1;
+ uint64_t iaperr:1;
+ uint64_t iserr:1;
+ uint64_t itsr_abt:1;
+ uint64_t imsc_msg:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_per:1;
+ uint64_t imr_tto:1;
+ uint64_t imr_abt:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_wtto:1;
+ uint64_t imr_wabt:1;
+ uint64_t itr_wabt:1;
+#else
+ uint64_t itr_wabt:1;
+ uint64_t imr_wabt:1;
+ uint64_t imr_wtto:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_abt:1;
+ uint64_t imr_tto:1;
+ uint64_t imsi_per:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsc_msg:1;
+ uint64_t itsr_abt:1;
+ uint64_t iserr:1;
+ uint64_t iaperr:1;
+ uint64_t idperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t irsl_int:1;
+ uint64_t ipcnt0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t iptime0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t idcnt0:1;
+ uint64_t idcnt1:1;
+ uint64_t idtime0:1;
+ uint64_t idtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn30xx;
+ struct cvmx_pci_int_enb_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t idtime1:1;
+ uint64_t idtime0:1;
+ uint64_t idcnt1:1;
+ uint64_t idcnt0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t iptime1:1;
+ uint64_t iptime0:1;
+ uint64_t reserved_19_20:2;
+ uint64_t ipcnt1:1;
+ uint64_t ipcnt0:1;
+ uint64_t irsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t idperr:1;
+ uint64_t iaperr:1;
+ uint64_t iserr:1;
+ uint64_t itsr_abt:1;
+ uint64_t imsc_msg:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_per:1;
+ uint64_t imr_tto:1;
+ uint64_t imr_abt:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_wtto:1;
+ uint64_t imr_wabt:1;
+ uint64_t itr_wabt:1;
+#else
+ uint64_t itr_wabt:1;
+ uint64_t imr_wabt:1;
+ uint64_t imr_wtto:1;
+ uint64_t itr_abt:1;
+ uint64_t imr_abt:1;
+ uint64_t imr_tto:1;
+ uint64_t imsi_per:1;
+ uint64_t imsi_tabt:1;
+ uint64_t imsi_mabt:1;
+ uint64_t imsc_msg:1;
+ uint64_t itsr_abt:1;
+ uint64_t iserr:1;
+ uint64_t iaperr:1;
+ uint64_t idperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t irsl_int:1;
+ uint64_t ipcnt0:1;
+ uint64_t ipcnt1:1;
+ uint64_t reserved_19_20:2;
+ uint64_t iptime0:1;
+ uint64_t iptime1:1;
+ uint64_t reserved_23_24:2;
+ uint64_t idcnt0:1;
+ uint64_t idcnt1:1;
+ uint64_t idtime0:1;
+ uint64_t idtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn31xx;
+ struct cvmx_pci_int_enb_s cn38xx;
+ struct cvmx_pci_int_enb_s cn38xxp2;
+ struct cvmx_pci_int_enb_cn31xx cn50xx;
+ struct cvmx_pci_int_enb_s cn58xx;
+ struct cvmx_pci_int_enb_s cn58xxp1;
+} cvmx_pci_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_int_enb2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t rdtime1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdcnt0:1;
+ uint64_t rptime3:1;
+ uint64_t rptime2:1;
+ uint64_t rptime1:1;
+ uint64_t rptime0:1;
+ uint64_t rpcnt3:1;
+ uint64_t rpcnt2:1;
+ uint64_t rpcnt1:1;
+ uint64_t rpcnt0:1;
+ uint64_t rrsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t rdperr:1;
+ uint64_t raperr:1;
+ uint64_t rserr:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmr_abt:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rtr_wabt:1;
+#else
+ uint64_t rtr_wabt:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_abt:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rserr:1;
+ uint64_t raperr:1;
+ uint64_t rdperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rrsl_int:1;
+ uint64_t rpcnt0:1;
+ uint64_t rpcnt1:1;
+ uint64_t rpcnt2:1;
+ uint64_t rpcnt3:1;
+ uint64_t rptime0:1;
+ uint64_t rptime1:1;
+ uint64_t rptime2:1;
+ uint64_t rptime3:1;
+ uint64_t rdcnt0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_pci_int_enb2_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t rdtime1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdcnt0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t rptime0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t rpcnt0:1;
+ uint64_t rrsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t rdperr:1;
+ uint64_t raperr:1;
+ uint64_t rserr:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmr_abt:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rtr_wabt:1;
+#else
+ uint64_t rtr_wabt:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_abt:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rserr:1;
+ uint64_t raperr:1;
+ uint64_t rdperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rrsl_int:1;
+ uint64_t rpcnt0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t rptime0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t rdcnt0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn30xx;
+ struct cvmx_pci_int_enb2_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t rdtime1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdcnt0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t rptime1:1;
+ uint64_t rptime0:1;
+ uint64_t reserved_19_20:2;
+ uint64_t rpcnt1:1;
+ uint64_t rpcnt0:1;
+ uint64_t rrsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t rdperr:1;
+ uint64_t raperr:1;
+ uint64_t rserr:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmr_abt:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rtr_wabt:1;
+#else
+ uint64_t rtr_wabt:1;
+ uint64_t rmr_wabt:1;
+ uint64_t rmr_wtto:1;
+ uint64_t rtr_abt:1;
+ uint64_t rmr_abt:1;
+ uint64_t rmr_tto:1;
+ uint64_t rmsi_per:1;
+ uint64_t rmsi_tabt:1;
+ uint64_t rmsi_mabt:1;
+ uint64_t rmsc_msg:1;
+ uint64_t rtsr_abt:1;
+ uint64_t rserr:1;
+ uint64_t raperr:1;
+ uint64_t rdperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rrsl_int:1;
+ uint64_t rpcnt0:1;
+ uint64_t rpcnt1:1;
+ uint64_t reserved_19_20:2;
+ uint64_t rptime0:1;
+ uint64_t rptime1:1;
+ uint64_t reserved_23_24:2;
+ uint64_t rdcnt0:1;
+ uint64_t rdcnt1:1;
+ uint64_t rdtime0:1;
+ uint64_t rdtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn31xx;
+ struct cvmx_pci_int_enb2_s cn38xx;
+ struct cvmx_pci_int_enb2_s cn38xxp2;
+ struct cvmx_pci_int_enb2_cn31xx cn50xx;
+ struct cvmx_pci_int_enb2_s cn58xx;
+ struct cvmx_pci_int_enb2_s cn58xxp1;
+} cvmx_pci_int_enb2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t ptime3:1;
+ uint64_t ptime2:1;
+ uint64_t ptime1:1;
+ uint64_t ptime0:1;
+ uint64_t pcnt3:1;
+ uint64_t pcnt2:1;
+ uint64_t pcnt1:1;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t pcnt1:1;
+ uint64_t pcnt2:1;
+ uint64_t pcnt3:1;
+ uint64_t ptime0:1;
+ uint64_t ptime1:1;
+ uint64_t ptime2:1;
+ uint64_t ptime3:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_pci_int_sum_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t ptime0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t ptime0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn30xx;
+ struct cvmx_pci_int_sum_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t ptime1:1;
+ uint64_t ptime0:1;
+ uint64_t reserved_19_20:2;
+ uint64_t pcnt1:1;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t pcnt1:1;
+ uint64_t reserved_19_20:2;
+ uint64_t ptime0:1;
+ uint64_t ptime1:1;
+ uint64_t reserved_23_24:2;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn31xx;
+ struct cvmx_pci_int_sum_s cn38xx;
+ struct cvmx_pci_int_sum_s cn38xxp2;
+ struct cvmx_pci_int_sum_cn31xx cn50xx;
+ struct cvmx_pci_int_sum_s cn58xx;
+ struct cvmx_pci_int_sum_s cn58xxp1;
+} cvmx_pci_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_int_sum2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t ptime3:1;
+ uint64_t ptime2:1;
+ uint64_t ptime1:1;
+ uint64_t ptime0:1;
+ uint64_t pcnt3:1;
+ uint64_t pcnt2:1;
+ uint64_t pcnt1:1;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t pcnt1:1;
+ uint64_t pcnt2:1;
+ uint64_t pcnt3:1;
+ uint64_t ptime0:1;
+ uint64_t ptime1:1;
+ uint64_t ptime2:1;
+ uint64_t ptime3:1;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } s;
+ struct cvmx_pci_int_sum2_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t ptime0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t reserved_18_20:3;
+ uint64_t ptime0:1;
+ uint64_t reserved_22_24:3;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn30xx;
+ struct cvmx_pci_int_sum2_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_34_63:30;
+ uint64_t ill_rd:1;
+ uint64_t ill_wr:1;
+ uint64_t win_wr:1;
+ uint64_t dma1_fi:1;
+ uint64_t dma0_fi:1;
+ uint64_t dtime1:1;
+ uint64_t dtime0:1;
+ uint64_t dcnt1:1;
+ uint64_t dcnt0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t ptime1:1;
+ uint64_t ptime0:1;
+ uint64_t reserved_19_20:2;
+ uint64_t pcnt1:1;
+ uint64_t pcnt0:1;
+ uint64_t rsl_int:1;
+ uint64_t ill_rrd:1;
+ uint64_t ill_rwr:1;
+ uint64_t dperr:1;
+ uint64_t aperr:1;
+ uint64_t serr:1;
+ uint64_t tsr_abt:1;
+ uint64_t msc_msg:1;
+ uint64_t msi_mabt:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_per:1;
+ uint64_t mr_tto:1;
+ uint64_t mr_abt:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_wtto:1;
+ uint64_t mr_wabt:1;
+ uint64_t tr_wabt:1;
+#else
+ uint64_t tr_wabt:1;
+ uint64_t mr_wabt:1;
+ uint64_t mr_wtto:1;
+ uint64_t tr_abt:1;
+ uint64_t mr_abt:1;
+ uint64_t mr_tto:1;
+ uint64_t msi_per:1;
+ uint64_t msi_tabt:1;
+ uint64_t msi_mabt:1;
+ uint64_t msc_msg:1;
+ uint64_t tsr_abt:1;
+ uint64_t serr:1;
+ uint64_t aperr:1;
+ uint64_t dperr:1;
+ uint64_t ill_rwr:1;
+ uint64_t ill_rrd:1;
+ uint64_t rsl_int:1;
+ uint64_t pcnt0:1;
+ uint64_t pcnt1:1;
+ uint64_t reserved_19_20:2;
+ uint64_t ptime0:1;
+ uint64_t ptime1:1;
+ uint64_t reserved_23_24:2;
+ uint64_t dcnt0:1;
+ uint64_t dcnt1:1;
+ uint64_t dtime0:1;
+ uint64_t dtime1:1;
+ uint64_t dma0_fi:1;
+ uint64_t dma1_fi:1;
+ uint64_t win_wr:1;
+ uint64_t ill_wr:1;
+ uint64_t ill_rd:1;
+ uint64_t reserved_34_63:30;
+#endif
+ } cn31xx;
+ struct cvmx_pci_int_sum2_s cn38xx;
+ struct cvmx_pci_int_sum2_s cn38xxp2;
+ struct cvmx_pci_int_sum2_cn31xx cn50xx;
+ struct cvmx_pci_int_sum2_s cn58xx;
+ struct cvmx_pci_int_sum2_s cn58xxp1;
+} cvmx_pci_int_sum2_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_msi_rcv_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_6_31:26;
+ uint32_t intr:6;
+#else
+ uint32_t intr:6;
+ uint32_t reserved_6_31:26;
+#endif
+ } s;
+ struct cvmx_pci_msi_rcv_s cn30xx;
+ struct cvmx_pci_msi_rcv_s cn31xx;
+ struct cvmx_pci_msi_rcv_s cn38xx;
+ struct cvmx_pci_msi_rcv_s cn38xxp2;
+ struct cvmx_pci_msi_rcv_s cn50xx;
+ struct cvmx_pci_msi_rcv_s cn58xx;
+ struct cvmx_pci_msi_rcv_s cn58xxp1;
+} cvmx_pci_msi_rcv_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_pkt_creditsx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pkt_cnt:16;
+ uint32_t ptr_cnt:16;
+#else
+ uint32_t ptr_cnt:16;
+ uint32_t pkt_cnt:16;
+#endif
+ } s;
+ struct cvmx_pci_pkt_creditsx_s cn30xx;
+ struct cvmx_pci_pkt_creditsx_s cn31xx;
+ struct cvmx_pci_pkt_creditsx_s cn38xx;
+ struct cvmx_pci_pkt_creditsx_s cn38xxp2;
+ struct cvmx_pci_pkt_creditsx_s cn50xx;
+ struct cvmx_pci_pkt_creditsx_s cn58xx;
+ struct cvmx_pci_pkt_creditsx_s cn58xxp1;
+} cvmx_pci_pkt_creditsx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_pkts_sentx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pkt_cnt:32;
+#else
+ uint32_t pkt_cnt:32;
+#endif
+ } s;
+ struct cvmx_pci_pkts_sentx_s cn30xx;
+ struct cvmx_pci_pkts_sentx_s cn31xx;
+ struct cvmx_pci_pkts_sentx_s cn38xx;
+ struct cvmx_pci_pkts_sentx_s cn38xxp2;
+ struct cvmx_pci_pkts_sentx_s cn50xx;
+ struct cvmx_pci_pkts_sentx_s cn58xx;
+ struct cvmx_pci_pkts_sentx_s cn58xxp1;
+} cvmx_pci_pkts_sentx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_pkts_sent_int_levx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pkt_cnt:32;
+#else
+ uint32_t pkt_cnt:32;
+#endif
+ } s;
+ struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
+ struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
+ struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
+ struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
+ struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
+ struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
+ struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
+} cvmx_pci_pkts_sent_int_levx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_pkts_sent_timex_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pkt_time:32;
+#else
+ uint32_t pkt_time:32;
+#endif
+ } s;
+ struct cvmx_pci_pkts_sent_timex_s cn30xx;
+ struct cvmx_pci_pkts_sent_timex_s cn31xx;
+ struct cvmx_pci_pkts_sent_timex_s cn38xx;
+ struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
+ struct cvmx_pci_pkts_sent_timex_s cn50xx;
+ struct cvmx_pci_pkts_sent_timex_s cn58xx;
+ struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
+} cvmx_pci_pkts_sent_timex_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_read_cmd_6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t min_data:6;
+ uint32_t prefetch:3;
+#else
+ uint32_t prefetch:3;
+ uint32_t min_data:6;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_pci_read_cmd_6_s cn30xx;
+ struct cvmx_pci_read_cmd_6_s cn31xx;
+ struct cvmx_pci_read_cmd_6_s cn38xx;
+ struct cvmx_pci_read_cmd_6_s cn38xxp2;
+ struct cvmx_pci_read_cmd_6_s cn50xx;
+ struct cvmx_pci_read_cmd_6_s cn58xx;
+ struct cvmx_pci_read_cmd_6_s cn58xxp1;
+} cvmx_pci_read_cmd_6_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_read_cmd_c_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t min_data:6;
+ uint32_t prefetch:3;
+#else
+ uint32_t prefetch:3;
+ uint32_t min_data:6;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_pci_read_cmd_c_s cn30xx;
+ struct cvmx_pci_read_cmd_c_s cn31xx;
+ struct cvmx_pci_read_cmd_c_s cn38xx;
+ struct cvmx_pci_read_cmd_c_s cn38xxp2;
+ struct cvmx_pci_read_cmd_c_s cn50xx;
+ struct cvmx_pci_read_cmd_c_s cn58xx;
+ struct cvmx_pci_read_cmd_c_s cn58xxp1;
+} cvmx_pci_read_cmd_c_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pci_read_cmd_e_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t min_data:6;
+ uint32_t prefetch:3;
+#else
+ uint32_t prefetch:3;
+ uint32_t min_data:6;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_pci_read_cmd_e_s cn30xx;
+ struct cvmx_pci_read_cmd_e_s cn31xx;
+ struct cvmx_pci_read_cmd_e_s cn38xx;
+ struct cvmx_pci_read_cmd_e_s cn38xxp2;
+ struct cvmx_pci_read_cmd_e_s cn50xx;
+ struct cvmx_pci_read_cmd_e_s cn58xx;
+ struct cvmx_pci_read_cmd_e_s cn58xxp1;
+} cvmx_pci_read_cmd_e_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_read_timeout_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t enb:1;
+ uint64_t cnt:31;
+#else
+ uint64_t cnt:31;
+ uint64_t enb:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pci_read_timeout_s cn30xx;
+ struct cvmx_pci_read_timeout_s cn31xx;
+ struct cvmx_pci_read_timeout_s cn38xx;
+ struct cvmx_pci_read_timeout_s cn38xxp2;
+ struct cvmx_pci_read_timeout_s cn50xx;
+ struct cvmx_pci_read_timeout_s cn58xx;
+ struct cvmx_pci_read_timeout_s cn58xxp1;
+} cvmx_pci_read_timeout_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_scm_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t scm:32;
+#else
+ uint64_t scm:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pci_scm_reg_s cn30xx;
+ struct cvmx_pci_scm_reg_s cn31xx;
+ struct cvmx_pci_scm_reg_s cn38xx;
+ struct cvmx_pci_scm_reg_s cn38xxp2;
+ struct cvmx_pci_scm_reg_s cn50xx;
+ struct cvmx_pci_scm_reg_s cn58xx;
+ struct cvmx_pci_scm_reg_s cn58xxp1;
+} cvmx_pci_scm_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_tsr_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t tsr:36;
+#else
+ uint64_t tsr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_pci_tsr_reg_s cn30xx;
+ struct cvmx_pci_tsr_reg_s cn31xx;
+ struct cvmx_pci_tsr_reg_s cn38xx;
+ struct cvmx_pci_tsr_reg_s cn38xxp2;
+ struct cvmx_pci_tsr_reg_s cn50xx;
+ struct cvmx_pci_tsr_reg_s cn58xx;
+ struct cvmx_pci_tsr_reg_s cn58xxp1;
+} cvmx_pci_tsr_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_win_rd_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t reserved_0_47:48;
+#else
+ uint64_t reserved_0_47:48;
+ uint64_t iobit:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_pci_win_rd_addr_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t rd_addr:46;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t rd_addr:46;
+ uint64_t iobit:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } cn30xx;
+ struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
+ struct cvmx_pci_win_rd_addr_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t rd_addr:45;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t rd_addr:45;
+ uint64_t iobit:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } cn38xx;
+ struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
+ struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
+ struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
+ struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
+} cvmx_pci_win_rd_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_win_rd_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t rd_data:64;
+#else
+ uint64_t rd_data:64;
+#endif
+ } s;
+ struct cvmx_pci_win_rd_data_s cn30xx;
+ struct cvmx_pci_win_rd_data_s cn31xx;
+ struct cvmx_pci_win_rd_data_s cn38xx;
+ struct cvmx_pci_win_rd_data_s cn38xxp2;
+ struct cvmx_pci_win_rd_data_s cn50xx;
+ struct cvmx_pci_win_rd_data_s cn58xx;
+ struct cvmx_pci_win_rd_data_s cn58xxp1;
+} cvmx_pci_win_rd_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_win_wr_addr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t wr_addr:45;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t wr_addr:45;
+ uint64_t iobit:1;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_pci_win_wr_addr_s cn30xx;
+ struct cvmx_pci_win_wr_addr_s cn31xx;
+ struct cvmx_pci_win_wr_addr_s cn38xx;
+ struct cvmx_pci_win_wr_addr_s cn38xxp2;
+ struct cvmx_pci_win_wr_addr_s cn50xx;
+ struct cvmx_pci_win_wr_addr_s cn58xx;
+ struct cvmx_pci_win_wr_addr_s cn58xxp1;
+} cvmx_pci_win_wr_addr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_win_wr_data_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t wr_data:64;
+#else
+ uint64_t wr_data:64;
+#endif
+ } s;
+ struct cvmx_pci_win_wr_data_s cn30xx;
+ struct cvmx_pci_win_wr_data_s cn31xx;
+ struct cvmx_pci_win_wr_data_s cn38xx;
+ struct cvmx_pci_win_wr_data_s cn38xxp2;
+ struct cvmx_pci_win_wr_data_s cn50xx;
+ struct cvmx_pci_win_wr_data_s cn58xx;
+ struct cvmx_pci_win_wr_data_s cn58xxp1;
+} cvmx_pci_win_wr_data_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pci_win_wr_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t wr_mask:8;
+#else
+ uint64_t wr_mask:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pci_win_wr_mask_s cn30xx;
+ struct cvmx_pci_win_wr_mask_s cn31xx;
+ struct cvmx_pci_win_wr_mask_s cn38xx;
+ struct cvmx_pci_win_wr_mask_s cn38xxp2;
+ struct cvmx_pci_win_wr_mask_s cn50xx;
+ struct cvmx_pci_win_wr_mask_s cn58xx;
+ struct cvmx_pci_win_wr_mask_s cn58xxp1;
+} cvmx_pci_win_wr_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg000_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t devid:16;
+ uint32_t vendid:16;
+#else
+ uint32_t vendid:16;
+ uint32_t devid:16;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg000_s cn52xx;
+ struct cvmx_pcieep_cfg000_s cn52xxp1;
+ struct cvmx_pcieep_cfg000_s cn56xx;
+ struct cvmx_pcieep_cfg000_s cn56xxp1;
+} cvmx_pcieep_cfg000_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg001_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dpe:1;
+ uint32_t sse:1;
+ uint32_t rma:1;
+ uint32_t rta:1;
+ uint32_t sta:1;
+ uint32_t devt:2;
+ uint32_t mdpe:1;
+ uint32_t fbb:1;
+ uint32_t reserved_22_22:1;
+ uint32_t m66:1;
+ uint32_t cl:1;
+ uint32_t i_stat:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_dis:1;
+ uint32_t fbbe:1;
+ uint32_t see:1;
+ uint32_t ids_wcc:1;
+ uint32_t per:1;
+ uint32_t vps:1;
+ uint32_t mwice:1;
+ uint32_t scse:1;
+ uint32_t me:1;
+ uint32_t msae:1;
+ uint32_t isae:1;
+#else
+ uint32_t isae:1;
+ uint32_t msae:1;
+ uint32_t me:1;
+ uint32_t scse:1;
+ uint32_t mwice:1;
+ uint32_t vps:1;
+ uint32_t per:1;
+ uint32_t ids_wcc:1;
+ uint32_t see:1;
+ uint32_t fbbe:1;
+ uint32_t i_dis:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_stat:1;
+ uint32_t cl:1;
+ uint32_t m66:1;
+ uint32_t reserved_22_22:1;
+ uint32_t fbb:1;
+ uint32_t mdpe:1;
+ uint32_t devt:2;
+ uint32_t sta:1;
+ uint32_t rta:1;
+ uint32_t rma:1;
+ uint32_t sse:1;
+ uint32_t dpe:1;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg001_s cn52xx;
+ struct cvmx_pcieep_cfg001_s cn52xxp1;
+ struct cvmx_pcieep_cfg001_s cn56xx;
+ struct cvmx_pcieep_cfg001_s cn56xxp1;
+} cvmx_pcieep_cfg001_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg002_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t bcc:8;
+ uint32_t sc:8;
+ uint32_t pi:8;
+ uint32_t rid:8;
+#else
+ uint32_t rid:8;
+ uint32_t pi:8;
+ uint32_t sc:8;
+ uint32_t bcc:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg002_s cn52xx;
+ struct cvmx_pcieep_cfg002_s cn52xxp1;
+ struct cvmx_pcieep_cfg002_s cn56xx;
+ struct cvmx_pcieep_cfg002_s cn56xxp1;
+} cvmx_pcieep_cfg002_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg003_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t bist:8;
+ uint32_t mfd:1;
+ uint32_t chf:7;
+ uint32_t lt:8;
+ uint32_t cls:8;
+#else
+ uint32_t cls:8;
+ uint32_t lt:8;
+ uint32_t chf:7;
+ uint32_t mfd:1;
+ uint32_t bist:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg003_s cn52xx;
+ struct cvmx_pcieep_cfg003_s cn52xxp1;
+ struct cvmx_pcieep_cfg003_s cn56xx;
+ struct cvmx_pcieep_cfg003_s cn56xxp1;
+} cvmx_pcieep_cfg003_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg004_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lbab:18;
+ uint32_t reserved_4_13:10;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t reserved_4_13:10;
+ uint32_t lbab:18;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg004_s cn52xx;
+ struct cvmx_pcieep_cfg004_s cn52xxp1;
+ struct cvmx_pcieep_cfg004_s cn56xx;
+ struct cvmx_pcieep_cfg004_s cn56xxp1;
+} cvmx_pcieep_cfg004_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg004_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmask:31;
+ uint32_t enb:1;
+#else
+ uint32_t enb:1;
+ uint32_t lmask:31;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg004_mask_s cn52xx;
+ struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg004_mask_s cn56xx;
+ struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
+} cvmx_pcieep_cfg004_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg005_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ubab:32;
+#else
+ uint32_t ubab:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg005_s cn52xx;
+ struct cvmx_pcieep_cfg005_s cn52xxp1;
+ struct cvmx_pcieep_cfg005_s cn56xx;
+ struct cvmx_pcieep_cfg005_s cn56xxp1;
+} cvmx_pcieep_cfg005_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg005_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umask:32;
+#else
+ uint32_t umask:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg005_mask_s cn52xx;
+ struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg005_mask_s cn56xx;
+ struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
+} cvmx_pcieep_cfg005_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg006_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lbab:6;
+ uint32_t reserved_4_25:22;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t reserved_4_25:22;
+ uint32_t lbab:6;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg006_s cn52xx;
+ struct cvmx_pcieep_cfg006_s cn52xxp1;
+ struct cvmx_pcieep_cfg006_s cn56xx;
+ struct cvmx_pcieep_cfg006_s cn56xxp1;
+} cvmx_pcieep_cfg006_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg006_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmask:31;
+ uint32_t enb:1;
+#else
+ uint32_t enb:1;
+ uint32_t lmask:31;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg006_mask_s cn52xx;
+ struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg006_mask_s cn56xx;
+ struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
+} cvmx_pcieep_cfg006_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg007_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ubab:32;
+#else
+ uint32_t ubab:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg007_s cn52xx;
+ struct cvmx_pcieep_cfg007_s cn52xxp1;
+ struct cvmx_pcieep_cfg007_s cn56xx;
+ struct cvmx_pcieep_cfg007_s cn56xxp1;
+} cvmx_pcieep_cfg007_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg007_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umask:32;
+#else
+ uint32_t umask:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg007_mask_s cn52xx;
+ struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg007_mask_s cn56xx;
+ struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
+} cvmx_pcieep_cfg007_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg008_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_4_31:28;
+ uint32_t pf:1;
+ uint32_t typ:2;
+ uint32_t mspc:1;
+#else
+ uint32_t mspc:1;
+ uint32_t typ:2;
+ uint32_t pf:1;
+ uint32_t reserved_4_31:28;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg008_s cn52xx;
+ struct cvmx_pcieep_cfg008_s cn52xxp1;
+ struct cvmx_pcieep_cfg008_s cn56xx;
+ struct cvmx_pcieep_cfg008_s cn56xxp1;
+} cvmx_pcieep_cfg008_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg008_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmask:31;
+ uint32_t enb:1;
+#else
+ uint32_t enb:1;
+ uint32_t lmask:31;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg008_mask_s cn52xx;
+ struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg008_mask_s cn56xx;
+ struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
+} cvmx_pcieep_cfg008_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg009_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ubab:25;
+ uint32_t reserved_0_6:7;
+#else
+ uint32_t reserved_0_6:7;
+ uint32_t ubab:25;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg009_s cn52xx;
+ struct cvmx_pcieep_cfg009_s cn52xxp1;
+ struct cvmx_pcieep_cfg009_s cn56xx;
+ struct cvmx_pcieep_cfg009_s cn56xxp1;
+} cvmx_pcieep_cfg009_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg009_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umask:32;
+#else
+ uint32_t umask:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg009_mask_s cn52xx;
+ struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg009_mask_s cn56xx;
+ struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
+} cvmx_pcieep_cfg009_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg010_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t cisp:32;
+#else
+ uint32_t cisp:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg010_s cn52xx;
+ struct cvmx_pcieep_cfg010_s cn52xxp1;
+ struct cvmx_pcieep_cfg010_s cn56xx;
+ struct cvmx_pcieep_cfg010_s cn56xxp1;
+} cvmx_pcieep_cfg010_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg011_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ssid:16;
+ uint32_t ssvid:16;
+#else
+ uint32_t ssvid:16;
+ uint32_t ssid:16;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg011_s cn52xx;
+ struct cvmx_pcieep_cfg011_s cn52xxp1;
+ struct cvmx_pcieep_cfg011_s cn56xx;
+ struct cvmx_pcieep_cfg011_s cn56xxp1;
+} cvmx_pcieep_cfg011_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg012_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t eraddr:16;
+ uint32_t reserved_1_15:15;
+ uint32_t er_en:1;
+#else
+ uint32_t er_en:1;
+ uint32_t reserved_1_15:15;
+ uint32_t eraddr:16;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg012_s cn52xx;
+ struct cvmx_pcieep_cfg012_s cn52xxp1;
+ struct cvmx_pcieep_cfg012_s cn56xx;
+ struct cvmx_pcieep_cfg012_s cn56xxp1;
+} cvmx_pcieep_cfg012_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg012_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t mask:31;
+ uint32_t enb:1;
+#else
+ uint32_t enb:1;
+ uint32_t mask:31;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg012_mask_s cn52xx;
+ struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
+ struct cvmx_pcieep_cfg012_mask_s cn56xx;
+ struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
+} cvmx_pcieep_cfg012_mask_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg013_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_8_31:24;
+ uint32_t cp:8;
+#else
+ uint32_t cp:8;
+ uint32_t reserved_8_31:24;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg013_s cn52xx;
+ struct cvmx_pcieep_cfg013_s cn52xxp1;
+ struct cvmx_pcieep_cfg013_s cn56xx;
+ struct cvmx_pcieep_cfg013_s cn56xxp1;
+} cvmx_pcieep_cfg013_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg015_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ml:8;
+ uint32_t mg:8;
+ uint32_t inta:8;
+ uint32_t il:8;
+#else
+ uint32_t il:8;
+ uint32_t inta:8;
+ uint32_t mg:8;
+ uint32_t ml:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg015_s cn52xx;
+ struct cvmx_pcieep_cfg015_s cn52xxp1;
+ struct cvmx_pcieep_cfg015_s cn56xx;
+ struct cvmx_pcieep_cfg015_s cn56xxp1;
+} cvmx_pcieep_cfg015_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg016_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmes:5;
+ uint32_t d2s:1;
+ uint32_t d1s:1;
+ uint32_t auxc:3;
+ uint32_t dsi:1;
+ uint32_t reserved_20_20:1;
+ uint32_t pme_clock:1;
+ uint32_t pmsv:3;
+ uint32_t ncp:8;
+ uint32_t pmcid:8;
+#else
+ uint32_t pmcid:8;
+ uint32_t ncp:8;
+ uint32_t pmsv:3;
+ uint32_t pme_clock:1;
+ uint32_t reserved_20_20:1;
+ uint32_t dsi:1;
+ uint32_t auxc:3;
+ uint32_t d1s:1;
+ uint32_t d2s:1;
+ uint32_t pmes:5;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg016_s cn52xx;
+ struct cvmx_pcieep_cfg016_s cn52xxp1;
+ struct cvmx_pcieep_cfg016_s cn56xx;
+ struct cvmx_pcieep_cfg016_s cn56xxp1;
+} cvmx_pcieep_cfg016_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg017_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmdia:8;
+ uint32_t bpccee:1;
+ uint32_t bd3h:1;
+ uint32_t reserved_16_21:6;
+ uint32_t pmess:1;
+ uint32_t pmedsia:2;
+ uint32_t pmds:4;
+ uint32_t pmeens:1;
+ uint32_t reserved_4_7:4;
+ uint32_t nsr:1;
+ uint32_t reserved_2_2:1;
+ uint32_t ps:2;
+#else
+ uint32_t ps:2;
+ uint32_t reserved_2_2:1;
+ uint32_t nsr:1;
+ uint32_t reserved_4_7:4;
+ uint32_t pmeens:1;
+ uint32_t pmds:4;
+ uint32_t pmedsia:2;
+ uint32_t pmess:1;
+ uint32_t reserved_16_21:6;
+ uint32_t bd3h:1;
+ uint32_t bpccee:1;
+ uint32_t pmdia:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg017_s cn52xx;
+ struct cvmx_pcieep_cfg017_s cn52xxp1;
+ struct cvmx_pcieep_cfg017_s cn56xx;
+ struct cvmx_pcieep_cfg017_s cn56xxp1;
+} cvmx_pcieep_cfg017_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg020_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t m64:1;
+ uint32_t mme:3;
+ uint32_t mmc:3;
+ uint32_t msien:1;
+ uint32_t ncp:8;
+ uint32_t msicid:8;
+#else
+ uint32_t msicid:8;
+ uint32_t ncp:8;
+ uint32_t msien:1;
+ uint32_t mmc:3;
+ uint32_t mme:3;
+ uint32_t m64:1;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg020_s cn52xx;
+ struct cvmx_pcieep_cfg020_s cn52xxp1;
+ struct cvmx_pcieep_cfg020_s cn56xx;
+ struct cvmx_pcieep_cfg020_s cn56xxp1;
+} cvmx_pcieep_cfg020_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg021_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmsi:30;
+ uint32_t reserved_0_1:2;
+#else
+ uint32_t reserved_0_1:2;
+ uint32_t lmsi:30;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg021_s cn52xx;
+ struct cvmx_pcieep_cfg021_s cn52xxp1;
+ struct cvmx_pcieep_cfg021_s cn56xx;
+ struct cvmx_pcieep_cfg021_s cn56xxp1;
+} cvmx_pcieep_cfg021_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg022_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umsi:32;
+#else
+ uint32_t umsi:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg022_s cn52xx;
+ struct cvmx_pcieep_cfg022_s cn52xxp1;
+ struct cvmx_pcieep_cfg022_s cn56xx;
+ struct cvmx_pcieep_cfg022_s cn56xxp1;
+} cvmx_pcieep_cfg022_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg023_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t msimd:16;
+#else
+ uint32_t msimd:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg023_s cn52xx;
+ struct cvmx_pcieep_cfg023_s cn52xxp1;
+ struct cvmx_pcieep_cfg023_s cn56xx;
+ struct cvmx_pcieep_cfg023_s cn56xxp1;
+} cvmx_pcieep_cfg023_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg028_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t imn:5;
+ uint32_t si:1;
+ uint32_t dpt:4;
+ uint32_t pciecv:4;
+ uint32_t ncp:8;
+ uint32_t pcieid:8;
+#else
+ uint32_t pcieid:8;
+ uint32_t ncp:8;
+ uint32_t pciecv:4;
+ uint32_t dpt:4;
+ uint32_t si:1;
+ uint32_t imn:5;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg028_s cn52xx;
+ struct cvmx_pcieep_cfg028_s cn52xxp1;
+ struct cvmx_pcieep_cfg028_s cn56xx;
+ struct cvmx_pcieep_cfg028_s cn56xxp1;
+} cvmx_pcieep_cfg028_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg029_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_28_31:4;
+ uint32_t cspls:2;
+ uint32_t csplv:8;
+ uint32_t reserved_16_17:2;
+ uint32_t rber:1;
+ uint32_t reserved_12_14:3;
+ uint32_t el1al:3;
+ uint32_t el0al:3;
+ uint32_t etfs:1;
+ uint32_t pfs:2;
+ uint32_t mpss:3;
+#else
+ uint32_t mpss:3;
+ uint32_t pfs:2;
+ uint32_t etfs:1;
+ uint32_t el0al:3;
+ uint32_t el1al:3;
+ uint32_t reserved_12_14:3;
+ uint32_t rber:1;
+ uint32_t reserved_16_17:2;
+ uint32_t csplv:8;
+ uint32_t cspls:2;
+ uint32_t reserved_28_31:4;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg029_s cn52xx;
+ struct cvmx_pcieep_cfg029_s cn52xxp1;
+ struct cvmx_pcieep_cfg029_s cn56xx;
+ struct cvmx_pcieep_cfg029_s cn56xxp1;
+} cvmx_pcieep_cfg029_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg030_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_22_31:10;
+ uint32_t tp:1;
+ uint32_t ap_d:1;
+ uint32_t ur_d:1;
+ uint32_t fe_d:1;
+ uint32_t nfe_d:1;
+ uint32_t ce_d:1;
+ uint32_t reserved_15_15:1;
+ uint32_t mrrs:3;
+ uint32_t ns_en:1;
+ uint32_t ap_en:1;
+ uint32_t pf_en:1;
+ uint32_t etf_en:1;
+ uint32_t mps:3;
+ uint32_t ro_en:1;
+ uint32_t ur_en:1;
+ uint32_t fe_en:1;
+ uint32_t nfe_en:1;
+ uint32_t ce_en:1;
+#else
+ uint32_t ce_en:1;
+ uint32_t nfe_en:1;
+ uint32_t fe_en:1;
+ uint32_t ur_en:1;
+ uint32_t ro_en:1;
+ uint32_t mps:3;
+ uint32_t etf_en:1;
+ uint32_t pf_en:1;
+ uint32_t ap_en:1;
+ uint32_t ns_en:1;
+ uint32_t mrrs:3;
+ uint32_t reserved_15_15:1;
+ uint32_t ce_d:1;
+ uint32_t nfe_d:1;
+ uint32_t fe_d:1;
+ uint32_t ur_d:1;
+ uint32_t ap_d:1;
+ uint32_t tp:1;
+ uint32_t reserved_22_31:10;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg030_s cn52xx;
+ struct cvmx_pcieep_cfg030_s cn52xxp1;
+ struct cvmx_pcieep_cfg030_s cn56xx;
+ struct cvmx_pcieep_cfg030_s cn56xxp1;
+} cvmx_pcieep_cfg030_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg031_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pnum:8;
+ uint32_t reserved_22_23:2;
+ uint32_t lbnc:1;
+ uint32_t dllarc:1;
+ uint32_t sderc:1;
+ uint32_t cpm:1;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t aslpms:2;
+ uint32_t mlw:6;
+ uint32_t mls:4;
+#else
+ uint32_t mls:4;
+ uint32_t mlw:6;
+ uint32_t aslpms:2;
+ uint32_t l0el:3;
+ uint32_t l1el:3;
+ uint32_t cpm:1;
+ uint32_t sderc:1;
+ uint32_t dllarc:1;
+ uint32_t lbnc:1;
+ uint32_t reserved_22_23:2;
+ uint32_t pnum:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg031_s cn52xx;
+ struct cvmx_pcieep_cfg031_s cn52xxp1;
+ struct cvmx_pcieep_cfg031_s cn56xx;
+ struct cvmx_pcieep_cfg031_s cn56xxp1;
+} cvmx_pcieep_cfg031_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg032_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t dlla:1;
+ uint32_t scc:1;
+ uint32_t lt:1;
+ uint32_t reserved_26_26:1;
+ uint32_t nlw:6;
+ uint32_t ls:4;
+ uint32_t reserved_10_15:6;
+ uint32_t hawd:1;
+ uint32_t ecpm:1;
+ uint32_t es:1;
+ uint32_t ccc:1;
+ uint32_t rl:1;
+ uint32_t ld:1;
+ uint32_t rcb:1;
+ uint32_t reserved_2_2:1;
+ uint32_t aslpc:2;
+#else
+ uint32_t aslpc:2;
+ uint32_t reserved_2_2:1;
+ uint32_t rcb:1;
+ uint32_t ld:1;
+ uint32_t rl:1;
+ uint32_t ccc:1;
+ uint32_t es:1;
+ uint32_t ecpm:1;
+ uint32_t hawd:1;
+ uint32_t reserved_10_15:6;
+ uint32_t ls:4;
+ uint32_t nlw:6;
+ uint32_t reserved_26_26:1;
+ uint32_t lt:1;
+ uint32_t scc:1;
+ uint32_t dlla:1;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg032_s cn52xx;
+ struct cvmx_pcieep_cfg032_s cn52xxp1;
+ struct cvmx_pcieep_cfg032_s cn56xx;
+ struct cvmx_pcieep_cfg032_s cn56xxp1;
+} cvmx_pcieep_cfg032_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg033_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ps_num:13;
+ uint32_t nccs:1;
+ uint32_t emip:1;
+ uint32_t sp_ls:2;
+ uint32_t sp_lv:8;
+ uint32_t hp_c:1;
+ uint32_t hp_s:1;
+ uint32_t pip:1;
+ uint32_t aip:1;
+ uint32_t mrlsp:1;
+ uint32_t pcp:1;
+ uint32_t abp:1;
+#else
+ uint32_t abp:1;
+ uint32_t pcp:1;
+ uint32_t mrlsp:1;
+ uint32_t aip:1;
+ uint32_t pip:1;
+ uint32_t hp_s:1;
+ uint32_t hp_c:1;
+ uint32_t sp_lv:8;
+ uint32_t sp_ls:2;
+ uint32_t emip:1;
+ uint32_t nccs:1;
+ uint32_t ps_num:13;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg033_s cn52xx;
+ struct cvmx_pcieep_cfg033_s cn52xxp1;
+ struct cvmx_pcieep_cfg033_s cn56xx;
+ struct cvmx_pcieep_cfg033_s cn56xxp1;
+} cvmx_pcieep_cfg033_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg034_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_25_31:7;
+ uint32_t dlls_c:1;
+ uint32_t emis:1;
+ uint32_t pds:1;
+ uint32_t mrlss:1;
+ uint32_t ccint_d:1;
+ uint32_t pd_c:1;
+ uint32_t mrls_c:1;
+ uint32_t pf_d:1;
+ uint32_t abp_d:1;
+ uint32_t reserved_13_15:3;
+ uint32_t dlls_en:1;
+ uint32_t emic:1;
+ uint32_t pcc:1;
+ uint32_t pic:2;
+ uint32_t aic:2;
+ uint32_t hpint_en:1;
+ uint32_t ccint_en:1;
+ uint32_t pd_en:1;
+ uint32_t mrls_en:1;
+ uint32_t pf_en:1;
+ uint32_t abp_en:1;
+#else
+ uint32_t abp_en:1;
+ uint32_t pf_en:1;
+ uint32_t mrls_en:1;
+ uint32_t pd_en:1;
+ uint32_t ccint_en:1;
+ uint32_t hpint_en:1;
+ uint32_t aic:2;
+ uint32_t pic:2;
+ uint32_t pcc:1;
+ uint32_t emic:1;
+ uint32_t dlls_en:1;
+ uint32_t reserved_13_15:3;
+ uint32_t abp_d:1;
+ uint32_t pf_d:1;
+ uint32_t mrls_c:1;
+ uint32_t pd_c:1;
+ uint32_t ccint_d:1;
+ uint32_t mrlss:1;
+ uint32_t pds:1;
+ uint32_t emis:1;
+ uint32_t dlls_c:1;
+ uint32_t reserved_25_31:7;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg034_s cn52xx;
+ struct cvmx_pcieep_cfg034_s cn52xxp1;
+ struct cvmx_pcieep_cfg034_s cn56xx;
+ struct cvmx_pcieep_cfg034_s cn56xxp1;
+} cvmx_pcieep_cfg034_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg037_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t ctds:1;
+ uint32_t ctrs:4;
+#else
+ uint32_t ctrs:4;
+ uint32_t ctds:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg037_s cn52xx;
+ struct cvmx_pcieep_cfg037_s cn52xxp1;
+ struct cvmx_pcieep_cfg037_s cn56xx;
+ struct cvmx_pcieep_cfg037_s cn56xxp1;
+} cvmx_pcieep_cfg037_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg038_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t ctd:1;
+ uint32_t ctv:4;
+#else
+ uint32_t ctv:4;
+ uint32_t ctd:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg038_s cn52xx;
+ struct cvmx_pcieep_cfg038_s cn52xxp1;
+ struct cvmx_pcieep_cfg038_s cn56xx;
+ struct cvmx_pcieep_cfg038_s cn56xxp1;
+} cvmx_pcieep_cfg038_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg039_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg039_s cn52xx;
+ struct cvmx_pcieep_cfg039_s cn52xxp1;
+ struct cvmx_pcieep_cfg039_s cn56xx;
+ struct cvmx_pcieep_cfg039_s cn56xxp1;
+} cvmx_pcieep_cfg039_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg040_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg040_s cn52xx;
+ struct cvmx_pcieep_cfg040_s cn52xxp1;
+ struct cvmx_pcieep_cfg040_s cn56xx;
+ struct cvmx_pcieep_cfg040_s cn56xxp1;
+} cvmx_pcieep_cfg040_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg041_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg041_s cn52xx;
+ struct cvmx_pcieep_cfg041_s cn52xxp1;
+ struct cvmx_pcieep_cfg041_s cn56xx;
+ struct cvmx_pcieep_cfg041_s cn56xxp1;
+} cvmx_pcieep_cfg041_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg042_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg042_s cn52xx;
+ struct cvmx_pcieep_cfg042_s cn52xxp1;
+ struct cvmx_pcieep_cfg042_s cn56xx;
+ struct cvmx_pcieep_cfg042_s cn56xxp1;
+} cvmx_pcieep_cfg042_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg064_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t nco:12;
+ uint32_t cv:4;
+ uint32_t pcieec:16;
+#else
+ uint32_t pcieec:16;
+ uint32_t cv:4;
+ uint32_t nco:12;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg064_s cn52xx;
+ struct cvmx_pcieep_cfg064_s cn52xxp1;
+ struct cvmx_pcieep_cfg064_s cn56xx;
+ struct cvmx_pcieep_cfg064_s cn56xxp1;
+} cvmx_pcieep_cfg064_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg065_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpes:1;
+ uint32_t sdes:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlps:1;
+ uint32_t fcpes:1;
+ uint32_t cts:1;
+ uint32_t cas:1;
+ uint32_t ucs:1;
+ uint32_t ros:1;
+ uint32_t mtlps:1;
+ uint32_t ecrces:1;
+ uint32_t ures:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg065_s cn52xx;
+ struct cvmx_pcieep_cfg065_s cn52xxp1;
+ struct cvmx_pcieep_cfg065_s cn56xx;
+ struct cvmx_pcieep_cfg065_s cn56xxp1;
+} cvmx_pcieep_cfg065_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg066_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t urem:1;
+ uint32_t ecrcem:1;
+ uint32_t mtlpm:1;
+ uint32_t rom:1;
+ uint32_t ucm:1;
+ uint32_t cam:1;
+ uint32_t ctm:1;
+ uint32_t fcpem:1;
+ uint32_t ptlpm:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdem:1;
+ uint32_t dlpem:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpem:1;
+ uint32_t sdem:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlpm:1;
+ uint32_t fcpem:1;
+ uint32_t ctm:1;
+ uint32_t cam:1;
+ uint32_t ucm:1;
+ uint32_t rom:1;
+ uint32_t mtlpm:1;
+ uint32_t ecrcem:1;
+ uint32_t urem:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg066_s cn52xx;
+ struct cvmx_pcieep_cfg066_s cn52xxp1;
+ struct cvmx_pcieep_cfg066_s cn56xx;
+ struct cvmx_pcieep_cfg066_s cn56xxp1;
+} cvmx_pcieep_cfg066_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg067_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpes:1;
+ uint32_t sdes:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlps:1;
+ uint32_t fcpes:1;
+ uint32_t cts:1;
+ uint32_t cas:1;
+ uint32_t ucs:1;
+ uint32_t ros:1;
+ uint32_t mtlps:1;
+ uint32_t ecrces:1;
+ uint32_t ures:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg067_s cn52xx;
+ struct cvmx_pcieep_cfg067_s cn52xxp1;
+ struct cvmx_pcieep_cfg067_s cn56xx;
+ struct cvmx_pcieep_cfg067_s cn56xxp1;
+} cvmx_pcieep_cfg067_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg068_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_14_31:18;
+ uint32_t anfes:1;
+ uint32_t rtts:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rnrs:1;
+ uint32_t bdllps:1;
+ uint32_t btlps:1;
+ uint32_t reserved_1_5:5;
+ uint32_t res:1;
+#else
+ uint32_t res:1;
+ uint32_t reserved_1_5:5;
+ uint32_t btlps:1;
+ uint32_t bdllps:1;
+ uint32_t rnrs:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rtts:1;
+ uint32_t anfes:1;
+ uint32_t reserved_14_31:18;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg068_s cn52xx;
+ struct cvmx_pcieep_cfg068_s cn52xxp1;
+ struct cvmx_pcieep_cfg068_s cn56xx;
+ struct cvmx_pcieep_cfg068_s cn56xxp1;
+} cvmx_pcieep_cfg068_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg069_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_14_31:18;
+ uint32_t anfem:1;
+ uint32_t rttm:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rnrm:1;
+ uint32_t bdllpm:1;
+ uint32_t btlpm:1;
+ uint32_t reserved_1_5:5;
+ uint32_t rem:1;
+#else
+ uint32_t rem:1;
+ uint32_t reserved_1_5:5;
+ uint32_t btlpm:1;
+ uint32_t bdllpm:1;
+ uint32_t rnrm:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rttm:1;
+ uint32_t anfem:1;
+ uint32_t reserved_14_31:18;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg069_s cn52xx;
+ struct cvmx_pcieep_cfg069_s cn52xxp1;
+ struct cvmx_pcieep_cfg069_s cn56xx;
+ struct cvmx_pcieep_cfg069_s cn56xxp1;
+} cvmx_pcieep_cfg069_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg070_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t ce:1;
+ uint32_t cc:1;
+ uint32_t ge:1;
+ uint32_t gc:1;
+ uint32_t fep:5;
+#else
+ uint32_t fep:5;
+ uint32_t gc:1;
+ uint32_t ge:1;
+ uint32_t cc:1;
+ uint32_t ce:1;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg070_s cn52xx;
+ struct cvmx_pcieep_cfg070_s cn52xxp1;
+ struct cvmx_pcieep_cfg070_s cn56xx;
+ struct cvmx_pcieep_cfg070_s cn56xxp1;
+} cvmx_pcieep_cfg070_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg071_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword1:32;
+#else
+ uint32_t dword1:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg071_s cn52xx;
+ struct cvmx_pcieep_cfg071_s cn52xxp1;
+ struct cvmx_pcieep_cfg071_s cn56xx;
+ struct cvmx_pcieep_cfg071_s cn56xxp1;
+} cvmx_pcieep_cfg071_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg072_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword2:32;
+#else
+ uint32_t dword2:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg072_s cn52xx;
+ struct cvmx_pcieep_cfg072_s cn52xxp1;
+ struct cvmx_pcieep_cfg072_s cn56xx;
+ struct cvmx_pcieep_cfg072_s cn56xxp1;
+} cvmx_pcieep_cfg072_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg073_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword3:32;
+#else
+ uint32_t dword3:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg073_s cn52xx;
+ struct cvmx_pcieep_cfg073_s cn52xxp1;
+ struct cvmx_pcieep_cfg073_s cn56xx;
+ struct cvmx_pcieep_cfg073_s cn56xxp1;
+} cvmx_pcieep_cfg073_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg074_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword4:32;
+#else
+ uint32_t dword4:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg074_s cn52xx;
+ struct cvmx_pcieep_cfg074_s cn52xxp1;
+ struct cvmx_pcieep_cfg074_s cn56xx;
+ struct cvmx_pcieep_cfg074_s cn56xxp1;
+} cvmx_pcieep_cfg074_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg448_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t rtl:16;
+ uint32_t rtltl:16;
+#else
+ uint32_t rtltl:16;
+ uint32_t rtl:16;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg448_s cn52xx;
+ struct cvmx_pcieep_cfg448_s cn52xxp1;
+ struct cvmx_pcieep_cfg448_s cn56xx;
+ struct cvmx_pcieep_cfg448_s cn56xxp1;
+} cvmx_pcieep_cfg448_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg449_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t omr:32;
+#else
+ uint32_t omr:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg449_s cn52xx;
+ struct cvmx_pcieep_cfg449_s cn52xxp1;
+ struct cvmx_pcieep_cfg449_s cn56xx;
+ struct cvmx_pcieep_cfg449_s cn56xxp1;
+} cvmx_pcieep_cfg449_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg450_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lpec:8;
+ uint32_t reserved_22_23:2;
+ uint32_t link_state:6;
+ uint32_t force_link:1;
+ uint32_t reserved_8_14:7;
+ uint32_t link_num:8;
+#else
+ uint32_t link_num:8;
+ uint32_t reserved_8_14:7;
+ uint32_t force_link:1;
+ uint32_t link_state:6;
+ uint32_t reserved_22_23:2;
+ uint32_t lpec:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg450_s cn52xx;
+ struct cvmx_pcieep_cfg450_s cn52xxp1;
+ struct cvmx_pcieep_cfg450_s cn56xx;
+ struct cvmx_pcieep_cfg450_s cn56xxp1;
+} cvmx_pcieep_cfg450_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg451_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t n_fts_cc:8;
+ uint32_t n_fts:8;
+ uint32_t ack_freq:8;
+#else
+ uint32_t ack_freq:8;
+ uint32_t n_fts:8;
+ uint32_t n_fts_cc:8;
+ uint32_t l0el:3;
+ uint32_t l1el:3;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg451_s cn52xx;
+ struct cvmx_pcieep_cfg451_s cn52xxp1;
+ struct cvmx_pcieep_cfg451_s cn56xx;
+ struct cvmx_pcieep_cfg451_s cn56xxp1;
+} cvmx_pcieep_cfg451_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg452_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t eccrc:1;
+ uint32_t reserved_22_24:3;
+ uint32_t lme:6;
+ uint32_t reserved_8_15:8;
+ uint32_t flm:1;
+ uint32_t reserved_6_6:1;
+ uint32_t dllle:1;
+ uint32_t reserved_4_4:1;
+ uint32_t ra:1;
+ uint32_t le:1;
+ uint32_t sd:1;
+ uint32_t omr:1;
+#else
+ uint32_t omr:1;
+ uint32_t sd:1;
+ uint32_t le:1;
+ uint32_t ra:1;
+ uint32_t reserved_4_4:1;
+ uint32_t dllle:1;
+ uint32_t reserved_6_6:1;
+ uint32_t flm:1;
+ uint32_t reserved_8_15:8;
+ uint32_t lme:6;
+ uint32_t reserved_22_24:3;
+ uint32_t eccrc:1;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg452_s cn52xx;
+ struct cvmx_pcieep_cfg452_s cn52xxp1;
+ struct cvmx_pcieep_cfg452_s cn56xx;
+ struct cvmx_pcieep_cfg452_s cn56xxp1;
+} cvmx_pcieep_cfg452_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg453_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dlld:1;
+ uint32_t reserved_26_30:5;
+ uint32_t ack_nak:1;
+ uint32_t fcd:1;
+ uint32_t ilst:24;
+#else
+ uint32_t ilst:24;
+ uint32_t fcd:1;
+ uint32_t ack_nak:1;
+ uint32_t reserved_26_30:5;
+ uint32_t dlld:1;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg453_s cn52xx;
+ struct cvmx_pcieep_cfg453_s cn52xxp1;
+ struct cvmx_pcieep_cfg453_s cn56xx;
+ struct cvmx_pcieep_cfg453_s cn56xxp1;
+} cvmx_pcieep_cfg453_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg454_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_29_31:3;
+ uint32_t tmfcwt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmrt:5;
+ uint32_t reserved_11_13:3;
+ uint32_t nskps:3;
+ uint32_t reserved_4_7:4;
+ uint32_t ntss:4;
+#else
+ uint32_t ntss:4;
+ uint32_t reserved_4_7:4;
+ uint32_t nskps:3;
+ uint32_t reserved_11_13:3;
+ uint32_t tmrt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmfcwt:5;
+ uint32_t reserved_29_31:3;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg454_s cn52xx;
+ struct cvmx_pcieep_cfg454_s cn52xxp1;
+ struct cvmx_pcieep_cfg454_s cn56xx;
+ struct cvmx_pcieep_cfg454_s cn56xxp1;
+} cvmx_pcieep_cfg454_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg455_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t m_cfg0_filt:1;
+ uint32_t m_io_filt:1;
+ uint32_t msg_ctrl:1;
+ uint32_t m_cpl_ecrc_filt:1;
+ uint32_t m_ecrc_filt:1;
+ uint32_t m_cpl_len_err:1;
+ uint32_t m_cpl_attr_err:1;
+ uint32_t m_cpl_tc_err:1;
+ uint32_t m_cpl_fun_err:1;
+ uint32_t m_cpl_rid_err:1;
+ uint32_t m_cpl_tag_err:1;
+ uint32_t m_lk_filt:1;
+ uint32_t m_cfg1_filt:1;
+ uint32_t m_bar_match:1;
+ uint32_t m_pois_filt:1;
+ uint32_t m_fun:1;
+ uint32_t dfcwt:1;
+ uint32_t reserved_11_14:4;
+ uint32_t skpiv:11;
+#else
+ uint32_t skpiv:11;
+ uint32_t reserved_11_14:4;
+ uint32_t dfcwt:1;
+ uint32_t m_fun:1;
+ uint32_t m_pois_filt:1;
+ uint32_t m_bar_match:1;
+ uint32_t m_cfg1_filt:1;
+ uint32_t m_lk_filt:1;
+ uint32_t m_cpl_tag_err:1;
+ uint32_t m_cpl_rid_err:1;
+ uint32_t m_cpl_fun_err:1;
+ uint32_t m_cpl_tc_err:1;
+ uint32_t m_cpl_attr_err:1;
+ uint32_t m_cpl_len_err:1;
+ uint32_t m_ecrc_filt:1;
+ uint32_t m_cpl_ecrc_filt:1;
+ uint32_t msg_ctrl:1;
+ uint32_t m_io_filt:1;
+ uint32_t m_cfg0_filt:1;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg455_s cn52xx;
+ struct cvmx_pcieep_cfg455_s cn52xxp1;
+ struct cvmx_pcieep_cfg455_s cn56xx;
+ struct cvmx_pcieep_cfg455_s cn56xxp1;
+} cvmx_pcieep_cfg455_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg456_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_2_31:30;
+ uint32_t m_vend1_drp:1;
+ uint32_t m_vend0_drp:1;
+#else
+ uint32_t m_vend0_drp:1;
+ uint32_t m_vend1_drp:1;
+ uint32_t reserved_2_31:30;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg456_s cn52xx;
+ struct cvmx_pcieep_cfg456_s cn52xxp1;
+ struct cvmx_pcieep_cfg456_s cn56xx;
+ struct cvmx_pcieep_cfg456_s cn56xxp1;
+} cvmx_pcieep_cfg456_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg458_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dbg_info_l32:32;
+#else
+ uint32_t dbg_info_l32:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg458_s cn52xx;
+ struct cvmx_pcieep_cfg458_s cn52xxp1;
+ struct cvmx_pcieep_cfg458_s cn56xx;
+ struct cvmx_pcieep_cfg458_s cn56xxp1;
+} cvmx_pcieep_cfg458_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg459_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dbg_info_u32:32;
+#else
+ uint32_t dbg_info_u32:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg459_s cn52xx;
+ struct cvmx_pcieep_cfg459_s cn52xxp1;
+ struct cvmx_pcieep_cfg459_s cn56xx;
+ struct cvmx_pcieep_cfg459_s cn56xxp1;
+} cvmx_pcieep_cfg459_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg460_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tphfcc:8;
+ uint32_t tpdfcc:12;
+#else
+ uint32_t tpdfcc:12;
+ uint32_t tphfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg460_s cn52xx;
+ struct cvmx_pcieep_cfg460_s cn52xxp1;
+ struct cvmx_pcieep_cfg460_s cn56xx;
+ struct cvmx_pcieep_cfg460_s cn56xxp1;
+} cvmx_pcieep_cfg460_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg461_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tchfcc:8;
+ uint32_t tcdfcc:12;
+#else
+ uint32_t tcdfcc:12;
+ uint32_t tchfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg461_s cn52xx;
+ struct cvmx_pcieep_cfg461_s cn52xxp1;
+ struct cvmx_pcieep_cfg461_s cn56xx;
+ struct cvmx_pcieep_cfg461_s cn56xxp1;
+} cvmx_pcieep_cfg461_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg462_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tchfcc:8;
+ uint32_t tcdfcc:12;
+#else
+ uint32_t tcdfcc:12;
+ uint32_t tchfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg462_s cn52xx;
+ struct cvmx_pcieep_cfg462_s cn52xxp1;
+ struct cvmx_pcieep_cfg462_s cn56xx;
+ struct cvmx_pcieep_cfg462_s cn56xxp1;
+} cvmx_pcieep_cfg462_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg463_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_3_31:29;
+ uint32_t rqne:1;
+ uint32_t trbne:1;
+ uint32_t rtlpfccnr:1;
+#else
+ uint32_t rtlpfccnr:1;
+ uint32_t trbne:1;
+ uint32_t rqne:1;
+ uint32_t reserved_3_31:29;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg463_s cn52xx;
+ struct cvmx_pcieep_cfg463_s cn52xxp1;
+ struct cvmx_pcieep_cfg463_s cn56xx;
+ struct cvmx_pcieep_cfg463_s cn56xxp1;
+} cvmx_pcieep_cfg463_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg464_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wrr_vc3:8;
+ uint32_t wrr_vc2:8;
+ uint32_t wrr_vc1:8;
+ uint32_t wrr_vc0:8;
+#else
+ uint32_t wrr_vc0:8;
+ uint32_t wrr_vc1:8;
+ uint32_t wrr_vc2:8;
+ uint32_t wrr_vc3:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg464_s cn52xx;
+ struct cvmx_pcieep_cfg464_s cn52xxp1;
+ struct cvmx_pcieep_cfg464_s cn56xx;
+ struct cvmx_pcieep_cfg464_s cn56xxp1;
+} cvmx_pcieep_cfg464_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg465_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wrr_vc7:8;
+ uint32_t wrr_vc6:8;
+ uint32_t wrr_vc5:8;
+ uint32_t wrr_vc4:8;
+#else
+ uint32_t wrr_vc4:8;
+ uint32_t wrr_vc5:8;
+ uint32_t wrr_vc6:8;
+ uint32_t wrr_vc7:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg465_s cn52xx;
+ struct cvmx_pcieep_cfg465_s cn52xxp1;
+ struct cvmx_pcieep_cfg465_s cn56xx;
+ struct cvmx_pcieep_cfg465_s cn56xxp1;
+} cvmx_pcieep_cfg465_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg466_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t rx_queue_order:1;
+ uint32_t type_ordering:1;
+ uint32_t reserved_24_29:6;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_29:6;
+ uint32_t type_ordering:1;
+ uint32_t rx_queue_order:1;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg466_s cn52xx;
+ struct cvmx_pcieep_cfg466_s cn52xxp1;
+ struct cvmx_pcieep_cfg466_s cn56xx;
+ struct cvmx_pcieep_cfg466_s cn56xxp1;
+} cvmx_pcieep_cfg466_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg467_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg467_s cn52xx;
+ struct cvmx_pcieep_cfg467_s cn52xxp1;
+ struct cvmx_pcieep_cfg467_s cn56xx;
+ struct cvmx_pcieep_cfg467_s cn56xxp1;
+} cvmx_pcieep_cfg467_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg468_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg468_s cn52xx;
+ struct cvmx_pcieep_cfg468_s cn52xxp1;
+ struct cvmx_pcieep_cfg468_s cn56xx;
+ struct cvmx_pcieep_cfg468_s cn56xxp1;
+} cvmx_pcieep_cfg468_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg490_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg490_s cn52xx;
+ struct cvmx_pcieep_cfg490_s cn52xxp1;
+ struct cvmx_pcieep_cfg490_s cn56xx;
+ struct cvmx_pcieep_cfg490_s cn56xxp1;
+} cvmx_pcieep_cfg490_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg491_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg491_s cn52xx;
+ struct cvmx_pcieep_cfg491_s cn52xxp1;
+ struct cvmx_pcieep_cfg491_s cn56xx;
+ struct cvmx_pcieep_cfg491_s cn56xxp1;
+} cvmx_pcieep_cfg491_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg492_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg492_s cn52xx;
+ struct cvmx_pcieep_cfg492_s cn52xxp1;
+ struct cvmx_pcieep_cfg492_s cn56xx;
+ struct cvmx_pcieep_cfg492_s cn56xxp1;
+} cvmx_pcieep_cfg492_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg516_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t phy_stat:32;
+#else
+ uint32_t phy_stat:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg516_s cn52xx;
+ struct cvmx_pcieep_cfg516_s cn52xxp1;
+ struct cvmx_pcieep_cfg516_s cn56xx;
+ struct cvmx_pcieep_cfg516_s cn56xxp1;
+} cvmx_pcieep_cfg516_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pcieep_cfg517_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t phy_ctrl:32;
+#else
+ uint32_t phy_ctrl:32;
+#endif
+ } s;
+ struct cvmx_pcieep_cfg517_s cn52xx;
+ struct cvmx_pcieep_cfg517_s cn52xxp1;
+ struct cvmx_pcieep_cfg517_s cn56xx;
+ struct cvmx_pcieep_cfg517_s cn56xxp1;
+} cvmx_pcieep_cfg517_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg000_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t devid:16;
+ uint32_t vendid:16;
+#else
+ uint32_t vendid:16;
+ uint32_t devid:16;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg000_s cn52xx;
+ struct cvmx_pciercx_cfg000_s cn52xxp1;
+ struct cvmx_pciercx_cfg000_s cn56xx;
+ struct cvmx_pciercx_cfg000_s cn56xxp1;
+} cvmx_pciercx_cfg000_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg001_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dpe:1;
+ uint32_t sse:1;
+ uint32_t rma:1;
+ uint32_t rta:1;
+ uint32_t sta:1;
+ uint32_t devt:2;
+ uint32_t mdpe:1;
+ uint32_t fbb:1;
+ uint32_t reserved_22_22:1;
+ uint32_t m66:1;
+ uint32_t cl:1;
+ uint32_t i_stat:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_dis:1;
+ uint32_t fbbe:1;
+ uint32_t see:1;
+ uint32_t ids_wcc:1;
+ uint32_t per:1;
+ uint32_t vps:1;
+ uint32_t mwice:1;
+ uint32_t scse:1;
+ uint32_t me:1;
+ uint32_t msae:1;
+ uint32_t isae:1;
+#else
+ uint32_t isae:1;
+ uint32_t msae:1;
+ uint32_t me:1;
+ uint32_t scse:1;
+ uint32_t mwice:1;
+ uint32_t vps:1;
+ uint32_t per:1;
+ uint32_t ids_wcc:1;
+ uint32_t see:1;
+ uint32_t fbbe:1;
+ uint32_t i_dis:1;
+ uint32_t reserved_11_18:8;
+ uint32_t i_stat:1;
+ uint32_t cl:1;
+ uint32_t m66:1;
+ uint32_t reserved_22_22:1;
+ uint32_t fbb:1;
+ uint32_t mdpe:1;
+ uint32_t devt:2;
+ uint32_t sta:1;
+ uint32_t rta:1;
+ uint32_t rma:1;
+ uint32_t sse:1;
+ uint32_t dpe:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg001_s cn52xx;
+ struct cvmx_pciercx_cfg001_s cn52xxp1;
+ struct cvmx_pciercx_cfg001_s cn56xx;
+ struct cvmx_pciercx_cfg001_s cn56xxp1;
+} cvmx_pciercx_cfg001_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg002_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t bcc:8;
+ uint32_t sc:8;
+ uint32_t pi:8;
+ uint32_t rid:8;
+#else
+ uint32_t rid:8;
+ uint32_t pi:8;
+ uint32_t sc:8;
+ uint32_t bcc:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg002_s cn52xx;
+ struct cvmx_pciercx_cfg002_s cn52xxp1;
+ struct cvmx_pciercx_cfg002_s cn56xx;
+ struct cvmx_pciercx_cfg002_s cn56xxp1;
+} cvmx_pciercx_cfg002_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg003_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t bist:8;
+ uint32_t mfd:1;
+ uint32_t chf:7;
+ uint32_t lt:8;
+ uint32_t cls:8;
+#else
+ uint32_t cls:8;
+ uint32_t lt:8;
+ uint32_t chf:7;
+ uint32_t mfd:1;
+ uint32_t bist:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg003_s cn52xx;
+ struct cvmx_pciercx_cfg003_s cn52xxp1;
+ struct cvmx_pciercx_cfg003_s cn56xx;
+ struct cvmx_pciercx_cfg003_s cn56xxp1;
+} cvmx_pciercx_cfg003_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg004_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg004_s cn52xx;
+ struct cvmx_pciercx_cfg004_s cn52xxp1;
+ struct cvmx_pciercx_cfg004_s cn56xx;
+ struct cvmx_pciercx_cfg004_s cn56xxp1;
+} cvmx_pciercx_cfg004_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg005_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg005_s cn52xx;
+ struct cvmx_pciercx_cfg005_s cn52xxp1;
+ struct cvmx_pciercx_cfg005_s cn56xx;
+ struct cvmx_pciercx_cfg005_s cn56xxp1;
+} cvmx_pciercx_cfg005_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg006_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t slt:8;
+ uint32_t subbnum:8;
+ uint32_t sbnum:8;
+ uint32_t pbnum:8;
+#else
+ uint32_t pbnum:8;
+ uint32_t sbnum:8;
+ uint32_t subbnum:8;
+ uint32_t slt:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg006_s cn52xx;
+ struct cvmx_pciercx_cfg006_s cn52xxp1;
+ struct cvmx_pciercx_cfg006_s cn56xx;
+ struct cvmx_pciercx_cfg006_s cn56xxp1;
+} cvmx_pciercx_cfg006_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg007_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dpe:1;
+ uint32_t sse:1;
+ uint32_t rma:1;
+ uint32_t rta:1;
+ uint32_t sta:1;
+ uint32_t devt:2;
+ uint32_t mdpe:1;
+ uint32_t fbb:1;
+ uint32_t reserved_22_22:1;
+ uint32_t m66:1;
+ uint32_t reserved_16_20:5;
+ uint32_t lio_limi:4;
+ uint32_t reserved_9_11:3;
+ uint32_t io32b:1;
+ uint32_t lio_base:4;
+ uint32_t reserved_1_3:3;
+ uint32_t io32a:1;
+#else
+ uint32_t io32a:1;
+ uint32_t reserved_1_3:3;
+ uint32_t lio_base:4;
+ uint32_t io32b:1;
+ uint32_t reserved_9_11:3;
+ uint32_t lio_limi:4;
+ uint32_t reserved_16_20:5;
+ uint32_t m66:1;
+ uint32_t reserved_22_22:1;
+ uint32_t fbb:1;
+ uint32_t mdpe:1;
+ uint32_t devt:2;
+ uint32_t sta:1;
+ uint32_t rta:1;
+ uint32_t rma:1;
+ uint32_t sse:1;
+ uint32_t dpe:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg007_s cn52xx;
+ struct cvmx_pciercx_cfg007_s cn52xxp1;
+ struct cvmx_pciercx_cfg007_s cn56xx;
+ struct cvmx_pciercx_cfg007_s cn56xxp1;
+} cvmx_pciercx_cfg007_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg008_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ml_addr:12;
+ uint32_t reserved_16_19:4;
+ uint32_t mb_addr:12;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t mb_addr:12;
+ uint32_t reserved_16_19:4;
+ uint32_t ml_addr:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg008_s cn52xx;
+ struct cvmx_pciercx_cfg008_s cn52xxp1;
+ struct cvmx_pciercx_cfg008_s cn56xx;
+ struct cvmx_pciercx_cfg008_s cn56xxp1;
+} cvmx_pciercx_cfg008_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg009_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmem_limit:12;
+ uint32_t reserved_17_19:3;
+ uint32_t mem64b:1;
+ uint32_t lmem_base:12;
+ uint32_t reserved_1_3:3;
+ uint32_t mem64a:1;
+#else
+ uint32_t mem64a:1;
+ uint32_t reserved_1_3:3;
+ uint32_t lmem_base:12;
+ uint32_t mem64b:1;
+ uint32_t reserved_17_19:3;
+ uint32_t lmem_limit:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg009_s cn52xx;
+ struct cvmx_pciercx_cfg009_s cn52xxp1;
+ struct cvmx_pciercx_cfg009_s cn56xx;
+ struct cvmx_pciercx_cfg009_s cn56xxp1;
+} cvmx_pciercx_cfg009_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg010_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umem_base:32;
+#else
+ uint32_t umem_base:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg010_s cn52xx;
+ struct cvmx_pciercx_cfg010_s cn52xxp1;
+ struct cvmx_pciercx_cfg010_s cn56xx;
+ struct cvmx_pciercx_cfg010_s cn56xxp1;
+} cvmx_pciercx_cfg010_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg011_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umem_limit:32;
+#else
+ uint32_t umem_limit:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg011_s cn52xx;
+ struct cvmx_pciercx_cfg011_s cn52xxp1;
+ struct cvmx_pciercx_cfg011_s cn56xx;
+ struct cvmx_pciercx_cfg011_s cn56xxp1;
+} cvmx_pciercx_cfg011_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg012_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t uio_limit:16;
+ uint32_t uio_base:16;
+#else
+ uint32_t uio_base:16;
+ uint32_t uio_limit:16;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg012_s cn52xx;
+ struct cvmx_pciercx_cfg012_s cn52xxp1;
+ struct cvmx_pciercx_cfg012_s cn56xx;
+ struct cvmx_pciercx_cfg012_s cn56xxp1;
+} cvmx_pciercx_cfg012_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg013_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_8_31:24;
+ uint32_t cp:8;
+#else
+ uint32_t cp:8;
+ uint32_t reserved_8_31:24;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg013_s cn52xx;
+ struct cvmx_pciercx_cfg013_s cn52xxp1;
+ struct cvmx_pciercx_cfg013_s cn56xx;
+ struct cvmx_pciercx_cfg013_s cn56xxp1;
+} cvmx_pciercx_cfg013_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg014_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg014_s cn52xx;
+ struct cvmx_pciercx_cfg014_s cn52xxp1;
+ struct cvmx_pciercx_cfg014_s cn56xx;
+ struct cvmx_pciercx_cfg014_s cn56xxp1;
+} cvmx_pciercx_cfg014_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg015_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_28_31:4;
+ uint32_t dtsees:1;
+ uint32_t dts:1;
+ uint32_t sdt:1;
+ uint32_t pdt:1;
+ uint32_t fbbe:1;
+ uint32_t sbrst:1;
+ uint32_t mam:1;
+ uint32_t vga16d:1;
+ uint32_t vgae:1;
+ uint32_t isae:1;
+ uint32_t see:1;
+ uint32_t pere:1;
+ uint32_t inta:8;
+ uint32_t il:8;
+#else
+ uint32_t il:8;
+ uint32_t inta:8;
+ uint32_t pere:1;
+ uint32_t see:1;
+ uint32_t isae:1;
+ uint32_t vgae:1;
+ uint32_t vga16d:1;
+ uint32_t mam:1;
+ uint32_t sbrst:1;
+ uint32_t fbbe:1;
+ uint32_t pdt:1;
+ uint32_t sdt:1;
+ uint32_t dts:1;
+ uint32_t dtsees:1;
+ uint32_t reserved_28_31:4;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg015_s cn52xx;
+ struct cvmx_pciercx_cfg015_s cn52xxp1;
+ struct cvmx_pciercx_cfg015_s cn56xx;
+ struct cvmx_pciercx_cfg015_s cn56xxp1;
+} cvmx_pciercx_cfg015_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg016_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmes:5;
+ uint32_t d2s:1;
+ uint32_t d1s:1;
+ uint32_t auxc:3;
+ uint32_t dsi:1;
+ uint32_t reserved_20_20:1;
+ uint32_t pme_clock:1;
+ uint32_t pmsv:3;
+ uint32_t ncp:8;
+ uint32_t pmcid:8;
+#else
+ uint32_t pmcid:8;
+ uint32_t ncp:8;
+ uint32_t pmsv:3;
+ uint32_t pme_clock:1;
+ uint32_t reserved_20_20:1;
+ uint32_t dsi:1;
+ uint32_t auxc:3;
+ uint32_t d1s:1;
+ uint32_t d2s:1;
+ uint32_t pmes:5;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg016_s cn52xx;
+ struct cvmx_pciercx_cfg016_s cn52xxp1;
+ struct cvmx_pciercx_cfg016_s cn56xx;
+ struct cvmx_pciercx_cfg016_s cn56xxp1;
+} cvmx_pciercx_cfg016_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg017_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pmdia:8;
+ uint32_t bpccee:1;
+ uint32_t bd3h:1;
+ uint32_t reserved_16_21:6;
+ uint32_t pmess:1;
+ uint32_t pmedsia:2;
+ uint32_t pmds:4;
+ uint32_t pmeens:1;
+ uint32_t reserved_4_7:4;
+ uint32_t nsr:1;
+ uint32_t reserved_2_2:1;
+ uint32_t ps:2;
+#else
+ uint32_t ps:2;
+ uint32_t reserved_2_2:1;
+ uint32_t nsr:1;
+ uint32_t reserved_4_7:4;
+ uint32_t pmeens:1;
+ uint32_t pmds:4;
+ uint32_t pmedsia:2;
+ uint32_t pmess:1;
+ uint32_t reserved_16_21:6;
+ uint32_t bd3h:1;
+ uint32_t bpccee:1;
+ uint32_t pmdia:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg017_s cn52xx;
+ struct cvmx_pciercx_cfg017_s cn52xxp1;
+ struct cvmx_pciercx_cfg017_s cn56xx;
+ struct cvmx_pciercx_cfg017_s cn56xxp1;
+} cvmx_pciercx_cfg017_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg020_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t m64:1;
+ uint32_t mme:3;
+ uint32_t mmc:3;
+ uint32_t msien:1;
+ uint32_t ncp:8;
+ uint32_t msicid:8;
+#else
+ uint32_t msicid:8;
+ uint32_t ncp:8;
+ uint32_t msien:1;
+ uint32_t mmc:3;
+ uint32_t mme:3;
+ uint32_t m64:1;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg020_s cn52xx;
+ struct cvmx_pciercx_cfg020_s cn52xxp1;
+ struct cvmx_pciercx_cfg020_s cn56xx;
+ struct cvmx_pciercx_cfg020_s cn56xxp1;
+} cvmx_pciercx_cfg020_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg021_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lmsi:30;
+ uint32_t reserved_0_1:2;
+#else
+ uint32_t reserved_0_1:2;
+ uint32_t lmsi:30;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg021_s cn52xx;
+ struct cvmx_pciercx_cfg021_s cn52xxp1;
+ struct cvmx_pciercx_cfg021_s cn56xx;
+ struct cvmx_pciercx_cfg021_s cn56xxp1;
+} cvmx_pciercx_cfg021_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg022_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t umsi:32;
+#else
+ uint32_t umsi:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg022_s cn52xx;
+ struct cvmx_pciercx_cfg022_s cn52xxp1;
+ struct cvmx_pciercx_cfg022_s cn56xx;
+ struct cvmx_pciercx_cfg022_s cn56xxp1;
+} cvmx_pciercx_cfg022_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg023_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t msimd:16;
+#else
+ uint32_t msimd:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg023_s cn52xx;
+ struct cvmx_pciercx_cfg023_s cn52xxp1;
+ struct cvmx_pciercx_cfg023_s cn56xx;
+ struct cvmx_pciercx_cfg023_s cn56xxp1;
+} cvmx_pciercx_cfg023_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg028_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t imn:5;
+ uint32_t si:1;
+ uint32_t dpt:4;
+ uint32_t pciecv:4;
+ uint32_t ncp:8;
+ uint32_t pcieid:8;
+#else
+ uint32_t pcieid:8;
+ uint32_t ncp:8;
+ uint32_t pciecv:4;
+ uint32_t dpt:4;
+ uint32_t si:1;
+ uint32_t imn:5;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg028_s cn52xx;
+ struct cvmx_pciercx_cfg028_s cn52xxp1;
+ struct cvmx_pciercx_cfg028_s cn56xx;
+ struct cvmx_pciercx_cfg028_s cn56xxp1;
+} cvmx_pciercx_cfg028_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg029_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_28_31:4;
+ uint32_t cspls:2;
+ uint32_t csplv:8;
+ uint32_t reserved_16_17:2;
+ uint32_t rber:1;
+ uint32_t reserved_12_14:3;
+ uint32_t el1al:3;
+ uint32_t el0al:3;
+ uint32_t etfs:1;
+ uint32_t pfs:2;
+ uint32_t mpss:3;
+#else
+ uint32_t mpss:3;
+ uint32_t pfs:2;
+ uint32_t etfs:1;
+ uint32_t el0al:3;
+ uint32_t el1al:3;
+ uint32_t reserved_12_14:3;
+ uint32_t rber:1;
+ uint32_t reserved_16_17:2;
+ uint32_t csplv:8;
+ uint32_t cspls:2;
+ uint32_t reserved_28_31:4;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg029_s cn52xx;
+ struct cvmx_pciercx_cfg029_s cn52xxp1;
+ struct cvmx_pciercx_cfg029_s cn56xx;
+ struct cvmx_pciercx_cfg029_s cn56xxp1;
+} cvmx_pciercx_cfg029_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg030_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_22_31:10;
+ uint32_t tp:1;
+ uint32_t ap_d:1;
+ uint32_t ur_d:1;
+ uint32_t fe_d:1;
+ uint32_t nfe_d:1;
+ uint32_t ce_d:1;
+ uint32_t reserved_15_15:1;
+ uint32_t mrrs:3;
+ uint32_t ns_en:1;
+ uint32_t ap_en:1;
+ uint32_t pf_en:1;
+ uint32_t etf_en:1;
+ uint32_t mps:3;
+ uint32_t ro_en:1;
+ uint32_t ur_en:1;
+ uint32_t fe_en:1;
+ uint32_t nfe_en:1;
+ uint32_t ce_en:1;
+#else
+ uint32_t ce_en:1;
+ uint32_t nfe_en:1;
+ uint32_t fe_en:1;
+ uint32_t ur_en:1;
+ uint32_t ro_en:1;
+ uint32_t mps:3;
+ uint32_t etf_en:1;
+ uint32_t pf_en:1;
+ uint32_t ap_en:1;
+ uint32_t ns_en:1;
+ uint32_t mrrs:3;
+ uint32_t reserved_15_15:1;
+ uint32_t ce_d:1;
+ uint32_t nfe_d:1;
+ uint32_t fe_d:1;
+ uint32_t ur_d:1;
+ uint32_t ap_d:1;
+ uint32_t tp:1;
+ uint32_t reserved_22_31:10;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg030_s cn52xx;
+ struct cvmx_pciercx_cfg030_s cn52xxp1;
+ struct cvmx_pciercx_cfg030_s cn56xx;
+ struct cvmx_pciercx_cfg030_s cn56xxp1;
+} cvmx_pciercx_cfg030_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg031_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t pnum:8;
+ uint32_t reserved_22_23:2;
+ uint32_t lbnc:1;
+ uint32_t dllarc:1;
+ uint32_t sderc:1;
+ uint32_t cpm:1;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t aslpms:2;
+ uint32_t mlw:6;
+ uint32_t mls:4;
+#else
+ uint32_t mls:4;
+ uint32_t mlw:6;
+ uint32_t aslpms:2;
+ uint32_t l0el:3;
+ uint32_t l1el:3;
+ uint32_t cpm:1;
+ uint32_t sderc:1;
+ uint32_t dllarc:1;
+ uint32_t lbnc:1;
+ uint32_t reserved_22_23:2;
+ uint32_t pnum:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg031_s cn52xx;
+ struct cvmx_pciercx_cfg031_s cn52xxp1;
+ struct cvmx_pciercx_cfg031_s cn56xx;
+ struct cvmx_pciercx_cfg031_s cn56xxp1;
+} cvmx_pciercx_cfg031_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg032_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lab:1;
+ uint32_t lbm:1;
+ uint32_t dlla:1;
+ uint32_t scc:1;
+ uint32_t lt:1;
+ uint32_t reserved_26_26:1;
+ uint32_t nlw:6;
+ uint32_t ls:4;
+ uint32_t reserved_12_15:4;
+ uint32_t lab_int_enb:1;
+ uint32_t lbm_int_enb:1;
+ uint32_t hawd:1;
+ uint32_t ecpm:1;
+ uint32_t es:1;
+ uint32_t ccc:1;
+ uint32_t rl:1;
+ uint32_t ld:1;
+ uint32_t rcb:1;
+ uint32_t reserved_2_2:1;
+ uint32_t aslpc:2;
+#else
+ uint32_t aslpc:2;
+ uint32_t reserved_2_2:1;
+ uint32_t rcb:1;
+ uint32_t ld:1;
+ uint32_t rl:1;
+ uint32_t ccc:1;
+ uint32_t es:1;
+ uint32_t ecpm:1;
+ uint32_t hawd:1;
+ uint32_t lbm_int_enb:1;
+ uint32_t lab_int_enb:1;
+ uint32_t reserved_12_15:4;
+ uint32_t ls:4;
+ uint32_t nlw:6;
+ uint32_t reserved_26_26:1;
+ uint32_t lt:1;
+ uint32_t scc:1;
+ uint32_t dlla:1;
+ uint32_t lbm:1;
+ uint32_t lab:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg032_s cn52xx;
+ struct cvmx_pciercx_cfg032_s cn52xxp1;
+ struct cvmx_pciercx_cfg032_s cn56xx;
+ struct cvmx_pciercx_cfg032_s cn56xxp1;
+} cvmx_pciercx_cfg032_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg033_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ps_num:13;
+ uint32_t nccs:1;
+ uint32_t emip:1;
+ uint32_t sp_ls:2;
+ uint32_t sp_lv:8;
+ uint32_t hp_c:1;
+ uint32_t hp_s:1;
+ uint32_t pip:1;
+ uint32_t aip:1;
+ uint32_t mrlsp:1;
+ uint32_t pcp:1;
+ uint32_t abp:1;
+#else
+ uint32_t abp:1;
+ uint32_t pcp:1;
+ uint32_t mrlsp:1;
+ uint32_t aip:1;
+ uint32_t pip:1;
+ uint32_t hp_s:1;
+ uint32_t hp_c:1;
+ uint32_t sp_lv:8;
+ uint32_t sp_ls:2;
+ uint32_t emip:1;
+ uint32_t nccs:1;
+ uint32_t ps_num:13;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg033_s cn52xx;
+ struct cvmx_pciercx_cfg033_s cn52xxp1;
+ struct cvmx_pciercx_cfg033_s cn56xx;
+ struct cvmx_pciercx_cfg033_s cn56xxp1;
+} cvmx_pciercx_cfg033_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg034_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_25_31:7;
+ uint32_t dlls_c:1;
+ uint32_t emis:1;
+ uint32_t pds:1;
+ uint32_t mrlss:1;
+ uint32_t ccint_d:1;
+ uint32_t pd_c:1;
+ uint32_t mrls_c:1;
+ uint32_t pf_d:1;
+ uint32_t abp_d:1;
+ uint32_t reserved_13_15:3;
+ uint32_t dlls_en:1;
+ uint32_t emic:1;
+ uint32_t pcc:1;
+ uint32_t pic:2;
+ uint32_t aic:2;
+ uint32_t hpint_en:1;
+ uint32_t ccint_en:1;
+ uint32_t pd_en:1;
+ uint32_t mrls_en:1;
+ uint32_t pf_en:1;
+ uint32_t abp_en:1;
+#else
+ uint32_t abp_en:1;
+ uint32_t pf_en:1;
+ uint32_t mrls_en:1;
+ uint32_t pd_en:1;
+ uint32_t ccint_en:1;
+ uint32_t hpint_en:1;
+ uint32_t aic:2;
+ uint32_t pic:2;
+ uint32_t pcc:1;
+ uint32_t emic:1;
+ uint32_t dlls_en:1;
+ uint32_t reserved_13_15:3;
+ uint32_t abp_d:1;
+ uint32_t pf_d:1;
+ uint32_t mrls_c:1;
+ uint32_t pd_c:1;
+ uint32_t ccint_d:1;
+ uint32_t mrlss:1;
+ uint32_t pds:1;
+ uint32_t emis:1;
+ uint32_t dlls_c:1;
+ uint32_t reserved_25_31:7;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg034_s cn52xx;
+ struct cvmx_pciercx_cfg034_s cn52xxp1;
+ struct cvmx_pciercx_cfg034_s cn56xx;
+ struct cvmx_pciercx_cfg034_s cn56xxp1;
+} cvmx_pciercx_cfg034_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg035_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_17_31:15;
+ uint32_t crssv:1;
+ uint32_t reserved_5_15:11;
+ uint32_t crssve:1;
+ uint32_t pmeie:1;
+ uint32_t sefee:1;
+ uint32_t senfee:1;
+ uint32_t secee:1;
+#else
+ uint32_t secee:1;
+ uint32_t senfee:1;
+ uint32_t sefee:1;
+ uint32_t pmeie:1;
+ uint32_t crssve:1;
+ uint32_t reserved_5_15:11;
+ uint32_t crssv:1;
+ uint32_t reserved_17_31:15;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg035_s cn52xx;
+ struct cvmx_pciercx_cfg035_s cn52xxp1;
+ struct cvmx_pciercx_cfg035_s cn56xx;
+ struct cvmx_pciercx_cfg035_s cn56xxp1;
+} cvmx_pciercx_cfg035_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg036_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_18_31:14;
+ uint32_t pme_pend:1;
+ uint32_t pme_stat:1;
+ uint32_t pme_rid:16;
+#else
+ uint32_t pme_rid:16;
+ uint32_t pme_stat:1;
+ uint32_t pme_pend:1;
+ uint32_t reserved_18_31:14;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg036_s cn52xx;
+ struct cvmx_pciercx_cfg036_s cn52xxp1;
+ struct cvmx_pciercx_cfg036_s cn56xx;
+ struct cvmx_pciercx_cfg036_s cn56xxp1;
+} cvmx_pciercx_cfg036_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg037_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t ctds:1;
+ uint32_t ctrs:4;
+#else
+ uint32_t ctrs:4;
+ uint32_t ctds:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg037_s cn52xx;
+ struct cvmx_pciercx_cfg037_s cn52xxp1;
+ struct cvmx_pciercx_cfg037_s cn56xx;
+ struct cvmx_pciercx_cfg037_s cn56xxp1;
+} cvmx_pciercx_cfg037_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg038_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t ctd:1;
+ uint32_t ctv:4;
+#else
+ uint32_t ctv:4;
+ uint32_t ctd:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg038_s cn52xx;
+ struct cvmx_pciercx_cfg038_s cn52xxp1;
+ struct cvmx_pciercx_cfg038_s cn56xx;
+ struct cvmx_pciercx_cfg038_s cn56xxp1;
+} cvmx_pciercx_cfg038_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg039_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg039_s cn52xx;
+ struct cvmx_pciercx_cfg039_s cn52xxp1;
+ struct cvmx_pciercx_cfg039_s cn56xx;
+ struct cvmx_pciercx_cfg039_s cn56xxp1;
+} cvmx_pciercx_cfg039_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg040_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg040_s cn52xx;
+ struct cvmx_pciercx_cfg040_s cn52xxp1;
+ struct cvmx_pciercx_cfg040_s cn56xx;
+ struct cvmx_pciercx_cfg040_s cn56xxp1;
+} cvmx_pciercx_cfg040_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg041_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg041_s cn52xx;
+ struct cvmx_pciercx_cfg041_s cn52xxp1;
+ struct cvmx_pciercx_cfg041_s cn56xx;
+ struct cvmx_pciercx_cfg041_s cn56xxp1;
+} cvmx_pciercx_cfg041_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg042_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_0_31:32;
+#else
+ uint32_t reserved_0_31:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg042_s cn52xx;
+ struct cvmx_pciercx_cfg042_s cn52xxp1;
+ struct cvmx_pciercx_cfg042_s cn56xx;
+ struct cvmx_pciercx_cfg042_s cn56xxp1;
+} cvmx_pciercx_cfg042_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg064_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t nco:12;
+ uint32_t cv:4;
+ uint32_t pcieec:16;
+#else
+ uint32_t pcieec:16;
+ uint32_t cv:4;
+ uint32_t nco:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg064_s cn52xx;
+ struct cvmx_pciercx_cfg064_s cn52xxp1;
+ struct cvmx_pciercx_cfg064_s cn56xx;
+ struct cvmx_pciercx_cfg064_s cn56xxp1;
+} cvmx_pciercx_cfg064_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg065_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpes:1;
+ uint32_t sdes:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlps:1;
+ uint32_t fcpes:1;
+ uint32_t cts:1;
+ uint32_t cas:1;
+ uint32_t ucs:1;
+ uint32_t ros:1;
+ uint32_t mtlps:1;
+ uint32_t ecrces:1;
+ uint32_t ures:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg065_s cn52xx;
+ struct cvmx_pciercx_cfg065_s cn52xxp1;
+ struct cvmx_pciercx_cfg065_s cn56xx;
+ struct cvmx_pciercx_cfg065_s cn56xxp1;
+} cvmx_pciercx_cfg065_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg066_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t urem:1;
+ uint32_t ecrcem:1;
+ uint32_t mtlpm:1;
+ uint32_t rom:1;
+ uint32_t ucm:1;
+ uint32_t cam:1;
+ uint32_t ctm:1;
+ uint32_t fcpem:1;
+ uint32_t ptlpm:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdem:1;
+ uint32_t dlpem:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpem:1;
+ uint32_t sdem:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlpm:1;
+ uint32_t fcpem:1;
+ uint32_t ctm:1;
+ uint32_t cam:1;
+ uint32_t ucm:1;
+ uint32_t rom:1;
+ uint32_t mtlpm:1;
+ uint32_t ecrcem:1;
+ uint32_t urem:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg066_s cn52xx;
+ struct cvmx_pciercx_cfg066_s cn52xxp1;
+ struct cvmx_pciercx_cfg066_s cn56xx;
+ struct cvmx_pciercx_cfg066_s cn56xxp1;
+} cvmx_pciercx_cfg066_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg067_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+#else
+ uint32_t reserved_0_3:4;
+ uint32_t dlpes:1;
+ uint32_t sdes:1;
+ uint32_t reserved_6_11:6;
+ uint32_t ptlps:1;
+ uint32_t fcpes:1;
+ uint32_t cts:1;
+ uint32_t cas:1;
+ uint32_t ucs:1;
+ uint32_t ros:1;
+ uint32_t mtlps:1;
+ uint32_t ecrces:1;
+ uint32_t ures:1;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg067_s cn52xx;
+ struct cvmx_pciercx_cfg067_s cn52xxp1;
+ struct cvmx_pciercx_cfg067_s cn56xx;
+ struct cvmx_pciercx_cfg067_s cn56xxp1;
+} cvmx_pciercx_cfg067_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg068_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_14_31:18;
+ uint32_t anfes:1;
+ uint32_t rtts:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rnrs:1;
+ uint32_t bdllps:1;
+ uint32_t btlps:1;
+ uint32_t reserved_1_5:5;
+ uint32_t res:1;
+#else
+ uint32_t res:1;
+ uint32_t reserved_1_5:5;
+ uint32_t btlps:1;
+ uint32_t bdllps:1;
+ uint32_t rnrs:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rtts:1;
+ uint32_t anfes:1;
+ uint32_t reserved_14_31:18;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg068_s cn52xx;
+ struct cvmx_pciercx_cfg068_s cn52xxp1;
+ struct cvmx_pciercx_cfg068_s cn56xx;
+ struct cvmx_pciercx_cfg068_s cn56xxp1;
+} cvmx_pciercx_cfg068_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg069_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_14_31:18;
+ uint32_t anfem:1;
+ uint32_t rttm:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rnrm:1;
+ uint32_t bdllpm:1;
+ uint32_t btlpm:1;
+ uint32_t reserved_1_5:5;
+ uint32_t rem:1;
+#else
+ uint32_t rem:1;
+ uint32_t reserved_1_5:5;
+ uint32_t btlpm:1;
+ uint32_t bdllpm:1;
+ uint32_t rnrm:1;
+ uint32_t reserved_9_11:3;
+ uint32_t rttm:1;
+ uint32_t anfem:1;
+ uint32_t reserved_14_31:18;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg069_s cn52xx;
+ struct cvmx_pciercx_cfg069_s cn52xxp1;
+ struct cvmx_pciercx_cfg069_s cn56xx;
+ struct cvmx_pciercx_cfg069_s cn56xxp1;
+} cvmx_pciercx_cfg069_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg070_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t ce:1;
+ uint32_t cc:1;
+ uint32_t ge:1;
+ uint32_t gc:1;
+ uint32_t fep:5;
+#else
+ uint32_t fep:5;
+ uint32_t gc:1;
+ uint32_t ge:1;
+ uint32_t cc:1;
+ uint32_t ce:1;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg070_s cn52xx;
+ struct cvmx_pciercx_cfg070_s cn52xxp1;
+ struct cvmx_pciercx_cfg070_s cn56xx;
+ struct cvmx_pciercx_cfg070_s cn56xxp1;
+} cvmx_pciercx_cfg070_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg071_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword1:32;
+#else
+ uint32_t dword1:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg071_s cn52xx;
+ struct cvmx_pciercx_cfg071_s cn52xxp1;
+ struct cvmx_pciercx_cfg071_s cn56xx;
+ struct cvmx_pciercx_cfg071_s cn56xxp1;
+} cvmx_pciercx_cfg071_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg072_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword2:32;
+#else
+ uint32_t dword2:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg072_s cn52xx;
+ struct cvmx_pciercx_cfg072_s cn52xxp1;
+ struct cvmx_pciercx_cfg072_s cn56xx;
+ struct cvmx_pciercx_cfg072_s cn56xxp1;
+} cvmx_pciercx_cfg072_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg073_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword3:32;
+#else
+ uint32_t dword3:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg073_s cn52xx;
+ struct cvmx_pciercx_cfg073_s cn52xxp1;
+ struct cvmx_pciercx_cfg073_s cn56xx;
+ struct cvmx_pciercx_cfg073_s cn56xxp1;
+} cvmx_pciercx_cfg073_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg074_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dword4:32;
+#else
+ uint32_t dword4:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg074_s cn52xx;
+ struct cvmx_pciercx_cfg074_s cn52xxp1;
+ struct cvmx_pciercx_cfg074_s cn56xx;
+ struct cvmx_pciercx_cfg074_s cn56xxp1;
+} cvmx_pciercx_cfg074_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg075_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_3_31:29;
+ uint32_t fere:1;
+ uint32_t nfere:1;
+ uint32_t cere:1;
+#else
+ uint32_t cere:1;
+ uint32_t nfere:1;
+ uint32_t fere:1;
+ uint32_t reserved_3_31:29;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg075_s cn52xx;
+ struct cvmx_pciercx_cfg075_s cn52xxp1;
+ struct cvmx_pciercx_cfg075_s cn56xx;
+ struct cvmx_pciercx_cfg075_s cn56xxp1;
+} cvmx_pciercx_cfg075_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg076_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t aeimn:5;
+ uint32_t reserved_7_26:20;
+ uint32_t femr:1;
+ uint32_t nfemr:1;
+ uint32_t fuf:1;
+ uint32_t multi_efnfr:1;
+ uint32_t efnfr:1;
+ uint32_t multi_ecr:1;
+ uint32_t ecr:1;
+#else
+ uint32_t ecr:1;
+ uint32_t multi_ecr:1;
+ uint32_t efnfr:1;
+ uint32_t multi_efnfr:1;
+ uint32_t fuf:1;
+ uint32_t nfemr:1;
+ uint32_t femr:1;
+ uint32_t reserved_7_26:20;
+ uint32_t aeimn:5;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg076_s cn52xx;
+ struct cvmx_pciercx_cfg076_s cn52xxp1;
+ struct cvmx_pciercx_cfg076_s cn56xx;
+ struct cvmx_pciercx_cfg076_s cn56xxp1;
+} cvmx_pciercx_cfg076_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg077_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t efnfsi:16;
+ uint32_t ecsi:16;
+#else
+ uint32_t ecsi:16;
+ uint32_t efnfsi:16;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg077_s cn52xx;
+ struct cvmx_pciercx_cfg077_s cn52xxp1;
+ struct cvmx_pciercx_cfg077_s cn56xx;
+ struct cvmx_pciercx_cfg077_s cn56xxp1;
+} cvmx_pciercx_cfg077_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg448_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t rtl:16;
+ uint32_t rtltl:16;
+#else
+ uint32_t rtltl:16;
+ uint32_t rtl:16;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg448_s cn52xx;
+ struct cvmx_pciercx_cfg448_s cn52xxp1;
+ struct cvmx_pciercx_cfg448_s cn56xx;
+ struct cvmx_pciercx_cfg448_s cn56xxp1;
+} cvmx_pciercx_cfg448_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg449_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t omr:32;
+#else
+ uint32_t omr:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg449_s cn52xx;
+ struct cvmx_pciercx_cfg449_s cn52xxp1;
+ struct cvmx_pciercx_cfg449_s cn56xx;
+ struct cvmx_pciercx_cfg449_s cn56xxp1;
+} cvmx_pciercx_cfg449_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg450_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t lpec:8;
+ uint32_t reserved_22_23:2;
+ uint32_t link_state:6;
+ uint32_t force_link:1;
+ uint32_t reserved_8_14:7;
+ uint32_t link_num:8;
+#else
+ uint32_t link_num:8;
+ uint32_t reserved_8_14:7;
+ uint32_t force_link:1;
+ uint32_t link_state:6;
+ uint32_t reserved_22_23:2;
+ uint32_t lpec:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg450_s cn52xx;
+ struct cvmx_pciercx_cfg450_s cn52xxp1;
+ struct cvmx_pciercx_cfg450_s cn56xx;
+ struct cvmx_pciercx_cfg450_s cn56xxp1;
+} cvmx_pciercx_cfg450_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg451_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t n_fts_cc:8;
+ uint32_t n_fts:8;
+ uint32_t ack_freq:8;
+#else
+ uint32_t ack_freq:8;
+ uint32_t n_fts:8;
+ uint32_t n_fts_cc:8;
+ uint32_t l0el:3;
+ uint32_t l1el:3;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg451_s cn52xx;
+ struct cvmx_pciercx_cfg451_s cn52xxp1;
+ struct cvmx_pciercx_cfg451_s cn56xx;
+ struct cvmx_pciercx_cfg451_s cn56xxp1;
+} cvmx_pciercx_cfg451_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg452_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t eccrc:1;
+ uint32_t reserved_22_24:3;
+ uint32_t lme:6;
+ uint32_t reserved_8_15:8;
+ uint32_t flm:1;
+ uint32_t reserved_6_6:1;
+ uint32_t dllle:1;
+ uint32_t reserved_4_4:1;
+ uint32_t ra:1;
+ uint32_t le:1;
+ uint32_t sd:1;
+ uint32_t omr:1;
+#else
+ uint32_t omr:1;
+ uint32_t sd:1;
+ uint32_t le:1;
+ uint32_t ra:1;
+ uint32_t reserved_4_4:1;
+ uint32_t dllle:1;
+ uint32_t reserved_6_6:1;
+ uint32_t flm:1;
+ uint32_t reserved_8_15:8;
+ uint32_t lme:6;
+ uint32_t reserved_22_24:3;
+ uint32_t eccrc:1;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg452_s cn52xx;
+ struct cvmx_pciercx_cfg452_s cn52xxp1;
+ struct cvmx_pciercx_cfg452_s cn56xx;
+ struct cvmx_pciercx_cfg452_s cn56xxp1;
+} cvmx_pciercx_cfg452_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg453_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dlld:1;
+ uint32_t reserved_26_30:5;
+ uint32_t ack_nak:1;
+ uint32_t fcd:1;
+ uint32_t ilst:24;
+#else
+ uint32_t ilst:24;
+ uint32_t fcd:1;
+ uint32_t ack_nak:1;
+ uint32_t reserved_26_30:5;
+ uint32_t dlld:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg453_s cn52xx;
+ struct cvmx_pciercx_cfg453_s cn52xxp1;
+ struct cvmx_pciercx_cfg453_s cn56xx;
+ struct cvmx_pciercx_cfg453_s cn56xxp1;
+} cvmx_pciercx_cfg453_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg454_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_29_31:3;
+ uint32_t tmfcwt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmrt:5;
+ uint32_t reserved_11_13:3;
+ uint32_t nskps:3;
+ uint32_t reserved_4_7:4;
+ uint32_t ntss:4;
+#else
+ uint32_t ntss:4;
+ uint32_t reserved_4_7:4;
+ uint32_t nskps:3;
+ uint32_t reserved_11_13:3;
+ uint32_t tmrt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmfcwt:5;
+ uint32_t reserved_29_31:3;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg454_s cn52xx;
+ struct cvmx_pciercx_cfg454_s cn52xxp1;
+ struct cvmx_pciercx_cfg454_s cn56xx;
+ struct cvmx_pciercx_cfg454_s cn56xxp1;
+} cvmx_pciercx_cfg454_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg455_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t m_cfg0_filt:1;
+ uint32_t m_io_filt:1;
+ uint32_t msg_ctrl:1;
+ uint32_t m_cpl_ecrc_filt:1;
+ uint32_t m_ecrc_filt:1;
+ uint32_t m_cpl_len_err:1;
+ uint32_t m_cpl_attr_err:1;
+ uint32_t m_cpl_tc_err:1;
+ uint32_t m_cpl_fun_err:1;
+ uint32_t m_cpl_rid_err:1;
+ uint32_t m_cpl_tag_err:1;
+ uint32_t m_lk_filt:1;
+ uint32_t m_cfg1_filt:1;
+ uint32_t m_bar_match:1;
+ uint32_t m_pois_filt:1;
+ uint32_t m_fun:1;
+ uint32_t dfcwt:1;
+ uint32_t reserved_11_14:4;
+ uint32_t skpiv:11;
+#else
+ uint32_t skpiv:11;
+ uint32_t reserved_11_14:4;
+ uint32_t dfcwt:1;
+ uint32_t m_fun:1;
+ uint32_t m_pois_filt:1;
+ uint32_t m_bar_match:1;
+ uint32_t m_cfg1_filt:1;
+ uint32_t m_lk_filt:1;
+ uint32_t m_cpl_tag_err:1;
+ uint32_t m_cpl_rid_err:1;
+ uint32_t m_cpl_fun_err:1;
+ uint32_t m_cpl_tc_err:1;
+ uint32_t m_cpl_attr_err:1;
+ uint32_t m_cpl_len_err:1;
+ uint32_t m_ecrc_filt:1;
+ uint32_t m_cpl_ecrc_filt:1;
+ uint32_t msg_ctrl:1;
+ uint32_t m_io_filt:1;
+ uint32_t m_cfg0_filt:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg455_s cn52xx;
+ struct cvmx_pciercx_cfg455_s cn52xxp1;
+ struct cvmx_pciercx_cfg455_s cn56xx;
+ struct cvmx_pciercx_cfg455_s cn56xxp1;
+} cvmx_pciercx_cfg455_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg456_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_2_31:30;
+ uint32_t m_vend1_drp:1;
+ uint32_t m_vend0_drp:1;
+#else
+ uint32_t m_vend0_drp:1;
+ uint32_t m_vend1_drp:1;
+ uint32_t reserved_2_31:30;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg456_s cn52xx;
+ struct cvmx_pciercx_cfg456_s cn52xxp1;
+ struct cvmx_pciercx_cfg456_s cn56xx;
+ struct cvmx_pciercx_cfg456_s cn56xxp1;
+} cvmx_pciercx_cfg456_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg458_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dbg_info_l32:32;
+#else
+ uint32_t dbg_info_l32:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg458_s cn52xx;
+ struct cvmx_pciercx_cfg458_s cn52xxp1;
+ struct cvmx_pciercx_cfg458_s cn56xx;
+ struct cvmx_pciercx_cfg458_s cn56xxp1;
+} cvmx_pciercx_cfg458_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg459_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dbg_info_u32:32;
+#else
+ uint32_t dbg_info_u32:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg459_s cn52xx;
+ struct cvmx_pciercx_cfg459_s cn52xxp1;
+ struct cvmx_pciercx_cfg459_s cn56xx;
+ struct cvmx_pciercx_cfg459_s cn56xxp1;
+} cvmx_pciercx_cfg459_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg460_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tphfcc:8;
+ uint32_t tpdfcc:12;
+#else
+ uint32_t tpdfcc:12;
+ uint32_t tphfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg460_s cn52xx;
+ struct cvmx_pciercx_cfg460_s cn52xxp1;
+ struct cvmx_pciercx_cfg460_s cn56xx;
+ struct cvmx_pciercx_cfg460_s cn56xxp1;
+} cvmx_pciercx_cfg460_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg461_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tchfcc:8;
+ uint32_t tcdfcc:12;
+#else
+ uint32_t tcdfcc:12;
+ uint32_t tchfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg461_s cn52xx;
+ struct cvmx_pciercx_cfg461_s cn52xxp1;
+ struct cvmx_pciercx_cfg461_s cn56xx;
+ struct cvmx_pciercx_cfg461_s cn56xxp1;
+} cvmx_pciercx_cfg461_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg462_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t tchfcc:8;
+ uint32_t tcdfcc:12;
+#else
+ uint32_t tcdfcc:12;
+ uint32_t tchfcc:8;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg462_s cn52xx;
+ struct cvmx_pciercx_cfg462_s cn52xxp1;
+ struct cvmx_pciercx_cfg462_s cn56xx;
+ struct cvmx_pciercx_cfg462_s cn56xxp1;
+} cvmx_pciercx_cfg462_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg463_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_3_31:29;
+ uint32_t rqne:1;
+ uint32_t trbne:1;
+ uint32_t rtlpfccnr:1;
+#else
+ uint32_t rtlpfccnr:1;
+ uint32_t trbne:1;
+ uint32_t rqne:1;
+ uint32_t reserved_3_31:29;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg463_s cn52xx;
+ struct cvmx_pciercx_cfg463_s cn52xxp1;
+ struct cvmx_pciercx_cfg463_s cn56xx;
+ struct cvmx_pciercx_cfg463_s cn56xxp1;
+} cvmx_pciercx_cfg463_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg464_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wrr_vc3:8;
+ uint32_t wrr_vc2:8;
+ uint32_t wrr_vc1:8;
+ uint32_t wrr_vc0:8;
+#else
+ uint32_t wrr_vc0:8;
+ uint32_t wrr_vc1:8;
+ uint32_t wrr_vc2:8;
+ uint32_t wrr_vc3:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg464_s cn52xx;
+ struct cvmx_pciercx_cfg464_s cn52xxp1;
+ struct cvmx_pciercx_cfg464_s cn56xx;
+ struct cvmx_pciercx_cfg464_s cn56xxp1;
+} cvmx_pciercx_cfg464_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg465_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wrr_vc7:8;
+ uint32_t wrr_vc6:8;
+ uint32_t wrr_vc5:8;
+ uint32_t wrr_vc4:8;
+#else
+ uint32_t wrr_vc4:8;
+ uint32_t wrr_vc5:8;
+ uint32_t wrr_vc6:8;
+ uint32_t wrr_vc7:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg465_s cn52xx;
+ struct cvmx_pciercx_cfg465_s cn52xxp1;
+ struct cvmx_pciercx_cfg465_s cn56xx;
+ struct cvmx_pciercx_cfg465_s cn56xxp1;
+} cvmx_pciercx_cfg465_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg466_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t rx_queue_order:1;
+ uint32_t type_ordering:1;
+ uint32_t reserved_24_29:6;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_29:6;
+ uint32_t type_ordering:1;
+ uint32_t rx_queue_order:1;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg466_s cn52xx;
+ struct cvmx_pciercx_cfg466_s cn52xxp1;
+ struct cvmx_pciercx_cfg466_s cn56xx;
+ struct cvmx_pciercx_cfg466_s cn56xxp1;
+} cvmx_pciercx_cfg466_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg467_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg467_s cn52xx;
+ struct cvmx_pciercx_cfg467_s cn52xxp1;
+ struct cvmx_pciercx_cfg467_s cn56xx;
+ struct cvmx_pciercx_cfg467_s cn56xxp1;
+} cvmx_pciercx_cfg467_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg468_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_24_31:8;
+ uint32_t queue_mode:3;
+ uint32_t reserved_20_20:1;
+ uint32_t header_credits:8;
+ uint32_t data_credits:12;
+#else
+ uint32_t data_credits:12;
+ uint32_t header_credits:8;
+ uint32_t reserved_20_20:1;
+ uint32_t queue_mode:3;
+ uint32_t reserved_24_31:8;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg468_s cn52xx;
+ struct cvmx_pciercx_cfg468_s cn52xxp1;
+ struct cvmx_pciercx_cfg468_s cn56xx;
+ struct cvmx_pciercx_cfg468_s cn56xxp1;
+} cvmx_pciercx_cfg468_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg490_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg490_s cn52xx;
+ struct cvmx_pciercx_cfg490_s cn52xxp1;
+ struct cvmx_pciercx_cfg490_s cn56xx;
+ struct cvmx_pciercx_cfg490_s cn56xxp1;
+} cvmx_pciercx_cfg490_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg491_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg491_s cn52xx;
+ struct cvmx_pciercx_cfg491_s cn52xxp1;
+ struct cvmx_pciercx_cfg491_s cn56xx;
+ struct cvmx_pciercx_cfg491_s cn56xxp1;
+} cvmx_pciercx_cfg491_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg492_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_26_31:6;
+ uint32_t header_depth:10;
+ uint32_t reserved_14_15:2;
+ uint32_t data_depth:14;
+#else
+ uint32_t data_depth:14;
+ uint32_t reserved_14_15:2;
+ uint32_t header_depth:10;
+ uint32_t reserved_26_31:6;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg492_s cn52xx;
+ struct cvmx_pciercx_cfg492_s cn52xxp1;
+ struct cvmx_pciercx_cfg492_s cn56xx;
+ struct cvmx_pciercx_cfg492_s cn56xxp1;
+} cvmx_pciercx_cfg492_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg516_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t phy_stat:32;
+#else
+ uint32_t phy_stat:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg516_s cn52xx;
+ struct cvmx_pciercx_cfg516_s cn52xxp1;
+ struct cvmx_pciercx_cfg516_s cn56xx;
+ struct cvmx_pciercx_cfg516_s cn56xxp1;
+} cvmx_pciercx_cfg516_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg517_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t phy_ctrl:32;
+#else
+ uint32_t phy_ctrl:32;
+#endif
+ } s;
+ struct cvmx_pciercx_cfg517_s cn52xx;
+ struct cvmx_pciercx_cfg517_s cn52xxp1;
+ struct cvmx_pciercx_cfg517_s cn56xx;
+ struct cvmx_pciercx_cfg517_s cn56xxp1;
+} cvmx_pciercx_cfg517_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_dma_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t rdpend:1;
+ uint64_t reserved_54_62:9;
+ uint64_t rxslots:10;
+ uint64_t reserved_42_43:2;
+ uint64_t txslots:10;
+ uint64_t reserved_30_31:2;
+ uint64_t rxst:10;
+ uint64_t reserved_19_19:1;
+ uint64_t useldt:1;
+ uint64_t txrd:10;
+ uint64_t fetchsiz:4;
+ uint64_t thresh:4;
+#else
+ uint64_t thresh:4;
+ uint64_t fetchsiz:4;
+ uint64_t txrd:10;
+ uint64_t useldt:1;
+ uint64_t reserved_19_19:1;
+ uint64_t rxst:10;
+ uint64_t reserved_30_31:2;
+ uint64_t txslots:10;
+ uint64_t reserved_42_43:2;
+ uint64_t rxslots:10;
+ uint64_t reserved_54_62:9;
+ uint64_t rdpend:1;
+#endif
+ } s;
+ struct cvmx_pcmx_dma_cfg_s cn30xx;
+ struct cvmx_pcmx_dma_cfg_s cn31xx;
+ struct cvmx_pcmx_dma_cfg_s cn50xx;
+} cvmx_pcmx_dma_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_int_ena_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rxovf:1;
+ uint64_t txempty:1;
+ uint64_t txrd:1;
+ uint64_t txwrap:1;
+ uint64_t rxst:1;
+ uint64_t rxwrap:1;
+ uint64_t fsyncextra:1;
+ uint64_t fsyncmissed:1;
+#else
+ uint64_t fsyncmissed:1;
+ uint64_t fsyncextra:1;
+ uint64_t rxwrap:1;
+ uint64_t rxst:1;
+ uint64_t txwrap:1;
+ uint64_t txrd:1;
+ uint64_t txempty:1;
+ uint64_t rxovf:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pcmx_int_ena_s cn30xx;
+ struct cvmx_pcmx_int_ena_s cn31xx;
+ struct cvmx_pcmx_int_ena_s cn50xx;
+} cvmx_pcmx_int_ena_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rxovf:1;
+ uint64_t txempty:1;
+ uint64_t txrd:1;
+ uint64_t txwrap:1;
+ uint64_t rxst:1;
+ uint64_t rxwrap:1;
+ uint64_t fsyncextra:1;
+ uint64_t fsyncmissed:1;
+#else
+ uint64_t fsyncmissed:1;
+ uint64_t fsyncextra:1;
+ uint64_t rxwrap:1;
+ uint64_t rxst:1;
+ uint64_t txwrap:1;
+ uint64_t txrd:1;
+ uint64_t txempty:1;
+ uint64_t rxovf:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pcmx_int_sum_s cn30xx;
+ struct cvmx_pcmx_int_sum_s cn31xx;
+ struct cvmx_pcmx_int_sum_s cn50xx;
+} cvmx_pcmx_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxaddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_pcmx_rxaddr_s cn30xx;
+ struct cvmx_pcmx_rxaddr_s cn31xx;
+ struct cvmx_pcmx_rxaddr_s cn50xx;
+} cvmx_pcmx_rxaddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxcnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcmx_rxcnt_s cn30xx;
+ struct cvmx_pcmx_rxcnt_s cn31xx;
+ struct cvmx_pcmx_rxcnt_s cn50xx;
+} cvmx_pcmx_rxcnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk0_s cn30xx;
+ struct cvmx_pcmx_rxmsk0_s cn31xx;
+ struct cvmx_pcmx_rxmsk0_s cn50xx;
+} cvmx_pcmx_rxmsk0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk1_s cn30xx;
+ struct cvmx_pcmx_rxmsk1_s cn31xx;
+ struct cvmx_pcmx_rxmsk1_s cn50xx;
+} cvmx_pcmx_rxmsk1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk2_s cn30xx;
+ struct cvmx_pcmx_rxmsk2_s cn31xx;
+ struct cvmx_pcmx_rxmsk2_s cn50xx;
+} cvmx_pcmx_rxmsk2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk3_s cn30xx;
+ struct cvmx_pcmx_rxmsk3_s cn31xx;
+ struct cvmx_pcmx_rxmsk3_s cn50xx;
+} cvmx_pcmx_rxmsk3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk4_s cn30xx;
+ struct cvmx_pcmx_rxmsk4_s cn31xx;
+ struct cvmx_pcmx_rxmsk4_s cn50xx;
+} cvmx_pcmx_rxmsk4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk5_s cn30xx;
+ struct cvmx_pcmx_rxmsk5_s cn31xx;
+ struct cvmx_pcmx_rxmsk5_s cn50xx;
+} cvmx_pcmx_rxmsk5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk6_s cn30xx;
+ struct cvmx_pcmx_rxmsk6_s cn31xx;
+ struct cvmx_pcmx_rxmsk6_s cn50xx;
+} cvmx_pcmx_rxmsk6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxmsk7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_rxmsk7_s cn30xx;
+ struct cvmx_pcmx_rxmsk7_s cn31xx;
+ struct cvmx_pcmx_rxmsk7_s cn50xx;
+} cvmx_pcmx_rxmsk7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_rxstart_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:33;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t addr:33;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_pcmx_rxstart_s cn30xx;
+ struct cvmx_pcmx_rxstart_s cn31xx;
+ struct cvmx_pcmx_rxstart_s cn50xx;
+} cvmx_pcmx_rxstart_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_tdm_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t drvtim:16;
+ uint64_t samppt:16;
+ uint64_t reserved_3_31:29;
+ uint64_t lsbfirst:1;
+ uint64_t useclk1:1;
+ uint64_t enable:1;
+#else
+ uint64_t enable:1;
+ uint64_t useclk1:1;
+ uint64_t lsbfirst:1;
+ uint64_t reserved_3_31:29;
+ uint64_t samppt:16;
+ uint64_t drvtim:16;
+#endif
+ } s;
+ struct cvmx_pcmx_tdm_cfg_s cn30xx;
+ struct cvmx_pcmx_tdm_cfg_s cn31xx;
+ struct cvmx_pcmx_tdm_cfg_s cn50xx;
+} cvmx_pcmx_tdm_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_tdm_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t debuginfo:64;
+#else
+ uint64_t debuginfo:64;
+#endif
+ } s;
+ struct cvmx_pcmx_tdm_dbg_s cn30xx;
+ struct cvmx_pcmx_tdm_dbg_s cn31xx;
+ struct cvmx_pcmx_tdm_dbg_s cn50xx;
+} cvmx_pcmx_tdm_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txaddr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:33;
+ uint64_t fram:3;
+#else
+ uint64_t fram:3;
+ uint64_t addr:33;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_pcmx_txaddr_s cn30xx;
+ struct cvmx_pcmx_txaddr_s cn31xx;
+ struct cvmx_pcmx_txaddr_s cn50xx;
+} cvmx_pcmx_txaddr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txcnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t cnt:16;
+#else
+ uint64_t cnt:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcmx_txcnt_s cn30xx;
+ struct cvmx_pcmx_txcnt_s cn31xx;
+ struct cvmx_pcmx_txcnt_s cn50xx;
+} cvmx_pcmx_txcnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk0_s cn30xx;
+ struct cvmx_pcmx_txmsk0_s cn31xx;
+ struct cvmx_pcmx_txmsk0_s cn50xx;
+} cvmx_pcmx_txmsk0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk1_s cn30xx;
+ struct cvmx_pcmx_txmsk1_s cn31xx;
+ struct cvmx_pcmx_txmsk1_s cn50xx;
+} cvmx_pcmx_txmsk1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk2_s cn30xx;
+ struct cvmx_pcmx_txmsk2_s cn31xx;
+ struct cvmx_pcmx_txmsk2_s cn50xx;
+} cvmx_pcmx_txmsk2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk3_s cn30xx;
+ struct cvmx_pcmx_txmsk3_s cn31xx;
+ struct cvmx_pcmx_txmsk3_s cn50xx;
+} cvmx_pcmx_txmsk3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk4_s cn30xx;
+ struct cvmx_pcmx_txmsk4_s cn31xx;
+ struct cvmx_pcmx_txmsk4_s cn50xx;
+} cvmx_pcmx_txmsk4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk5_s cn30xx;
+ struct cvmx_pcmx_txmsk5_s cn31xx;
+ struct cvmx_pcmx_txmsk5_s cn50xx;
+} cvmx_pcmx_txmsk5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk6_s cn30xx;
+ struct cvmx_pcmx_txmsk6_s cn31xx;
+ struct cvmx_pcmx_txmsk6_s cn50xx;
+} cvmx_pcmx_txmsk6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txmsk7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t mask:64;
+#else
+ uint64_t mask:64;
+#endif
+ } s;
+ struct cvmx_pcmx_txmsk7_s cn30xx;
+ struct cvmx_pcmx_txmsk7_s cn31xx;
+ struct cvmx_pcmx_txmsk7_s cn50xx;
+} cvmx_pcmx_txmsk7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcmx_txstart_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:33;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t addr:33;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_pcmx_txstart_s cn30xx;
+ struct cvmx_pcmx_txstart_s cn31xx;
+ struct cvmx_pcmx_txstart_s cn50xx;
+} cvmx_pcmx_txstart_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcm_clkx_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fsyncgood:1;
+ uint64_t reserved_48_62:15;
+ uint64_t fsyncsamp:16;
+ uint64_t reserved_26_31:6;
+ uint64_t fsynclen:5;
+ uint64_t fsyncloc:5;
+ uint64_t numslots:10;
+ uint64_t extrabit:1;
+ uint64_t bitlen:2;
+ uint64_t bclkpol:1;
+ uint64_t fsyncpol:1;
+ uint64_t ena:1;
+#else
+ uint64_t ena:1;
+ uint64_t fsyncpol:1;
+ uint64_t bclkpol:1;
+ uint64_t bitlen:2;
+ uint64_t extrabit:1;
+ uint64_t numslots:10;
+ uint64_t fsyncloc:5;
+ uint64_t fsynclen:5;
+ uint64_t reserved_26_31:6;
+ uint64_t fsyncsamp:16;
+ uint64_t reserved_48_62:15;
+ uint64_t fsyncgood:1;
+#endif
+ } s;
+ struct cvmx_pcm_clkx_cfg_s cn30xx;
+ struct cvmx_pcm_clkx_cfg_s cn31xx;
+ struct cvmx_pcm_clkx_cfg_s cn50xx;
+} cvmx_pcm_clkx_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcm_clkx_dbg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t debuginfo:64;
+#else
+ uint64_t debuginfo:64;
+#endif
+ } s;
+ struct cvmx_pcm_clkx_dbg_s cn30xx;
+ struct cvmx_pcm_clkx_dbg_s cn31xx;
+ struct cvmx_pcm_clkx_dbg_s cn50xx;
+} cvmx_pcm_clkx_dbg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcm_clkx_gen_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t deltasamp:16;
+ uint64_t numsamp:16;
+ uint64_t n:32;
+#else
+ uint64_t n:32;
+ uint64_t numsamp:16;
+ uint64_t deltasamp:16;
+#endif
+ } s;
+ struct cvmx_pcm_clkx_gen_s cn30xx;
+ struct cvmx_pcm_clkx_gen_s cn31xx;
+ struct cvmx_pcm_clkx_gen_s cn50xx;
+} cvmx_pcm_clkx_gen_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_anx_adv_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t np:1;
+ uint64_t reserved_14_14:1;
+ uint64_t rem_flt:2;
+ uint64_t reserved_9_11:3;
+ uint64_t pause:2;
+ uint64_t hfd:1;
+ uint64_t fd:1;
+ uint64_t reserved_0_4:5;
+#else
+ uint64_t reserved_0_4:5;
+ uint64_t fd:1;
+ uint64_t hfd:1;
+ uint64_t pause:2;
+ uint64_t reserved_9_11:3;
+ uint64_t rem_flt:2;
+ uint64_t reserved_14_14:1;
+ uint64_t np:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_anx_adv_reg_s cn52xx;
+ struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
+ struct cvmx_pcsx_anx_adv_reg_s cn56xx;
+ struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
+} cvmx_pcsx_anx_adv_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_anx_ext_st_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t thou_xfd:1;
+ uint64_t thou_xhd:1;
+ uint64_t thou_tfd:1;
+ uint64_t thou_thd:1;
+ uint64_t reserved_0_11:12;
+#else
+ uint64_t reserved_0_11:12;
+ uint64_t thou_thd:1;
+ uint64_t thou_tfd:1;
+ uint64_t thou_xhd:1;
+ uint64_t thou_xfd:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
+ struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
+ struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
+ struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
+} cvmx_pcsx_anx_ext_st_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_anx_lp_abil_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t np:1;
+ uint64_t ack:1;
+ uint64_t rem_flt:2;
+ uint64_t reserved_9_11:3;
+ uint64_t pause:2;
+ uint64_t hfd:1;
+ uint64_t fd:1;
+ uint64_t reserved_0_4:5;
+#else
+ uint64_t reserved_0_4:5;
+ uint64_t fd:1;
+ uint64_t hfd:1;
+ uint64_t pause:2;
+ uint64_t reserved_9_11:3;
+ uint64_t rem_flt:2;
+ uint64_t ack:1;
+ uint64_t np:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
+ struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
+ struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
+ struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
+} cvmx_pcsx_anx_lp_abil_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_anx_results_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t pause:2;
+ uint64_t spd:2;
+ uint64_t an_cpt:1;
+ uint64_t dup:1;
+ uint64_t link_ok:1;
+#else
+ uint64_t link_ok:1;
+ uint64_t dup:1;
+ uint64_t an_cpt:1;
+ uint64_t spd:2;
+ uint64_t pause:2;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_pcsx_anx_results_reg_s cn52xx;
+ struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
+ struct cvmx_pcsx_anx_results_reg_s cn56xx;
+ struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
+} cvmx_pcsx_anx_results_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_intx_en_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t dup:1;
+ uint64_t sync_bad_en:1;
+ uint64_t an_bad_en:1;
+ uint64_t rxlock_en:1;
+ uint64_t rxbad_en:1;
+ uint64_t rxerr_en:1;
+ uint64_t txbad_en:1;
+ uint64_t txfifo_en:1;
+ uint64_t txfifu_en:1;
+ uint64_t an_err_en:1;
+ uint64_t xmit_en:1;
+ uint64_t lnkspd_en:1;
+#else
+ uint64_t lnkspd_en:1;
+ uint64_t xmit_en:1;
+ uint64_t an_err_en:1;
+ uint64_t txfifu_en:1;
+ uint64_t txfifo_en:1;
+ uint64_t txbad_en:1;
+ uint64_t rxerr_en:1;
+ uint64_t rxbad_en:1;
+ uint64_t rxlock_en:1;
+ uint64_t an_bad_en:1;
+ uint64_t sync_bad_en:1;
+ uint64_t dup:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_pcsx_intx_en_reg_s cn52xx;
+ struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
+ struct cvmx_pcsx_intx_en_reg_s cn56xx;
+ struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
+} cvmx_pcsx_intx_en_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_intx_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t dup:1;
+ uint64_t sync_bad:1;
+ uint64_t an_bad:1;
+ uint64_t rxlock:1;
+ uint64_t rxbad:1;
+ uint64_t rxerr:1;
+ uint64_t txbad:1;
+ uint64_t txfifo:1;
+ uint64_t txfifu:1;
+ uint64_t an_err:1;
+ uint64_t xmit:1;
+ uint64_t lnkspd:1;
+#else
+ uint64_t lnkspd:1;
+ uint64_t xmit:1;
+ uint64_t an_err:1;
+ uint64_t txfifu:1;
+ uint64_t txfifo:1;
+ uint64_t txbad:1;
+ uint64_t rxerr:1;
+ uint64_t rxbad:1;
+ uint64_t rxlock:1;
+ uint64_t an_bad:1;
+ uint64_t sync_bad:1;
+ uint64_t dup:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_pcsx_intx_reg_s cn52xx;
+ struct cvmx_pcsx_intx_reg_s cn52xxp1;
+ struct cvmx_pcsx_intx_reg_s cn56xx;
+ struct cvmx_pcsx_intx_reg_s cn56xxp1;
+} cvmx_pcsx_intx_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_linkx_timer_count_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t count:16;
+#else
+ uint64_t count:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
+ struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
+ struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
+ struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
+} cvmx_pcsx_linkx_timer_count_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_log_anlx_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t lafifovfl:1;
+ uint64_t la_en:1;
+ uint64_t pkt_sz:2;
+#else
+ uint64_t pkt_sz:2;
+ uint64_t la_en:1;
+ uint64_t lafifovfl:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pcsx_log_anlx_reg_s cn52xx;
+ struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
+ struct cvmx_pcsx_log_anlx_reg_s cn56xx;
+ struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
+} cvmx_pcsx_log_anlx_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_miscx_ctl_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t sgmii:1;
+ uint64_t gmxeno:1;
+ uint64_t loopbck2:1;
+ uint64_t mac_phy:1;
+ uint64_t mode:1;
+ uint64_t an_ovrd:1;
+ uint64_t samp_pt:7;
+#else
+ uint64_t samp_pt:7;
+ uint64_t an_ovrd:1;
+ uint64_t mode:1;
+ uint64_t mac_phy:1;
+ uint64_t loopbck2:1;
+ uint64_t gmxeno:1;
+ uint64_t sgmii:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
+ struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
+ struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
+ struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
+} cvmx_pcsx_miscx_ctl_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_mrx_control_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t reset:1;
+ uint64_t loopbck1:1;
+ uint64_t spdlsb:1;
+ uint64_t an_en:1;
+ uint64_t pwr_dn:1;
+ uint64_t reserved_10_10:1;
+ uint64_t rst_an:1;
+ uint64_t dup:1;
+ uint64_t coltst:1;
+ uint64_t spdmsb:1;
+ uint64_t uni:1;
+ uint64_t reserved_0_4:5;
+#else
+ uint64_t reserved_0_4:5;
+ uint64_t uni:1;
+ uint64_t spdmsb:1;
+ uint64_t coltst:1;
+ uint64_t dup:1;
+ uint64_t rst_an:1;
+ uint64_t reserved_10_10:1;
+ uint64_t pwr_dn:1;
+ uint64_t an_en:1;
+ uint64_t spdlsb:1;
+ uint64_t loopbck1:1;
+ uint64_t reset:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_mrx_control_reg_s cn52xx;
+ struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
+ struct cvmx_pcsx_mrx_control_reg_s cn56xx;
+ struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
+} cvmx_pcsx_mrx_control_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_mrx_status_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t hun_t4:1;
+ uint64_t hun_xfd:1;
+ uint64_t hun_xhd:1;
+ uint64_t ten_fd:1;
+ uint64_t ten_hd:1;
+ uint64_t hun_t2fd:1;
+ uint64_t hun_t2hd:1;
+ uint64_t ext_st:1;
+ uint64_t reserved_7_7:1;
+ uint64_t prb_sup:1;
+ uint64_t an_cpt:1;
+ uint64_t rm_flt:1;
+ uint64_t an_abil:1;
+ uint64_t lnk_st:1;
+ uint64_t reserved_1_1:1;
+ uint64_t extnd:1;
+#else
+ uint64_t extnd:1;
+ uint64_t reserved_1_1:1;
+ uint64_t lnk_st:1;
+ uint64_t an_abil:1;
+ uint64_t rm_flt:1;
+ uint64_t an_cpt:1;
+ uint64_t prb_sup:1;
+ uint64_t reserved_7_7:1;
+ uint64_t ext_st:1;
+ uint64_t hun_t2hd:1;
+ uint64_t hun_t2fd:1;
+ uint64_t ten_hd:1;
+ uint64_t ten_fd:1;
+ uint64_t hun_xhd:1;
+ uint64_t hun_xfd:1;
+ uint64_t hun_t4:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_mrx_status_reg_s cn52xx;
+ struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
+ struct cvmx_pcsx_mrx_status_reg_s cn56xx;
+ struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
+} cvmx_pcsx_mrx_status_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_rxx_states_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t rx_bad:1;
+ uint64_t rx_st:5;
+ uint64_t sync_bad:1;
+ uint64_t sync:4;
+ uint64_t an_bad:1;
+ uint64_t an_st:4;
+#else
+ uint64_t an_st:4;
+ uint64_t an_bad:1;
+ uint64_t sync:4;
+ uint64_t sync_bad:1;
+ uint64_t rx_st:5;
+ uint64_t rx_bad:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_rxx_states_reg_s cn52xx;
+ struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
+ struct cvmx_pcsx_rxx_states_reg_s cn56xx;
+ struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
+} cvmx_pcsx_rxx_states_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_rxx_sync_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t sync:1;
+ uint64_t bit_lock:1;
+#else
+ uint64_t bit_lock:1;
+ uint64_t sync:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
+ struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
+ struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
+ struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
+} cvmx_pcsx_rxx_sync_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_sgmx_an_adv_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t link:1;
+ uint64_t ack:1;
+ uint64_t reserved_13_13:1;
+ uint64_t dup:1;
+ uint64_t speed:2;
+ uint64_t reserved_1_9:9;
+ uint64_t one:1;
+#else
+ uint64_t one:1;
+ uint64_t reserved_1_9:9;
+ uint64_t speed:2;
+ uint64_t dup:1;
+ uint64_t reserved_13_13:1;
+ uint64_t ack:1;
+ uint64_t link:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
+ struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
+ struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
+ struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
+} cvmx_pcsx_sgmx_an_adv_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_sgmx_lp_adv_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t link:1;
+ uint64_t reserved_13_14:2;
+ uint64_t dup:1;
+ uint64_t speed:2;
+ uint64_t reserved_1_9:9;
+ uint64_t one:1;
+#else
+ uint64_t one:1;
+ uint64_t reserved_1_9:9;
+ uint64_t speed:2;
+ uint64_t dup:1;
+ uint64_t reserved_13_14:2;
+ uint64_t link:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
+ struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
+ struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
+ struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
+} cvmx_pcsx_sgmx_lp_adv_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_txx_states_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t xmit:2;
+ uint64_t tx_bad:1;
+ uint64_t ord_st:4;
+#else
+ uint64_t ord_st:4;
+ uint64_t tx_bad:1;
+ uint64_t xmit:2;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_pcsx_txx_states_reg_s cn52xx;
+ struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
+ struct cvmx_pcsx_txx_states_reg_s cn56xx;
+ struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
+} cvmx_pcsx_txx_states_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsx_tx_rxx_polarity_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t rxovrd:1;
+ uint64_t autorxpl:1;
+ uint64_t rxplrt:1;
+ uint64_t txplrt:1;
+#else
+ uint64_t txplrt:1;
+ uint64_t rxplrt:1;
+ uint64_t autorxpl:1;
+ uint64_t rxovrd:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
+ struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
+ struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
+ struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
+} cvmx_pcsx_tx_rxx_polarity_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_10gbx_status_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t alignd:1;
+ uint64_t pattst:1;
+ uint64_t reserved_4_10:7;
+ uint64_t l3sync:1;
+ uint64_t l2sync:1;
+ uint64_t l1sync:1;
+ uint64_t l0sync:1;
+#else
+ uint64_t l0sync:1;
+ uint64_t l1sync:1;
+ uint64_t l2sync:1;
+ uint64_t l3sync:1;
+ uint64_t reserved_4_10:7;
+ uint64_t pattst:1;
+ uint64_t alignd:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
+ struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
+ struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
+ struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
+} cvmx_pcsxx_10gbx_status_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_bist_status_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t bist_status:1;
+#else
+ uint64_t bist_status:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_pcsxx_bist_status_reg_s cn52xx;
+ struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
+ struct cvmx_pcsxx_bist_status_reg_s cn56xx;
+ struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
+} cvmx_pcsxx_bist_status_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_bit_lock_status_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t bitlck3:1;
+ uint64_t bitlck2:1;
+ uint64_t bitlck1:1;
+ uint64_t bitlck0:1;
+#else
+ uint64_t bitlck0:1;
+ uint64_t bitlck1:1;
+ uint64_t bitlck2:1;
+ uint64_t bitlck3:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
+ struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
+ struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
+ struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
+} cvmx_pcsxx_bit_lock_status_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_control1_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t reset:1;
+ uint64_t loopbck1:1;
+ uint64_t spdsel1:1;
+ uint64_t reserved_12_12:1;
+ uint64_t lo_pwr:1;
+ uint64_t reserved_7_10:4;
+ uint64_t spdsel0:1;
+ uint64_t spd:4;
+ uint64_t reserved_0_1:2;
+#else
+ uint64_t reserved_0_1:2;
+ uint64_t spd:4;
+ uint64_t spdsel0:1;
+ uint64_t reserved_7_10:4;
+ uint64_t lo_pwr:1;
+ uint64_t reserved_12_12:1;
+ uint64_t spdsel1:1;
+ uint64_t loopbck1:1;
+ uint64_t reset:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsxx_control1_reg_s cn52xx;
+ struct cvmx_pcsxx_control1_reg_s cn52xxp1;
+ struct cvmx_pcsxx_control1_reg_s cn56xx;
+ struct cvmx_pcsxx_control1_reg_s cn56xxp1;
+} cvmx_pcsxx_control1_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_control2_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t type:2;
+#else
+ uint64_t type:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pcsxx_control2_reg_s cn52xx;
+ struct cvmx_pcsxx_control2_reg_s cn52xxp1;
+ struct cvmx_pcsxx_control2_reg_s cn56xx;
+ struct cvmx_pcsxx_control2_reg_s cn56xxp1;
+} cvmx_pcsxx_control2_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_int_en_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t algnlos_en:1;
+ uint64_t synlos_en:1;
+ uint64_t bitlckls_en:1;
+ uint64_t rxsynbad_en:1;
+ uint64_t rxbad_en:1;
+ uint64_t txflt_en:1;
+#else
+ uint64_t txflt_en:1;
+ uint64_t rxbad_en:1;
+ uint64_t rxsynbad_en:1;
+ uint64_t bitlckls_en:1;
+ uint64_t synlos_en:1;
+ uint64_t algnlos_en:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_pcsxx_int_en_reg_s cn52xx;
+ struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
+ struct cvmx_pcsxx_int_en_reg_s cn56xx;
+ struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
+} cvmx_pcsxx_int_en_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t algnlos:1;
+ uint64_t synlos:1;
+ uint64_t bitlckls:1;
+ uint64_t rxsynbad:1;
+ uint64_t rxbad:1;
+ uint64_t txflt:1;
+#else
+ uint64_t txflt:1;
+ uint64_t rxbad:1;
+ uint64_t rxsynbad:1;
+ uint64_t bitlckls:1;
+ uint64_t synlos:1;
+ uint64_t algnlos:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_pcsxx_int_reg_s cn52xx;
+ struct cvmx_pcsxx_int_reg_s cn52xxp1;
+ struct cvmx_pcsxx_int_reg_s cn56xx;
+ struct cvmx_pcsxx_int_reg_s cn56xxp1;
+} cvmx_pcsxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_log_anl_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t enc_mode:1;
+ uint64_t drop_ln:2;
+ uint64_t lafifovfl:1;
+ uint64_t la_en:1;
+ uint64_t pkt_sz:2;
+#else
+ uint64_t pkt_sz:2;
+ uint64_t la_en:1;
+ uint64_t lafifovfl:1;
+ uint64_t drop_ln:2;
+ uint64_t enc_mode:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_pcsxx_log_anl_reg_s cn52xx;
+ struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
+ struct cvmx_pcsxx_log_anl_reg_s cn56xx;
+ struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
+} cvmx_pcsxx_log_anl_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_misc_ctl_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t tx_swap:1;
+ uint64_t rx_swap:1;
+ uint64_t xaui:1;
+ uint64_t gmxeno:1;
+#else
+ uint64_t gmxeno:1;
+ uint64_t xaui:1;
+ uint64_t rx_swap:1;
+ uint64_t tx_swap:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
+ struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
+ struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
+ struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
+} cvmx_pcsxx_misc_ctl_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_rx_sync_states_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t sync3st:4;
+ uint64_t sync2st:4;
+ uint64_t sync1st:4;
+ uint64_t sync0st:4;
+#else
+ uint64_t sync0st:4;
+ uint64_t sync1st:4;
+ uint64_t sync2st:4;
+ uint64_t sync3st:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
+ struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
+ struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
+ struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
+} cvmx_pcsxx_rx_sync_states_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_spd_abil_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t tenpasst:1;
+ uint64_t tengb:1;
+#else
+ uint64_t tengb:1;
+ uint64_t tenpasst:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
+ struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
+ struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
+ struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
+} cvmx_pcsxx_spd_abil_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_status1_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t flt:1;
+ uint64_t reserved_3_6:4;
+ uint64_t rcv_lnk:1;
+ uint64_t lpable:1;
+ uint64_t reserved_0_0:1;
+#else
+ uint64_t reserved_0_0:1;
+ uint64_t lpable:1;
+ uint64_t rcv_lnk:1;
+ uint64_t reserved_3_6:4;
+ uint64_t flt:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pcsxx_status1_reg_s cn52xx;
+ struct cvmx_pcsxx_status1_reg_s cn52xxp1;
+ struct cvmx_pcsxx_status1_reg_s cn56xx;
+ struct cvmx_pcsxx_status1_reg_s cn56xxp1;
+} cvmx_pcsxx_status1_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_status2_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t dev:2;
+ uint64_t reserved_12_13:2;
+ uint64_t xmtflt:1;
+ uint64_t rcvflt:1;
+ uint64_t reserved_3_9:7;
+ uint64_t tengb_w:1;
+ uint64_t tengb_x:1;
+ uint64_t tengb_r:1;
+#else
+ uint64_t tengb_r:1;
+ uint64_t tengb_x:1;
+ uint64_t tengb_w:1;
+ uint64_t reserved_3_9:7;
+ uint64_t rcvflt:1;
+ uint64_t xmtflt:1;
+ uint64_t reserved_12_13:2;
+ uint64_t dev:2;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pcsxx_status2_reg_s cn52xx;
+ struct cvmx_pcsxx_status2_reg_s cn52xxp1;
+ struct cvmx_pcsxx_status2_reg_s cn56xx;
+ struct cvmx_pcsxx_status2_reg_s cn56xxp1;
+} cvmx_pcsxx_status2_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_tx_rx_polarity_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t xor_rxplrt:4;
+ uint64_t xor_txplrt:4;
+ uint64_t rxplrt:1;
+ uint64_t txplrt:1;
+#else
+ uint64_t txplrt:1;
+ uint64_t rxplrt:1;
+ uint64_t xor_txplrt:4;
+ uint64_t xor_rxplrt:4;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
+ struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t rxplrt:1;
+ uint64_t txplrt:1;
+#else
+ uint64_t txplrt:1;
+ uint64_t rxplrt:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn52xxp1;
+ struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
+ struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
+} cvmx_pcsxx_tx_rx_polarity_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pcsxx_tx_rx_states_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t term_err:1;
+ uint64_t syn3bad:1;
+ uint64_t syn2bad:1;
+ uint64_t syn1bad:1;
+ uint64_t syn0bad:1;
+ uint64_t rxbad:1;
+ uint64_t algn_st:3;
+ uint64_t rx_st:2;
+ uint64_t tx_st:3;
+#else
+ uint64_t tx_st:3;
+ uint64_t rx_st:2;
+ uint64_t algn_st:3;
+ uint64_t rxbad:1;
+ uint64_t syn0bad:1;
+ uint64_t syn1bad:1;
+ uint64_t syn2bad:1;
+ uint64_t syn3bad:1;
+ uint64_t term_err:1;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
+ struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t syn3bad:1;
+ uint64_t syn2bad:1;
+ uint64_t syn1bad:1;
+ uint64_t syn0bad:1;
+ uint64_t rxbad:1;
+ uint64_t algn_st:3;
+ uint64_t rx_st:2;
+ uint64_t tx_st:3;
+#else
+ uint64_t tx_st:3;
+ uint64_t rx_st:2;
+ uint64_t algn_st:3;
+ uint64_t rxbad:1;
+ uint64_t syn0bad:1;
+ uint64_t syn1bad:1;
+ uint64_t syn2bad:1;
+ uint64_t syn3bad:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn52xxp1;
+ struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
+ struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
+} cvmx_pcsxx_tx_rx_states_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t rqdata5:1;
+ uint64_t ctlp_or:1;
+ uint64_t ntlp_or:1;
+ uint64_t ptlp_or:1;
+ uint64_t retry:1;
+ uint64_t rqdata0:1;
+ uint64_t rqdata1:1;
+ uint64_t rqdata2:1;
+ uint64_t rqdata3:1;
+ uint64_t rqdata4:1;
+ uint64_t rqhdr1:1;
+ uint64_t rqhdr0:1;
+ uint64_t sot:1;
+#else
+ uint64_t sot:1;
+ uint64_t rqhdr0:1;
+ uint64_t rqhdr1:1;
+ uint64_t rqdata4:1;
+ uint64_t rqdata3:1;
+ uint64_t rqdata2:1;
+ uint64_t rqdata1:1;
+ uint64_t rqdata0:1;
+ uint64_t retry:1;
+ uint64_t ptlp_or:1;
+ uint64_t ntlp_or:1;
+ uint64_t ctlp_or:1;
+ uint64_t rqdata5:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_pescx_bist_status_s cn52xx;
+ struct cvmx_pescx_bist_status_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t ctlp_or:1;
+ uint64_t ntlp_or:1;
+ uint64_t ptlp_or:1;
+ uint64_t retry:1;
+ uint64_t rqdata0:1;
+ uint64_t rqdata1:1;
+ uint64_t rqdata2:1;
+ uint64_t rqdata3:1;
+ uint64_t rqdata4:1;
+ uint64_t rqhdr1:1;
+ uint64_t rqhdr0:1;
+ uint64_t sot:1;
+#else
+ uint64_t sot:1;
+ uint64_t rqhdr0:1;
+ uint64_t rqhdr1:1;
+ uint64_t rqdata4:1;
+ uint64_t rqdata3:1;
+ uint64_t rqdata2:1;
+ uint64_t rqdata1:1;
+ uint64_t rqdata0:1;
+ uint64_t retry:1;
+ uint64_t ptlp_or:1;
+ uint64_t ntlp_or:1;
+ uint64_t ctlp_or:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn52xxp1;
+ struct cvmx_pescx_bist_status_s cn56xx;
+ struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
+} cvmx_pescx_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_bist_status2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t cto_p2e:1;
+ uint64_t e2p_cpl:1;
+ uint64_t e2p_n:1;
+ uint64_t e2p_p:1;
+ uint64_t e2p_rsl:1;
+ uint64_t dbg_p2e:1;
+ uint64_t peai_p2e:1;
+ uint64_t rsl_p2e:1;
+ uint64_t pef_tpf1:1;
+ uint64_t pef_tpf0:1;
+ uint64_t pef_tnf:1;
+ uint64_t pef_tcf1:1;
+ uint64_t pef_tc0:1;
+ uint64_t ppf:1;
+#else
+ uint64_t ppf:1;
+ uint64_t pef_tc0:1;
+ uint64_t pef_tcf1:1;
+ uint64_t pef_tnf:1;
+ uint64_t pef_tpf0:1;
+ uint64_t pef_tpf1:1;
+ uint64_t rsl_p2e:1;
+ uint64_t peai_p2e:1;
+ uint64_t dbg_p2e:1;
+ uint64_t e2p_rsl:1;
+ uint64_t e2p_p:1;
+ uint64_t e2p_n:1;
+ uint64_t e2p_cpl:1;
+ uint64_t cto_p2e:1;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_pescx_bist_status2_s cn52xx;
+ struct cvmx_pescx_bist_status2_s cn52xxp1;
+ struct cvmx_pescx_bist_status2_s cn56xx;
+ struct cvmx_pescx_bist_status2_s cn56xxp1;
+} cvmx_pescx_bist_status2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_cfg_rd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:32;
+ uint64_t addr:32;
+#else
+ uint64_t addr:32;
+ uint64_t data:32;
+#endif
+ } s;
+ struct cvmx_pescx_cfg_rd_s cn52xx;
+ struct cvmx_pescx_cfg_rd_s cn52xxp1;
+ struct cvmx_pescx_cfg_rd_s cn56xx;
+ struct cvmx_pescx_cfg_rd_s cn56xxp1;
+} cvmx_pescx_cfg_rd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_cfg_wr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:32;
+ uint64_t addr:32;
+#else
+ uint64_t addr:32;
+ uint64_t data:32;
+#endif
+ } s;
+ struct cvmx_pescx_cfg_wr_s cn52xx;
+ struct cvmx_pescx_cfg_wr_s cn52xxp1;
+ struct cvmx_pescx_cfg_wr_s cn56xx;
+ struct cvmx_pescx_cfg_wr_s cn56xxp1;
+} cvmx_pescx_cfg_wr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_cpl_lut_valid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t tag:32;
+#else
+ uint64_t tag:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pescx_cpl_lut_valid_s cn52xx;
+ struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
+ struct cvmx_pescx_cpl_lut_valid_s cn56xx;
+ struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
+} cvmx_pescx_cpl_lut_valid_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t dnum:5;
+ uint64_t pbus:8;
+ uint64_t qlm_cfg:2;
+ uint64_t lane_swp:1;
+ uint64_t pm_xtoff:1;
+ uint64_t pm_xpme:1;
+ uint64_t ob_p_cmd:1;
+ uint64_t reserved_7_8:2;
+ uint64_t nf_ecrc:1;
+ uint64_t dly_one:1;
+ uint64_t lnk_enb:1;
+ uint64_t ro_ctlp:1;
+ uint64_t reserved_2_2:1;
+ uint64_t inv_ecrc:1;
+ uint64_t inv_lcrc:1;
+#else
+ uint64_t inv_lcrc:1;
+ uint64_t inv_ecrc:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ro_ctlp:1;
+ uint64_t lnk_enb:1;
+ uint64_t dly_one:1;
+ uint64_t nf_ecrc:1;
+ uint64_t reserved_7_8:2;
+ uint64_t ob_p_cmd:1;
+ uint64_t pm_xpme:1;
+ uint64_t pm_xtoff:1;
+ uint64_t lane_swp:1;
+ uint64_t qlm_cfg:2;
+ uint64_t pbus:8;
+ uint64_t dnum:5;
+ uint64_t reserved_28_63:36;
+#endif
+ } s;
+ struct cvmx_pescx_ctl_status_s cn52xx;
+ struct cvmx_pescx_ctl_status_s cn52xxp1;
+ struct cvmx_pescx_ctl_status_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t dnum:5;
+ uint64_t pbus:8;
+ uint64_t qlm_cfg:2;
+ uint64_t reserved_12_12:1;
+ uint64_t pm_xtoff:1;
+ uint64_t pm_xpme:1;
+ uint64_t ob_p_cmd:1;
+ uint64_t reserved_7_8:2;
+ uint64_t nf_ecrc:1;
+ uint64_t dly_one:1;
+ uint64_t lnk_enb:1;
+ uint64_t ro_ctlp:1;
+ uint64_t reserved_2_2:1;
+ uint64_t inv_ecrc:1;
+ uint64_t inv_lcrc:1;
+#else
+ uint64_t inv_lcrc:1;
+ uint64_t inv_ecrc:1;
+ uint64_t reserved_2_2:1;
+ uint64_t ro_ctlp:1;
+ uint64_t lnk_enb:1;
+ uint64_t dly_one:1;
+ uint64_t nf_ecrc:1;
+ uint64_t reserved_7_8:2;
+ uint64_t ob_p_cmd:1;
+ uint64_t pm_xpme:1;
+ uint64_t pm_xtoff:1;
+ uint64_t reserved_12_12:1;
+ uint64_t qlm_cfg:2;
+ uint64_t pbus:8;
+ uint64_t dnum:5;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn56xx;
+ struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
+} cvmx_pescx_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_ctl_status2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t pclk_run:1;
+ uint64_t pcierst:1;
+#else
+ uint64_t pcierst:1;
+ uint64_t pclk_run:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pescx_ctl_status2_s cn52xx;
+ struct cvmx_pescx_ctl_status2_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t pcierst:1;
+#else
+ uint64_t pcierst:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } cn52xxp1;
+ struct cvmx_pescx_ctl_status2_s cn56xx;
+ struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
+} cvmx_pescx_ctl_status2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_dbg_info_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t ecrc_e:1;
+ uint64_t rawwpp:1;
+ uint64_t racpp:1;
+ uint64_t ramtlp:1;
+ uint64_t rarwdns:1;
+ uint64_t caar:1;
+ uint64_t racca:1;
+ uint64_t racur:1;
+ uint64_t rauc:1;
+ uint64_t rqo:1;
+ uint64_t fcuv:1;
+ uint64_t rpe:1;
+ uint64_t fcpvwt:1;
+ uint64_t dpeoosd:1;
+ uint64_t rtwdle:1;
+ uint64_t rdwdle:1;
+ uint64_t mre:1;
+ uint64_t rte:1;
+ uint64_t acto:1;
+ uint64_t rvdm:1;
+ uint64_t rumep:1;
+ uint64_t rptamrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rfemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rcemrc:1;
+ uint64_t rpoison:1;
+ uint64_t recrce:1;
+ uint64_t rtlplle:1;
+ uint64_t rtlpmal:1;
+ uint64_t spoison:1;
+#else
+ uint64_t spoison:1;
+ uint64_t rtlpmal:1;
+ uint64_t rtlplle:1;
+ uint64_t recrce:1;
+ uint64_t rpoison:1;
+ uint64_t rcemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rfemrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rptamrc:1;
+ uint64_t rumep:1;
+ uint64_t rvdm:1;
+ uint64_t acto:1;
+ uint64_t rte:1;
+ uint64_t mre:1;
+ uint64_t rdwdle:1;
+ uint64_t rtwdle:1;
+ uint64_t dpeoosd:1;
+ uint64_t fcpvwt:1;
+ uint64_t rpe:1;
+ uint64_t fcuv:1;
+ uint64_t rqo:1;
+ uint64_t rauc:1;
+ uint64_t racur:1;
+ uint64_t racca:1;
+ uint64_t caar:1;
+ uint64_t rarwdns:1;
+ uint64_t ramtlp:1;
+ uint64_t racpp:1;
+ uint64_t rawwpp:1;
+ uint64_t ecrc_e:1;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_pescx_dbg_info_s cn52xx;
+ struct cvmx_pescx_dbg_info_s cn52xxp1;
+ struct cvmx_pescx_dbg_info_s cn56xx;
+ struct cvmx_pescx_dbg_info_s cn56xxp1;
+} cvmx_pescx_dbg_info_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_dbg_info_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t ecrc_e:1;
+ uint64_t rawwpp:1;
+ uint64_t racpp:1;
+ uint64_t ramtlp:1;
+ uint64_t rarwdns:1;
+ uint64_t caar:1;
+ uint64_t racca:1;
+ uint64_t racur:1;
+ uint64_t rauc:1;
+ uint64_t rqo:1;
+ uint64_t fcuv:1;
+ uint64_t rpe:1;
+ uint64_t fcpvwt:1;
+ uint64_t dpeoosd:1;
+ uint64_t rtwdle:1;
+ uint64_t rdwdle:1;
+ uint64_t mre:1;
+ uint64_t rte:1;
+ uint64_t acto:1;
+ uint64_t rvdm:1;
+ uint64_t rumep:1;
+ uint64_t rptamrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rfemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rcemrc:1;
+ uint64_t rpoison:1;
+ uint64_t recrce:1;
+ uint64_t rtlplle:1;
+ uint64_t rtlpmal:1;
+ uint64_t spoison:1;
+#else
+ uint64_t spoison:1;
+ uint64_t rtlpmal:1;
+ uint64_t rtlplle:1;
+ uint64_t recrce:1;
+ uint64_t rpoison:1;
+ uint64_t rcemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rfemrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rptamrc:1;
+ uint64_t rumep:1;
+ uint64_t rvdm:1;
+ uint64_t acto:1;
+ uint64_t rte:1;
+ uint64_t mre:1;
+ uint64_t rdwdle:1;
+ uint64_t rtwdle:1;
+ uint64_t dpeoosd:1;
+ uint64_t fcpvwt:1;
+ uint64_t rpe:1;
+ uint64_t fcuv:1;
+ uint64_t rqo:1;
+ uint64_t rauc:1;
+ uint64_t racur:1;
+ uint64_t racca:1;
+ uint64_t caar:1;
+ uint64_t rarwdns:1;
+ uint64_t ramtlp:1;
+ uint64_t racpp:1;
+ uint64_t rawwpp:1;
+ uint64_t ecrc_e:1;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_pescx_dbg_info_en_s cn52xx;
+ struct cvmx_pescx_dbg_info_en_s cn52xxp1;
+ struct cvmx_pescx_dbg_info_en_s cn56xx;
+ struct cvmx_pescx_dbg_info_en_s cn56xxp1;
+} cvmx_pescx_dbg_info_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_diag_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t pm_dst:1;
+ uint64_t pm_stat:1;
+ uint64_t pm_en:1;
+ uint64_t aux_en:1;
+#else
+ uint64_t aux_en:1;
+ uint64_t pm_en:1;
+ uint64_t pm_stat:1;
+ uint64_t pm_dst:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pescx_diag_status_s cn52xx;
+ struct cvmx_pescx_diag_status_s cn52xxp1;
+ struct cvmx_pescx_diag_status_s cn56xx;
+ struct cvmx_pescx_diag_status_s cn56xxp1;
+} cvmx_pescx_diag_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_p2n_bar0_start_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:50;
+ uint64_t reserved_0_13:14;
+#else
+ uint64_t reserved_0_13:14;
+ uint64_t addr:50;
+#endif
+ } s;
+ struct cvmx_pescx_p2n_bar0_start_s cn52xx;
+ struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
+ struct cvmx_pescx_p2n_bar0_start_s cn56xx;
+ struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
+} cvmx_pescx_p2n_bar0_start_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_p2n_bar1_start_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:38;
+ uint64_t reserved_0_25:26;
+#else
+ uint64_t reserved_0_25:26;
+ uint64_t addr:38;
+#endif
+ } s;
+ struct cvmx_pescx_p2n_bar1_start_s cn52xx;
+ struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
+ struct cvmx_pescx_p2n_bar1_start_s cn56xx;
+ struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
+} cvmx_pescx_p2n_bar1_start_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_p2n_bar2_start_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:25;
+ uint64_t reserved_0_38:39;
+#else
+ uint64_t reserved_0_38:39;
+ uint64_t addr:25;
+#endif
+ } s;
+ struct cvmx_pescx_p2n_bar2_start_s cn52xx;
+ struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
+ struct cvmx_pescx_p2n_bar2_start_s cn56xx;
+ struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
+} cvmx_pescx_p2n_bar2_start_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_p2p_barx_end_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:52;
+ uint64_t reserved_0_11:12;
+#else
+ uint64_t reserved_0_11:12;
+ uint64_t addr:52;
+#endif
+ } s;
+ struct cvmx_pescx_p2p_barx_end_s cn52xx;
+ struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
+ struct cvmx_pescx_p2p_barx_end_s cn56xx;
+ struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
+} cvmx_pescx_p2p_barx_end_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_p2p_barx_start_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t addr:52;
+ uint64_t reserved_0_11:12;
+#else
+ uint64_t reserved_0_11:12;
+ uint64_t addr:52;
+#endif
+ } s;
+ struct cvmx_pescx_p2p_barx_start_s cn52xx;
+ struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
+ struct cvmx_pescx_p2p_barx_start_s cn56xx;
+ struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
+} cvmx_pescx_p2p_barx_start_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pescx_tlp_credits_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pescx_tlp_credits_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t peai_ppf:8;
+ uint64_t pesc_cpl:8;
+ uint64_t pesc_np:8;
+ uint64_t pesc_p:8;
+ uint64_t npei_cpl:8;
+ uint64_t npei_np:8;
+ uint64_t npei_p:8;
+#else
+ uint64_t npei_p:8;
+ uint64_t npei_np:8;
+ uint64_t npei_cpl:8;
+ uint64_t pesc_p:8;
+ uint64_t pesc_np:8;
+ uint64_t pesc_cpl:8;
+ uint64_t peai_ppf:8;
+ uint64_t reserved_56_63:8;
+#endif
+ } cn52xx;
+ struct cvmx_pescx_tlp_credits_cn52xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t peai_ppf:8;
+ uint64_t pesc_cpl:5;
+ uint64_t pesc_np:5;
+ uint64_t pesc_p:5;
+ uint64_t npei_cpl:5;
+ uint64_t npei_np:5;
+ uint64_t npei_p:5;
+#else
+ uint64_t npei_p:5;
+ uint64_t npei_np:5;
+ uint64_t npei_cpl:5;
+ uint64_t pesc_p:5;
+ uint64_t pesc_np:5;
+ uint64_t pesc_cpl:5;
+ uint64_t peai_ppf:8;
+ uint64_t reserved_38_63:26;
+#endif
+ } cn52xxp1;
+ struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
+ struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
+} cvmx_pescx_tlp_credits_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_bck_prs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bckprs:1;
+ uint64_t reserved_13_62:50;
+ uint64_t hiwater:5;
+ uint64_t reserved_5_7:3;
+ uint64_t lowater:5;
+#else
+ uint64_t lowater:5;
+ uint64_t reserved_5_7:3;
+ uint64_t hiwater:5;
+ uint64_t reserved_13_62:50;
+ uint64_t bckprs:1;
+#endif
+ } s;
+ struct cvmx_pip_bck_prs_s cn38xx;
+ struct cvmx_pip_bck_prs_s cn38xxp2;
+ struct cvmx_pip_bck_prs_s cn56xx;
+ struct cvmx_pip_bck_prs_s cn56xxp1;
+ struct cvmx_pip_bck_prs_s cn58xx;
+ struct cvmx_pip_bck_prs_s cn58xxp1;
+} cvmx_pip_bck_prs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t bist:18;
+#else
+ uint64_t bist:18;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_pip_bist_status_s cn30xx;
+ struct cvmx_pip_bist_status_s cn31xx;
+ struct cvmx_pip_bist_status_s cn38xx;
+ struct cvmx_pip_bist_status_s cn38xxp2;
+ struct cvmx_pip_bist_status_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t bist:17;
+#else
+ uint64_t bist:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn50xx;
+ struct cvmx_pip_bist_status_s cn52xx;
+ struct cvmx_pip_bist_status_s cn52xxp1;
+ struct cvmx_pip_bist_status_s cn56xx;
+ struct cvmx_pip_bist_status_s cn56xxp1;
+ struct cvmx_pip_bist_status_s cn58xx;
+ struct cvmx_pip_bist_status_s cn58xxp1;
+} cvmx_pip_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_crc_ctlx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t invres:1;
+ uint64_t reflect:1;
+#else
+ uint64_t reflect:1;
+ uint64_t invres:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pip_crc_ctlx_s cn38xx;
+ struct cvmx_pip_crc_ctlx_s cn38xxp2;
+ struct cvmx_pip_crc_ctlx_s cn58xx;
+ struct cvmx_pip_crc_ctlx_s cn58xxp1;
+} cvmx_pip_crc_ctlx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_crc_ivx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iv:32;
+#else
+ uint64_t iv:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pip_crc_ivx_s cn38xx;
+ struct cvmx_pip_crc_ivx_s cn38xxp2;
+ struct cvmx_pip_crc_ivx_s cn58xx;
+ struct cvmx_pip_crc_ivx_s cn58xxp1;
+} cvmx_pip_crc_ivx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_dec_ipsecx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t tcp:1;
+ uint64_t udp:1;
+ uint64_t dprt:16;
+#else
+ uint64_t dprt:16;
+ uint64_t udp:1;
+ uint64_t tcp:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_pip_dec_ipsecx_s cn30xx;
+ struct cvmx_pip_dec_ipsecx_s cn31xx;
+ struct cvmx_pip_dec_ipsecx_s cn38xx;
+ struct cvmx_pip_dec_ipsecx_s cn38xxp2;
+ struct cvmx_pip_dec_ipsecx_s cn50xx;
+ struct cvmx_pip_dec_ipsecx_s cn52xx;
+ struct cvmx_pip_dec_ipsecx_s cn52xxp1;
+ struct cvmx_pip_dec_ipsecx_s cn56xx;
+ struct cvmx_pip_dec_ipsecx_s cn56xxp1;
+ struct cvmx_pip_dec_ipsecx_s cn58xx;
+ struct cvmx_pip_dec_ipsecx_s cn58xxp1;
+} cvmx_pip_dec_ipsecx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_dsa_src_grp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t map15:4;
+ uint64_t map14:4;
+ uint64_t map13:4;
+ uint64_t map12:4;
+ uint64_t map11:4;
+ uint64_t map10:4;
+ uint64_t map9:4;
+ uint64_t map8:4;
+ uint64_t map7:4;
+ uint64_t map6:4;
+ uint64_t map5:4;
+ uint64_t map4:4;
+ uint64_t map3:4;
+ uint64_t map2:4;
+ uint64_t map1:4;
+ uint64_t map0:4;
+#else
+ uint64_t map0:4;
+ uint64_t map1:4;
+ uint64_t map2:4;
+ uint64_t map3:4;
+ uint64_t map4:4;
+ uint64_t map5:4;
+ uint64_t map6:4;
+ uint64_t map7:4;
+ uint64_t map8:4;
+ uint64_t map9:4;
+ uint64_t map10:4;
+ uint64_t map11:4;
+ uint64_t map12:4;
+ uint64_t map13:4;
+ uint64_t map14:4;
+ uint64_t map15:4;
+#endif
+ } s;
+ struct cvmx_pip_dsa_src_grp_s cn52xx;
+ struct cvmx_pip_dsa_src_grp_s cn52xxp1;
+ struct cvmx_pip_dsa_src_grp_s cn56xx;
+} cvmx_pip_dsa_src_grp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_dsa_vid_grp_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t map15:4;
+ uint64_t map14:4;
+ uint64_t map13:4;
+ uint64_t map12:4;
+ uint64_t map11:4;
+ uint64_t map10:4;
+ uint64_t map9:4;
+ uint64_t map8:4;
+ uint64_t map7:4;
+ uint64_t map6:4;
+ uint64_t map5:4;
+ uint64_t map4:4;
+ uint64_t map3:4;
+ uint64_t map2:4;
+ uint64_t map1:4;
+ uint64_t map0:4;
+#else
+ uint64_t map0:4;
+ uint64_t map1:4;
+ uint64_t map2:4;
+ uint64_t map3:4;
+ uint64_t map4:4;
+ uint64_t map5:4;
+ uint64_t map6:4;
+ uint64_t map7:4;
+ uint64_t map8:4;
+ uint64_t map9:4;
+ uint64_t map10:4;
+ uint64_t map11:4;
+ uint64_t map12:4;
+ uint64_t map13:4;
+ uint64_t map14:4;
+ uint64_t map15:4;
+#endif
+ } s;
+ struct cvmx_pip_dsa_vid_grp_s cn52xx;
+ struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
+ struct cvmx_pip_dsa_vid_grp_s cn56xx;
+} cvmx_pip_dsa_vid_grp_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_frm_len_chkx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t maxlen:16;
+ uint64_t minlen:16;
+#else
+ uint64_t minlen:16;
+ uint64_t maxlen:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pip_frm_len_chkx_s cn50xx;
+ struct cvmx_pip_frm_len_chkx_s cn52xx;
+ struct cvmx_pip_frm_len_chkx_s cn52xxp1;
+ struct cvmx_pip_frm_len_chkx_s cn56xx;
+ struct cvmx_pip_frm_len_chkx_s cn56xxp1;
+} cvmx_pip_frm_len_chkx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_gbl_cfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_19_63:45;
+ uint64_t tag_syn:1;
+ uint64_t ip6_udp:1;
+ uint64_t max_l2:1;
+ uint64_t reserved_11_15:5;
+ uint64_t raw_shf:3;
+ uint64_t reserved_3_7:5;
+ uint64_t nip_shf:3;
+#else
+ uint64_t nip_shf:3;
+ uint64_t reserved_3_7:5;
+ uint64_t raw_shf:3;
+ uint64_t reserved_11_15:5;
+ uint64_t max_l2:1;
+ uint64_t ip6_udp:1;
+ uint64_t tag_syn:1;
+ uint64_t reserved_19_63:45;
+#endif
+ } s;
+ struct cvmx_pip_gbl_cfg_s cn30xx;
+ struct cvmx_pip_gbl_cfg_s cn31xx;
+ struct cvmx_pip_gbl_cfg_s cn38xx;
+ struct cvmx_pip_gbl_cfg_s cn38xxp2;
+ struct cvmx_pip_gbl_cfg_s cn50xx;
+ struct cvmx_pip_gbl_cfg_s cn52xx;
+ struct cvmx_pip_gbl_cfg_s cn52xxp1;
+ struct cvmx_pip_gbl_cfg_s cn56xx;
+ struct cvmx_pip_gbl_cfg_s cn56xxp1;
+ struct cvmx_pip_gbl_cfg_s cn58xx;
+ struct cvmx_pip_gbl_cfg_s cn58xxp1;
+} cvmx_pip_gbl_cfg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_gbl_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t dsa_grp_tvid:1;
+ uint64_t dsa_grp_scmd:1;
+ uint64_t dsa_grp_sid:1;
+ uint64_t reserved_21_23:3;
+ uint64_t ring_en:1;
+ uint64_t reserved_17_19:3;
+ uint64_t ignrs:1;
+ uint64_t vs_wqe:1;
+ uint64_t vs_qos:1;
+ uint64_t l2_mal:1;
+ uint64_t tcp_flag:1;
+ uint64_t l4_len:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_mal:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ip6_eext:2;
+ uint64_t ip4_opts:1;
+ uint64_t ip_hop:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_chk:1;
+#else
+ uint64_t ip_chk:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_hop:1;
+ uint64_t ip4_opts:1;
+ uint64_t ip6_eext:2;
+ uint64_t reserved_6_7:2;
+ uint64_t l4_mal:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_len:1;
+ uint64_t tcp_flag:1;
+ uint64_t l2_mal:1;
+ uint64_t vs_qos:1;
+ uint64_t vs_wqe:1;
+ uint64_t ignrs:1;
+ uint64_t reserved_17_19:3;
+ uint64_t ring_en:1;
+ uint64_t reserved_21_23:3;
+ uint64_t dsa_grp_sid:1;
+ uint64_t dsa_grp_scmd:1;
+ uint64_t dsa_grp_tvid:1;
+ uint64_t reserved_27_63:37;
+#endif
+ } s;
+ struct cvmx_pip_gbl_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t ignrs:1;
+ uint64_t vs_wqe:1;
+ uint64_t vs_qos:1;
+ uint64_t l2_mal:1;
+ uint64_t tcp_flag:1;
+ uint64_t l4_len:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_mal:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ip6_eext:2;
+ uint64_t ip4_opts:1;
+ uint64_t ip_hop:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_chk:1;
+#else
+ uint64_t ip_chk:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_hop:1;
+ uint64_t ip4_opts:1;
+ uint64_t ip6_eext:2;
+ uint64_t reserved_6_7:2;
+ uint64_t l4_mal:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_len:1;
+ uint64_t tcp_flag:1;
+ uint64_t l2_mal:1;
+ uint64_t vs_qos:1;
+ uint64_t vs_wqe:1;
+ uint64_t ignrs:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn30xx;
+ struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
+ struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
+ struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
+ struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
+ struct cvmx_pip_gbl_ctl_s cn52xx;
+ struct cvmx_pip_gbl_ctl_s cn52xxp1;
+ struct cvmx_pip_gbl_ctl_s cn56xx;
+ struct cvmx_pip_gbl_ctl_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t ring_en:1;
+ uint64_t reserved_17_19:3;
+ uint64_t ignrs:1;
+ uint64_t vs_wqe:1;
+ uint64_t vs_qos:1;
+ uint64_t l2_mal:1;
+ uint64_t tcp_flag:1;
+ uint64_t l4_len:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_mal:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ip6_eext:2;
+ uint64_t ip4_opts:1;
+ uint64_t ip_hop:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_chk:1;
+#else
+ uint64_t ip_chk:1;
+ uint64_t ip_mal:1;
+ uint64_t ip_hop:1;
+ uint64_t ip4_opts:1;
+ uint64_t ip6_eext:2;
+ uint64_t reserved_6_7:2;
+ uint64_t l4_mal:1;
+ uint64_t l4_prt:1;
+ uint64_t l4_chk:1;
+ uint64_t l4_len:1;
+ uint64_t tcp_flag:1;
+ uint64_t l2_mal:1;
+ uint64_t vs_qos:1;
+ uint64_t vs_wqe:1;
+ uint64_t ignrs:1;
+ uint64_t reserved_17_19:3;
+ uint64_t ring_en:1;
+ uint64_t reserved_21_63:43;
+#endif
+ } cn56xxp1;
+ struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
+ struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
+} cvmx_pip_gbl_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_hg_pri_qos_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t qos:3;
+ uint64_t reserved_6_7:2;
+ uint64_t pri:6;
+#else
+ uint64_t pri:6;
+ uint64_t reserved_6_7:2;
+ uint64_t qos:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_pip_hg_pri_qos_s cn52xx;
+ struct cvmx_pip_hg_pri_qos_s cn52xxp1;
+ struct cvmx_pip_hg_pri_qos_s cn56xx;
+} cvmx_pip_hg_pri_qos_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_pip_int_en_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn30xx;
+ struct cvmx_pip_int_en_cn30xx cn31xx;
+ struct cvmx_pip_int_en_cn30xx cn38xx;
+ struct cvmx_pip_int_en_cn30xx cn38xxp2;
+ struct cvmx_pip_int_en_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t reserved_1_1:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn50xx;
+ struct cvmx_pip_int_en_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t reserved_1_1:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn52xx;
+ struct cvmx_pip_int_en_cn52xx cn52xxp1;
+ struct cvmx_pip_int_en_s cn56xx;
+ struct cvmx_pip_int_en_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xxp1;
+ struct cvmx_pip_int_en_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t reserved_9_11:3;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t reserved_9_11:3;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn58xx;
+ struct cvmx_pip_int_en_cn30xx cn58xxp1;
+} cvmx_pip_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_pip_int_reg_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn30xx;
+ struct cvmx_pip_int_reg_cn30xx cn31xx;
+ struct cvmx_pip_int_reg_cn30xx cn38xx;
+ struct cvmx_pip_int_reg_cn30xx cn38xxp2;
+ struct cvmx_pip_int_reg_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t reserved_1_1:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn50xx;
+ struct cvmx_pip_int_reg_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t reserved_1_1:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t reserved_1_1:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn52xx;
+ struct cvmx_pip_int_reg_cn52xx cn52xxp1;
+ struct cvmx_pip_int_reg_s cn56xx;
+ struct cvmx_pip_int_reg_cn56xxp1 {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t lenerr:1;
+ uint64_t maxerr:1;
+ uint64_t minerr:1;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t minerr:1;
+ uint64_t maxerr:1;
+ uint64_t lenerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } cn56xxp1;
+ struct cvmx_pip_int_reg_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t punyerr:1;
+ uint64_t reserved_9_11:3;
+ uint64_t beperr:1;
+ uint64_t feperr:1;
+ uint64_t todoovr:1;
+ uint64_t skprunt:1;
+ uint64_t badtag:1;
+ uint64_t prtnxa:1;
+ uint64_t bckprs:1;
+ uint64_t crcerr:1;
+ uint64_t pktdrp:1;
+#else
+ uint64_t pktdrp:1;
+ uint64_t crcerr:1;
+ uint64_t bckprs:1;
+ uint64_t prtnxa:1;
+ uint64_t badtag:1;
+ uint64_t skprunt:1;
+ uint64_t todoovr:1;
+ uint64_t feperr:1;
+ uint64_t beperr:1;
+ uint64_t reserved_9_11:3;
+ uint64_t punyerr:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } cn58xx;
+ struct cvmx_pip_int_reg_cn30xx cn58xxp1;
+} cvmx_pip_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_ip_offset_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t offset:3;
+#else
+ uint64_t offset:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_pip_ip_offset_s cn30xx;
+ struct cvmx_pip_ip_offset_s cn31xx;
+ struct cvmx_pip_ip_offset_s cn38xx;
+ struct cvmx_pip_ip_offset_s cn38xxp2;
+ struct cvmx_pip_ip_offset_s cn50xx;
+ struct cvmx_pip_ip_offset_s cn52xx;
+ struct cvmx_pip_ip_offset_s cn52xxp1;
+ struct cvmx_pip_ip_offset_s cn56xx;
+ struct cvmx_pip_ip_offset_s cn56xxp1;
+ struct cvmx_pip_ip_offset_s cn58xx;
+ struct cvmx_pip_ip_offset_s cn58xxp1;
+} cvmx_pip_ip_offset_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_prt_cfgx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_53_63:11;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t lenerr_en:1;
+ uint64_t maxerr_en:1;
+ uint64_t minerr_en:1;
+ uint64_t grp_wat_47:4;
+ uint64_t qos_wat_47:4;
+ uint64_t reserved_37_39:3;
+ uint64_t rawdrp:1;
+ uint64_t tag_inc:2;
+ uint64_t dyn_rs:1;
+ uint64_t inst_hdr:1;
+ uint64_t grp_wat:4;
+ uint64_t hg_qos:1;
+ uint64_t qos:3;
+ uint64_t qos_wat:4;
+ uint64_t qos_vsel:1;
+ uint64_t qos_vod:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vlan:1;
+ uint64_t reserved_13_15:3;
+ uint64_t crc_en:1;
+ uint64_t higig_en:1;
+ uint64_t dsa_en:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_7_7:1;
+ uint64_t skip:7;
+#else
+ uint64_t skip:7;
+ uint64_t reserved_7_7:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t dsa_en:1;
+ uint64_t higig_en:1;
+ uint64_t crc_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t qos_vlan:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vod:1;
+ uint64_t qos_vsel:1;
+ uint64_t qos_wat:4;
+ uint64_t qos:3;
+ uint64_t hg_qos:1;
+ uint64_t grp_wat:4;
+ uint64_t inst_hdr:1;
+ uint64_t dyn_rs:1;
+ uint64_t tag_inc:2;
+ uint64_t rawdrp:1;
+ uint64_t reserved_37_39:3;
+ uint64_t qos_wat_47:4;
+ uint64_t grp_wat_47:4;
+ uint64_t minerr_en:1;
+ uint64_t maxerr_en:1;
+ uint64_t lenerr_en:1;
+ uint64_t vlan_len:1;
+ uint64_t pad_len:1;
+ uint64_t reserved_53_63:11;
+#endif
+ } s;
+ struct cvmx_pip_prt_cfgx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t rawdrp:1;
+ uint64_t tag_inc:2;
+ uint64_t dyn_rs:1;
+ uint64_t inst_hdr:1;
+ uint64_t grp_wat:4;
+ uint64_t reserved_27_27:1;
+ uint64_t qos:3;
+ uint64_t qos_wat:4;
+ uint64_t reserved_18_19:2;
+ uint64_t qos_diff:1;
+ uint64_t qos_vlan:1;
+ uint64_t reserved_10_15:6;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_7_7:1;
+ uint64_t skip:7;
+#else
+ uint64_t skip:7;
+ uint64_t reserved_7_7:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_10_15:6;
+ uint64_t qos_vlan:1;
+ uint64_t qos_diff:1;
+ uint64_t reserved_18_19:2;
+ uint64_t qos_wat:4;
+ uint64_t qos:3;
+ uint64_t reserved_27_27:1;
+ uint64_t grp_wat:4;
+ uint64_t inst_hdr:1;
+ uint64_t dyn_rs:1;
+ uint64_t tag_inc:2;
+ uint64_t rawdrp:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } cn30xx;
+ struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
+ struct cvmx_pip_prt_cfgx_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t rawdrp:1;
+ uint64_t tag_inc:2;
+ uint64_t dyn_rs:1;
+ uint64_t inst_hdr:1;
+ uint64_t grp_wat:4;
+ uint64_t reserved_27_27:1;
+ uint64_t qos:3;
+ uint64_t qos_wat:4;
+ uint64_t reserved_18_19:2;
+ uint64_t qos_diff:1;
+ uint64_t qos_vlan:1;
+ uint64_t reserved_13_15:3;
+ uint64_t crc_en:1;
+ uint64_t reserved_10_11:2;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_7_7:1;
+ uint64_t skip:7;
+#else
+ uint64_t skip:7;
+ uint64_t reserved_7_7:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_10_11:2;
+ uint64_t crc_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t qos_vlan:1;
+ uint64_t qos_diff:1;
+ uint64_t reserved_18_19:2;
+ uint64_t qos_wat:4;
+ uint64_t qos:3;
+ uint64_t reserved_27_27:1;
+ uint64_t grp_wat:4;
+ uint64_t inst_hdr:1;
+ uint64_t dyn_rs:1;
+ uint64_t tag_inc:2;
+ uint64_t rawdrp:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } cn38xx;
+ struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
+ struct cvmx_pip_prt_cfgx_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_53_63:11;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t lenerr_en:1;
+ uint64_t maxerr_en:1;
+ uint64_t minerr_en:1;
+ uint64_t grp_wat_47:4;
+ uint64_t qos_wat_47:4;
+ uint64_t reserved_37_39:3;
+ uint64_t rawdrp:1;
+ uint64_t tag_inc:2;
+ uint64_t dyn_rs:1;
+ uint64_t inst_hdr:1;
+ uint64_t grp_wat:4;
+ uint64_t reserved_27_27:1;
+ uint64_t qos:3;
+ uint64_t qos_wat:4;
+ uint64_t reserved_19_19:1;
+ uint64_t qos_vod:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vlan:1;
+ uint64_t reserved_13_15:3;
+ uint64_t crc_en:1;
+ uint64_t reserved_10_11:2;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_7_7:1;
+ uint64_t skip:7;
+#else
+ uint64_t skip:7;
+ uint64_t reserved_7_7:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_10_11:2;
+ uint64_t crc_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t qos_vlan:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vod:1;
+ uint64_t reserved_19_19:1;
+ uint64_t qos_wat:4;
+ uint64_t qos:3;
+ uint64_t reserved_27_27:1;
+ uint64_t grp_wat:4;
+ uint64_t inst_hdr:1;
+ uint64_t dyn_rs:1;
+ uint64_t tag_inc:2;
+ uint64_t rawdrp:1;
+ uint64_t reserved_37_39:3;
+ uint64_t qos_wat_47:4;
+ uint64_t grp_wat_47:4;
+ uint64_t minerr_en:1;
+ uint64_t maxerr_en:1;
+ uint64_t lenerr_en:1;
+ uint64_t vlan_len:1;
+ uint64_t pad_len:1;
+ uint64_t reserved_53_63:11;
+#endif
+ } cn50xx;
+ struct cvmx_pip_prt_cfgx_s cn52xx;
+ struct cvmx_pip_prt_cfgx_s cn52xxp1;
+ struct cvmx_pip_prt_cfgx_s cn56xx;
+ struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
+ struct cvmx_pip_prt_cfgx_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t rawdrp:1;
+ uint64_t tag_inc:2;
+ uint64_t dyn_rs:1;
+ uint64_t inst_hdr:1;
+ uint64_t grp_wat:4;
+ uint64_t reserved_27_27:1;
+ uint64_t qos:3;
+ uint64_t qos_wat:4;
+ uint64_t reserved_19_19:1;
+ uint64_t qos_vod:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vlan:1;
+ uint64_t reserved_13_15:3;
+ uint64_t crc_en:1;
+ uint64_t reserved_10_11:2;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_7_7:1;
+ uint64_t skip:7;
+#else
+ uint64_t skip:7;
+ uint64_t reserved_7_7:1;
+ cvmx_pip_port_parse_mode_t mode:2;
+ uint64_t reserved_10_11:2;
+ uint64_t crc_en:1;
+ uint64_t reserved_13_15:3;
+ uint64_t qos_vlan:1;
+ uint64_t qos_diff:1;
+ uint64_t qos_vod:1;
+ uint64_t reserved_19_19:1;
+ uint64_t qos_wat:4;
+ uint64_t qos:3;
+ uint64_t reserved_27_27:1;
+ uint64_t grp_wat:4;
+ uint64_t inst_hdr:1;
+ uint64_t dyn_rs:1;
+ uint64_t tag_inc:2;
+ uint64_t rawdrp:1;
+ uint64_t reserved_37_63:27;
+#endif
+ } cn58xx;
+ struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
+} cvmx_pip_prt_cfgx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_prt_tagx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t grptagbase:4;
+ uint64_t grptagmask:4;
+ uint64_t grptag:1;
+ uint64_t grptag_mskip:1;
+ uint64_t tag_mode:2;
+ uint64_t inc_vs:2;
+ uint64_t inc_vlan:1;
+ uint64_t inc_prt_flag:1;
+ uint64_t ip6_dprt_flag:1;
+ uint64_t ip4_dprt_flag:1;
+ uint64_t ip6_sprt_flag:1;
+ uint64_t ip4_sprt_flag:1;
+ uint64_t ip6_nxth_flag:1;
+ uint64_t ip4_pctl_flag:1;
+ uint64_t ip6_dst_flag:1;
+ uint64_t ip4_dst_flag:1;
+ uint64_t ip6_src_flag:1;
+ uint64_t ip4_src_flag:1;
+ cvmx_pow_tag_type_t tcp6_tag_type:2;
+ cvmx_pow_tag_type_t tcp4_tag_type:2;
+ cvmx_pow_tag_type_t ip6_tag_type:2;
+ cvmx_pow_tag_type_t ip4_tag_type:2;
+ cvmx_pow_tag_type_t non_tag_type:2;
+ uint64_t grp:4;
+#else
+ uint64_t grp:4;
+ cvmx_pow_tag_type_t non_tag_type:2;
+ cvmx_pow_tag_type_t ip4_tag_type:2;
+ cvmx_pow_tag_type_t ip6_tag_type:2;
+ cvmx_pow_tag_type_t tcp4_tag_type:2;
+ cvmx_pow_tag_type_t tcp6_tag_type:2;
+ uint64_t ip4_src_flag:1;
+ uint64_t ip6_src_flag:1;
+ uint64_t ip4_dst_flag:1;
+ uint64_t ip6_dst_flag:1;
+ uint64_t ip4_pctl_flag:1;
+ uint64_t ip6_nxth_flag:1;
+ uint64_t ip4_sprt_flag:1;
+ uint64_t ip6_sprt_flag:1;
+ uint64_t ip4_dprt_flag:1;
+ uint64_t ip6_dprt_flag:1;
+ uint64_t inc_prt_flag:1;
+ uint64_t inc_vlan:1;
+ uint64_t inc_vs:2;
+ uint64_t tag_mode:2;
+ uint64_t grptag_mskip:1;
+ uint64_t grptag:1;
+ uint64_t grptagmask:4;
+ uint64_t grptagbase:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_pip_prt_tagx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t grptagbase:4;
+ uint64_t grptagmask:4;
+ uint64_t grptag:1;
+ uint64_t reserved_30_30:1;
+ uint64_t tag_mode:2;
+ uint64_t inc_vs:2;
+ uint64_t inc_vlan:1;
+ uint64_t inc_prt_flag:1;
+ uint64_t ip6_dprt_flag:1;
+ uint64_t ip4_dprt_flag:1;
+ uint64_t ip6_sprt_flag:1;
+ uint64_t ip4_sprt_flag:1;
+ uint64_t ip6_nxth_flag:1;
+ uint64_t ip4_pctl_flag:1;
+ uint64_t ip6_dst_flag:1;
+ uint64_t ip4_dst_flag:1;
+ uint64_t ip6_src_flag:1;
+ uint64_t ip4_src_flag:1;
+ cvmx_pow_tag_type_t tcp6_tag_type:2;
+ cvmx_pow_tag_type_t tcp4_tag_type:2;
+ cvmx_pow_tag_type_t ip6_tag_type:2;
+ cvmx_pow_tag_type_t ip4_tag_type:2;
+ cvmx_pow_tag_type_t non_tag_type:2;
+ uint64_t grp:4;
+#else
+ uint64_t grp:4;
+ cvmx_pow_tag_type_t non_tag_type:2;
+ cvmx_pow_tag_type_t ip4_tag_type:2;
+ cvmx_pow_tag_type_t ip6_tag_type:2;
+ cvmx_pow_tag_type_t tcp4_tag_type:2;
+ cvmx_pow_tag_type_t tcp6_tag_type:2;
+ uint64_t ip4_src_flag:1;
+ uint64_t ip6_src_flag:1;
+ uint64_t ip4_dst_flag:1;
+ uint64_t ip6_dst_flag:1;
+ uint64_t ip4_pctl_flag:1;
+ uint64_t ip6_nxth_flag:1;
+ uint64_t ip4_sprt_flag:1;
+ uint64_t ip6_sprt_flag:1;
+ uint64_t ip4_dprt_flag:1;
+ uint64_t ip6_dprt_flag:1;
+ uint64_t inc_prt_flag:1;
+ uint64_t inc_vlan:1;
+ uint64_t inc_vs:2;
+ uint64_t tag_mode:2;
+ uint64_t reserved_30_30:1;
+ uint64_t grptag:1;
+ uint64_t grptagmask:4;
+ uint64_t grptagbase:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } cn30xx;
+ struct cvmx_pip_prt_tagx_cn30xx cn31xx;
+ struct cvmx_pip_prt_tagx_cn30xx cn38xx;
+ struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
+ struct cvmx_pip_prt_tagx_s cn50xx;
+ struct cvmx_pip_prt_tagx_s cn52xx;
+ struct cvmx_pip_prt_tagx_s cn52xxp1;
+ struct cvmx_pip_prt_tagx_s cn56xx;
+ struct cvmx_pip_prt_tagx_s cn56xxp1;
+ struct cvmx_pip_prt_tagx_cn30xx cn58xx;
+ struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
+} cvmx_pip_prt_tagx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_qos_diffx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_pip_qos_diffx_s cn30xx;
+ struct cvmx_pip_qos_diffx_s cn31xx;
+ struct cvmx_pip_qos_diffx_s cn38xx;
+ struct cvmx_pip_qos_diffx_s cn38xxp2;
+ struct cvmx_pip_qos_diffx_s cn50xx;
+ struct cvmx_pip_qos_diffx_s cn52xx;
+ struct cvmx_pip_qos_diffx_s cn52xxp1;
+ struct cvmx_pip_qos_diffx_s cn56xx;
+ struct cvmx_pip_qos_diffx_s cn56xxp1;
+ struct cvmx_pip_qos_diffx_s cn58xx;
+ struct cvmx_pip_qos_diffx_s cn58xxp1;
+} cvmx_pip_qos_diffx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_qos_vlanx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t qos1:3;
+ uint64_t reserved_3_3:1;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t reserved_3_3:1;
+ uint64_t qos1:3;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_pip_qos_vlanx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
+ struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
+ struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
+ struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
+ struct cvmx_pip_qos_vlanx_s cn52xx;
+ struct cvmx_pip_qos_vlanx_s cn52xxp1;
+ struct cvmx_pip_qos_vlanx_s cn56xx;
+ struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
+ struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
+ struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
+} cvmx_pip_qos_vlanx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_qos_watchx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t mask:16;
+ uint64_t reserved_28_31:4;
+ uint64_t grp:4;
+ uint64_t reserved_23_23:1;
+ uint64_t qos:3;
+ uint64_t reserved_19_19:1;
+ cvmx_pip_qos_watch_types match_type:3;
+
+ uint64_t match_value:16;
+#else
+ uint64_t match_value:16;
+ cvmx_pip_qos_watch_types match_type:3;
+ uint64_t reserved_19_19:1;
+ uint64_t qos:3;
+ uint64_t reserved_23_23:1;
+ uint64_t grp:4;
+ uint64_t reserved_28_31:4;
+ uint64_t mask:16;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_pip_qos_watchx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t mask:16;
+ uint64_t reserved_28_31:4;
+ uint64_t grp:4;
+ uint64_t reserved_23_23:1;
+ uint64_t qos:3;
+ uint64_t reserved_18_19:2;
+ cvmx_pip_qos_watch_types match_type:2;
+
+ uint64_t match_value:16;
+#else
+ uint64_t match_value:16;
+ cvmx_pip_qos_watch_types match_type:2;
+ uint64_t reserved_18_19:2;
+ uint64_t qos:3;
+ uint64_t reserved_23_23:1;
+ uint64_t grp:4;
+ uint64_t reserved_28_31:4;
+ uint64_t mask:16;
+ uint64_t reserved_48_63:16;
+#endif
+ } cn30xx;
+ struct cvmx_pip_qos_watchx_cn30xx cn31xx;
+ struct cvmx_pip_qos_watchx_cn30xx cn38xx;
+ struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
+ struct cvmx_pip_qos_watchx_s cn50xx;
+ struct cvmx_pip_qos_watchx_s cn52xx;
+ struct cvmx_pip_qos_watchx_s cn52xxp1;
+ struct cvmx_pip_qos_watchx_s cn56xx;
+ struct cvmx_pip_qos_watchx_s cn56xxp1;
+ struct cvmx_pip_qos_watchx_cn30xx cn58xx;
+ struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
+} cvmx_pip_qos_watchx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_raw_word_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_56_63:8;
+ uint64_t word:56;
+#else
+ uint64_t word:56;
+ uint64_t reserved_56_63:8;
+#endif
+ } s;
+ struct cvmx_pip_raw_word_s cn30xx;
+ struct cvmx_pip_raw_word_s cn31xx;
+ struct cvmx_pip_raw_word_s cn38xx;
+ struct cvmx_pip_raw_word_s cn38xxp2;
+ struct cvmx_pip_raw_word_s cn50xx;
+ struct cvmx_pip_raw_word_s cn52xx;
+ struct cvmx_pip_raw_word_s cn52xxp1;
+ struct cvmx_pip_raw_word_s cn56xx;
+ struct cvmx_pip_raw_word_s cn56xxp1;
+ struct cvmx_pip_raw_word_s cn58xx;
+ struct cvmx_pip_raw_word_s cn58xxp1;
+} cvmx_pip_raw_word_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_sft_rst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rst:1;
+#else
+ uint64_t rst:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_pip_sft_rst_s cn30xx;
+ struct cvmx_pip_sft_rst_s cn31xx;
+ struct cvmx_pip_sft_rst_s cn38xx;
+ struct cvmx_pip_sft_rst_s cn50xx;
+ struct cvmx_pip_sft_rst_s cn52xx;
+ struct cvmx_pip_sft_rst_s cn52xxp1;
+ struct cvmx_pip_sft_rst_s cn56xx;
+ struct cvmx_pip_sft_rst_s cn56xxp1;
+ struct cvmx_pip_sft_rst_s cn58xx;
+ struct cvmx_pip_sft_rst_s cn58xxp1;
+} cvmx_pip_sft_rst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat0_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t drp_pkts:32;
+ uint64_t drp_octs:32;
+#else
+ uint64_t drp_octs:32;
+ uint64_t drp_pkts:32;
+#endif
+ } s;
+ struct cvmx_pip_stat0_prtx_s cn30xx;
+ struct cvmx_pip_stat0_prtx_s cn31xx;
+ struct cvmx_pip_stat0_prtx_s cn38xx;
+ struct cvmx_pip_stat0_prtx_s cn38xxp2;
+ struct cvmx_pip_stat0_prtx_s cn50xx;
+ struct cvmx_pip_stat0_prtx_s cn52xx;
+ struct cvmx_pip_stat0_prtx_s cn52xxp1;
+ struct cvmx_pip_stat0_prtx_s cn56xx;
+ struct cvmx_pip_stat0_prtx_s cn56xxp1;
+ struct cvmx_pip_stat0_prtx_s cn58xx;
+ struct cvmx_pip_stat0_prtx_s cn58xxp1;
+} cvmx_pip_stat0_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat1_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t octs:48;
+#else
+ uint64_t octs:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_pip_stat1_prtx_s cn30xx;
+ struct cvmx_pip_stat1_prtx_s cn31xx;
+ struct cvmx_pip_stat1_prtx_s cn38xx;
+ struct cvmx_pip_stat1_prtx_s cn38xxp2;
+ struct cvmx_pip_stat1_prtx_s cn50xx;
+ struct cvmx_pip_stat1_prtx_s cn52xx;
+ struct cvmx_pip_stat1_prtx_s cn52xxp1;
+ struct cvmx_pip_stat1_prtx_s cn56xx;
+ struct cvmx_pip_stat1_prtx_s cn56xxp1;
+ struct cvmx_pip_stat1_prtx_s cn58xx;
+ struct cvmx_pip_stat1_prtx_s cn58xxp1;
+} cvmx_pip_stat1_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat2_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t pkts:32;
+ uint64_t raw:32;
+#else
+ uint64_t raw:32;
+ uint64_t pkts:32;
+#endif
+ } s;
+ struct cvmx_pip_stat2_prtx_s cn30xx;
+ struct cvmx_pip_stat2_prtx_s cn31xx;
+ struct cvmx_pip_stat2_prtx_s cn38xx;
+ struct cvmx_pip_stat2_prtx_s cn38xxp2;
+ struct cvmx_pip_stat2_prtx_s cn50xx;
+ struct cvmx_pip_stat2_prtx_s cn52xx;
+ struct cvmx_pip_stat2_prtx_s cn52xxp1;
+ struct cvmx_pip_stat2_prtx_s cn56xx;
+ struct cvmx_pip_stat2_prtx_s cn56xxp1;
+ struct cvmx_pip_stat2_prtx_s cn58xx;
+ struct cvmx_pip_stat2_prtx_s cn58xxp1;
+} cvmx_pip_stat2_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat3_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bcst:32;
+ uint64_t mcst:32;
+#else
+ uint64_t mcst:32;
+ uint64_t bcst:32;
+#endif
+ } s;
+ struct cvmx_pip_stat3_prtx_s cn30xx;
+ struct cvmx_pip_stat3_prtx_s cn31xx;
+ struct cvmx_pip_stat3_prtx_s cn38xx;
+ struct cvmx_pip_stat3_prtx_s cn38xxp2;
+ struct cvmx_pip_stat3_prtx_s cn50xx;
+ struct cvmx_pip_stat3_prtx_s cn52xx;
+ struct cvmx_pip_stat3_prtx_s cn52xxp1;
+ struct cvmx_pip_stat3_prtx_s cn56xx;
+ struct cvmx_pip_stat3_prtx_s cn56xxp1;
+ struct cvmx_pip_stat3_prtx_s cn58xx;
+ struct cvmx_pip_stat3_prtx_s cn58xxp1;
+} cvmx_pip_stat3_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat4_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t h65to127:32;
+ uint64_t h64:32;
+#else
+ uint64_t h64:32;
+ uint64_t h65to127:32;
+#endif
+ } s;
+ struct cvmx_pip_stat4_prtx_s cn30xx;
+ struct cvmx_pip_stat4_prtx_s cn31xx;
+ struct cvmx_pip_stat4_prtx_s cn38xx;
+ struct cvmx_pip_stat4_prtx_s cn38xxp2;
+ struct cvmx_pip_stat4_prtx_s cn50xx;
+ struct cvmx_pip_stat4_prtx_s cn52xx;
+ struct cvmx_pip_stat4_prtx_s cn52xxp1;
+ struct cvmx_pip_stat4_prtx_s cn56xx;
+ struct cvmx_pip_stat4_prtx_s cn56xxp1;
+ struct cvmx_pip_stat4_prtx_s cn58xx;
+ struct cvmx_pip_stat4_prtx_s cn58xxp1;
+} cvmx_pip_stat4_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat5_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t h256to511:32;
+ uint64_t h128to255:32;
+#else
+ uint64_t h128to255:32;
+ uint64_t h256to511:32;
+#endif
+ } s;
+ struct cvmx_pip_stat5_prtx_s cn30xx;
+ struct cvmx_pip_stat5_prtx_s cn31xx;
+ struct cvmx_pip_stat5_prtx_s cn38xx;
+ struct cvmx_pip_stat5_prtx_s cn38xxp2;
+ struct cvmx_pip_stat5_prtx_s cn50xx;
+ struct cvmx_pip_stat5_prtx_s cn52xx;
+ struct cvmx_pip_stat5_prtx_s cn52xxp1;
+ struct cvmx_pip_stat5_prtx_s cn56xx;
+ struct cvmx_pip_stat5_prtx_s cn56xxp1;
+ struct cvmx_pip_stat5_prtx_s cn58xx;
+ struct cvmx_pip_stat5_prtx_s cn58xxp1;
+} cvmx_pip_stat5_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat6_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t h1024to1518:32;
+ uint64_t h512to1023:32;
+#else
+ uint64_t h512to1023:32;
+ uint64_t h1024to1518:32;
+#endif
+ } s;
+ struct cvmx_pip_stat6_prtx_s cn30xx;
+ struct cvmx_pip_stat6_prtx_s cn31xx;
+ struct cvmx_pip_stat6_prtx_s cn38xx;
+ struct cvmx_pip_stat6_prtx_s cn38xxp2;
+ struct cvmx_pip_stat6_prtx_s cn50xx;
+ struct cvmx_pip_stat6_prtx_s cn52xx;
+ struct cvmx_pip_stat6_prtx_s cn52xxp1;
+ struct cvmx_pip_stat6_prtx_s cn56xx;
+ struct cvmx_pip_stat6_prtx_s cn56xxp1;
+ struct cvmx_pip_stat6_prtx_s cn58xx;
+ struct cvmx_pip_stat6_prtx_s cn58xxp1;
+} cvmx_pip_stat6_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat7_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fcs:32;
+ uint64_t h1519:32;
+#else
+ uint64_t h1519:32;
+ uint64_t fcs:32;
+#endif
+ } s;
+ struct cvmx_pip_stat7_prtx_s cn30xx;
+ struct cvmx_pip_stat7_prtx_s cn31xx;
+ struct cvmx_pip_stat7_prtx_s cn38xx;
+ struct cvmx_pip_stat7_prtx_s cn38xxp2;
+ struct cvmx_pip_stat7_prtx_s cn50xx;
+ struct cvmx_pip_stat7_prtx_s cn52xx;
+ struct cvmx_pip_stat7_prtx_s cn52xxp1;
+ struct cvmx_pip_stat7_prtx_s cn56xx;
+ struct cvmx_pip_stat7_prtx_s cn56xxp1;
+ struct cvmx_pip_stat7_prtx_s cn58xx;
+ struct cvmx_pip_stat7_prtx_s cn58xxp1;
+} cvmx_pip_stat7_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat8_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t frag:32;
+ uint64_t undersz:32;
+#else
+ uint64_t undersz:32;
+ uint64_t frag:32;
+#endif
+ } s;
+ struct cvmx_pip_stat8_prtx_s cn30xx;
+ struct cvmx_pip_stat8_prtx_s cn31xx;
+ struct cvmx_pip_stat8_prtx_s cn38xx;
+ struct cvmx_pip_stat8_prtx_s cn38xxp2;
+ struct cvmx_pip_stat8_prtx_s cn50xx;
+ struct cvmx_pip_stat8_prtx_s cn52xx;
+ struct cvmx_pip_stat8_prtx_s cn52xxp1;
+ struct cvmx_pip_stat8_prtx_s cn56xx;
+ struct cvmx_pip_stat8_prtx_s cn56xxp1;
+ struct cvmx_pip_stat8_prtx_s cn58xx;
+ struct cvmx_pip_stat8_prtx_s cn58xxp1;
+} cvmx_pip_stat8_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat9_prtx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t jabber:32;
+ uint64_t oversz:32;
+#else
+ uint64_t oversz:32;
+ uint64_t jabber:32;
+#endif
+ } s;
+ struct cvmx_pip_stat9_prtx_s cn30xx;
+ struct cvmx_pip_stat9_prtx_s cn31xx;
+ struct cvmx_pip_stat9_prtx_s cn38xx;
+ struct cvmx_pip_stat9_prtx_s cn38xxp2;
+ struct cvmx_pip_stat9_prtx_s cn50xx;
+ struct cvmx_pip_stat9_prtx_s cn52xx;
+ struct cvmx_pip_stat9_prtx_s cn52xxp1;
+ struct cvmx_pip_stat9_prtx_s cn56xx;
+ struct cvmx_pip_stat9_prtx_s cn56xxp1;
+ struct cvmx_pip_stat9_prtx_s cn58xx;
+ struct cvmx_pip_stat9_prtx_s cn58xxp1;
+} cvmx_pip_stat9_prtx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t rdclr:1;
+#else
+ uint64_t rdclr:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_pip_stat_ctl_s cn30xx;
+ struct cvmx_pip_stat_ctl_s cn31xx;
+ struct cvmx_pip_stat_ctl_s cn38xx;
+ struct cvmx_pip_stat_ctl_s cn38xxp2;
+ struct cvmx_pip_stat_ctl_s cn50xx;
+ struct cvmx_pip_stat_ctl_s cn52xx;
+ struct cvmx_pip_stat_ctl_s cn52xxp1;
+ struct cvmx_pip_stat_ctl_s cn56xx;
+ struct cvmx_pip_stat_ctl_s cn56xxp1;
+ struct cvmx_pip_stat_ctl_s cn58xx;
+ struct cvmx_pip_stat_ctl_s cn58xxp1;
+} cvmx_pip_stat_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat_inb_errsx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t errs:16;
+#else
+ uint64_t errs:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pip_stat_inb_errsx_s cn30xx;
+ struct cvmx_pip_stat_inb_errsx_s cn31xx;
+ struct cvmx_pip_stat_inb_errsx_s cn38xx;
+ struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
+ struct cvmx_pip_stat_inb_errsx_s cn50xx;
+ struct cvmx_pip_stat_inb_errsx_s cn52xx;
+ struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
+ struct cvmx_pip_stat_inb_errsx_s cn56xx;
+ struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
+ struct cvmx_pip_stat_inb_errsx_s cn58xx;
+ struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
+} cvmx_pip_stat_inb_errsx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat_inb_octsx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t octs:48;
+#else
+ uint64_t octs:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_pip_stat_inb_octsx_s cn30xx;
+ struct cvmx_pip_stat_inb_octsx_s cn31xx;
+ struct cvmx_pip_stat_inb_octsx_s cn38xx;
+ struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
+ struct cvmx_pip_stat_inb_octsx_s cn50xx;
+ struct cvmx_pip_stat_inb_octsx_s cn52xx;
+ struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
+ struct cvmx_pip_stat_inb_octsx_s cn56xx;
+ struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
+ struct cvmx_pip_stat_inb_octsx_s cn58xx;
+ struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
+} cvmx_pip_stat_inb_octsx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_stat_inb_pktsx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pkts:32;
+#else
+ uint64_t pkts:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pip_stat_inb_pktsx_s cn30xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn31xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn38xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
+ struct cvmx_pip_stat_inb_pktsx_s cn50xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn52xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
+ struct cvmx_pip_stat_inb_pktsx_s cn56xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
+ struct cvmx_pip_stat_inb_pktsx_s cn58xx;
+ struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
+} cvmx_pip_stat_inb_pktsx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_tag_incx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t en:8;
+#else
+ uint64_t en:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pip_tag_incx_s cn30xx;
+ struct cvmx_pip_tag_incx_s cn31xx;
+ struct cvmx_pip_tag_incx_s cn38xx;
+ struct cvmx_pip_tag_incx_s cn38xxp2;
+ struct cvmx_pip_tag_incx_s cn50xx;
+ struct cvmx_pip_tag_incx_s cn52xx;
+ struct cvmx_pip_tag_incx_s cn52xxp1;
+ struct cvmx_pip_tag_incx_s cn56xx;
+ struct cvmx_pip_tag_incx_s cn56xxp1;
+ struct cvmx_pip_tag_incx_s cn58xx;
+ struct cvmx_pip_tag_incx_s cn58xxp1;
+} cvmx_pip_tag_incx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_tag_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+#else
+ uint64_t mask:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pip_tag_mask_s cn30xx;
+ struct cvmx_pip_tag_mask_s cn31xx;
+ struct cvmx_pip_tag_mask_s cn38xx;
+ struct cvmx_pip_tag_mask_s cn38xxp2;
+ struct cvmx_pip_tag_mask_s cn50xx;
+ struct cvmx_pip_tag_mask_s cn52xx;
+ struct cvmx_pip_tag_mask_s cn52xxp1;
+ struct cvmx_pip_tag_mask_s cn56xx;
+ struct cvmx_pip_tag_mask_s cn56xxp1;
+ struct cvmx_pip_tag_mask_s cn58xx;
+ struct cvmx_pip_tag_mask_s cn58xxp1;
+} cvmx_pip_tag_mask_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_tag_secret_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t dst:16;
+ uint64_t src:16;
+#else
+ uint64_t src:16;
+ uint64_t dst:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pip_tag_secret_s cn30xx;
+ struct cvmx_pip_tag_secret_s cn31xx;
+ struct cvmx_pip_tag_secret_s cn38xx;
+ struct cvmx_pip_tag_secret_s cn38xxp2;
+ struct cvmx_pip_tag_secret_s cn50xx;
+ struct cvmx_pip_tag_secret_s cn52xx;
+ struct cvmx_pip_tag_secret_s cn52xxp1;
+ struct cvmx_pip_tag_secret_s cn56xx;
+ struct cvmx_pip_tag_secret_s cn56xxp1;
+ struct cvmx_pip_tag_secret_s cn58xx;
+ struct cvmx_pip_tag_secret_s cn58xxp1;
+} cvmx_pip_tag_secret_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pip_todo_entry_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t val:1;
+ uint64_t reserved_62_62:1;
+ uint64_t entry:62;
+#else
+ uint64_t entry:62;
+ uint64_t reserved_62_62:1;
+ uint64_t val:1;
+#endif
+ } s;
+ struct cvmx_pip_todo_entry_s cn30xx;
+ struct cvmx_pip_todo_entry_s cn31xx;
+ struct cvmx_pip_todo_entry_s cn38xx;
+ struct cvmx_pip_todo_entry_s cn38xxp2;
+ struct cvmx_pip_todo_entry_s cn50xx;
+ struct cvmx_pip_todo_entry_s cn52xx;
+ struct cvmx_pip_todo_entry_s cn52xxp1;
+ struct cvmx_pip_todo_entry_s cn56xx;
+ struct cvmx_pip_todo_entry_s cn56xxp1;
+ struct cvmx_pip_todo_entry_s cn58xx;
+ struct cvmx_pip_todo_entry_s cn58xxp1;
+} cvmx_pip_todo_entry_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_count0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t count:32;
+#else
+ uint64_t count:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pko_mem_count0_s cn30xx;
+ struct cvmx_pko_mem_count0_s cn31xx;
+ struct cvmx_pko_mem_count0_s cn38xx;
+ struct cvmx_pko_mem_count0_s cn38xxp2;
+ struct cvmx_pko_mem_count0_s cn50xx;
+ struct cvmx_pko_mem_count0_s cn52xx;
+ struct cvmx_pko_mem_count0_s cn52xxp1;
+ struct cvmx_pko_mem_count0_s cn56xx;
+ struct cvmx_pko_mem_count0_s cn56xxp1;
+ struct cvmx_pko_mem_count0_s cn58xx;
+ struct cvmx_pko_mem_count0_s cn58xxp1;
+} cvmx_pko_mem_count0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_count1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t count:48;
+#else
+ uint64_t count:48;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_pko_mem_count1_s cn30xx;
+ struct cvmx_pko_mem_count1_s cn31xx;
+ struct cvmx_pko_mem_count1_s cn38xx;
+ struct cvmx_pko_mem_count1_s cn38xxp2;
+ struct cvmx_pko_mem_count1_s cn50xx;
+ struct cvmx_pko_mem_count1_s cn52xx;
+ struct cvmx_pko_mem_count1_s cn52xxp1;
+ struct cvmx_pko_mem_count1_s cn56xx;
+ struct cvmx_pko_mem_count1_s cn56xxp1;
+ struct cvmx_pko_mem_count1_s cn58xx;
+ struct cvmx_pko_mem_count1_s cn58xxp1;
+} cvmx_pko_mem_count1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fau:28;
+ uint64_t cmd:14;
+ uint64_t segs:6;
+ uint64_t size:16;
+#else
+ uint64_t size:16;
+ uint64_t segs:6;
+ uint64_t cmd:14;
+ uint64_t fau:28;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug0_s cn30xx;
+ struct cvmx_pko_mem_debug0_s cn31xx;
+ struct cvmx_pko_mem_debug0_s cn38xx;
+ struct cvmx_pko_mem_debug0_s cn38xxp2;
+ struct cvmx_pko_mem_debug0_s cn50xx;
+ struct cvmx_pko_mem_debug0_s cn52xx;
+ struct cvmx_pko_mem_debug0_s cn52xxp1;
+ struct cvmx_pko_mem_debug0_s cn56xx;
+ struct cvmx_pko_mem_debug0_s cn56xxp1;
+ struct cvmx_pko_mem_debug0_s cn58xx;
+ struct cvmx_pko_mem_debug0_s cn58xxp1;
+} cvmx_pko_mem_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug1_s cn30xx;
+ struct cvmx_pko_mem_debug1_s cn31xx;
+ struct cvmx_pko_mem_debug1_s cn38xx;
+ struct cvmx_pko_mem_debug1_s cn38xxp2;
+ struct cvmx_pko_mem_debug1_s cn50xx;
+ struct cvmx_pko_mem_debug1_s cn52xx;
+ struct cvmx_pko_mem_debug1_s cn52xxp1;
+ struct cvmx_pko_mem_debug1_s cn56xx;
+ struct cvmx_pko_mem_debug1_s cn56xxp1;
+ struct cvmx_pko_mem_debug1_s cn58xx;
+ struct cvmx_pko_mem_debug1_s cn58xxp1;
+} cvmx_pko_mem_debug1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug10_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug10_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fau:28;
+ uint64_t cmd:14;
+ uint64_t segs:6;
+ uint64_t size:16;
+#else
+ uint64_t size:16;
+ uint64_t segs:6;
+ uint64_t cmd:14;
+ uint64_t fau:28;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug10_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug10_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug10_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t ptrs1:17;
+ uint64_t reserved_17_31:15;
+ uint64_t ptrs2:17;
+#else
+ uint64_t ptrs2:17;
+ uint64_t reserved_17_31:15;
+ uint64_t ptrs1:17;
+ uint64_t reserved_49_63:15;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug10_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug10_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug10_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug10_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug11_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t reserved_0_39:40;
+#else
+ uint64_t reserved_0_39:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug11_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug11_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug11_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug11_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t maj:1;
+ uint64_t uid:3;
+ uint64_t sop:1;
+ uint64_t len:1;
+ uint64_t chk:1;
+ uint64_t cnt:13;
+ uint64_t mod:3;
+#else
+ uint64_t mod:3;
+ uint64_t cnt:13;
+ uint64_t chk:1;
+ uint64_t len:1;
+ uint64_t sop:1;
+ uint64_t uid:3;
+ uint64_t maj:1;
+ uint64_t reserved_23_63:41;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug11_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug11_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug11_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug11_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug12_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug12_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug12_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug12_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug12_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t fau:28;
+ uint64_t cmd:14;
+ uint64_t segs:6;
+ uint64_t size:16;
+#else
+ uint64_t size:16;
+ uint64_t segs:6;
+ uint64_t cmd:14;
+ uint64_t fau:28;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug12_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug12_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug12_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug12_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug13_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t reserved_0_55:56;
+#else
+ uint64_t reserved_0_55:56;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug13_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_51_63:13;
+ uint64_t widx:17;
+ uint64_t ridx2:17;
+ uint64_t widx2:17;
+#else
+ uint64_t widx2:17;
+ uint64_t ridx2:17;
+ uint64_t widx:17;
+ uint64_t reserved_51_63:13;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug13_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug13_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug13_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug13_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug13_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug13_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug13_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug14_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug14_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t ridx:17;
+#else
+ uint64_t ridx:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug14_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug14_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug14_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } cn52xx;
+ struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
+ struct cvmx_pko_mem_debug14_cn52xx cn56xx;
+ struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
+} cvmx_pko_mem_debug14_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug2_s cn30xx;
+ struct cvmx_pko_mem_debug2_s cn31xx;
+ struct cvmx_pko_mem_debug2_s cn38xx;
+ struct cvmx_pko_mem_debug2_s cn38xxp2;
+ struct cvmx_pko_mem_debug2_s cn50xx;
+ struct cvmx_pko_mem_debug2_s cn52xx;
+ struct cvmx_pko_mem_debug2_s cn52xxp1;
+ struct cvmx_pko_mem_debug2_s cn56xx;
+ struct cvmx_pko_mem_debug2_s cn56xxp1;
+ struct cvmx_pko_mem_debug2_s cn58xx;
+ struct cvmx_pko_mem_debug2_s cn58xxp1;
+} cvmx_pko_mem_debug2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug3_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t i:1;
+ uint64_t back:4;
+ uint64_t pool:3;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t pool:3;
+ uint64_t back:4;
+ uint64_t i:1;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug3_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug3_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug3_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug3_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug3_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug3_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug4_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug4_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug4_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug4_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cmnd_segs:3;
+ uint64_t cmnd_siz:16;
+ uint64_t cmnd_off:6;
+ uint64_t uid:3;
+ uint64_t dread_sop:1;
+ uint64_t init_dwrite:1;
+ uint64_t chk_once:1;
+ uint64_t chk_mode:1;
+ uint64_t active:1;
+ uint64_t static_p:1;
+ uint64_t qos:3;
+ uint64_t qcb_ridx:5;
+ uint64_t qid_off_max:4;
+ uint64_t qid_off:4;
+ uint64_t qid_base:8;
+ uint64_t wait:1;
+ uint64_t minor:2;
+ uint64_t major:3;
+#else
+ uint64_t major:3;
+ uint64_t minor:2;
+ uint64_t wait:1;
+ uint64_t qid_base:8;
+ uint64_t qid_off:4;
+ uint64_t qid_off_max:4;
+ uint64_t qcb_ridx:5;
+ uint64_t qos:3;
+ uint64_t static_p:1;
+ uint64_t active:1;
+ uint64_t chk_mode:1;
+ uint64_t chk_once:1;
+ uint64_t init_dwrite:1;
+ uint64_t dread_sop:1;
+ uint64_t uid:3;
+ uint64_t cmnd_off:6;
+ uint64_t cmnd_siz:16;
+ uint64_t cmnd_segs:3;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug4_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t curr_siz:8;
+ uint64_t curr_off:16;
+ uint64_t cmnd_segs:6;
+ uint64_t cmnd_siz:16;
+ uint64_t cmnd_off:6;
+ uint64_t uid:2;
+ uint64_t dread_sop:1;
+ uint64_t init_dwrite:1;
+ uint64_t chk_once:1;
+ uint64_t chk_mode:1;
+ uint64_t wait:1;
+ uint64_t minor:2;
+ uint64_t major:3;
+#else
+ uint64_t major:3;
+ uint64_t minor:2;
+ uint64_t wait:1;
+ uint64_t chk_mode:1;
+ uint64_t chk_once:1;
+ uint64_t init_dwrite:1;
+ uint64_t dread_sop:1;
+ uint64_t uid:2;
+ uint64_t cmnd_off:6;
+ uint64_t cmnd_siz:16;
+ uint64_t cmnd_segs:6;
+ uint64_t curr_off:16;
+ uint64_t curr_siz:8;
+#endif
+ } cn52xx;
+ struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
+ struct cvmx_pko_mem_debug4_cn52xx cn56xx;
+ struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
+ struct cvmx_pko_mem_debug4_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug5_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dwri_mod:1;
+ uint64_t dwri_sop:1;
+ uint64_t dwri_len:1;
+ uint64_t dwri_cnt:13;
+ uint64_t cmnd_siz:16;
+ uint64_t uid:1;
+ uint64_t xfer_wor:1;
+ uint64_t xfer_dwr:1;
+ uint64_t cbuf_fre:1;
+ uint64_t reserved_27_27:1;
+ uint64_t chk_mode:1;
+ uint64_t active:1;
+ uint64_t qos:3;
+ uint64_t qcb_ridx:5;
+ uint64_t qid_off:3;
+ uint64_t qid_base:7;
+ uint64_t wait:1;
+ uint64_t minor:2;
+ uint64_t major:4;
+#else
+ uint64_t major:4;
+ uint64_t minor:2;
+ uint64_t wait:1;
+ uint64_t qid_base:7;
+ uint64_t qid_off:3;
+ uint64_t qcb_ridx:5;
+ uint64_t qos:3;
+ uint64_t active:1;
+ uint64_t chk_mode:1;
+ uint64_t reserved_27_27:1;
+ uint64_t cbuf_fre:1;
+ uint64_t xfer_dwr:1;
+ uint64_t xfer_wor:1;
+ uint64_t uid:1;
+ uint64_t cmnd_siz:16;
+ uint64_t dwri_cnt:13;
+ uint64_t dwri_len:1;
+ uint64_t dwri_sop:1;
+ uint64_t dwri_mod:1;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug5_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug5_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug5_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t curr_ptr:29;
+ uint64_t curr_siz:16;
+ uint64_t curr_off:16;
+ uint64_t cmnd_segs:3;
+#else
+ uint64_t cmnd_segs:3;
+ uint64_t curr_off:16;
+ uint64_t curr_siz:16;
+ uint64_t curr_ptr:29;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug5_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_54_63:10;
+ uint64_t nxt_inflt:6;
+ uint64_t curr_ptr:40;
+ uint64_t curr_siz:8;
+#else
+ uint64_t curr_siz:8;
+ uint64_t curr_ptr:40;
+ uint64_t nxt_inflt:6;
+ uint64_t reserved_54_63:10;
+#endif
+ } cn52xx;
+ struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
+ struct cvmx_pko_mem_debug5_cn52xx cn56xx;
+ struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
+ struct cvmx_pko_mem_debug5_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t qid_offres:4;
+ uint64_t qid_offths:4;
+ uint64_t preempter:1;
+ uint64_t preemptee:1;
+ uint64_t preempted:1;
+ uint64_t active:1;
+ uint64_t statc:1;
+ uint64_t qos:3;
+ uint64_t qcb_ridx:5;
+ uint64_t qid_offmax:4;
+ uint64_t reserved_0_11:12;
+#else
+ uint64_t reserved_0_11:12;
+ uint64_t qid_offmax:4;
+ uint64_t qcb_ridx:5;
+ uint64_t qos:3;
+ uint64_t statc:1;
+ uint64_t active:1;
+ uint64_t preempted:1;
+ uint64_t preemptee:1;
+ uint64_t preempter:1;
+ uint64_t qid_offths:4;
+ uint64_t qid_offres:4;
+ uint64_t reserved_37_63:27;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug6_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t qid_offm:3;
+ uint64_t static_p:1;
+ uint64_t work_min:3;
+ uint64_t dwri_chk:1;
+ uint64_t dwri_uid:1;
+ uint64_t dwri_mod:2;
+#else
+ uint64_t dwri_mod:2;
+ uint64_t dwri_uid:1;
+ uint64_t dwri_chk:1;
+ uint64_t work_min:3;
+ uint64_t static_p:1;
+ uint64_t qid_offm:3;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug6_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug6_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug6_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t curr_ptr:11;
+#else
+ uint64_t curr_ptr:11;
+ uint64_t reserved_11_63:53;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug6_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_37_63:27;
+ uint64_t qid_offres:4;
+ uint64_t qid_offths:4;
+ uint64_t preempter:1;
+ uint64_t preemptee:1;
+ uint64_t preempted:1;
+ uint64_t active:1;
+ uint64_t statc:1;
+ uint64_t qos:3;
+ uint64_t qcb_ridx:5;
+ uint64_t qid_offmax:4;
+ uint64_t qid_off:4;
+ uint64_t qid_base:8;
+#else
+ uint64_t qid_base:8;
+ uint64_t qid_off:4;
+ uint64_t qid_offmax:4;
+ uint64_t qcb_ridx:5;
+ uint64_t qos:3;
+ uint64_t statc:1;
+ uint64_t active:1;
+ uint64_t preempted:1;
+ uint64_t preemptee:1;
+ uint64_t preempter:1;
+ uint64_t qid_offths:4;
+ uint64_t qid_offres:4;
+ uint64_t reserved_37_63:27;
+#endif
+ } cn52xx;
+ struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
+ struct cvmx_pko_mem_debug6_cn52xx cn56xx;
+ struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
+ struct cvmx_pko_mem_debug6_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t qos:5;
+ uint64_t tail:1;
+ uint64_t reserved_0_57:58;
+#else
+ uint64_t reserved_0_57:58;
+ uint64_t tail:1;
+ uint64_t qos:5;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug7_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_58_63:6;
+ uint64_t dwb:9;
+ uint64_t start:33;
+ uint64_t size:16;
+#else
+ uint64_t size:16;
+ uint64_t start:33;
+ uint64_t dwb:9;
+ uint64_t reserved_58_63:6;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug7_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug7_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug7_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t qos:5;
+ uint64_t tail:1;
+ uint64_t buf_siz:13;
+ uint64_t buf_ptr:33;
+ uint64_t qcb_widx:6;
+ uint64_t qcb_ridx:6;
+#else
+ uint64_t qcb_ridx:6;
+ uint64_t qcb_widx:6;
+ uint64_t buf_ptr:33;
+ uint64_t buf_siz:13;
+ uint64_t tail:1;
+ uint64_t qos:5;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug7_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug7_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug7_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug8_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_59_63:5;
+ uint64_t tail:1;
+ uint64_t buf_siz:13;
+ uint64_t reserved_0_44:45;
+#else
+ uint64_t reserved_0_44:45;
+ uint64_t buf_siz:13;
+ uint64_t tail:1;
+ uint64_t reserved_59_63:5;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug8_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t qos:5;
+ uint64_t tail:1;
+ uint64_t buf_siz:13;
+ uint64_t buf_ptr:33;
+ uint64_t qcb_widx:6;
+ uint64_t qcb_ridx:6;
+#else
+ uint64_t qcb_ridx:6;
+ uint64_t qcb_widx:6;
+ uint64_t buf_ptr:33;
+ uint64_t buf_siz:13;
+ uint64_t tail:1;
+ uint64_t qos:5;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug8_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug8_cn30xx cn38xx;
+ struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
+ struct cvmx_pko_mem_debug8_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t doorbell:20;
+ uint64_t reserved_6_7:2;
+ uint64_t static_p:1;
+ uint64_t s_tail:1;
+ uint64_t static_q:1;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t static_q:1;
+ uint64_t s_tail:1;
+ uint64_t static_p:1;
+ uint64_t reserved_6_7:2;
+ uint64_t doorbell:20;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug8_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t preempter:1;
+ uint64_t doorbell:20;
+ uint64_t reserved_7_7:1;
+ uint64_t preemptee:1;
+ uint64_t static_p:1;
+ uint64_t s_tail:1;
+ uint64_t static_q:1;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t static_q:1;
+ uint64_t s_tail:1;
+ uint64_t static_p:1;
+ uint64_t preemptee:1;
+ uint64_t reserved_7_7:1;
+ uint64_t doorbell:20;
+ uint64_t preempter:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn52xx;
+ struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
+ struct cvmx_pko_mem_debug8_cn52xx cn56xx;
+ struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
+ struct cvmx_pko_mem_debug8_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug8_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_debug9_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t ptrs0:17;
+ uint64_t reserved_0_31:32;
+#else
+ uint64_t reserved_0_31:32;
+ uint64_t ptrs0:17;
+ uint64_t reserved_49_63:15;
+#endif
+ } s;
+ struct cvmx_pko_mem_debug9_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t doorbell:20;
+ uint64_t reserved_5_7:3;
+ uint64_t s_tail:1;
+ uint64_t static_q:1;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t static_q:1;
+ uint64_t s_tail:1;
+ uint64_t reserved_5_7:3;
+ uint64_t doorbell:20;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn30xx;
+ struct cvmx_pko_mem_debug9_cn30xx cn31xx;
+ struct cvmx_pko_mem_debug9_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t doorbell:20;
+ uint64_t reserved_6_7:2;
+ uint64_t static_p:1;
+ uint64_t s_tail:1;
+ uint64_t static_q:1;
+ uint64_t qos:3;
+#else
+ uint64_t qos:3;
+ uint64_t static_q:1;
+ uint64_t s_tail:1;
+ uint64_t static_p:1;
+ uint64_t reserved_6_7:2;
+ uint64_t doorbell:20;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn38xx;
+ struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
+ struct cvmx_pko_mem_debug9_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_49_63:15;
+ uint64_t ptrs0:17;
+ uint64_t reserved_17_31:15;
+ uint64_t ptrs3:17;
+#else
+ uint64_t ptrs3:17;
+ uint64_t reserved_17_31:15;
+ uint64_t ptrs0:17;
+ uint64_t reserved_49_63:15;
+#endif
+ } cn50xx;
+ struct cvmx_pko_mem_debug9_cn50xx cn52xx;
+ struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
+ struct cvmx_pko_mem_debug9_cn50xx cn56xx;
+ struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
+ struct cvmx_pko_mem_debug9_cn50xx cn58xx;
+ struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
+} cvmx_pko_mem_debug9_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_port_ptrs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_62_63:2;
+ uint64_t static_p:1;
+ uint64_t qos_mask:8;
+ uint64_t reserved_16_52:37;
+ uint64_t bp_port:6;
+ uint64_t eid:4;
+ uint64_t pid:6;
+#else
+ uint64_t pid:6;
+ uint64_t eid:4;
+ uint64_t bp_port:6;
+ uint64_t reserved_16_52:37;
+ uint64_t qos_mask:8;
+ uint64_t static_p:1;
+ uint64_t reserved_62_63:2;
+#endif
+ } s;
+ struct cvmx_pko_mem_port_ptrs_s cn52xx;
+ struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
+ struct cvmx_pko_mem_port_ptrs_s cn56xx;
+ struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
+} cvmx_pko_mem_port_ptrs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_port_qos_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_61_63:3;
+ uint64_t qos_mask:8;
+ uint64_t reserved_10_52:43;
+ uint64_t eid:4;
+ uint64_t pid:6;
+#else
+ uint64_t pid:6;
+ uint64_t eid:4;
+ uint64_t reserved_10_52:43;
+ uint64_t qos_mask:8;
+ uint64_t reserved_61_63:3;
+#endif
+ } s;
+ struct cvmx_pko_mem_port_qos_s cn52xx;
+ struct cvmx_pko_mem_port_qos_s cn52xxp1;
+ struct cvmx_pko_mem_port_qos_s cn56xx;
+ struct cvmx_pko_mem_port_qos_s cn56xxp1;
+} cvmx_pko_mem_port_qos_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_port_rate0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_51_63:13;
+ uint64_t rate_word:19;
+ uint64_t rate_pkt:24;
+ uint64_t reserved_6_7:2;
+ uint64_t pid:6;
+#else
+ uint64_t pid:6;
+ uint64_t reserved_6_7:2;
+ uint64_t rate_pkt:24;
+ uint64_t rate_word:19;
+ uint64_t reserved_51_63:13;
+#endif
+ } s;
+ struct cvmx_pko_mem_port_rate0_s cn52xx;
+ struct cvmx_pko_mem_port_rate0_s cn52xxp1;
+ struct cvmx_pko_mem_port_rate0_s cn56xx;
+ struct cvmx_pko_mem_port_rate0_s cn56xxp1;
+} cvmx_pko_mem_port_rate0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_port_rate1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rate_lim:24;
+ uint64_t reserved_6_7:2;
+ uint64_t pid:6;
+#else
+ uint64_t pid:6;
+ uint64_t reserved_6_7:2;
+ uint64_t rate_lim:24;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pko_mem_port_rate1_s cn52xx;
+ struct cvmx_pko_mem_port_rate1_s cn52xxp1;
+ struct cvmx_pko_mem_port_rate1_s cn56xx;
+ struct cvmx_pko_mem_port_rate1_s cn56xxp1;
+} cvmx_pko_mem_port_rate1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_queue_ptrs_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t s_tail:1;
+ uint64_t static_p:1;
+ uint64_t static_q:1;
+ uint64_t qos_mask:8;
+ uint64_t buf_ptr:36;
+ uint64_t tail:1;
+ uint64_t index:3;
+ uint64_t port:6;
+ uint64_t queue:7;
+#else
+ uint64_t queue:7;
+ uint64_t port:6;
+ uint64_t index:3;
+ uint64_t tail:1;
+ uint64_t buf_ptr:36;
+ uint64_t qos_mask:8;
+ uint64_t static_q:1;
+ uint64_t static_p:1;
+ uint64_t s_tail:1;
+#endif
+ } s;
+ struct cvmx_pko_mem_queue_ptrs_s cn30xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn31xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn38xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
+ struct cvmx_pko_mem_queue_ptrs_s cn50xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn52xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
+ struct cvmx_pko_mem_queue_ptrs_s cn56xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
+ struct cvmx_pko_mem_queue_ptrs_s cn58xx;
+ struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
+} cvmx_pko_mem_queue_ptrs_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_mem_queue_qos_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_61_63:3;
+ uint64_t qos_mask:8;
+ uint64_t reserved_13_52:40;
+ uint64_t pid:6;
+ uint64_t qid:7;
+#else
+ uint64_t qid:7;
+ uint64_t pid:6;
+ uint64_t reserved_13_52:40;
+ uint64_t qos_mask:8;
+ uint64_t reserved_61_63:3;
+#endif
+ } s;
+ struct cvmx_pko_mem_queue_qos_s cn30xx;
+ struct cvmx_pko_mem_queue_qos_s cn31xx;
+ struct cvmx_pko_mem_queue_qos_s cn38xx;
+ struct cvmx_pko_mem_queue_qos_s cn38xxp2;
+ struct cvmx_pko_mem_queue_qos_s cn50xx;
+ struct cvmx_pko_mem_queue_qos_s cn52xx;
+ struct cvmx_pko_mem_queue_qos_s cn52xxp1;
+ struct cvmx_pko_mem_queue_qos_s cn56xx;
+ struct cvmx_pko_mem_queue_qos_s cn56xxp1;
+ struct cvmx_pko_mem_queue_qos_s cn58xx;
+ struct cvmx_pko_mem_queue_qos_s cn58xxp1;
+} cvmx_pko_mem_queue_qos_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_bist_result_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_pko_reg_bist_result_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_27_63:37;
+ uint64_t psb2:5;
+ uint64_t count:1;
+ uint64_t rif:1;
+ uint64_t wif:1;
+ uint64_t ncb:1;
+ uint64_t out:1;
+ uint64_t crc:1;
+ uint64_t chk:1;
+ uint64_t qsb:2;
+ uint64_t qcb:2;
+ uint64_t pdb:4;
+ uint64_t psb:7;
+#else
+ uint64_t psb:7;
+ uint64_t pdb:4;
+ uint64_t qcb:2;
+ uint64_t qsb:2;
+ uint64_t chk:1;
+ uint64_t crc:1;
+ uint64_t out:1;
+ uint64_t ncb:1;
+ uint64_t wif:1;
+ uint64_t rif:1;
+ uint64_t count:1;
+ uint64_t psb2:5;
+ uint64_t reserved_27_63:37;
+#endif
+ } cn30xx;
+ struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
+ struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
+ struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
+ struct cvmx_pko_reg_bist_result_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_33_63:31;
+ uint64_t csr:1;
+ uint64_t iob:1;
+ uint64_t out_crc:1;
+ uint64_t out_ctl:3;
+ uint64_t out_sta:1;
+ uint64_t out_wif:1;
+ uint64_t prt_chk:3;
+ uint64_t prt_nxt:1;
+ uint64_t prt_psb:6;
+ uint64_t ncb_inb:2;
+ uint64_t prt_qcb:2;
+ uint64_t prt_qsb:3;
+ uint64_t dat_dat:4;
+ uint64_t dat_ptr:4;
+#else
+ uint64_t dat_ptr:4;
+ uint64_t dat_dat:4;
+ uint64_t prt_qsb:3;
+ uint64_t prt_qcb:2;
+ uint64_t ncb_inb:2;
+ uint64_t prt_psb:6;
+ uint64_t prt_nxt:1;
+ uint64_t prt_chk:3;
+ uint64_t out_wif:1;
+ uint64_t out_sta:1;
+ uint64_t out_ctl:3;
+ uint64_t out_crc:1;
+ uint64_t iob:1;
+ uint64_t csr:1;
+ uint64_t reserved_33_63:31;
+#endif
+ } cn50xx;
+ struct cvmx_pko_reg_bist_result_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_35_63:29;
+ uint64_t csr:1;
+ uint64_t iob:1;
+ uint64_t out_dat:1;
+ uint64_t out_ctl:3;
+ uint64_t out_sta:1;
+ uint64_t out_wif:1;
+ uint64_t prt_chk:3;
+ uint64_t prt_nxt:1;
+ uint64_t prt_psb:8;
+ uint64_t ncb_inb:2;
+ uint64_t prt_qcb:2;
+ uint64_t prt_qsb:3;
+ uint64_t prt_ctl:2;
+ uint64_t dat_dat:2;
+ uint64_t dat_ptr:4;
+#else
+ uint64_t dat_ptr:4;
+ uint64_t dat_dat:2;
+ uint64_t prt_ctl:2;
+ uint64_t prt_qsb:3;
+ uint64_t prt_qcb:2;
+ uint64_t ncb_inb:2;
+ uint64_t prt_psb:8;
+ uint64_t prt_nxt:1;
+ uint64_t prt_chk:3;
+ uint64_t out_wif:1;
+ uint64_t out_sta:1;
+ uint64_t out_ctl:3;
+ uint64_t out_dat:1;
+ uint64_t iob:1;
+ uint64_t csr:1;
+ uint64_t reserved_35_63:29;
+#endif
+ } cn52xx;
+ struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
+ struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
+ struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
+ struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
+ struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
+} cvmx_pko_reg_bist_result_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_cmd_buf_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_23_63:41;
+ uint64_t pool:3;
+ uint64_t reserved_13_19:7;
+ uint64_t size:13;
+#else
+ uint64_t size:13;
+ uint64_t reserved_13_19:7;
+ uint64_t pool:3;
+ uint64_t reserved_23_63:41;
+#endif
+ } s;
+ struct cvmx_pko_reg_cmd_buf_s cn30xx;
+ struct cvmx_pko_reg_cmd_buf_s cn31xx;
+ struct cvmx_pko_reg_cmd_buf_s cn38xx;
+ struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
+ struct cvmx_pko_reg_cmd_buf_s cn50xx;
+ struct cvmx_pko_reg_cmd_buf_s cn52xx;
+ struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
+ struct cvmx_pko_reg_cmd_buf_s cn56xx;
+ struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
+ struct cvmx_pko_reg_cmd_buf_s cn58xx;
+ struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
+} cvmx_pko_reg_cmd_buf_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_crc_ctlx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t invres:1;
+ uint64_t refin:1;
+#else
+ uint64_t refin:1;
+ uint64_t invres:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pko_reg_crc_ctlx_s cn38xx;
+ struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
+ struct cvmx_pko_reg_crc_ctlx_s cn58xx;
+ struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
+} cvmx_pko_reg_crc_ctlx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_crc_enable_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t enable:32;
+#else
+ uint64_t enable:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pko_reg_crc_enable_s cn38xx;
+ struct cvmx_pko_reg_crc_enable_s cn38xxp2;
+ struct cvmx_pko_reg_crc_enable_s cn58xx;
+ struct cvmx_pko_reg_crc_enable_s cn58xxp1;
+} cvmx_pko_reg_crc_enable_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_crc_ivx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iv:32;
+#else
+ uint64_t iv:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pko_reg_crc_ivx_s cn38xx;
+ struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
+ struct cvmx_pko_reg_crc_ivx_s cn58xx;
+ struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
+} cvmx_pko_reg_crc_ivx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t asserts:64;
+#else
+ uint64_t asserts:64;
+#endif
+ } s;
+ struct cvmx_pko_reg_debug0_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t asserts:17;
+#else
+ uint64_t asserts:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn30xx;
+ struct cvmx_pko_reg_debug0_cn30xx cn31xx;
+ struct cvmx_pko_reg_debug0_cn30xx cn38xx;
+ struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
+ struct cvmx_pko_reg_debug0_s cn50xx;
+ struct cvmx_pko_reg_debug0_s cn52xx;
+ struct cvmx_pko_reg_debug0_s cn52xxp1;
+ struct cvmx_pko_reg_debug0_s cn56xx;
+ struct cvmx_pko_reg_debug0_s cn56xxp1;
+ struct cvmx_pko_reg_debug0_s cn58xx;
+ struct cvmx_pko_reg_debug0_s cn58xxp1;
+} cvmx_pko_reg_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_debug1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t asserts:64;
+#else
+ uint64_t asserts:64;
+#endif
+ } s;
+ struct cvmx_pko_reg_debug1_s cn50xx;
+ struct cvmx_pko_reg_debug1_s cn52xx;
+ struct cvmx_pko_reg_debug1_s cn52xxp1;
+ struct cvmx_pko_reg_debug1_s cn56xx;
+ struct cvmx_pko_reg_debug1_s cn56xxp1;
+ struct cvmx_pko_reg_debug1_s cn58xx;
+ struct cvmx_pko_reg_debug1_s cn58xxp1;
+} cvmx_pko_reg_debug1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_debug2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t asserts:64;
+#else
+ uint64_t asserts:64;
+#endif
+ } s;
+ struct cvmx_pko_reg_debug2_s cn50xx;
+ struct cvmx_pko_reg_debug2_s cn52xx;
+ struct cvmx_pko_reg_debug2_s cn52xxp1;
+ struct cvmx_pko_reg_debug2_s cn56xx;
+ struct cvmx_pko_reg_debug2_s cn56xxp1;
+ struct cvmx_pko_reg_debug2_s cn58xx;
+ struct cvmx_pko_reg_debug2_s cn58xxp1;
+} cvmx_pko_reg_debug2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_debug3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t asserts:64;
+#else
+ uint64_t asserts:64;
+#endif
+ } s;
+ struct cvmx_pko_reg_debug3_s cn50xx;
+ struct cvmx_pko_reg_debug3_s cn52xx;
+ struct cvmx_pko_reg_debug3_s cn52xxp1;
+ struct cvmx_pko_reg_debug3_s cn56xx;
+ struct cvmx_pko_reg_debug3_s cn56xxp1;
+ struct cvmx_pko_reg_debug3_s cn58xx;
+ struct cvmx_pko_reg_debug3_s cn58xxp1;
+} cvmx_pko_reg_debug3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_engine_inflight_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t engine9:4;
+ uint64_t engine8:4;
+ uint64_t engine7:4;
+ uint64_t engine6:4;
+ uint64_t engine5:4;
+ uint64_t engine4:4;
+ uint64_t engine3:4;
+ uint64_t engine2:4;
+ uint64_t engine1:4;
+ uint64_t engine0:4;
+#else
+ uint64_t engine0:4;
+ uint64_t engine1:4;
+ uint64_t engine2:4;
+ uint64_t engine3:4;
+ uint64_t engine4:4;
+ uint64_t engine5:4;
+ uint64_t engine6:4;
+ uint64_t engine7:4;
+ uint64_t engine8:4;
+ uint64_t engine9:4;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_pko_reg_engine_inflight_s cn52xx;
+ struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
+ struct cvmx_pko_reg_engine_inflight_s cn56xx;
+ struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
+} cvmx_pko_reg_engine_inflight_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_engine_thresh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t mask:10;
+#else
+ uint64_t mask:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_pko_reg_engine_thresh_s cn52xx;
+ struct cvmx_pko_reg_engine_thresh_s cn52xxp1;
+ struct cvmx_pko_reg_engine_thresh_s cn56xx;
+ struct cvmx_pko_reg_engine_thresh_s cn56xxp1;
+} cvmx_pko_reg_engine_thresh_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_error_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t currzero:1;
+ uint64_t doorbell:1;
+ uint64_t parity:1;
+#else
+ uint64_t parity:1;
+ uint64_t doorbell:1;
+ uint64_t currzero:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_pko_reg_error_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t doorbell:1;
+ uint64_t parity:1;
+#else
+ uint64_t parity:1;
+ uint64_t doorbell:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn30xx;
+ struct cvmx_pko_reg_error_cn30xx cn31xx;
+ struct cvmx_pko_reg_error_cn30xx cn38xx;
+ struct cvmx_pko_reg_error_cn30xx cn38xxp2;
+ struct cvmx_pko_reg_error_s cn50xx;
+ struct cvmx_pko_reg_error_s cn52xx;
+ struct cvmx_pko_reg_error_s cn52xxp1;
+ struct cvmx_pko_reg_error_s cn56xx;
+ struct cvmx_pko_reg_error_s cn56xxp1;
+ struct cvmx_pko_reg_error_s cn58xx;
+ struct cvmx_pko_reg_error_s cn58xxp1;
+} cvmx_pko_reg_error_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_flags_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t reset:1;
+ uint64_t store_be:1;
+ uint64_t ena_dwb:1;
+ uint64_t ena_pko:1;
+#else
+ uint64_t ena_pko:1;
+ uint64_t ena_dwb:1;
+ uint64_t store_be:1;
+ uint64_t reset:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_pko_reg_flags_s cn30xx;
+ struct cvmx_pko_reg_flags_s cn31xx;
+ struct cvmx_pko_reg_flags_s cn38xx;
+ struct cvmx_pko_reg_flags_s cn38xxp2;
+ struct cvmx_pko_reg_flags_s cn50xx;
+ struct cvmx_pko_reg_flags_s cn52xx;
+ struct cvmx_pko_reg_flags_s cn52xxp1;
+ struct cvmx_pko_reg_flags_s cn56xx;
+ struct cvmx_pko_reg_flags_s cn56xxp1;
+ struct cvmx_pko_reg_flags_s cn58xx;
+ struct cvmx_pko_reg_flags_s cn58xxp1;
+} cvmx_pko_reg_flags_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_gmx_port_mode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mode1:3;
+ uint64_t mode0:3;
+#else
+ uint64_t mode0:3;
+ uint64_t mode1:3;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
+ struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
+ struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
+ struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
+ struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
+} cvmx_pko_reg_gmx_port_mode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_int_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t currzero:1;
+ uint64_t doorbell:1;
+ uint64_t parity:1;
+#else
+ uint64_t parity:1;
+ uint64_t doorbell:1;
+ uint64_t currzero:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_pko_reg_int_mask_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t doorbell:1;
+ uint64_t parity:1;
+#else
+ uint64_t parity:1;
+ uint64_t doorbell:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } cn30xx;
+ struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
+ struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
+ struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
+ struct cvmx_pko_reg_int_mask_s cn50xx;
+ struct cvmx_pko_reg_int_mask_s cn52xx;
+ struct cvmx_pko_reg_int_mask_s cn52xxp1;
+ struct cvmx_pko_reg_int_mask_s cn56xx;
+ struct cvmx_pko_reg_int_mask_s cn56xxp1;
+ struct cvmx_pko_reg_int_mask_s cn58xx;
+ struct cvmx_pko_reg_int_mask_s cn58xxp1;
+} cvmx_pko_reg_int_mask_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_queue_mode_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t mode:2;
+#else
+ uint64_t mode:2;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pko_reg_queue_mode_s cn30xx;
+ struct cvmx_pko_reg_queue_mode_s cn31xx;
+ struct cvmx_pko_reg_queue_mode_s cn38xx;
+ struct cvmx_pko_reg_queue_mode_s cn38xxp2;
+ struct cvmx_pko_reg_queue_mode_s cn50xx;
+ struct cvmx_pko_reg_queue_mode_s cn52xx;
+ struct cvmx_pko_reg_queue_mode_s cn52xxp1;
+ struct cvmx_pko_reg_queue_mode_s cn56xx;
+ struct cvmx_pko_reg_queue_mode_s cn56xxp1;
+ struct cvmx_pko_reg_queue_mode_s cn58xx;
+ struct cvmx_pko_reg_queue_mode_s cn58xxp1;
+} cvmx_pko_reg_queue_mode_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_queue_ptrs1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t idx3:1;
+ uint64_t qid7:1;
+#else
+ uint64_t qid7:1;
+ uint64_t idx3:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
+ struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
+ struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
+ struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
+ struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
+ struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
+ struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
+} cvmx_pko_reg_queue_ptrs1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pko_reg_read_idx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t inc:8;
+ uint64_t index:8;
+#else
+ uint64_t index:8;
+ uint64_t inc:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_pko_reg_read_idx_s cn30xx;
+ struct cvmx_pko_reg_read_idx_s cn31xx;
+ struct cvmx_pko_reg_read_idx_s cn38xx;
+ struct cvmx_pko_reg_read_idx_s cn38xxp2;
+ struct cvmx_pko_reg_read_idx_s cn50xx;
+ struct cvmx_pko_reg_read_idx_s cn52xx;
+ struct cvmx_pko_reg_read_idx_s cn52xxp1;
+ struct cvmx_pko_reg_read_idx_s cn56xx;
+ struct cvmx_pko_reg_read_idx_s cn56xxp1;
+ struct cvmx_pko_reg_read_idx_s cn58xx;
+ struct cvmx_pko_reg_read_idx_s cn58xxp1;
+} cvmx_pko_reg_read_idx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_bist_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pp:16;
+ uint64_t reserved_0_15:16;
+#else
+ uint64_t reserved_0_15:16;
+ uint64_t pp:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_bist_stat_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t pp:1;
+ uint64_t reserved_9_15:7;
+ uint64_t cam:1;
+ uint64_t nbt1:1;
+ uint64_t nbt0:1;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t nbr1:1;
+ uint64_t nbr0:1;
+ uint64_t pend:1;
+ uint64_t adr:1;
+#else
+ uint64_t adr:1;
+ uint64_t pend:1;
+ uint64_t nbr0:1;
+ uint64_t nbr1:1;
+ uint64_t fidx:1;
+ uint64_t index:1;
+ uint64_t nbt0:1;
+ uint64_t nbt1:1;
+ uint64_t cam:1;
+ uint64_t reserved_9_15:7;
+ uint64_t pp:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn30xx;
+ struct cvmx_pow_bist_stat_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t pp:2;
+ uint64_t reserved_9_15:7;
+ uint64_t cam:1;
+ uint64_t nbt1:1;
+ uint64_t nbt0:1;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t nbr1:1;
+ uint64_t nbr0:1;
+ uint64_t pend:1;
+ uint64_t adr:1;
+#else
+ uint64_t adr:1;
+ uint64_t pend:1;
+ uint64_t nbr0:1;
+ uint64_t nbr1:1;
+ uint64_t fidx:1;
+ uint64_t index:1;
+ uint64_t nbt0:1;
+ uint64_t nbt1:1;
+ uint64_t cam:1;
+ uint64_t reserved_9_15:7;
+ uint64_t pp:2;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn31xx;
+ struct cvmx_pow_bist_stat_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t pp:16;
+ uint64_t reserved_10_15:6;
+ uint64_t cam:1;
+ uint64_t nbt:1;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t nbr1:1;
+ uint64_t nbr0:1;
+ uint64_t pend1:1;
+ uint64_t pend0:1;
+ uint64_t adr1:1;
+ uint64_t adr0:1;
+#else
+ uint64_t adr0:1;
+ uint64_t adr1:1;
+ uint64_t pend0:1;
+ uint64_t pend1:1;
+ uint64_t nbr0:1;
+ uint64_t nbr1:1;
+ uint64_t fidx:1;
+ uint64_t index:1;
+ uint64_t nbt:1;
+ uint64_t cam:1;
+ uint64_t reserved_10_15:6;
+ uint64_t pp:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } cn38xx;
+ struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
+ struct cvmx_pow_bist_stat_cn31xx cn50xx;
+ struct cvmx_pow_bist_stat_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t pp:4;
+ uint64_t reserved_9_15:7;
+ uint64_t cam:1;
+ uint64_t nbt1:1;
+ uint64_t nbt0:1;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t nbr1:1;
+ uint64_t nbr0:1;
+ uint64_t pend:1;
+ uint64_t adr:1;
+#else
+ uint64_t adr:1;
+ uint64_t pend:1;
+ uint64_t nbr0:1;
+ uint64_t nbr1:1;
+ uint64_t fidx:1;
+ uint64_t index:1;
+ uint64_t nbt0:1;
+ uint64_t nbt1:1;
+ uint64_t cam:1;
+ uint64_t reserved_9_15:7;
+ uint64_t pp:4;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn52xx;
+ struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
+ struct cvmx_pow_bist_stat_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t pp:12;
+ uint64_t reserved_10_15:6;
+ uint64_t cam:1;
+ uint64_t nbt:1;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t nbr1:1;
+ uint64_t nbr0:1;
+ uint64_t pend1:1;
+ uint64_t pend0:1;
+ uint64_t adr1:1;
+ uint64_t adr0:1;
+#else
+ uint64_t adr0:1;
+ uint64_t adr1:1;
+ uint64_t pend0:1;
+ uint64_t pend1:1;
+ uint64_t nbr0:1;
+ uint64_t nbr1:1;
+ uint64_t fidx:1;
+ uint64_t index:1;
+ uint64_t nbt:1;
+ uint64_t cam:1;
+ uint64_t reserved_10_15:6;
+ uint64_t pp:12;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn56xx;
+ struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
+ struct cvmx_pow_bist_stat_cn38xx cn58xx;
+ struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
+} cvmx_pow_bist_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_ds_pc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ds_pc:32;
+#else
+ uint64_t ds_pc:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_ds_pc_s cn30xx;
+ struct cvmx_pow_ds_pc_s cn31xx;
+ struct cvmx_pow_ds_pc_s cn38xx;
+ struct cvmx_pow_ds_pc_s cn38xxp2;
+ struct cvmx_pow_ds_pc_s cn50xx;
+ struct cvmx_pow_ds_pc_s cn52xx;
+ struct cvmx_pow_ds_pc_s cn52xxp1;
+ struct cvmx_pow_ds_pc_s cn56xx;
+ struct cvmx_pow_ds_pc_s cn56xxp1;
+ struct cvmx_pow_ds_pc_s cn58xx;
+ struct cvmx_pow_ds_pc_s cn58xxp1;
+} cvmx_pow_ds_pc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_ecc_err_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_45_63:19;
+ uint64_t iop_ie:13;
+ uint64_t reserved_29_31:3;
+ uint64_t iop:13;
+ uint64_t reserved_14_15:2;
+ uint64_t rpe_ie:1;
+ uint64_t rpe:1;
+ uint64_t reserved_9_11:3;
+ uint64_t syn:5;
+ uint64_t dbe_ie:1;
+ uint64_t sbe_ie:1;
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+#else
+ uint64_t sbe:1;
+ uint64_t dbe:1;
+ uint64_t sbe_ie:1;
+ uint64_t dbe_ie:1;
+ uint64_t syn:5;
+ uint64_t reserved_9_11:3;
+ uint64_t rpe:1;
+ uint64_t rpe_ie:1;
+ uint64_t reserved_14_15:2;
+ uint64_t iop:13;
+ uint64_t reserved_29_31:3;
+ uint64_t iop_ie:13;
+ uint64_t reserved_45_63:19;
+#endif
+ } s;
+ struct cvmx_pow_ecc_err_s cn30xx;
+ struct cvmx_pow_ecc_err_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t rpe_ie:1;
+ uint64_t rpe:1;
+ uint64_t reserved_9_11:3;
+ uint64_t syn:5;
+ uint64_t dbe_ie:1;
+ uint64_t sbe_ie:1;
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+#else
+ uint64_t sbe:1;
+ uint64_t dbe:1;
+ uint64_t sbe_ie:1;
+ uint64_t dbe_ie:1;
+ uint64_t syn:5;
+ uint64_t reserved_9_11:3;
+ uint64_t rpe:1;
+ uint64_t rpe_ie:1;
+ uint64_t reserved_14_63:50;
+#endif
+ } cn31xx;
+ struct cvmx_pow_ecc_err_s cn38xx;
+ struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
+ struct cvmx_pow_ecc_err_s cn50xx;
+ struct cvmx_pow_ecc_err_s cn52xx;
+ struct cvmx_pow_ecc_err_s cn52xxp1;
+ struct cvmx_pow_ecc_err_s cn56xx;
+ struct cvmx_pow_ecc_err_s cn56xxp1;
+ struct cvmx_pow_ecc_err_s cn58xx;
+ struct cvmx_pow_ecc_err_s cn58xxp1;
+} cvmx_pow_ecc_err_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_int_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t pfr_dis:1;
+ uint64_t nbr_thr:5;
+#else
+ uint64_t nbr_thr:5;
+ uint64_t pfr_dis:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_pow_int_ctl_s cn30xx;
+ struct cvmx_pow_int_ctl_s cn31xx;
+ struct cvmx_pow_int_ctl_s cn38xx;
+ struct cvmx_pow_int_ctl_s cn38xxp2;
+ struct cvmx_pow_int_ctl_s cn50xx;
+ struct cvmx_pow_int_ctl_s cn52xx;
+ struct cvmx_pow_int_ctl_s cn52xxp1;
+ struct cvmx_pow_int_ctl_s cn56xx;
+ struct cvmx_pow_int_ctl_s cn56xxp1;
+ struct cvmx_pow_int_ctl_s cn58xx;
+ struct cvmx_pow_int_ctl_s cn58xxp1;
+} cvmx_pow_int_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_iq_cntx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iq_cnt:32;
+#else
+ uint64_t iq_cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_iq_cntx_s cn30xx;
+ struct cvmx_pow_iq_cntx_s cn31xx;
+ struct cvmx_pow_iq_cntx_s cn38xx;
+ struct cvmx_pow_iq_cntx_s cn38xxp2;
+ struct cvmx_pow_iq_cntx_s cn50xx;
+ struct cvmx_pow_iq_cntx_s cn52xx;
+ struct cvmx_pow_iq_cntx_s cn52xxp1;
+ struct cvmx_pow_iq_cntx_s cn56xx;
+ struct cvmx_pow_iq_cntx_s cn56xxp1;
+ struct cvmx_pow_iq_cntx_s cn58xx;
+ struct cvmx_pow_iq_cntx_s cn58xxp1;
+} cvmx_pow_iq_cntx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_iq_com_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iq_cnt:32;
+#else
+ uint64_t iq_cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_iq_com_cnt_s cn30xx;
+ struct cvmx_pow_iq_com_cnt_s cn31xx;
+ struct cvmx_pow_iq_com_cnt_s cn38xx;
+ struct cvmx_pow_iq_com_cnt_s cn38xxp2;
+ struct cvmx_pow_iq_com_cnt_s cn50xx;
+ struct cvmx_pow_iq_com_cnt_s cn52xx;
+ struct cvmx_pow_iq_com_cnt_s cn52xxp1;
+ struct cvmx_pow_iq_com_cnt_s cn56xx;
+ struct cvmx_pow_iq_com_cnt_s cn56xxp1;
+ struct cvmx_pow_iq_com_cnt_s cn58xx;
+ struct cvmx_pow_iq_com_cnt_s cn58xxp1;
+} cvmx_pow_iq_com_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_iq_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t iq_int:8;
+#else
+ uint64_t iq_int:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pow_iq_int_s cn52xx;
+ struct cvmx_pow_iq_int_s cn52xxp1;
+ struct cvmx_pow_iq_int_s cn56xx;
+ struct cvmx_pow_iq_int_s cn56xxp1;
+} cvmx_pow_iq_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_iq_int_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t int_en:8;
+#else
+ uint64_t int_en:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pow_iq_int_en_s cn52xx;
+ struct cvmx_pow_iq_int_en_s cn52xxp1;
+ struct cvmx_pow_iq_int_en_s cn56xx;
+ struct cvmx_pow_iq_int_en_s cn56xxp1;
+} cvmx_pow_iq_int_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_iq_thrx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iq_thr:32;
+#else
+ uint64_t iq_thr:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_iq_thrx_s cn52xx;
+ struct cvmx_pow_iq_thrx_s cn52xxp1;
+ struct cvmx_pow_iq_thrx_s cn56xx;
+ struct cvmx_pow_iq_thrx_s cn56xxp1;
+} cvmx_pow_iq_thrx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_nos_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t nos_cnt:12;
+#else
+ uint64_t nos_cnt:12;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_pow_nos_cnt_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t nos_cnt:7;
+#else
+ uint64_t nos_cnt:7;
+ uint64_t reserved_7_63:57;
+#endif
+ } cn30xx;
+ struct cvmx_pow_nos_cnt_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t nos_cnt:9;
+#else
+ uint64_t nos_cnt:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } cn31xx;
+ struct cvmx_pow_nos_cnt_s cn38xx;
+ struct cvmx_pow_nos_cnt_s cn38xxp2;
+ struct cvmx_pow_nos_cnt_cn31xx cn50xx;
+ struct cvmx_pow_nos_cnt_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t nos_cnt:10;
+#else
+ uint64_t nos_cnt:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } cn52xx;
+ struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
+ struct cvmx_pow_nos_cnt_s cn56xx;
+ struct cvmx_pow_nos_cnt_s cn56xxp1;
+ struct cvmx_pow_nos_cnt_s cn58xx;
+ struct cvmx_pow_nos_cnt_s cn58xxp1;
+} cvmx_pow_nos_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_nw_tim_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_10_63:54;
+ uint64_t nw_tim:10;
+#else
+ uint64_t nw_tim:10;
+ uint64_t reserved_10_63:54;
+#endif
+ } s;
+ struct cvmx_pow_nw_tim_s cn30xx;
+ struct cvmx_pow_nw_tim_s cn31xx;
+ struct cvmx_pow_nw_tim_s cn38xx;
+ struct cvmx_pow_nw_tim_s cn38xxp2;
+ struct cvmx_pow_nw_tim_s cn50xx;
+ struct cvmx_pow_nw_tim_s cn52xx;
+ struct cvmx_pow_nw_tim_s cn52xxp1;
+ struct cvmx_pow_nw_tim_s cn56xx;
+ struct cvmx_pow_nw_tim_s cn56xxp1;
+ struct cvmx_pow_nw_tim_s cn58xx;
+ struct cvmx_pow_nw_tim_s cn58xxp1;
+} cvmx_pow_nw_tim_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_pf_rst_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t rst_msk:8;
+#else
+ uint64_t rst_msk:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_pow_pf_rst_msk_s cn50xx;
+ struct cvmx_pow_pf_rst_msk_s cn52xx;
+ struct cvmx_pow_pf_rst_msk_s cn52xxp1;
+ struct cvmx_pow_pf_rst_msk_s cn56xx;
+ struct cvmx_pow_pf_rst_msk_s cn56xxp1;
+ struct cvmx_pow_pf_rst_msk_s cn58xx;
+ struct cvmx_pow_pf_rst_msk_s cn58xxp1;
+} cvmx_pow_pf_rst_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_pp_grp_mskx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t qos7_pri:4;
+ uint64_t qos6_pri:4;
+ uint64_t qos5_pri:4;
+ uint64_t qos4_pri:4;
+ uint64_t qos3_pri:4;
+ uint64_t qos2_pri:4;
+ uint64_t qos1_pri:4;
+ uint64_t qos0_pri:4;
+ uint64_t grp_msk:16;
+#else
+ uint64_t grp_msk:16;
+ uint64_t qos0_pri:4;
+ uint64_t qos1_pri:4;
+ uint64_t qos2_pri:4;
+ uint64_t qos3_pri:4;
+ uint64_t qos4_pri:4;
+ uint64_t qos5_pri:4;
+ uint64_t qos6_pri:4;
+ uint64_t qos7_pri:4;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_pow_pp_grp_mskx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t grp_msk:16;
+#else
+ uint64_t grp_msk:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn30xx;
+ struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
+ struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
+ struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
+ struct cvmx_pow_pp_grp_mskx_s cn50xx;
+ struct cvmx_pow_pp_grp_mskx_s cn52xx;
+ struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
+ struct cvmx_pow_pp_grp_mskx_s cn56xx;
+ struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
+ struct cvmx_pow_pp_grp_mskx_s cn58xx;
+ struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
+} cvmx_pow_pp_grp_mskx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_qos_rndx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t rnd_p3:8;
+ uint64_t rnd_p2:8;
+ uint64_t rnd_p1:8;
+ uint64_t rnd:8;
+#else
+ uint64_t rnd:8;
+ uint64_t rnd_p1:8;
+ uint64_t rnd_p2:8;
+ uint64_t rnd_p3:8;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_qos_rndx_s cn30xx;
+ struct cvmx_pow_qos_rndx_s cn31xx;
+ struct cvmx_pow_qos_rndx_s cn38xx;
+ struct cvmx_pow_qos_rndx_s cn38xxp2;
+ struct cvmx_pow_qos_rndx_s cn50xx;
+ struct cvmx_pow_qos_rndx_s cn52xx;
+ struct cvmx_pow_qos_rndx_s cn52xxp1;
+ struct cvmx_pow_qos_rndx_s cn56xx;
+ struct cvmx_pow_qos_rndx_s cn56xxp1;
+ struct cvmx_pow_qos_rndx_s cn58xx;
+ struct cvmx_pow_qos_rndx_s cn58xxp1;
+} cvmx_pow_qos_rndx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_qos_thrx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_60_63:4;
+ uint64_t des_cnt:12;
+ uint64_t buf_cnt:12;
+ uint64_t free_cnt:12;
+ uint64_t reserved_23_23:1;
+ uint64_t max_thr:11;
+ uint64_t reserved_11_11:1;
+ uint64_t min_thr:11;
+#else
+ uint64_t min_thr:11;
+ uint64_t reserved_11_11:1;
+ uint64_t max_thr:11;
+ uint64_t reserved_23_23:1;
+ uint64_t free_cnt:12;
+ uint64_t buf_cnt:12;
+ uint64_t des_cnt:12;
+ uint64_t reserved_60_63:4;
+#endif
+ } s;
+ struct cvmx_pow_qos_thrx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_55_63:9;
+ uint64_t des_cnt:7;
+ uint64_t reserved_43_47:5;
+ uint64_t buf_cnt:7;
+ uint64_t reserved_31_35:5;
+ uint64_t free_cnt:7;
+ uint64_t reserved_18_23:6;
+ uint64_t max_thr:6;
+ uint64_t reserved_6_11:6;
+ uint64_t min_thr:6;
+#else
+ uint64_t min_thr:6;
+ uint64_t reserved_6_11:6;
+ uint64_t max_thr:6;
+ uint64_t reserved_18_23:6;
+ uint64_t free_cnt:7;
+ uint64_t reserved_31_35:5;
+ uint64_t buf_cnt:7;
+ uint64_t reserved_43_47:5;
+ uint64_t des_cnt:7;
+ uint64_t reserved_55_63:9;
+#endif
+ } cn30xx;
+ struct cvmx_pow_qos_thrx_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_57_63:7;
+ uint64_t des_cnt:9;
+ uint64_t reserved_45_47:3;
+ uint64_t buf_cnt:9;
+ uint64_t reserved_33_35:3;
+ uint64_t free_cnt:9;
+ uint64_t reserved_20_23:4;
+ uint64_t max_thr:8;
+ uint64_t reserved_8_11:4;
+ uint64_t min_thr:8;
+#else
+ uint64_t min_thr:8;
+ uint64_t reserved_8_11:4;
+ uint64_t max_thr:8;
+ uint64_t reserved_20_23:4;
+ uint64_t free_cnt:9;
+ uint64_t reserved_33_35:3;
+ uint64_t buf_cnt:9;
+ uint64_t reserved_45_47:3;
+ uint64_t des_cnt:9;
+ uint64_t reserved_57_63:7;
+#endif
+ } cn31xx;
+ struct cvmx_pow_qos_thrx_s cn38xx;
+ struct cvmx_pow_qos_thrx_s cn38xxp2;
+ struct cvmx_pow_qos_thrx_cn31xx cn50xx;
+ struct cvmx_pow_qos_thrx_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_58_63:6;
+ uint64_t des_cnt:10;
+ uint64_t reserved_46_47:2;
+ uint64_t buf_cnt:10;
+ uint64_t reserved_34_35:2;
+ uint64_t free_cnt:10;
+ uint64_t reserved_21_23:3;
+ uint64_t max_thr:9;
+ uint64_t reserved_9_11:3;
+ uint64_t min_thr:9;
+#else
+ uint64_t min_thr:9;
+ uint64_t reserved_9_11:3;
+ uint64_t max_thr:9;
+ uint64_t reserved_21_23:3;
+ uint64_t free_cnt:10;
+ uint64_t reserved_34_35:2;
+ uint64_t buf_cnt:10;
+ uint64_t reserved_46_47:2;
+ uint64_t des_cnt:10;
+ uint64_t reserved_58_63:6;
+#endif
+ } cn52xx;
+ struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
+ struct cvmx_pow_qos_thrx_s cn56xx;
+ struct cvmx_pow_qos_thrx_s cn56xxp1;
+ struct cvmx_pow_qos_thrx_s cn58xx;
+ struct cvmx_pow_qos_thrx_s cn58xxp1;
+} cvmx_pow_qos_thrx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_ts_pc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ts_pc:32;
+#else
+ uint64_t ts_pc:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_ts_pc_s cn30xx;
+ struct cvmx_pow_ts_pc_s cn31xx;
+ struct cvmx_pow_ts_pc_s cn38xx;
+ struct cvmx_pow_ts_pc_s cn38xxp2;
+ struct cvmx_pow_ts_pc_s cn50xx;
+ struct cvmx_pow_ts_pc_s cn52xx;
+ struct cvmx_pow_ts_pc_s cn52xxp1;
+ struct cvmx_pow_ts_pc_s cn56xx;
+ struct cvmx_pow_ts_pc_s cn56xxp1;
+ struct cvmx_pow_ts_pc_s cn58xx;
+ struct cvmx_pow_ts_pc_s cn58xxp1;
+} cvmx_pow_ts_pc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wa_com_pc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wa_pc:32;
+#else
+ uint64_t wa_pc:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_wa_com_pc_s cn30xx;
+ struct cvmx_pow_wa_com_pc_s cn31xx;
+ struct cvmx_pow_wa_com_pc_s cn38xx;
+ struct cvmx_pow_wa_com_pc_s cn38xxp2;
+ struct cvmx_pow_wa_com_pc_s cn50xx;
+ struct cvmx_pow_wa_com_pc_s cn52xx;
+ struct cvmx_pow_wa_com_pc_s cn52xxp1;
+ struct cvmx_pow_wa_com_pc_s cn56xx;
+ struct cvmx_pow_wa_com_pc_s cn56xxp1;
+ struct cvmx_pow_wa_com_pc_s cn58xx;
+ struct cvmx_pow_wa_com_pc_s cn58xxp1;
+} cvmx_pow_wa_com_pc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wa_pcx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t wa_pc:32;
+#else
+ uint64_t wa_pc:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_wa_pcx_s cn30xx;
+ struct cvmx_pow_wa_pcx_s cn31xx;
+ struct cvmx_pow_wa_pcx_s cn38xx;
+ struct cvmx_pow_wa_pcx_s cn38xxp2;
+ struct cvmx_pow_wa_pcx_s cn50xx;
+ struct cvmx_pow_wa_pcx_s cn52xx;
+ struct cvmx_pow_wa_pcx_s cn52xxp1;
+ struct cvmx_pow_wa_pcx_s cn56xx;
+ struct cvmx_pow_wa_pcx_s cn56xxp1;
+ struct cvmx_pow_wa_pcx_s cn58xx;
+ struct cvmx_pow_wa_pcx_s cn58xxp1;
+} cvmx_pow_wa_pcx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wq_int_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t iq_dis:16;
+ uint64_t wq_int:16;
+#else
+ uint64_t wq_int:16;
+ uint64_t iq_dis:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_wq_int_s cn30xx;
+ struct cvmx_pow_wq_int_s cn31xx;
+ struct cvmx_pow_wq_int_s cn38xx;
+ struct cvmx_pow_wq_int_s cn38xxp2;
+ struct cvmx_pow_wq_int_s cn50xx;
+ struct cvmx_pow_wq_int_s cn52xx;
+ struct cvmx_pow_wq_int_s cn52xxp1;
+ struct cvmx_pow_wq_int_s cn56xx;
+ struct cvmx_pow_wq_int_s cn56xxp1;
+ struct cvmx_pow_wq_int_s cn58xx;
+ struct cvmx_pow_wq_int_s cn58xxp1;
+} cvmx_pow_wq_int_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wq_int_cntx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t ds_cnt:12;
+ uint64_t iq_cnt:12;
+#else
+ uint64_t iq_cnt:12;
+ uint64_t ds_cnt:12;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_28_63:36;
+#endif
+ } s;
+ struct cvmx_pow_wq_int_cntx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_19_23:5;
+ uint64_t ds_cnt:7;
+ uint64_t reserved_7_11:5;
+ uint64_t iq_cnt:7;
+#else
+ uint64_t iq_cnt:7;
+ uint64_t reserved_7_11:5;
+ uint64_t ds_cnt:7;
+ uint64_t reserved_19_23:5;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn30xx;
+ struct cvmx_pow_wq_int_cntx_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_21_23:3;
+ uint64_t ds_cnt:9;
+ uint64_t reserved_9_11:3;
+ uint64_t iq_cnt:9;
+#else
+ uint64_t iq_cnt:9;
+ uint64_t reserved_9_11:3;
+ uint64_t ds_cnt:9;
+ uint64_t reserved_21_23:3;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn31xx;
+ struct cvmx_pow_wq_int_cntx_s cn38xx;
+ struct cvmx_pow_wq_int_cntx_s cn38xxp2;
+ struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
+ struct cvmx_pow_wq_int_cntx_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_22_23:2;
+ uint64_t ds_cnt:10;
+ uint64_t reserved_10_11:2;
+ uint64_t iq_cnt:10;
+#else
+ uint64_t iq_cnt:10;
+ uint64_t reserved_10_11:2;
+ uint64_t ds_cnt:10;
+ uint64_t reserved_22_23:2;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_28_63:36;
+#endif
+ } cn52xx;
+ struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
+ struct cvmx_pow_wq_int_cntx_s cn56xx;
+ struct cvmx_pow_wq_int_cntx_s cn56xxp1;
+ struct cvmx_pow_wq_int_cntx_s cn58xx;
+ struct cvmx_pow_wq_int_cntx_s cn58xxp1;
+} cvmx_pow_wq_int_cntx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wq_int_pc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_60_63:4;
+ uint64_t pc:28;
+ uint64_t reserved_28_31:4;
+ uint64_t pc_thr:20;
+ uint64_t reserved_0_7:8;
+#else
+ uint64_t reserved_0_7:8;
+ uint64_t pc_thr:20;
+ uint64_t reserved_28_31:4;
+ uint64_t pc:28;
+ uint64_t reserved_60_63:4;
+#endif
+ } s;
+ struct cvmx_pow_wq_int_pc_s cn30xx;
+ struct cvmx_pow_wq_int_pc_s cn31xx;
+ struct cvmx_pow_wq_int_pc_s cn38xx;
+ struct cvmx_pow_wq_int_pc_s cn38xxp2;
+ struct cvmx_pow_wq_int_pc_s cn50xx;
+ struct cvmx_pow_wq_int_pc_s cn52xx;
+ struct cvmx_pow_wq_int_pc_s cn52xxp1;
+ struct cvmx_pow_wq_int_pc_s cn56xx;
+ struct cvmx_pow_wq_int_pc_s cn56xxp1;
+ struct cvmx_pow_wq_int_pc_s cn58xx;
+ struct cvmx_pow_wq_int_pc_s cn58xxp1;
+} cvmx_pow_wq_int_pc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_wq_int_thrx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_23_23:1;
+ uint64_t ds_thr:11;
+ uint64_t reserved_11_11:1;
+ uint64_t iq_thr:11;
+#else
+ uint64_t iq_thr:11;
+ uint64_t reserved_11_11:1;
+ uint64_t ds_thr:11;
+ uint64_t reserved_23_23:1;
+ uint64_t tc_thr:4;
+ uint64_t tc_en:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } s;
+ struct cvmx_pow_wq_int_thrx_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_18_23:6;
+ uint64_t ds_thr:6;
+ uint64_t reserved_6_11:6;
+ uint64_t iq_thr:6;
+#else
+ uint64_t iq_thr:6;
+ uint64_t reserved_6_11:6;
+ uint64_t ds_thr:6;
+ uint64_t reserved_18_23:6;
+ uint64_t tc_thr:4;
+ uint64_t tc_en:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn30xx;
+ struct cvmx_pow_wq_int_thrx_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_20_23:4;
+ uint64_t ds_thr:8;
+ uint64_t reserved_8_11:4;
+ uint64_t iq_thr:8;
+#else
+ uint64_t iq_thr:8;
+ uint64_t reserved_8_11:4;
+ uint64_t ds_thr:8;
+ uint64_t reserved_20_23:4;
+ uint64_t tc_thr:4;
+ uint64_t tc_en:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn31xx;
+ struct cvmx_pow_wq_int_thrx_s cn38xx;
+ struct cvmx_pow_wq_int_thrx_s cn38xxp2;
+ struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
+ struct cvmx_pow_wq_int_thrx_cn52xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_21_23:3;
+ uint64_t ds_thr:9;
+ uint64_t reserved_9_11:3;
+ uint64_t iq_thr:9;
+#else
+ uint64_t iq_thr:9;
+ uint64_t reserved_9_11:3;
+ uint64_t ds_thr:9;
+ uint64_t reserved_21_23:3;
+ uint64_t tc_thr:4;
+ uint64_t tc_en:1;
+ uint64_t reserved_29_63:35;
+#endif
+ } cn52xx;
+ struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
+ struct cvmx_pow_wq_int_thrx_s cn56xx;
+ struct cvmx_pow_wq_int_thrx_s cn56xxp1;
+ struct cvmx_pow_wq_int_thrx_s cn58xx;
+ struct cvmx_pow_wq_int_thrx_s cn58xxp1;
+} cvmx_pow_wq_int_thrx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_pow_ws_pcx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t ws_pc:32;
+#else
+ uint64_t ws_pc:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_pow_ws_pcx_s cn30xx;
+ struct cvmx_pow_ws_pcx_s cn31xx;
+ struct cvmx_pow_ws_pcx_s cn38xx;
+ struct cvmx_pow_ws_pcx_s cn38xxp2;
+ struct cvmx_pow_ws_pcx_s cn50xx;
+ struct cvmx_pow_ws_pcx_s cn52xx;
+ struct cvmx_pow_ws_pcx_s cn52xxp1;
+ struct cvmx_pow_ws_pcx_s cn56xx;
+ struct cvmx_pow_ws_pcx_s cn56xxp1;
+ struct cvmx_pow_ws_pcx_s cn58xx;
+ struct cvmx_pow_ws_pcx_s cn58xxp1;
+} cvmx_pow_ws_pcx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_mem_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t iword:64;
+#else
+ uint64_t iword:64;
+#endif
+ } s;
+ struct cvmx_rad_mem_debug0_s cn52xx;
+ struct cvmx_rad_mem_debug0_s cn52xxp1;
+ struct cvmx_rad_mem_debug0_s cn56xx;
+ struct cvmx_rad_mem_debug0_s cn56xxp1;
+} cvmx_rad_mem_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_mem_debug1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t p_dat:64;
+#else
+ uint64_t p_dat:64;
+#endif
+ } s;
+ struct cvmx_rad_mem_debug1_s cn52xx;
+ struct cvmx_rad_mem_debug1_s cn52xxp1;
+ struct cvmx_rad_mem_debug1_s cn56xx;
+ struct cvmx_rad_mem_debug1_s cn56xxp1;
+} cvmx_rad_mem_debug1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_mem_debug2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t q_dat:64;
+#else
+ uint64_t q_dat:64;
+#endif
+ } s;
+ struct cvmx_rad_mem_debug2_s cn52xx;
+ struct cvmx_rad_mem_debug2_s cn52xxp1;
+ struct cvmx_rad_mem_debug2_s cn56xx;
+ struct cvmx_rad_mem_debug2_s cn56xxp1;
+} cvmx_rad_mem_debug2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_bist_result_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t sta:1;
+ uint64_t ncb_oub:1;
+ uint64_t ncb_inb:2;
+ uint64_t dat:2;
+#else
+ uint64_t dat:2;
+ uint64_t ncb_inb:2;
+ uint64_t ncb_oub:1;
+ uint64_t sta:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_rad_reg_bist_result_s cn52xx;
+ struct cvmx_rad_reg_bist_result_s cn52xxp1;
+ struct cvmx_rad_reg_bist_result_s cn56xx;
+ struct cvmx_rad_reg_bist_result_s cn56xxp1;
+} cvmx_rad_reg_bist_result_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_cmd_buf_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_58_63:6;
+ uint64_t dwb:9;
+ uint64_t pool:3;
+ uint64_t size:13;
+ uint64_t ptr:33;
+#else
+ uint64_t ptr:33;
+ uint64_t size:13;
+ uint64_t pool:3;
+ uint64_t dwb:9;
+ uint64_t reserved_58_63:6;
+#endif
+ } s;
+ struct cvmx_rad_reg_cmd_buf_s cn52xx;
+ struct cvmx_rad_reg_cmd_buf_s cn52xxp1;
+ struct cvmx_rad_reg_cmd_buf_s cn56xx;
+ struct cvmx_rad_reg_cmd_buf_s cn56xxp1;
+} cvmx_rad_reg_cmd_buf_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t max_read:4;
+ uint64_t store_le:1;
+ uint64_t reset:1;
+#else
+ uint64_t reset:1;
+ uint64_t store_le:1;
+ uint64_t max_read:4;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_rad_reg_ctl_s cn52xx;
+ struct cvmx_rad_reg_ctl_s cn52xxp1;
+ struct cvmx_rad_reg_ctl_s cn56xx;
+ struct cvmx_rad_reg_ctl_s cn56xxp1;
+} cvmx_rad_reg_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_57_63:7;
+ uint64_t loop:25;
+ uint64_t reserved_22_31:10;
+ uint64_t iridx:6;
+ uint64_t reserved_14_15:2;
+ uint64_t iwidx:6;
+ uint64_t owordqv:1;
+ uint64_t owordpv:1;
+ uint64_t commit:1;
+ uint64_t state:5;
+#else
+ uint64_t state:5;
+ uint64_t commit:1;
+ uint64_t owordpv:1;
+ uint64_t owordqv:1;
+ uint64_t iwidx:6;
+ uint64_t reserved_14_15:2;
+ uint64_t iridx:6;
+ uint64_t reserved_22_31:10;
+ uint64_t loop:25;
+ uint64_t reserved_57_63:7;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug0_s cn52xx;
+ struct cvmx_rad_reg_debug0_s cn52xxp1;
+ struct cvmx_rad_reg_debug0_s cn56xx;
+ struct cvmx_rad_reg_debug0_s cn56xxp1;
+} cvmx_rad_reg_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cword:64;
+#else
+ uint64_t cword:64;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug1_s cn52xx;
+ struct cvmx_rad_reg_debug1_s cn52xxp1;
+ struct cvmx_rad_reg_debug1_s cn56xx;
+ struct cvmx_rad_reg_debug1_s cn56xxp1;
+} cvmx_rad_reg_debug1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug10_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t flags:8;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t flags:8;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug10_s cn52xx;
+ struct cvmx_rad_reg_debug10_s cn52xxp1;
+ struct cvmx_rad_reg_debug10_s cn56xx;
+ struct cvmx_rad_reg_debug10_s cn56xxp1;
+} cvmx_rad_reg_debug10_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug11_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t q:1;
+ uint64_t p:1;
+ uint64_t wc:1;
+ uint64_t eod:1;
+ uint64_t sod:1;
+ uint64_t index:8;
+#else
+ uint64_t index:8;
+ uint64_t sod:1;
+ uint64_t eod:1;
+ uint64_t wc:1;
+ uint64_t p:1;
+ uint64_t q:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug11_s cn52xx;
+ struct cvmx_rad_reg_debug11_s cn52xxp1;
+ struct cvmx_rad_reg_debug11_s cn56xx;
+ struct cvmx_rad_reg_debug11_s cn56xxp1;
+} cvmx_rad_reg_debug11_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug12_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t asserts:15;
+#else
+ uint64_t asserts:15;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug12_s cn52xx;
+ struct cvmx_rad_reg_debug12_s cn52xxp1;
+ struct cvmx_rad_reg_debug12_s cn56xx;
+ struct cvmx_rad_reg_debug12_s cn56xxp1;
+} cvmx_rad_reg_debug12_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t owordp:64;
+#else
+ uint64_t owordp:64;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug2_s cn52xx;
+ struct cvmx_rad_reg_debug2_s cn52xxp1;
+ struct cvmx_rad_reg_debug2_s cn56xx;
+ struct cvmx_rad_reg_debug2_s cn56xxp1;
+} cvmx_rad_reg_debug2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t owordq:64;
+#else
+ uint64_t owordq:64;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug3_s cn52xx;
+ struct cvmx_rad_reg_debug3_s cn52xxp1;
+ struct cvmx_rad_reg_debug3_s cn56xx;
+ struct cvmx_rad_reg_debug3_s cn56xxp1;
+} cvmx_rad_reg_debug3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t rword:64;
+#else
+ uint64_t rword:64;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug4_s cn52xx;
+ struct cvmx_rad_reg_debug4_s cn52xxp1;
+ struct cvmx_rad_reg_debug4_s cn56xx;
+ struct cvmx_rad_reg_debug4_s cn56xxp1;
+} cvmx_rad_reg_debug4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_53_63:11;
+ uint64_t niropc7:3;
+ uint64_t nirque7:2;
+ uint64_t nirval7:5;
+ uint64_t niropc6:3;
+ uint64_t nirque6:2;
+ uint64_t nirarb6:1;
+ uint64_t nirval6:5;
+ uint64_t niridx1:4;
+ uint64_t niwidx1:4;
+ uint64_t niridx0:4;
+ uint64_t niwidx0:4;
+ uint64_t wccreds:2;
+ uint64_t fpacreds:2;
+ uint64_t reserved_10_11:2;
+ uint64_t powcreds:2;
+ uint64_t n1creds:4;
+ uint64_t n0creds:4;
+#else
+ uint64_t n0creds:4;
+ uint64_t n1creds:4;
+ uint64_t powcreds:2;
+ uint64_t reserved_10_11:2;
+ uint64_t fpacreds:2;
+ uint64_t wccreds:2;
+ uint64_t niwidx0:4;
+ uint64_t niridx0:4;
+ uint64_t niwidx1:4;
+ uint64_t niridx1:4;
+ uint64_t nirval6:5;
+ uint64_t nirarb6:1;
+ uint64_t nirque6:2;
+ uint64_t niropc6:3;
+ uint64_t nirval7:5;
+ uint64_t nirque7:2;
+ uint64_t niropc7:3;
+ uint64_t reserved_53_63:11;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug5_s cn52xx;
+ struct cvmx_rad_reg_debug5_s cn52xxp1;
+ struct cvmx_rad_reg_debug5_s cn56xx;
+ struct cvmx_rad_reg_debug5_s cn56xxp1;
+} cvmx_rad_reg_debug5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cnt:8;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t cnt:8;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug6_s cn52xx;
+ struct cvmx_rad_reg_debug6_s cn52xxp1;
+ struct cvmx_rad_reg_debug6_s cn56xx;
+ struct cvmx_rad_reg_debug6_s cn56xxp1;
+} cvmx_rad_reg_debug6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t cnt:15;
+#else
+ uint64_t cnt:15;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug7_s cn52xx;
+ struct cvmx_rad_reg_debug7_s cn52xxp1;
+ struct cvmx_rad_reg_debug7_s cn56xx;
+ struct cvmx_rad_reg_debug7_s cn56xxp1;
+} cvmx_rad_reg_debug7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug8_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t flags:8;
+ uint64_t size:16;
+ uint64_t ptr:40;
+#else
+ uint64_t ptr:40;
+ uint64_t size:16;
+ uint64_t flags:8;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug8_s cn52xx;
+ struct cvmx_rad_reg_debug8_s cn52xxp1;
+ struct cvmx_rad_reg_debug8_s cn56xx;
+ struct cvmx_rad_reg_debug8_s cn56xxp1;
+} cvmx_rad_reg_debug8_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_debug9_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t eod:1;
+ uint64_t ini:1;
+ uint64_t q:1;
+ uint64_t p:1;
+ uint64_t mul:8;
+ uint64_t index:8;
+#else
+ uint64_t index:8;
+ uint64_t mul:8;
+ uint64_t p:1;
+ uint64_t q:1;
+ uint64_t ini:1;
+ uint64_t eod:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_rad_reg_debug9_s cn52xx;
+ struct cvmx_rad_reg_debug9_s cn52xxp1;
+ struct cvmx_rad_reg_debug9_s cn56xx;
+ struct cvmx_rad_reg_debug9_s cn56xxp1;
+} cvmx_rad_reg_debug9_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_error_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t doorbell:1;
+#else
+ uint64_t doorbell:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_rad_reg_error_s cn52xx;
+ struct cvmx_rad_reg_error_s cn52xxp1;
+ struct cvmx_rad_reg_error_s cn56xx;
+ struct cvmx_rad_reg_error_s cn56xxp1;
+} cvmx_rad_reg_error_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_int_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t doorbell:1;
+#else
+ uint64_t doorbell:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_rad_reg_int_mask_s cn52xx;
+ struct cvmx_rad_reg_int_mask_s cn52xxp1;
+ struct cvmx_rad_reg_int_mask_s cn56xx;
+ struct cvmx_rad_reg_int_mask_s cn56xxp1;
+} cvmx_rad_reg_int_mask_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_polynomial_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t coeffs:8;
+#else
+ uint64_t coeffs:8;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_rad_reg_polynomial_s cn52xx;
+ struct cvmx_rad_reg_polynomial_s cn52xxp1;
+ struct cvmx_rad_reg_polynomial_s cn56xx;
+ struct cvmx_rad_reg_polynomial_s cn56xxp1;
+} cvmx_rad_reg_polynomial_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rad_reg_read_idx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t inc:16;
+ uint64_t index:16;
+#else
+ uint64_t index:16;
+ uint64_t inc:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_rad_reg_read_idx_s cn52xx;
+ struct cvmx_rad_reg_read_idx_s cn52xxp1;
+ struct cvmx_rad_reg_read_idx_s cn56xx;
+ struct cvmx_rad_reg_read_idx_s cn56xxp1;
+} cvmx_rad_reg_read_idx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rnm_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t rrc:1;
+ uint64_t mem:1;
+#else
+ uint64_t mem:1;
+ uint64_t rrc:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_rnm_bist_status_s cn30xx;
+ struct cvmx_rnm_bist_status_s cn31xx;
+ struct cvmx_rnm_bist_status_s cn38xx;
+ struct cvmx_rnm_bist_status_s cn38xxp2;
+ struct cvmx_rnm_bist_status_s cn50xx;
+ struct cvmx_rnm_bist_status_s cn52xx;
+ struct cvmx_rnm_bist_status_s cn52xxp1;
+ struct cvmx_rnm_bist_status_s cn56xx;
+ struct cvmx_rnm_bist_status_s cn56xxp1;
+ struct cvmx_rnm_bist_status_s cn58xx;
+ struct cvmx_rnm_bist_status_s cn58xxp1;
+} cvmx_rnm_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_rnm_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t ent_sel:4;
+ uint64_t exp_ent:1;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+#else
+ uint64_t ent_en:1;
+ uint64_t rng_en:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_rst:1;
+ uint64_t exp_ent:1;
+ uint64_t ent_sel:4;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_rnm_ctl_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+#else
+ uint64_t ent_en:1;
+ uint64_t rng_en:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_rst:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } cn30xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn31xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn38xx;
+ struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
+ struct cvmx_rnm_ctl_status_s cn50xx;
+ struct cvmx_rnm_ctl_status_s cn52xx;
+ struct cvmx_rnm_ctl_status_s cn52xxp1;
+ struct cvmx_rnm_ctl_status_s cn56xx;
+ struct cvmx_rnm_ctl_status_s cn56xxp1;
+ struct cvmx_rnm_ctl_status_s cn58xx;
+ struct cvmx_rnm_ctl_status_s cn58xxp1;
+} cvmx_rnm_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_smix_clk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_25_63:39;
+ uint64_t mode:1;
+ uint64_t reserved_21_23:3;
+ uint64_t sample_hi:5;
+ uint64_t sample_mode:1;
+ uint64_t reserved_14_14:1;
+ uint64_t clk_idle:1;
+ uint64_t preamble:1;
+ uint64_t sample:4;
+ uint64_t phase:8;
+#else
+ uint64_t phase:8;
+ uint64_t sample:4;
+ uint64_t preamble:1;
+ uint64_t clk_idle:1;
+ uint64_t reserved_14_14:1;
+ uint64_t sample_mode:1;
+ uint64_t sample_hi:5;
+ uint64_t reserved_21_23:3;
+ uint64_t mode:1;
+ uint64_t reserved_25_63:39;
+#endif
+ } s;
+ struct cvmx_smix_clk_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_21_63:43;
+ uint64_t sample_hi:5;
+ uint64_t reserved_14_15:2;
+ uint64_t clk_idle:1;
+ uint64_t preamble:1;
+ uint64_t sample:4;
+ uint64_t phase:8;
+#else
+ uint64_t phase:8;
+ uint64_t sample:4;
+ uint64_t preamble:1;
+ uint64_t clk_idle:1;
+ uint64_t reserved_14_15:2;
+ uint64_t sample_hi:5;
+ uint64_t reserved_21_63:43;
+#endif
+ } cn30xx;
+ struct cvmx_smix_clk_cn30xx cn31xx;
+ struct cvmx_smix_clk_cn30xx cn38xx;
+ struct cvmx_smix_clk_cn30xx cn38xxp2;
+ struct cvmx_smix_clk_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_25_63:39;
+ uint64_t mode:1;
+ uint64_t reserved_21_23:3;
+ uint64_t sample_hi:5;
+ uint64_t reserved_14_15:2;
+ uint64_t clk_idle:1;
+ uint64_t preamble:1;
+ uint64_t sample:4;
+ uint64_t phase:8;
+#else
+ uint64_t phase:8;
+ uint64_t sample:4;
+ uint64_t preamble:1;
+ uint64_t clk_idle:1;
+ uint64_t reserved_14_15:2;
+ uint64_t sample_hi:5;
+ uint64_t reserved_21_23:3;
+ uint64_t mode:1;
+ uint64_t reserved_25_63:39;
+#endif
+ } cn50xx;
+ struct cvmx_smix_clk_s cn52xx;
+ struct cvmx_smix_clk_cn50xx cn52xxp1;
+ struct cvmx_smix_clk_s cn56xx;
+ struct cvmx_smix_clk_cn50xx cn56xxp1;
+ struct cvmx_smix_clk_cn30xx cn58xx;
+ struct cvmx_smix_clk_cn30xx cn58xxp1;
+} cvmx_smix_clk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_smix_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t phy_op:2;
+ uint64_t reserved_13_15:3;
+ uint64_t phy_adr:5;
+ uint64_t reserved_5_7:3;
+ uint64_t reg_adr:5;
+#else
+ uint64_t reg_adr:5;
+ uint64_t reserved_5_7:3;
+ uint64_t phy_adr:5;
+ uint64_t reserved_13_15:3;
+ uint64_t phy_op:2;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_smix_cmd_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t phy_op:1;
+ uint64_t reserved_13_15:3;
+ uint64_t phy_adr:5;
+ uint64_t reserved_5_7:3;
+ uint64_t reg_adr:5;
+#else
+ uint64_t reg_adr:5;
+ uint64_t reserved_5_7:3;
+ uint64_t phy_adr:5;
+ uint64_t reserved_13_15:3;
+ uint64_t phy_op:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } cn30xx;
+ struct cvmx_smix_cmd_cn30xx cn31xx;
+ struct cvmx_smix_cmd_cn30xx cn38xx;
+ struct cvmx_smix_cmd_cn30xx cn38xxp2;
+ struct cvmx_smix_cmd_s cn50xx;
+ struct cvmx_smix_cmd_s cn52xx;
+ struct cvmx_smix_cmd_s cn52xxp1;
+ struct cvmx_smix_cmd_s cn56xx;
+ struct cvmx_smix_cmd_s cn56xxp1;
+ struct cvmx_smix_cmd_cn30xx cn58xx;
+ struct cvmx_smix_cmd_cn30xx cn58xxp1;
+} cvmx_smix_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_smix_en_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+#else
+ uint64_t en:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_smix_en_s cn30xx;
+ struct cvmx_smix_en_s cn31xx;
+ struct cvmx_smix_en_s cn38xx;
+ struct cvmx_smix_en_s cn38xxp2;
+ struct cvmx_smix_en_s cn50xx;
+ struct cvmx_smix_en_s cn52xx;
+ struct cvmx_smix_en_s cn52xxp1;
+ struct cvmx_smix_en_s cn56xx;
+ struct cvmx_smix_en_s cn56xxp1;
+ struct cvmx_smix_en_s cn58xx;
+ struct cvmx_smix_en_s cn58xxp1;
+} cvmx_smix_en_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_smix_rd_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t pending:1;
+ uint64_t val:1;
+ uint64_t dat:16;
+#else
+ uint64_t dat:16;
+ uint64_t val:1;
+ uint64_t pending:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_smix_rd_dat_s cn30xx;
+ struct cvmx_smix_rd_dat_s cn31xx;
+ struct cvmx_smix_rd_dat_s cn38xx;
+ struct cvmx_smix_rd_dat_s cn38xxp2;
+ struct cvmx_smix_rd_dat_s cn50xx;
+ struct cvmx_smix_rd_dat_s cn52xx;
+ struct cvmx_smix_rd_dat_s cn52xxp1;
+ struct cvmx_smix_rd_dat_s cn56xx;
+ struct cvmx_smix_rd_dat_s cn56xxp1;
+ struct cvmx_smix_rd_dat_s cn58xx;
+ struct cvmx_smix_rd_dat_s cn58xxp1;
+} cvmx_smix_rd_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_smix_wr_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t pending:1;
+ uint64_t val:1;
+ uint64_t dat:16;
+#else
+ uint64_t dat:16;
+ uint64_t val:1;
+ uint64_t pending:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } s;
+ struct cvmx_smix_wr_dat_s cn30xx;
+ struct cvmx_smix_wr_dat_s cn31xx;
+ struct cvmx_smix_wr_dat_s cn38xx;
+ struct cvmx_smix_wr_dat_s cn38xxp2;
+ struct cvmx_smix_wr_dat_s cn50xx;
+ struct cvmx_smix_wr_dat_s cn52xx;
+ struct cvmx_smix_wr_dat_s cn52xxp1;
+ struct cvmx_smix_wr_dat_s cn56xx;
+ struct cvmx_smix_wr_dat_s cn56xxp1;
+ struct cvmx_smix_wr_dat_s cn58xx;
+ struct cvmx_smix_wr_dat_s cn58xxp1;
+} cvmx_smix_wr_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_bckprs_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_spxx_bckprs_cnt_s cn38xx;
+ struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
+ struct cvmx_spxx_bckprs_cnt_s cn58xx;
+ struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
+} cvmx_spxx_bckprs_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_bist_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t stat2:1;
+ uint64_t stat1:1;
+ uint64_t stat0:1;
+#else
+ uint64_t stat0:1;
+ uint64_t stat1:1;
+ uint64_t stat2:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_spxx_bist_stat_s cn38xx;
+ struct cvmx_spxx_bist_stat_s cn38xxp2;
+ struct cvmx_spxx_bist_stat_s cn58xx;
+ struct cvmx_spxx_bist_stat_s cn58xxp1;
+} cvmx_spxx_bist_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_clk_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t seetrn:1;
+ uint64_t reserved_12_15:4;
+ uint64_t clkdly:5;
+ uint64_t runbist:1;
+ uint64_t statdrv:1;
+ uint64_t statrcv:1;
+ uint64_t sndtrn:1;
+ uint64_t drptrn:1;
+ uint64_t rcvtrn:1;
+ uint64_t srxdlck:1;
+#else
+ uint64_t srxdlck:1;
+ uint64_t rcvtrn:1;
+ uint64_t drptrn:1;
+ uint64_t sndtrn:1;
+ uint64_t statrcv:1;
+ uint64_t statdrv:1;
+ uint64_t runbist:1;
+ uint64_t clkdly:5;
+ uint64_t reserved_12_15:4;
+ uint64_t seetrn:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_spxx_clk_ctl_s cn38xx;
+ struct cvmx_spxx_clk_ctl_s cn38xxp2;
+ struct cvmx_spxx_clk_ctl_s cn58xx;
+ struct cvmx_spxx_clk_ctl_s cn58xxp1;
+} cvmx_spxx_clk_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_clk_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_11_63:53;
+ uint64_t stxcal:1;
+ uint64_t reserved_9_9:1;
+ uint64_t srxtrn:1;
+ uint64_t s4clk1:1;
+ uint64_t s4clk0:1;
+ uint64_t d4clk1:1;
+ uint64_t d4clk0:1;
+ uint64_t reserved_0_3:4;
+#else
+ uint64_t reserved_0_3:4;
+ uint64_t d4clk0:1;
+ uint64_t d4clk1:1;
+ uint64_t s4clk0:1;
+ uint64_t s4clk1:1;
+ uint64_t srxtrn:1;
+ uint64_t reserved_9_9:1;
+ uint64_t stxcal:1;
+ uint64_t reserved_11_63:53;
+#endif
+ } s;
+ struct cvmx_spxx_clk_stat_s cn38xx;
+ struct cvmx_spxx_clk_stat_s cn38xxp2;
+ struct cvmx_spxx_clk_stat_s cn58xx;
+ struct cvmx_spxx_clk_stat_s cn58xxp1;
+} cvmx_spxx_clk_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_dbg_deskew_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_30_63:34;
+ uint64_t fallnop:1;
+ uint64_t fall8:1;
+ uint64_t reserved_26_27:2;
+ uint64_t sstep_go:1;
+ uint64_t sstep:1;
+ uint64_t reserved_22_23:2;
+ uint64_t clrdly:1;
+ uint64_t dec:1;
+ uint64_t inc:1;
+ uint64_t mux:1;
+ uint64_t offset:5;
+ uint64_t bitsel:5;
+ uint64_t offdly:6;
+ uint64_t dllfrc:1;
+ uint64_t dlldis:1;
+#else
+ uint64_t dlldis:1;
+ uint64_t dllfrc:1;
+ uint64_t offdly:6;
+ uint64_t bitsel:5;
+ uint64_t offset:5;
+ uint64_t mux:1;
+ uint64_t inc:1;
+ uint64_t dec:1;
+ uint64_t clrdly:1;
+ uint64_t reserved_22_23:2;
+ uint64_t sstep:1;
+ uint64_t sstep_go:1;
+ uint64_t reserved_26_27:2;
+ uint64_t fall8:1;
+ uint64_t fallnop:1;
+ uint64_t reserved_30_63:34;
+#endif
+ } s;
+ struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
+ struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
+ struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
+ struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
+} cvmx_spxx_dbg_deskew_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_dbg_deskew_state_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t testres:1;
+ uint64_t unxterm:1;
+ uint64_t muxsel:2;
+ uint64_t offset:5;
+#else
+ uint64_t offset:5;
+ uint64_t muxsel:2;
+ uint64_t unxterm:1;
+ uint64_t testres:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_spxx_dbg_deskew_state_s cn38xx;
+ struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
+ struct cvmx_spxx_dbg_deskew_state_s cn58xx;
+ struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
+} cvmx_spxx_dbg_deskew_state_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_drv_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_0_63:64;
+#else
+ uint64_t reserved_0_63:64;
+#endif
+ } s;
+ struct cvmx_spxx_drv_ctl_cn38xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t stx4ncmp:4;
+ uint64_t stx4pcmp:4;
+ uint64_t srx4cmp:8;
+#else
+ uint64_t srx4cmp:8;
+ uint64_t stx4pcmp:4;
+ uint64_t stx4ncmp:4;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn38xx;
+ struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
+ struct cvmx_spxx_drv_ctl_cn58xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t stx4ncmp:4;
+ uint64_t stx4pcmp:4;
+ uint64_t reserved_10_15:6;
+ uint64_t srx4cmp:10;
+#else
+ uint64_t srx4cmp:10;
+ uint64_t reserved_10_15:6;
+ uint64_t stx4pcmp:4;
+ uint64_t stx4ncmp:4;
+ uint64_t reserved_24_63:40;
+#endif
+ } cn58xx;
+ struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
+} cvmx_spxx_drv_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_err_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t prtnxa:1;
+ uint64_t dipcls:1;
+ uint64_t dippay:1;
+ uint64_t reserved_4_5:2;
+ uint64_t errcnt:4;
+#else
+ uint64_t errcnt:4;
+ uint64_t reserved_4_5:2;
+ uint64_t dippay:1;
+ uint64_t dipcls:1;
+ uint64_t prtnxa:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_spxx_err_ctl_s cn38xx;
+ struct cvmx_spxx_err_ctl_s cn38xxp2;
+ struct cvmx_spxx_err_ctl_s cn58xx;
+ struct cvmx_spxx_err_ctl_s cn58xxp1;
+} cvmx_spxx_err_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_int_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t mul:1;
+ uint64_t reserved_14_30:17;
+ uint64_t calbnk:2;
+ uint64_t rsvop:4;
+ uint64_t prt:8;
+#else
+ uint64_t prt:8;
+ uint64_t rsvop:4;
+ uint64_t calbnk:2;
+ uint64_t reserved_14_30:17;
+ uint64_t mul:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_spxx_int_dat_s cn38xx;
+ struct cvmx_spxx_int_dat_s cn38xxp2;
+ struct cvmx_spxx_int_dat_s cn58xx;
+ struct cvmx_spxx_int_dat_s cn58xxp1;
+} cvmx_spxx_int_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_int_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t calerr:1;
+ uint64_t syncerr:1;
+ uint64_t diperr:1;
+ uint64_t tpaovr:1;
+ uint64_t rsverr:1;
+ uint64_t drwnng:1;
+ uint64_t clserr:1;
+ uint64_t spiovr:1;
+ uint64_t reserved_2_3:2;
+ uint64_t abnorm:1;
+ uint64_t prtnxa:1;
+#else
+ uint64_t prtnxa:1;
+ uint64_t abnorm:1;
+ uint64_t reserved_2_3:2;
+ uint64_t spiovr:1;
+ uint64_t clserr:1;
+ uint64_t drwnng:1;
+ uint64_t rsverr:1;
+ uint64_t tpaovr:1;
+ uint64_t diperr:1;
+ uint64_t syncerr:1;
+ uint64_t calerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_spxx_int_msk_s cn38xx;
+ struct cvmx_spxx_int_msk_s cn38xxp2;
+ struct cvmx_spxx_int_msk_s cn58xx;
+ struct cvmx_spxx_int_msk_s cn58xxp1;
+} cvmx_spxx_int_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t spf:1;
+ uint64_t reserved_12_30:19;
+ uint64_t calerr:1;
+ uint64_t syncerr:1;
+ uint64_t diperr:1;
+ uint64_t tpaovr:1;
+ uint64_t rsverr:1;
+ uint64_t drwnng:1;
+ uint64_t clserr:1;
+ uint64_t spiovr:1;
+ uint64_t reserved_2_3:2;
+ uint64_t abnorm:1;
+ uint64_t prtnxa:1;
+#else
+ uint64_t prtnxa:1;
+ uint64_t abnorm:1;
+ uint64_t reserved_2_3:2;
+ uint64_t spiovr:1;
+ uint64_t clserr:1;
+ uint64_t drwnng:1;
+ uint64_t rsverr:1;
+ uint64_t tpaovr:1;
+ uint64_t diperr:1;
+ uint64_t syncerr:1;
+ uint64_t calerr:1;
+ uint64_t reserved_12_30:19;
+ uint64_t spf:1;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_spxx_int_reg_s cn38xx;
+ struct cvmx_spxx_int_reg_s cn38xxp2;
+ struct cvmx_spxx_int_reg_s cn58xx;
+ struct cvmx_spxx_int_reg_s cn58xxp1;
+} cvmx_spxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_int_sync_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_12_63:52;
+ uint64_t calerr:1;
+ uint64_t syncerr:1;
+ uint64_t diperr:1;
+ uint64_t tpaovr:1;
+ uint64_t rsverr:1;
+ uint64_t drwnng:1;
+ uint64_t clserr:1;
+ uint64_t spiovr:1;
+ uint64_t reserved_2_3:2;
+ uint64_t abnorm:1;
+ uint64_t prtnxa:1;
+#else
+ uint64_t prtnxa:1;
+ uint64_t abnorm:1;
+ uint64_t reserved_2_3:2;
+ uint64_t spiovr:1;
+ uint64_t clserr:1;
+ uint64_t drwnng:1;
+ uint64_t rsverr:1;
+ uint64_t tpaovr:1;
+ uint64_t diperr:1;
+ uint64_t syncerr:1;
+ uint64_t calerr:1;
+ uint64_t reserved_12_63:52;
+#endif
+ } s;
+ struct cvmx_spxx_int_sync_s cn38xx;
+ struct cvmx_spxx_int_sync_s cn38xxp2;
+ struct cvmx_spxx_int_sync_s cn58xx;
+ struct cvmx_spxx_int_sync_s cn58xxp1;
+} cvmx_spxx_int_sync_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_tpa_acc_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_spxx_tpa_acc_s cn38xx;
+ struct cvmx_spxx_tpa_acc_s cn38xxp2;
+ struct cvmx_spxx_tpa_acc_s cn58xx;
+ struct cvmx_spxx_tpa_acc_s cn58xxp1;
+} cvmx_spxx_tpa_acc_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_tpa_max_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t max:32;
+#else
+ uint64_t max:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_spxx_tpa_max_s cn38xx;
+ struct cvmx_spxx_tpa_max_s cn38xxp2;
+ struct cvmx_spxx_tpa_max_s cn58xx;
+ struct cvmx_spxx_tpa_max_s cn58xxp1;
+} cvmx_spxx_tpa_max_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_tpa_sel_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t prtsel:4;
+#else
+ uint64_t prtsel:4;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_spxx_tpa_sel_s cn38xx;
+ struct cvmx_spxx_tpa_sel_s cn38xxp2;
+ struct cvmx_spxx_tpa_sel_s cn58xx;
+ struct cvmx_spxx_tpa_sel_s cn58xxp1;
+} cvmx_spxx_tpa_sel_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spxx_trn4_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_13_63:51;
+ uint64_t trntest:1;
+ uint64_t jitter:3;
+ uint64_t clr_boot:1;
+ uint64_t set_boot:1;
+ uint64_t maxdist:5;
+ uint64_t macro_en:1;
+ uint64_t mux_en:1;
+#else
+ uint64_t mux_en:1;
+ uint64_t macro_en:1;
+ uint64_t maxdist:5;
+ uint64_t set_boot:1;
+ uint64_t clr_boot:1;
+ uint64_t jitter:3;
+ uint64_t trntest:1;
+ uint64_t reserved_13_63:51;
+#endif
+ } s;
+ struct cvmx_spxx_trn4_ctl_s cn38xx;
+ struct cvmx_spxx_trn4_ctl_s cn38xxp2;
+ struct cvmx_spxx_trn4_ctl_s cn58xx;
+ struct cvmx_spxx_trn4_ctl_s cn58xxp1;
+} cvmx_spxx_trn4_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spx0_pll_bw_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t bw_ctl:5;
+#else
+ uint64_t bw_ctl:5;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_spx0_pll_bw_ctl_s cn38xx;
+ struct cvmx_spx0_pll_bw_ctl_s cn38xxp2;
+} cvmx_spx0_pll_bw_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_spx0_pll_setting_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t setting:17;
+#else
+ uint64_t setting:17;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_spx0_pll_setting_s cn38xx;
+ struct cvmx_spx0_pll_setting_s cn38xxp2;
+} cvmx_spx0_pll_setting_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_com_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t prts:4;
+ uint64_t st_en:1;
+ uint64_t reserved_1_2:2;
+ uint64_t inf_en:1;
+#else
+ uint64_t inf_en:1;
+ uint64_t reserved_1_2:2;
+ uint64_t st_en:1;
+ uint64_t prts:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_srxx_com_ctl_s cn38xx;
+ struct cvmx_srxx_com_ctl_s cn38xxp2;
+ struct cvmx_srxx_com_ctl_s cn58xx;
+ struct cvmx_srxx_com_ctl_s cn58xxp1;
+} cvmx_srxx_com_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_ign_rx_full_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t ignore:16;
+#else
+ uint64_t ignore:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_srxx_ign_rx_full_s cn38xx;
+ struct cvmx_srxx_ign_rx_full_s cn38xxp2;
+ struct cvmx_srxx_ign_rx_full_s cn58xx;
+ struct cvmx_srxx_ign_rx_full_s cn58xxp1;
+} cvmx_srxx_ign_rx_full_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_spi4_calx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t oddpar:1;
+ uint64_t prt3:4;
+ uint64_t prt2:4;
+ uint64_t prt1:4;
+ uint64_t prt0:4;
+#else
+ uint64_t prt0:4;
+ uint64_t prt1:4;
+ uint64_t prt2:4;
+ uint64_t prt3:4;
+ uint64_t oddpar:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_srxx_spi4_calx_s cn38xx;
+ struct cvmx_srxx_spi4_calx_s cn38xxp2;
+ struct cvmx_srxx_spi4_calx_s cn58xx;
+ struct cvmx_srxx_spi4_calx_s cn58xxp1;
+} cvmx_srxx_spi4_calx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_spi4_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t m:8;
+ uint64_t reserved_7_7:1;
+ uint64_t len:7;
+#else
+ uint64_t len:7;
+ uint64_t reserved_7_7:1;
+ uint64_t m:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_srxx_spi4_stat_s cn38xx;
+ struct cvmx_srxx_spi4_stat_s cn38xxp2;
+ struct cvmx_srxx_spi4_stat_s cn58xx;
+ struct cvmx_srxx_spi4_stat_s cn58xxp1;
+} cvmx_srxx_spi4_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_sw_tick_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t eop:1;
+ uint64_t sop:1;
+ uint64_t mod:4;
+ uint64_t opc:4;
+ uint64_t adr:4;
+#else
+ uint64_t adr:4;
+ uint64_t opc:4;
+ uint64_t mod:4;
+ uint64_t sop:1;
+ uint64_t eop:1;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_srxx_sw_tick_ctl_s cn38xx;
+ struct cvmx_srxx_sw_tick_ctl_s cn58xx;
+ struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
+} cvmx_srxx_sw_tick_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_srxx_sw_tick_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t dat:64;
+#else
+ uint64_t dat:64;
+#endif
+ } s;
+ struct cvmx_srxx_sw_tick_dat_s cn38xx;
+ struct cvmx_srxx_sw_tick_dat_s cn58xx;
+ struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
+} cvmx_srxx_sw_tick_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_arb_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t mintrn:1;
+ uint64_t reserved_4_4:1;
+ uint64_t igntpa:1;
+ uint64_t reserved_0_2:3;
+#else
+ uint64_t reserved_0_2:3;
+ uint64_t igntpa:1;
+ uint64_t reserved_4_4:1;
+ uint64_t mintrn:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_stxx_arb_ctl_s cn38xx;
+ struct cvmx_stxx_arb_ctl_s cn38xxp2;
+ struct cvmx_stxx_arb_ctl_s cn58xx;
+ struct cvmx_stxx_arb_ctl_s cn58xxp1;
+} cvmx_stxx_arb_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_bckprs_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_stxx_bckprs_cnt_s cn38xx;
+ struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
+ struct cvmx_stxx_bckprs_cnt_s cn58xx;
+ struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
+} cvmx_stxx_bckprs_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_com_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t st_en:1;
+ uint64_t reserved_1_2:2;
+ uint64_t inf_en:1;
+#else
+ uint64_t inf_en:1;
+ uint64_t reserved_1_2:2;
+ uint64_t st_en:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_stxx_com_ctl_s cn38xx;
+ struct cvmx_stxx_com_ctl_s cn38xxp2;
+ struct cvmx_stxx_com_ctl_s cn58xx;
+ struct cvmx_stxx_com_ctl_s cn58xxp1;
+} cvmx_stxx_com_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_dip_cnt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t frmmax:4;
+ uint64_t dipmax:4;
+#else
+ uint64_t dipmax:4;
+ uint64_t frmmax:4;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_stxx_dip_cnt_s cn38xx;
+ struct cvmx_stxx_dip_cnt_s cn38xxp2;
+ struct cvmx_stxx_dip_cnt_s cn58xx;
+ struct cvmx_stxx_dip_cnt_s cn58xxp1;
+} cvmx_stxx_dip_cnt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_ign_cal_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t igntpa:16;
+#else
+ uint64_t igntpa:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_stxx_ign_cal_s cn38xx;
+ struct cvmx_stxx_ign_cal_s cn38xxp2;
+ struct cvmx_stxx_ign_cal_s cn58xx;
+ struct cvmx_stxx_ign_cal_s cn58xxp1;
+} cvmx_stxx_ign_cal_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_int_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t frmerr:1;
+ uint64_t unxfrm:1;
+ uint64_t nosync:1;
+ uint64_t diperr:1;
+ uint64_t datovr:1;
+ uint64_t ovrbst:1;
+ uint64_t calpar1:1;
+ uint64_t calpar0:1;
+#else
+ uint64_t calpar0:1;
+ uint64_t calpar1:1;
+ uint64_t ovrbst:1;
+ uint64_t datovr:1;
+ uint64_t diperr:1;
+ uint64_t nosync:1;
+ uint64_t unxfrm:1;
+ uint64_t frmerr:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_stxx_int_msk_s cn38xx;
+ struct cvmx_stxx_int_msk_s cn38xxp2;
+ struct cvmx_stxx_int_msk_s cn58xx;
+ struct cvmx_stxx_int_msk_s cn58xxp1;
+} cvmx_stxx_int_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_int_reg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t syncerr:1;
+ uint64_t frmerr:1;
+ uint64_t unxfrm:1;
+ uint64_t nosync:1;
+ uint64_t diperr:1;
+ uint64_t datovr:1;
+ uint64_t ovrbst:1;
+ uint64_t calpar1:1;
+ uint64_t calpar0:1;
+#else
+ uint64_t calpar0:1;
+ uint64_t calpar1:1;
+ uint64_t ovrbst:1;
+ uint64_t datovr:1;
+ uint64_t diperr:1;
+ uint64_t nosync:1;
+ uint64_t unxfrm:1;
+ uint64_t frmerr:1;
+ uint64_t syncerr:1;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_stxx_int_reg_s cn38xx;
+ struct cvmx_stxx_int_reg_s cn38xxp2;
+ struct cvmx_stxx_int_reg_s cn58xx;
+ struct cvmx_stxx_int_reg_s cn58xxp1;
+} cvmx_stxx_int_reg_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_int_sync_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_8_63:56;
+ uint64_t frmerr:1;
+ uint64_t unxfrm:1;
+ uint64_t nosync:1;
+ uint64_t diperr:1;
+ uint64_t datovr:1;
+ uint64_t ovrbst:1;
+ uint64_t calpar1:1;
+ uint64_t calpar0:1;
+#else
+ uint64_t calpar0:1;
+ uint64_t calpar1:1;
+ uint64_t ovrbst:1;
+ uint64_t datovr:1;
+ uint64_t diperr:1;
+ uint64_t nosync:1;
+ uint64_t unxfrm:1;
+ uint64_t frmerr:1;
+ uint64_t reserved_8_63:56;
+#endif
+ } s;
+ struct cvmx_stxx_int_sync_s cn38xx;
+ struct cvmx_stxx_int_sync_s cn38xxp2;
+ struct cvmx_stxx_int_sync_s cn58xx;
+ struct cvmx_stxx_int_sync_s cn58xxp1;
+} cvmx_stxx_int_sync_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_min_bst_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_9_63:55;
+ uint64_t minb:9;
+#else
+ uint64_t minb:9;
+ uint64_t reserved_9_63:55;
+#endif
+ } s;
+ struct cvmx_stxx_min_bst_s cn38xx;
+ struct cvmx_stxx_min_bst_s cn38xxp2;
+ struct cvmx_stxx_min_bst_s cn58xx;
+ struct cvmx_stxx_min_bst_s cn58xxp1;
+} cvmx_stxx_min_bst_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_spi4_calx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t oddpar:1;
+ uint64_t prt3:4;
+ uint64_t prt2:4;
+ uint64_t prt1:4;
+ uint64_t prt0:4;
+#else
+ uint64_t prt0:4;
+ uint64_t prt1:4;
+ uint64_t prt2:4;
+ uint64_t prt3:4;
+ uint64_t oddpar:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_stxx_spi4_calx_s cn38xx;
+ struct cvmx_stxx_spi4_calx_s cn38xxp2;
+ struct cvmx_stxx_spi4_calx_s cn58xx;
+ struct cvmx_stxx_spi4_calx_s cn58xxp1;
+} cvmx_stxx_spi4_calx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_spi4_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t alpha:16;
+ uint64_t max_t:16;
+#else
+ uint64_t max_t:16;
+ uint64_t alpha:16;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_stxx_spi4_dat_s cn38xx;
+ struct cvmx_stxx_spi4_dat_s cn38xxp2;
+ struct cvmx_stxx_spi4_dat_s cn58xx;
+ struct cvmx_stxx_spi4_dat_s cn58xxp1;
+} cvmx_stxx_spi4_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_spi4_stat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t m:8;
+ uint64_t reserved_7_7:1;
+ uint64_t len:7;
+#else
+ uint64_t len:7;
+ uint64_t reserved_7_7:1;
+ uint64_t m:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_stxx_spi4_stat_s cn38xx;
+ struct cvmx_stxx_spi4_stat_s cn38xxp2;
+ struct cvmx_stxx_spi4_stat_s cn58xx;
+ struct cvmx_stxx_spi4_stat_s cn58xxp1;
+} cvmx_stxx_spi4_stat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_stat_bytes_hi_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_stxx_stat_bytes_hi_s cn38xx;
+ struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
+ struct cvmx_stxx_stat_bytes_hi_s cn58xx;
+ struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
+} cvmx_stxx_stat_bytes_hi_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_stat_bytes_lo_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_stxx_stat_bytes_lo_s cn38xx;
+ struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
+ struct cvmx_stxx_stat_bytes_lo_s cn58xx;
+ struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
+} cvmx_stxx_stat_bytes_lo_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_stat_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_5_63:59;
+ uint64_t clr:1;
+ uint64_t bckprs:4;
+#else
+ uint64_t bckprs:4;
+ uint64_t clr:1;
+ uint64_t reserved_5_63:59;
+#endif
+ } s;
+ struct cvmx_stxx_stat_ctl_s cn38xx;
+ struct cvmx_stxx_stat_ctl_s cn38xxp2;
+ struct cvmx_stxx_stat_ctl_s cn58xx;
+ struct cvmx_stxx_stat_ctl_s cn58xxp1;
+} cvmx_stxx_stat_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_stxx_stat_pkt_xmt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+#else
+ uint64_t cnt:32;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
+ struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
+ struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
+ struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
+} cvmx_stxx_stat_pkt_xmt_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_mem_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t ena:1;
+ uint64_t reserved_46_46:1;
+ uint64_t count:22;
+ uint64_t reserved_22_23:2;
+ uint64_t interval:22;
+#else
+ uint64_t interval:22;
+ uint64_t reserved_22_23:2;
+ uint64_t count:22;
+ uint64_t reserved_46_46:1;
+ uint64_t ena:1;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_tim_mem_debug0_s cn30xx;
+ struct cvmx_tim_mem_debug0_s cn31xx;
+ struct cvmx_tim_mem_debug0_s cn38xx;
+ struct cvmx_tim_mem_debug0_s cn38xxp2;
+ struct cvmx_tim_mem_debug0_s cn50xx;
+ struct cvmx_tim_mem_debug0_s cn52xx;
+ struct cvmx_tim_mem_debug0_s cn52xxp1;
+ struct cvmx_tim_mem_debug0_s cn56xx;
+ struct cvmx_tim_mem_debug0_s cn56xxp1;
+ struct cvmx_tim_mem_debug0_s cn58xx;
+ struct cvmx_tim_mem_debug0_s cn58xxp1;
+} cvmx_tim_mem_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_mem_debug1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t bucket:13;
+ uint64_t base:31;
+ uint64_t bsize:20;
+#else
+ uint64_t bsize:20;
+ uint64_t base:31;
+ uint64_t bucket:13;
+#endif
+ } s;
+ struct cvmx_tim_mem_debug1_s cn30xx;
+ struct cvmx_tim_mem_debug1_s cn31xx;
+ struct cvmx_tim_mem_debug1_s cn38xx;
+ struct cvmx_tim_mem_debug1_s cn38xxp2;
+ struct cvmx_tim_mem_debug1_s cn50xx;
+ struct cvmx_tim_mem_debug1_s cn52xx;
+ struct cvmx_tim_mem_debug1_s cn52xxp1;
+ struct cvmx_tim_mem_debug1_s cn56xx;
+ struct cvmx_tim_mem_debug1_s cn56xxp1;
+ struct cvmx_tim_mem_debug1_s cn58xx;
+ struct cvmx_tim_mem_debug1_s cn58xxp1;
+} cvmx_tim_mem_debug1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_mem_debug2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_24_63:40;
+ uint64_t cpool:3;
+ uint64_t csize:13;
+ uint64_t reserved_7_7:1;
+ uint64_t bucket:7;
+#else
+ uint64_t bucket:7;
+ uint64_t reserved_7_7:1;
+ uint64_t csize:13;
+ uint64_t cpool:3;
+ uint64_t reserved_24_63:40;
+#endif
+ } s;
+ struct cvmx_tim_mem_debug2_s cn30xx;
+ struct cvmx_tim_mem_debug2_s cn31xx;
+ struct cvmx_tim_mem_debug2_s cn38xx;
+ struct cvmx_tim_mem_debug2_s cn38xxp2;
+ struct cvmx_tim_mem_debug2_s cn50xx;
+ struct cvmx_tim_mem_debug2_s cn52xx;
+ struct cvmx_tim_mem_debug2_s cn52xxp1;
+ struct cvmx_tim_mem_debug2_s cn56xx;
+ struct cvmx_tim_mem_debug2_s cn56xxp1;
+ struct cvmx_tim_mem_debug2_s cn58xx;
+ struct cvmx_tim_mem_debug2_s cn58xxp1;
+} cvmx_tim_mem_debug2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_mem_ring0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_55_63:9;
+ uint64_t first_bucket:31;
+ uint64_t num_buckets:20;
+ uint64_t ring:4;
+#else
+ uint64_t ring:4;
+ uint64_t num_buckets:20;
+ uint64_t first_bucket:31;
+ uint64_t reserved_55_63:9;
+#endif
+ } s;
+ struct cvmx_tim_mem_ring0_s cn30xx;
+ struct cvmx_tim_mem_ring0_s cn31xx;
+ struct cvmx_tim_mem_ring0_s cn38xx;
+ struct cvmx_tim_mem_ring0_s cn38xxp2;
+ struct cvmx_tim_mem_ring0_s cn50xx;
+ struct cvmx_tim_mem_ring0_s cn52xx;
+ struct cvmx_tim_mem_ring0_s cn52xxp1;
+ struct cvmx_tim_mem_ring0_s cn56xx;
+ struct cvmx_tim_mem_ring0_s cn56xxp1;
+ struct cvmx_tim_mem_ring0_s cn58xx;
+ struct cvmx_tim_mem_ring0_s cn58xxp1;
+} cvmx_tim_mem_ring0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_mem_ring1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_43_63:21;
+ uint64_t enable:1;
+ uint64_t pool:3;
+ uint64_t words_per_chunk:13;
+ uint64_t interval:22;
+ uint64_t ring:4;
+#else
+ uint64_t ring:4;
+ uint64_t interval:22;
+ uint64_t words_per_chunk:13;
+ uint64_t pool:3;
+ uint64_t enable:1;
+ uint64_t reserved_43_63:21;
+#endif
+ } s;
+ struct cvmx_tim_mem_ring1_s cn30xx;
+ struct cvmx_tim_mem_ring1_s cn31xx;
+ struct cvmx_tim_mem_ring1_s cn38xx;
+ struct cvmx_tim_mem_ring1_s cn38xxp2;
+ struct cvmx_tim_mem_ring1_s cn50xx;
+ struct cvmx_tim_mem_ring1_s cn52xx;
+ struct cvmx_tim_mem_ring1_s cn52xxp1;
+ struct cvmx_tim_mem_ring1_s cn56xx;
+ struct cvmx_tim_mem_ring1_s cn56xxp1;
+ struct cvmx_tim_mem_ring1_s cn58xx;
+ struct cvmx_tim_mem_ring1_s cn58xxp1;
+} cvmx_tim_mem_ring1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_reg_bist_result_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t sta:2;
+ uint64_t ncb:1;
+ uint64_t ctl:1;
+#else
+ uint64_t ctl:1;
+ uint64_t ncb:1;
+ uint64_t sta:2;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_tim_reg_bist_result_s cn30xx;
+ struct cvmx_tim_reg_bist_result_s cn31xx;
+ struct cvmx_tim_reg_bist_result_s cn38xx;
+ struct cvmx_tim_reg_bist_result_s cn38xxp2;
+ struct cvmx_tim_reg_bist_result_s cn50xx;
+ struct cvmx_tim_reg_bist_result_s cn52xx;
+ struct cvmx_tim_reg_bist_result_s cn52xxp1;
+ struct cvmx_tim_reg_bist_result_s cn56xx;
+ struct cvmx_tim_reg_bist_result_s cn56xxp1;
+ struct cvmx_tim_reg_bist_result_s cn58xx;
+ struct cvmx_tim_reg_bist_result_s cn58xxp1;
+} cvmx_tim_reg_bist_result_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_reg_error_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+#else
+ uint64_t mask:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_tim_reg_error_s cn30xx;
+ struct cvmx_tim_reg_error_s cn31xx;
+ struct cvmx_tim_reg_error_s cn38xx;
+ struct cvmx_tim_reg_error_s cn38xxp2;
+ struct cvmx_tim_reg_error_s cn50xx;
+ struct cvmx_tim_reg_error_s cn52xx;
+ struct cvmx_tim_reg_error_s cn52xxp1;
+ struct cvmx_tim_reg_error_s cn56xx;
+ struct cvmx_tim_reg_error_s cn56xxp1;
+ struct cvmx_tim_reg_error_s cn58xx;
+ struct cvmx_tim_reg_error_s cn58xxp1;
+} cvmx_tim_reg_error_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_reg_flags_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t reset:1;
+ uint64_t enable_dwb:1;
+ uint64_t enable_timers:1;
+#else
+ uint64_t enable_timers:1;
+ uint64_t enable_dwb:1;
+ uint64_t reset:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_tim_reg_flags_s cn30xx;
+ struct cvmx_tim_reg_flags_s cn31xx;
+ struct cvmx_tim_reg_flags_s cn38xx;
+ struct cvmx_tim_reg_flags_s cn38xxp2;
+ struct cvmx_tim_reg_flags_s cn50xx;
+ struct cvmx_tim_reg_flags_s cn52xx;
+ struct cvmx_tim_reg_flags_s cn52xxp1;
+ struct cvmx_tim_reg_flags_s cn56xx;
+ struct cvmx_tim_reg_flags_s cn56xxp1;
+ struct cvmx_tim_reg_flags_s cn58xx;
+ struct cvmx_tim_reg_flags_s cn58xxp1;
+} cvmx_tim_reg_flags_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_reg_int_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+#else
+ uint64_t mask:16;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_tim_reg_int_mask_s cn30xx;
+ struct cvmx_tim_reg_int_mask_s cn31xx;
+ struct cvmx_tim_reg_int_mask_s cn38xx;
+ struct cvmx_tim_reg_int_mask_s cn38xxp2;
+ struct cvmx_tim_reg_int_mask_s cn50xx;
+ struct cvmx_tim_reg_int_mask_s cn52xx;
+ struct cvmx_tim_reg_int_mask_s cn52xxp1;
+ struct cvmx_tim_reg_int_mask_s cn56xx;
+ struct cvmx_tim_reg_int_mask_s cn56xxp1;
+ struct cvmx_tim_reg_int_mask_s cn58xx;
+ struct cvmx_tim_reg_int_mask_s cn58xxp1;
+} cvmx_tim_reg_int_mask_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tim_reg_read_idx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t inc:8;
+ uint64_t index:8;
+#else
+ uint64_t index:8;
+ uint64_t inc:8;
+ uint64_t reserved_16_63:48;
+#endif
+ } s;
+ struct cvmx_tim_reg_read_idx_s cn30xx;
+ struct cvmx_tim_reg_read_idx_s cn31xx;
+ struct cvmx_tim_reg_read_idx_s cn38xx;
+ struct cvmx_tim_reg_read_idx_s cn38xxp2;
+ struct cvmx_tim_reg_read_idx_s cn50xx;
+ struct cvmx_tim_reg_read_idx_s cn52xx;
+ struct cvmx_tim_reg_read_idx_s cn52xxp1;
+ struct cvmx_tim_reg_read_idx_s cn56xx;
+ struct cvmx_tim_reg_read_idx_s cn56xxp1;
+ struct cvmx_tim_reg_read_idx_s cn58xx;
+ struct cvmx_tim_reg_read_idx_s cn58xxp1;
+} cvmx_tim_reg_read_idx_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t tcf:1;
+ uint64_t tdf1:1;
+ uint64_t tdf0:1;
+#else
+ uint64_t tdf0:1;
+ uint64_t tdf1:1;
+ uint64_t tcf:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } s;
+ struct cvmx_tra_bist_status_s cn31xx;
+ struct cvmx_tra_bist_status_s cn38xx;
+ struct cvmx_tra_bist_status_s cn38xxp2;
+ struct cvmx_tra_bist_status_s cn52xx;
+ struct cvmx_tra_bist_status_s cn52xxp1;
+ struct cvmx_tra_bist_status_s cn56xx;
+ struct cvmx_tra_bist_status_s cn56xxp1;
+ struct cvmx_tra_bist_status_s cn58xx;
+ struct cvmx_tra_bist_status_s cn58xxp1;
+} cvmx_tra_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_15_63:49;
+ uint64_t ignore_o:1;
+ uint64_t mcd0_ena:1;
+ uint64_t mcd0_thr:1;
+ uint64_t mcd0_trg:1;
+ uint64_t ciu_thr:1;
+ uint64_t ciu_trg:1;
+ uint64_t full_thr:2;
+ uint64_t time_grn:3;
+ uint64_t trig_ctl:2;
+ uint64_t wrap:1;
+ uint64_t ena:1;
+#else
+ uint64_t ena:1;
+ uint64_t wrap:1;
+ uint64_t trig_ctl:2;
+ uint64_t time_grn:3;
+ uint64_t full_thr:2;
+ uint64_t ciu_trg:1;
+ uint64_t ciu_thr:1;
+ uint64_t mcd0_trg:1;
+ uint64_t mcd0_thr:1;
+ uint64_t mcd0_ena:1;
+ uint64_t ignore_o:1;
+ uint64_t reserved_15_63:49;
+#endif
+ } s;
+ struct cvmx_tra_ctl_s cn31xx;
+ struct cvmx_tra_ctl_s cn38xx;
+ struct cvmx_tra_ctl_s cn38xxp2;
+ struct cvmx_tra_ctl_s cn52xx;
+ struct cvmx_tra_ctl_s cn52xxp1;
+ struct cvmx_tra_ctl_s cn56xx;
+ struct cvmx_tra_ctl_s cn56xxp1;
+ struct cvmx_tra_ctl_s cn58xx;
+ struct cvmx_tra_ctl_s cn58xxp1;
+} cvmx_tra_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_cycles_since_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cycles:48;
+ uint64_t rptr:8;
+ uint64_t wptr:8;
+#else
+ uint64_t wptr:8;
+ uint64_t rptr:8;
+ uint64_t cycles:48;
+#endif
+ } s;
+ struct cvmx_tra_cycles_since_s cn31xx;
+ struct cvmx_tra_cycles_since_s cn38xx;
+ struct cvmx_tra_cycles_since_s cn38xxp2;
+ struct cvmx_tra_cycles_since_s cn52xx;
+ struct cvmx_tra_cycles_since_s cn52xxp1;
+ struct cvmx_tra_cycles_since_s cn56xx;
+ struct cvmx_tra_cycles_since_s cn56xxp1;
+ struct cvmx_tra_cycles_since_s cn58xx;
+ struct cvmx_tra_cycles_since_s cn58xxp1;
+} cvmx_tra_cycles_since_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_cycles_since1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t cycles:40;
+ uint64_t reserved_22_23:2;
+ uint64_t rptr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t wptr:10;
+#else
+ uint64_t wptr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t rptr:10;
+ uint64_t reserved_22_23:2;
+ uint64_t cycles:40;
+#endif
+ } s;
+ struct cvmx_tra_cycles_since1_s cn52xx;
+ struct cvmx_tra_cycles_since1_s cn52xxp1;
+ struct cvmx_tra_cycles_since1_s cn56xx;
+ struct cvmx_tra_cycles_since1_s cn56xxp1;
+ struct cvmx_tra_cycles_since1_s cn58xx;
+ struct cvmx_tra_cycles_since1_s cn58xxp1;
+} cvmx_tra_cycles_since1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_filt_adr_adr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_filt_adr_adr_s cn31xx;
+ struct cvmx_tra_filt_adr_adr_s cn38xx;
+ struct cvmx_tra_filt_adr_adr_s cn38xxp2;
+ struct cvmx_tra_filt_adr_adr_s cn52xx;
+ struct cvmx_tra_filt_adr_adr_s cn52xxp1;
+ struct cvmx_tra_filt_adr_adr_s cn56xx;
+ struct cvmx_tra_filt_adr_adr_s cn56xxp1;
+ struct cvmx_tra_filt_adr_adr_s cn58xx;
+ struct cvmx_tra_filt_adr_adr_s cn58xxp1;
+} cvmx_tra_filt_adr_adr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_filt_adr_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_filt_adr_msk_s cn31xx;
+ struct cvmx_tra_filt_adr_msk_s cn38xx;
+ struct cvmx_tra_filt_adr_msk_s cn38xxp2;
+ struct cvmx_tra_filt_adr_msk_s cn52xx;
+ struct cvmx_tra_filt_adr_msk_s cn52xxp1;
+ struct cvmx_tra_filt_adr_msk_s cn56xx;
+ struct cvmx_tra_filt_adr_msk_s cn56xxp1;
+ struct cvmx_tra_filt_adr_msk_s cn58xx;
+ struct cvmx_tra_filt_adr_msk_s cn58xxp1;
+} cvmx_tra_filt_adr_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_filt_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t saa:1;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t saa:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_tra_filt_cmd_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn31xx;
+ struct cvmx_tra_filt_cmd_cn31xx cn38xx;
+ struct cvmx_tra_filt_cmd_cn31xx cn38xxp2;
+ struct cvmx_tra_filt_cmd_s cn52xx;
+ struct cvmx_tra_filt_cmd_s cn52xxp1;
+ struct cvmx_tra_filt_cmd_s cn56xx;
+ struct cvmx_tra_filt_cmd_s cn56xxp1;
+ struct cvmx_tra_filt_cmd_s cn58xx;
+ struct cvmx_tra_filt_cmd_s cn58xxp1;
+} cvmx_tra_filt_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_filt_did_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t illegal:19;
+ uint64_t pow:1;
+ uint64_t illegal2:3;
+ uint64_t rng:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t pci:1;
+ uint64_t illegal3:2;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t illegal3:2;
+ uint64_t pci:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rng:1;
+ uint64_t illegal2:3;
+ uint64_t pow:1;
+ uint64_t illegal:19;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_tra_filt_did_s cn31xx;
+ struct cvmx_tra_filt_did_s cn38xx;
+ struct cvmx_tra_filt_did_s cn38xxp2;
+ struct cvmx_tra_filt_did_s cn52xx;
+ struct cvmx_tra_filt_did_s cn52xxp1;
+ struct cvmx_tra_filt_did_s cn56xx;
+ struct cvmx_tra_filt_did_s cn56xxp1;
+ struct cvmx_tra_filt_did_s cn58xx;
+ struct cvmx_tra_filt_did_s cn58xxp1;
+} cvmx_tra_filt_did_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_filt_sid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t dwb:1;
+ uint64_t iobreq:1;
+ uint64_t pko:1;
+ uint64_t pki:1;
+ uint64_t pp:16;
+#else
+ uint64_t pp:16;
+ uint64_t pki:1;
+ uint64_t pko:1;
+ uint64_t iobreq:1;
+ uint64_t dwb:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_tra_filt_sid_s cn31xx;
+ struct cvmx_tra_filt_sid_s cn38xx;
+ struct cvmx_tra_filt_sid_s cn38xxp2;
+ struct cvmx_tra_filt_sid_s cn52xx;
+ struct cvmx_tra_filt_sid_s cn52xxp1;
+ struct cvmx_tra_filt_sid_s cn56xx;
+ struct cvmx_tra_filt_sid_s cn56xxp1;
+ struct cvmx_tra_filt_sid_s cn58xx;
+ struct cvmx_tra_filt_sid_s cn58xxp1;
+} cvmx_tra_filt_sid_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_int_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_4_63:60;
+ uint64_t mcd0_thr:1;
+ uint64_t mcd0_trg:1;
+ uint64_t ciu_thr:1;
+ uint64_t ciu_trg:1;
+#else
+ uint64_t ciu_trg:1;
+ uint64_t ciu_thr:1;
+ uint64_t mcd0_trg:1;
+ uint64_t mcd0_thr:1;
+ uint64_t reserved_4_63:60;
+#endif
+ } s;
+ struct cvmx_tra_int_status_s cn31xx;
+ struct cvmx_tra_int_status_s cn38xx;
+ struct cvmx_tra_int_status_s cn38xxp2;
+ struct cvmx_tra_int_status_s cn52xx;
+ struct cvmx_tra_int_status_s cn52xxp1;
+ struct cvmx_tra_int_status_s cn56xx;
+ struct cvmx_tra_int_status_s cn56xxp1;
+ struct cvmx_tra_int_status_s cn58xx;
+ struct cvmx_tra_int_status_s cn58xxp1;
+} cvmx_tra_int_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_read_dat_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t data:64;
+#else
+ uint64_t data:64;
+#endif
+ } s;
+ struct cvmx_tra_read_dat_s cn31xx;
+ struct cvmx_tra_read_dat_s cn38xx;
+ struct cvmx_tra_read_dat_s cn38xxp2;
+ struct cvmx_tra_read_dat_s cn52xx;
+ struct cvmx_tra_read_dat_s cn52xxp1;
+ struct cvmx_tra_read_dat_s cn56xx;
+ struct cvmx_tra_read_dat_s cn56xxp1;
+ struct cvmx_tra_read_dat_s cn58xx;
+ struct cvmx_tra_read_dat_s cn58xxp1;
+} cvmx_tra_read_dat_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig0_adr_adr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_trig0_adr_adr_s cn31xx;
+ struct cvmx_tra_trig0_adr_adr_s cn38xx;
+ struct cvmx_tra_trig0_adr_adr_s cn38xxp2;
+ struct cvmx_tra_trig0_adr_adr_s cn52xx;
+ struct cvmx_tra_trig0_adr_adr_s cn52xxp1;
+ struct cvmx_tra_trig0_adr_adr_s cn56xx;
+ struct cvmx_tra_trig0_adr_adr_s cn56xxp1;
+ struct cvmx_tra_trig0_adr_adr_s cn58xx;
+ struct cvmx_tra_trig0_adr_adr_s cn58xxp1;
+} cvmx_tra_trig0_adr_adr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig0_adr_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_trig0_adr_msk_s cn31xx;
+ struct cvmx_tra_trig0_adr_msk_s cn38xx;
+ struct cvmx_tra_trig0_adr_msk_s cn38xxp2;
+ struct cvmx_tra_trig0_adr_msk_s cn52xx;
+ struct cvmx_tra_trig0_adr_msk_s cn52xxp1;
+ struct cvmx_tra_trig0_adr_msk_s cn56xx;
+ struct cvmx_tra_trig0_adr_msk_s cn56xxp1;
+ struct cvmx_tra_trig0_adr_msk_s cn58xx;
+ struct cvmx_tra_trig0_adr_msk_s cn58xxp1;
+} cvmx_tra_trig0_adr_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig0_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t saa:1;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t saa:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_tra_trig0_cmd_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn31xx;
+ struct cvmx_tra_trig0_cmd_cn31xx cn38xx;
+ struct cvmx_tra_trig0_cmd_cn31xx cn38xxp2;
+ struct cvmx_tra_trig0_cmd_s cn52xx;
+ struct cvmx_tra_trig0_cmd_s cn52xxp1;
+ struct cvmx_tra_trig0_cmd_s cn56xx;
+ struct cvmx_tra_trig0_cmd_s cn56xxp1;
+ struct cvmx_tra_trig0_cmd_s cn58xx;
+ struct cvmx_tra_trig0_cmd_s cn58xxp1;
+} cvmx_tra_trig0_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig0_did_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t illegal:19;
+ uint64_t pow:1;
+ uint64_t illegal2:3;
+ uint64_t rng:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t pci:1;
+ uint64_t illegal3:2;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t illegal3:2;
+ uint64_t pci:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rng:1;
+ uint64_t illegal2:3;
+ uint64_t pow:1;
+ uint64_t illegal:19;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_tra_trig0_did_s cn31xx;
+ struct cvmx_tra_trig0_did_s cn38xx;
+ struct cvmx_tra_trig0_did_s cn38xxp2;
+ struct cvmx_tra_trig0_did_s cn52xx;
+ struct cvmx_tra_trig0_did_s cn52xxp1;
+ struct cvmx_tra_trig0_did_s cn56xx;
+ struct cvmx_tra_trig0_did_s cn56xxp1;
+ struct cvmx_tra_trig0_did_s cn58xx;
+ struct cvmx_tra_trig0_did_s cn58xxp1;
+} cvmx_tra_trig0_did_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig0_sid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t dwb:1;
+ uint64_t iobreq:1;
+ uint64_t pko:1;
+ uint64_t pki:1;
+ uint64_t pp:16;
+#else
+ uint64_t pp:16;
+ uint64_t pki:1;
+ uint64_t pko:1;
+ uint64_t iobreq:1;
+ uint64_t dwb:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_tra_trig0_sid_s cn31xx;
+ struct cvmx_tra_trig0_sid_s cn38xx;
+ struct cvmx_tra_trig0_sid_s cn38xxp2;
+ struct cvmx_tra_trig0_sid_s cn52xx;
+ struct cvmx_tra_trig0_sid_s cn52xxp1;
+ struct cvmx_tra_trig0_sid_s cn56xx;
+ struct cvmx_tra_trig0_sid_s cn56xxp1;
+ struct cvmx_tra_trig0_sid_s cn58xx;
+ struct cvmx_tra_trig0_sid_s cn58xxp1;
+} cvmx_tra_trig0_sid_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig1_adr_adr_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_trig1_adr_adr_s cn31xx;
+ struct cvmx_tra_trig1_adr_adr_s cn38xx;
+ struct cvmx_tra_trig1_adr_adr_s cn38xxp2;
+ struct cvmx_tra_trig1_adr_adr_s cn52xx;
+ struct cvmx_tra_trig1_adr_adr_s cn52xxp1;
+ struct cvmx_tra_trig1_adr_adr_s cn56xx;
+ struct cvmx_tra_trig1_adr_adr_s cn56xxp1;
+ struct cvmx_tra_trig1_adr_adr_s cn58xx;
+ struct cvmx_tra_trig1_adr_adr_s cn58xxp1;
+} cvmx_tra_trig1_adr_adr_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig1_adr_msk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t adr:36;
+#else
+ uint64_t adr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_tra_trig1_adr_msk_s cn31xx;
+ struct cvmx_tra_trig1_adr_msk_s cn38xx;
+ struct cvmx_tra_trig1_adr_msk_s cn38xxp2;
+ struct cvmx_tra_trig1_adr_msk_s cn52xx;
+ struct cvmx_tra_trig1_adr_msk_s cn52xxp1;
+ struct cvmx_tra_trig1_adr_msk_s cn56xx;
+ struct cvmx_tra_trig1_adr_msk_s cn56xxp1;
+ struct cvmx_tra_trig1_adr_msk_s cn58xx;
+ struct cvmx_tra_trig1_adr_msk_s cn58xxp1;
+} cvmx_tra_trig1_adr_msk_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig1_cmd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_17_63:47;
+ uint64_t saa:1;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t saa:1;
+ uint64_t reserved_17_63:47;
+#endif
+ } s;
+ struct cvmx_tra_trig1_cmd_cn31xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_16_63:48;
+ uint64_t iobdma:1;
+ uint64_t iobst:1;
+ uint64_t iobld64:1;
+ uint64_t iobld32:1;
+ uint64_t iobld16:1;
+ uint64_t iobld8:1;
+ uint64_t stt:1;
+ uint64_t stp:1;
+ uint64_t stc:1;
+ uint64_t stf:1;
+ uint64_t ldt:1;
+ uint64_t ldi:1;
+ uint64_t ldd:1;
+ uint64_t psl1:1;
+ uint64_t pl2:1;
+ uint64_t dwb:1;
+#else
+ uint64_t dwb:1;
+ uint64_t pl2:1;
+ uint64_t psl1:1;
+ uint64_t ldd:1;
+ uint64_t ldi:1;
+ uint64_t ldt:1;
+ uint64_t stf:1;
+ uint64_t stc:1;
+ uint64_t stp:1;
+ uint64_t stt:1;
+ uint64_t iobld8:1;
+ uint64_t iobld16:1;
+ uint64_t iobld32:1;
+ uint64_t iobld64:1;
+ uint64_t iobst:1;
+ uint64_t iobdma:1;
+ uint64_t reserved_16_63:48;
+#endif
+ } cn31xx;
+ struct cvmx_tra_trig1_cmd_cn31xx cn38xx;
+ struct cvmx_tra_trig1_cmd_cn31xx cn38xxp2;
+ struct cvmx_tra_trig1_cmd_s cn52xx;
+ struct cvmx_tra_trig1_cmd_s cn52xxp1;
+ struct cvmx_tra_trig1_cmd_s cn56xx;
+ struct cvmx_tra_trig1_cmd_s cn56xxp1;
+ struct cvmx_tra_trig1_cmd_s cn58xx;
+ struct cvmx_tra_trig1_cmd_s cn58xxp1;
+} cvmx_tra_trig1_cmd_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig1_did_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_32_63:32;
+ uint64_t illegal:19;
+ uint64_t pow:1;
+ uint64_t illegal2:3;
+ uint64_t rng:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t pci:1;
+ uint64_t illegal3:2;
+ uint64_t mio:1;
+#else
+ uint64_t mio:1;
+ uint64_t illegal3:2;
+ uint64_t pci:1;
+ uint64_t key:1;
+ uint64_t fpa:1;
+ uint64_t dfa:1;
+ uint64_t zip:1;
+ uint64_t rng:1;
+ uint64_t illegal2:3;
+ uint64_t pow:1;
+ uint64_t illegal:19;
+ uint64_t reserved_32_63:32;
+#endif
+ } s;
+ struct cvmx_tra_trig1_did_s cn31xx;
+ struct cvmx_tra_trig1_did_s cn38xx;
+ struct cvmx_tra_trig1_did_s cn38xxp2;
+ struct cvmx_tra_trig1_did_s cn52xx;
+ struct cvmx_tra_trig1_did_s cn52xxp1;
+ struct cvmx_tra_trig1_did_s cn56xx;
+ struct cvmx_tra_trig1_did_s cn56xxp1;
+ struct cvmx_tra_trig1_did_s cn58xx;
+ struct cvmx_tra_trig1_did_s cn58xxp1;
+} cvmx_tra_trig1_did_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_tra_trig1_sid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t dwb:1;
+ uint64_t iobreq:1;
+ uint64_t pko:1;
+ uint64_t pki:1;
+ uint64_t pp:16;
+#else
+ uint64_t pp:16;
+ uint64_t pki:1;
+ uint64_t pko:1;
+ uint64_t iobreq:1;
+ uint64_t dwb:1;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_tra_trig1_sid_s cn31xx;
+ struct cvmx_tra_trig1_sid_s cn38xx;
+ struct cvmx_tra_trig1_sid_s cn38xxp2;
+ struct cvmx_tra_trig1_sid_s cn52xx;
+ struct cvmx_tra_trig1_sid_s cn52xxp1;
+ struct cvmx_tra_trig1_sid_s cn56xx;
+ struct cvmx_tra_trig1_sid_s cn56xxp1;
+ struct cvmx_tra_trig1_sid_s cn58xx;
+ struct cvmx_tra_trig1_sid_s cn58xxp1;
+} cvmx_tra_trig1_sid_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_daint_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t outepint:16;
+ uint32_t inepint:16;
+#else
+ uint32_t inepint:16;
+ uint32_t outepint:16;
+#endif
+ } s;
+ struct cvmx_usbcx_daint_s cn30xx;
+ struct cvmx_usbcx_daint_s cn31xx;
+ struct cvmx_usbcx_daint_s cn50xx;
+ struct cvmx_usbcx_daint_s cn52xx;
+ struct cvmx_usbcx_daint_s cn52xxp1;
+ struct cvmx_usbcx_daint_s cn56xx;
+ struct cvmx_usbcx_daint_s cn56xxp1;
+} cvmx_usbcx_daint_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_daintmsk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t outepmsk:16;
+ uint32_t inepmsk:16;
+#else
+ uint32_t inepmsk:16;
+ uint32_t outepmsk:16;
+#endif
+ } s;
+ struct cvmx_usbcx_daintmsk_s cn30xx;
+ struct cvmx_usbcx_daintmsk_s cn31xx;
+ struct cvmx_usbcx_daintmsk_s cn50xx;
+ struct cvmx_usbcx_daintmsk_s cn52xx;
+ struct cvmx_usbcx_daintmsk_s cn52xxp1;
+ struct cvmx_usbcx_daintmsk_s cn56xx;
+ struct cvmx_usbcx_daintmsk_s cn56xxp1;
+} cvmx_usbcx_daintmsk_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_23_31:9;
+ uint32_t epmiscnt:5;
+ uint32_t reserved_13_17:5;
+ uint32_t perfrint:2;
+ uint32_t devaddr:7;
+ uint32_t reserved_3_3:1;
+ uint32_t nzstsouthshk:1;
+ uint32_t devspd:2;
+#else
+ uint32_t devspd:2;
+ uint32_t nzstsouthshk:1;
+ uint32_t reserved_3_3:1;
+ uint32_t devaddr:7;
+ uint32_t perfrint:2;
+ uint32_t reserved_13_17:5;
+ uint32_t epmiscnt:5;
+ uint32_t reserved_23_31:9;
+#endif
+ } s;
+ struct cvmx_usbcx_dcfg_s cn30xx;
+ struct cvmx_usbcx_dcfg_s cn31xx;
+ struct cvmx_usbcx_dcfg_s cn50xx;
+ struct cvmx_usbcx_dcfg_s cn52xx;
+ struct cvmx_usbcx_dcfg_s cn52xxp1;
+ struct cvmx_usbcx_dcfg_s cn56xx;
+ struct cvmx_usbcx_dcfg_s cn56xxp1;
+} cvmx_usbcx_dcfg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_12_31:20;
+ uint32_t pwronprgdone:1;
+ uint32_t cgoutnak:1;
+ uint32_t sgoutnak:1;
+ uint32_t cgnpinnak:1;
+ uint32_t sgnpinnak:1;
+ uint32_t tstctl:3;
+ uint32_t goutnaksts:1;
+ uint32_t gnpinnaksts:1;
+ uint32_t sftdiscon:1;
+ uint32_t rmtwkupsig:1;
+#else
+ uint32_t rmtwkupsig:1;
+ uint32_t sftdiscon:1;
+ uint32_t gnpinnaksts:1;
+ uint32_t goutnaksts:1;
+ uint32_t tstctl:3;
+ uint32_t sgnpinnak:1;
+ uint32_t cgnpinnak:1;
+ uint32_t sgoutnak:1;
+ uint32_t cgoutnak:1;
+ uint32_t pwronprgdone:1;
+ uint32_t reserved_12_31:20;
+#endif
+ } s;
+ struct cvmx_usbcx_dctl_s cn30xx;
+ struct cvmx_usbcx_dctl_s cn31xx;
+ struct cvmx_usbcx_dctl_s cn50xx;
+ struct cvmx_usbcx_dctl_s cn52xx;
+ struct cvmx_usbcx_dctl_s cn52xxp1;
+ struct cvmx_usbcx_dctl_s cn56xx;
+ struct cvmx_usbcx_dctl_s cn56xxp1;
+} cvmx_usbcx_dctl_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_diepctlx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t epena:1;
+ uint32_t epdis:1;
+ uint32_t setd1pid:1;
+ uint32_t setd0pid:1;
+ uint32_t snak:1;
+ uint32_t cnak:1;
+ uint32_t txfnum:4;
+ uint32_t stall:1;
+ uint32_t reserved_20_20:1;
+ uint32_t eptype:2;
+ uint32_t naksts:1;
+ uint32_t dpid:1;
+ uint32_t usbactep:1;
+ uint32_t nextep:4;
+ uint32_t mps:11;
+#else
+ uint32_t mps:11;
+ uint32_t nextep:4;
+ uint32_t usbactep:1;
+ uint32_t dpid:1;
+ uint32_t naksts:1;
+ uint32_t eptype:2;
+ uint32_t reserved_20_20:1;
+ uint32_t stall:1;
+ uint32_t txfnum:4;
+ uint32_t cnak:1;
+ uint32_t snak:1;
+ uint32_t setd0pid:1;
+ uint32_t setd1pid:1;
+ uint32_t epdis:1;
+ uint32_t epena:1;
+#endif
+ } s;
+ struct cvmx_usbcx_diepctlx_s cn30xx;
+ struct cvmx_usbcx_diepctlx_s cn31xx;
+ struct cvmx_usbcx_diepctlx_s cn50xx;
+ struct cvmx_usbcx_diepctlx_s cn52xx;
+ struct cvmx_usbcx_diepctlx_s cn52xxp1;
+ struct cvmx_usbcx_diepctlx_s cn56xx;
+ struct cvmx_usbcx_diepctlx_s cn56xxp1;
+} cvmx_usbcx_diepctlx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_diepintx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_7_31:25;
+ uint32_t inepnakeff:1;
+ uint32_t intknepmis:1;
+ uint32_t intkntxfemp:1;
+ uint32_t timeout:1;
+ uint32_t ahberr:1;
+ uint32_t epdisbld:1;
+ uint32_t xfercompl:1;
+#else
+ uint32_t xfercompl:1;
+ uint32_t epdisbld:1;
+ uint32_t ahberr:1;
+ uint32_t timeout:1;
+ uint32_t intkntxfemp:1;
+ uint32_t intknepmis:1;
+ uint32_t inepnakeff:1;
+ uint32_t reserved_7_31:25;
+#endif
+ } s;
+ struct cvmx_usbcx_diepintx_s cn30xx;
+ struct cvmx_usbcx_diepintx_s cn31xx;
+ struct cvmx_usbcx_diepintx_s cn50xx;
+ struct cvmx_usbcx_diepintx_s cn52xx;
+ struct cvmx_usbcx_diepintx_s cn52xxp1;
+ struct cvmx_usbcx_diepintx_s cn56xx;
+ struct cvmx_usbcx_diepintx_s cn56xxp1;
+} cvmx_usbcx_diepintx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_diepmsk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_7_31:25;
+ uint32_t inepnakeffmsk:1;
+ uint32_t intknepmismsk:1;
+ uint32_t intkntxfempmsk:1;
+ uint32_t timeoutmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t epdisbldmsk:1;
+ uint32_t xfercomplmsk:1;
+#else
+ uint32_t xfercomplmsk:1;
+ uint32_t epdisbldmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t timeoutmsk:1;
+ uint32_t intkntxfempmsk:1;
+ uint32_t intknepmismsk:1;
+ uint32_t inepnakeffmsk:1;
+ uint32_t reserved_7_31:25;
+#endif
+ } s;
+ struct cvmx_usbcx_diepmsk_s cn30xx;
+ struct cvmx_usbcx_diepmsk_s cn31xx;
+ struct cvmx_usbcx_diepmsk_s cn50xx;
+ struct cvmx_usbcx_diepmsk_s cn52xx;
+ struct cvmx_usbcx_diepmsk_s cn52xxp1;
+ struct cvmx_usbcx_diepmsk_s cn56xx;
+ struct cvmx_usbcx_diepmsk_s cn56xxp1;
+} cvmx_usbcx_diepmsk_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dieptsizx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_31_31:1;
+ uint32_t mc:2;
+ uint32_t pktcnt:10;
+ uint32_t xfersize:19;
+#else
+ uint32_t xfersize:19;
+ uint32_t pktcnt:10;
+ uint32_t mc:2;
+ uint32_t reserved_31_31:1;
+#endif
+ } s;
+ struct cvmx_usbcx_dieptsizx_s cn30xx;
+ struct cvmx_usbcx_dieptsizx_s cn31xx;
+ struct cvmx_usbcx_dieptsizx_s cn50xx;
+ struct cvmx_usbcx_dieptsizx_s cn52xx;
+ struct cvmx_usbcx_dieptsizx_s cn52xxp1;
+ struct cvmx_usbcx_dieptsizx_s cn56xx;
+ struct cvmx_usbcx_dieptsizx_s cn56xxp1;
+} cvmx_usbcx_dieptsizx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_doepctlx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t epena:1;
+ uint32_t epdis:1;
+ uint32_t setd1pid:1;
+ uint32_t setd0pid:1;
+ uint32_t snak:1;
+ uint32_t cnak:1;
+ uint32_t reserved_22_25:4;
+ uint32_t stall:1;
+ uint32_t snp:1;
+ uint32_t eptype:2;
+ uint32_t naksts:1;
+ uint32_t dpid:1;
+ uint32_t usbactep:1;
+ uint32_t reserved_11_14:4;
+ uint32_t mps:11;
+#else
+ uint32_t mps:11;
+ uint32_t reserved_11_14:4;
+ uint32_t usbactep:1;
+ uint32_t dpid:1;
+ uint32_t naksts:1;
+ uint32_t eptype:2;
+ uint32_t snp:1;
+ uint32_t stall:1;
+ uint32_t reserved_22_25:4;
+ uint32_t cnak:1;
+ uint32_t snak:1;
+ uint32_t setd0pid:1;
+ uint32_t setd1pid:1;
+ uint32_t epdis:1;
+ uint32_t epena:1;
+#endif
+ } s;
+ struct cvmx_usbcx_doepctlx_s cn30xx;
+ struct cvmx_usbcx_doepctlx_s cn31xx;
+ struct cvmx_usbcx_doepctlx_s cn50xx;
+ struct cvmx_usbcx_doepctlx_s cn52xx;
+ struct cvmx_usbcx_doepctlx_s cn52xxp1;
+ struct cvmx_usbcx_doepctlx_s cn56xx;
+ struct cvmx_usbcx_doepctlx_s cn56xxp1;
+} cvmx_usbcx_doepctlx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_doepintx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t outtknepdis:1;
+ uint32_t setup:1;
+ uint32_t ahberr:1;
+ uint32_t epdisbld:1;
+ uint32_t xfercompl:1;
+#else
+ uint32_t xfercompl:1;
+ uint32_t epdisbld:1;
+ uint32_t ahberr:1;
+ uint32_t setup:1;
+ uint32_t outtknepdis:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_usbcx_doepintx_s cn30xx;
+ struct cvmx_usbcx_doepintx_s cn31xx;
+ struct cvmx_usbcx_doepintx_s cn50xx;
+ struct cvmx_usbcx_doepintx_s cn52xx;
+ struct cvmx_usbcx_doepintx_s cn52xxp1;
+ struct cvmx_usbcx_doepintx_s cn56xx;
+ struct cvmx_usbcx_doepintx_s cn56xxp1;
+} cvmx_usbcx_doepintx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_doepmsk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t outtknepdismsk:1;
+ uint32_t setupmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t epdisbldmsk:1;
+ uint32_t xfercomplmsk:1;
+#else
+ uint32_t xfercomplmsk:1;
+ uint32_t epdisbldmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t setupmsk:1;
+ uint32_t outtknepdismsk:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_usbcx_doepmsk_s cn30xx;
+ struct cvmx_usbcx_doepmsk_s cn31xx;
+ struct cvmx_usbcx_doepmsk_s cn50xx;
+ struct cvmx_usbcx_doepmsk_s cn52xx;
+ struct cvmx_usbcx_doepmsk_s cn52xxp1;
+ struct cvmx_usbcx_doepmsk_s cn56xx;
+ struct cvmx_usbcx_doepmsk_s cn56xxp1;
+} cvmx_usbcx_doepmsk_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_doeptsizx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_31_31:1;
+ uint32_t mc:2;
+ uint32_t pktcnt:10;
+ uint32_t xfersize:19;
+#else
+ uint32_t xfersize:19;
+ uint32_t pktcnt:10;
+ uint32_t mc:2;
+ uint32_t reserved_31_31:1;
+#endif
+ } s;
+ struct cvmx_usbcx_doeptsizx_s cn30xx;
+ struct cvmx_usbcx_doeptsizx_s cn31xx;
+ struct cvmx_usbcx_doeptsizx_s cn50xx;
+ struct cvmx_usbcx_doeptsizx_s cn52xx;
+ struct cvmx_usbcx_doeptsizx_s cn52xxp1;
+ struct cvmx_usbcx_doeptsizx_s cn56xx;
+ struct cvmx_usbcx_doeptsizx_s cn56xxp1;
+} cvmx_usbcx_doeptsizx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dptxfsizx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dptxfsize:16;
+ uint32_t dptxfstaddr:16;
+#else
+ uint32_t dptxfstaddr:16;
+ uint32_t dptxfsize:16;
+#endif
+ } s;
+ struct cvmx_usbcx_dptxfsizx_s cn30xx;
+ struct cvmx_usbcx_dptxfsizx_s cn31xx;
+ struct cvmx_usbcx_dptxfsizx_s cn50xx;
+ struct cvmx_usbcx_dptxfsizx_s cn52xx;
+ struct cvmx_usbcx_dptxfsizx_s cn52xxp1;
+ struct cvmx_usbcx_dptxfsizx_s cn56xx;
+ struct cvmx_usbcx_dptxfsizx_s cn56xxp1;
+} cvmx_usbcx_dptxfsizx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dsts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_22_31:10;
+ uint32_t soffn:14;
+ uint32_t reserved_4_7:4;
+ uint32_t errticerr:1;
+ uint32_t enumspd:2;
+ uint32_t suspsts:1;
+#else
+ uint32_t suspsts:1;
+ uint32_t enumspd:2;
+ uint32_t errticerr:1;
+ uint32_t reserved_4_7:4;
+ uint32_t soffn:14;
+ uint32_t reserved_22_31:10;
+#endif
+ } s;
+ struct cvmx_usbcx_dsts_s cn30xx;
+ struct cvmx_usbcx_dsts_s cn31xx;
+ struct cvmx_usbcx_dsts_s cn50xx;
+ struct cvmx_usbcx_dsts_s cn52xx;
+ struct cvmx_usbcx_dsts_s cn52xxp1;
+ struct cvmx_usbcx_dsts_s cn56xx;
+ struct cvmx_usbcx_dsts_s cn56xxp1;
+} cvmx_usbcx_dsts_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dtknqr1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t eptkn:24;
+ uint32_t wrapbit:1;
+ uint32_t reserved_5_6:2;
+ uint32_t intknwptr:5;
+#else
+ uint32_t intknwptr:5;
+ uint32_t reserved_5_6:2;
+ uint32_t wrapbit:1;
+ uint32_t eptkn:24;
+#endif
+ } s;
+ struct cvmx_usbcx_dtknqr1_s cn30xx;
+ struct cvmx_usbcx_dtknqr1_s cn31xx;
+ struct cvmx_usbcx_dtknqr1_s cn50xx;
+ struct cvmx_usbcx_dtknqr1_s cn52xx;
+ struct cvmx_usbcx_dtknqr1_s cn52xxp1;
+ struct cvmx_usbcx_dtknqr1_s cn56xx;
+ struct cvmx_usbcx_dtknqr1_s cn56xxp1;
+} cvmx_usbcx_dtknqr1_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dtknqr2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t eptkn:32;
+#else
+ uint32_t eptkn:32;
+#endif
+ } s;
+ struct cvmx_usbcx_dtknqr2_s cn30xx;
+ struct cvmx_usbcx_dtknqr2_s cn31xx;
+ struct cvmx_usbcx_dtknqr2_s cn50xx;
+ struct cvmx_usbcx_dtknqr2_s cn52xx;
+ struct cvmx_usbcx_dtknqr2_s cn52xxp1;
+ struct cvmx_usbcx_dtknqr2_s cn56xx;
+ struct cvmx_usbcx_dtknqr2_s cn56xxp1;
+} cvmx_usbcx_dtknqr2_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dtknqr3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t eptkn:32;
+#else
+ uint32_t eptkn:32;
+#endif
+ } s;
+ struct cvmx_usbcx_dtknqr3_s cn30xx;
+ struct cvmx_usbcx_dtknqr3_s cn31xx;
+ struct cvmx_usbcx_dtknqr3_s cn50xx;
+ struct cvmx_usbcx_dtknqr3_s cn52xx;
+ struct cvmx_usbcx_dtknqr3_s cn52xxp1;
+ struct cvmx_usbcx_dtknqr3_s cn56xx;
+ struct cvmx_usbcx_dtknqr3_s cn56xxp1;
+} cvmx_usbcx_dtknqr3_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_dtknqr4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t eptkn:32;
+#else
+ uint32_t eptkn:32;
+#endif
+ } s;
+ struct cvmx_usbcx_dtknqr4_s cn30xx;
+ struct cvmx_usbcx_dtknqr4_s cn31xx;
+ struct cvmx_usbcx_dtknqr4_s cn50xx;
+ struct cvmx_usbcx_dtknqr4_s cn52xx;
+ struct cvmx_usbcx_dtknqr4_s cn52xxp1;
+ struct cvmx_usbcx_dtknqr4_s cn56xx;
+ struct cvmx_usbcx_dtknqr4_s cn56xxp1;
+} cvmx_usbcx_dtknqr4_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gahbcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_9_31:23;
+ uint32_t ptxfemplvl:1;
+ uint32_t nptxfemplvl:1;
+ uint32_t reserved_6_6:1;
+ uint32_t dmaen:1;
+ uint32_t hbstlen:4;
+ uint32_t glblintrmsk:1;
+#else
+ uint32_t glblintrmsk:1;
+ uint32_t hbstlen:4;
+ uint32_t dmaen:1;
+ uint32_t reserved_6_6:1;
+ uint32_t nptxfemplvl:1;
+ uint32_t ptxfemplvl:1;
+ uint32_t reserved_9_31:23;
+#endif
+ } s;
+ struct cvmx_usbcx_gahbcfg_s cn30xx;
+ struct cvmx_usbcx_gahbcfg_s cn31xx;
+ struct cvmx_usbcx_gahbcfg_s cn50xx;
+ struct cvmx_usbcx_gahbcfg_s cn52xx;
+ struct cvmx_usbcx_gahbcfg_s cn52xxp1;
+ struct cvmx_usbcx_gahbcfg_s cn56xx;
+ struct cvmx_usbcx_gahbcfg_s cn56xxp1;
+} cvmx_usbcx_gahbcfg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_ghwcfg1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t epdir:32;
+#else
+ uint32_t epdir:32;
+#endif
+ } s;
+ struct cvmx_usbcx_ghwcfg1_s cn30xx;
+ struct cvmx_usbcx_ghwcfg1_s cn31xx;
+ struct cvmx_usbcx_ghwcfg1_s cn50xx;
+ struct cvmx_usbcx_ghwcfg1_s cn52xx;
+ struct cvmx_usbcx_ghwcfg1_s cn52xxp1;
+ struct cvmx_usbcx_ghwcfg1_s cn56xx;
+ struct cvmx_usbcx_ghwcfg1_s cn56xxp1;
+} cvmx_usbcx_ghwcfg1_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_ghwcfg2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_31_31:1;
+ uint32_t tknqdepth:5;
+ uint32_t ptxqdepth:2;
+ uint32_t nptxqdepth:2;
+ uint32_t reserved_20_21:2;
+ uint32_t dynfifosizing:1;
+ uint32_t periosupport:1;
+ uint32_t numhstchnl:4;
+ uint32_t numdeveps:4;
+ uint32_t fsphytype:2;
+ uint32_t hsphytype:2;
+ uint32_t singpnt:1;
+ uint32_t otgarch:2;
+ uint32_t otgmode:3;
+#else
+ uint32_t otgmode:3;
+ uint32_t otgarch:2;
+ uint32_t singpnt:1;
+ uint32_t hsphytype:2;
+ uint32_t fsphytype:2;
+ uint32_t numdeveps:4;
+ uint32_t numhstchnl:4;
+ uint32_t periosupport:1;
+ uint32_t dynfifosizing:1;
+ uint32_t reserved_20_21:2;
+ uint32_t nptxqdepth:2;
+ uint32_t ptxqdepth:2;
+ uint32_t tknqdepth:5;
+ uint32_t reserved_31_31:1;
+#endif
+ } s;
+ struct cvmx_usbcx_ghwcfg2_s cn30xx;
+ struct cvmx_usbcx_ghwcfg2_s cn31xx;
+ struct cvmx_usbcx_ghwcfg2_s cn50xx;
+ struct cvmx_usbcx_ghwcfg2_s cn52xx;
+ struct cvmx_usbcx_ghwcfg2_s cn52xxp1;
+ struct cvmx_usbcx_ghwcfg2_s cn56xx;
+ struct cvmx_usbcx_ghwcfg2_s cn56xxp1;
+} cvmx_usbcx_ghwcfg2_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_ghwcfg3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dfifodepth:16;
+ uint32_t reserved_13_15:3;
+ uint32_t ahbphysync:1;
+ uint32_t rsttype:1;
+ uint32_t optfeature:1;
+ uint32_t vendor_control_interface_support:1;
+
+ uint32_t i2c_selection:1;
+ uint32_t otgen:1;
+ uint32_t pktsizewidth:3;
+ uint32_t xfersizewidth:4;
+#else
+ uint32_t xfersizewidth:4;
+ uint32_t pktsizewidth:3;
+ uint32_t otgen:1;
+ uint32_t i2c_selection:1;
+ uint32_t vendor_control_interface_support:1;
+ uint32_t optfeature:1;
+ uint32_t rsttype:1;
+ uint32_t ahbphysync:1;
+ uint32_t reserved_13_15:3;
+ uint32_t dfifodepth:16;
+#endif
+ } s;
+ struct cvmx_usbcx_ghwcfg3_s cn30xx;
+ struct cvmx_usbcx_ghwcfg3_s cn31xx;
+ struct cvmx_usbcx_ghwcfg3_s cn50xx;
+ struct cvmx_usbcx_ghwcfg3_s cn52xx;
+ struct cvmx_usbcx_ghwcfg3_s cn52xxp1;
+ struct cvmx_usbcx_ghwcfg3_s cn56xx;
+ struct cvmx_usbcx_ghwcfg3_s cn56xxp1;
+} cvmx_usbcx_ghwcfg3_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_ghwcfg4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_30_31:2;
+ uint32_t numdevmodinend:4;
+ uint32_t endedtrfifo:1;
+ uint32_t sessendfltr:1;
+ uint32_t bvalidfltr:1;
+ uint32_t avalidfltr:1;
+ uint32_t vbusvalidfltr:1;
+ uint32_t iddgfltr:1;
+ uint32_t numctleps:4;
+ uint32_t phydatawidth:2;
+ uint32_t reserved_6_13:8;
+ uint32_t ahbfreq:1;
+ uint32_t enablepwropt:1;
+ uint32_t numdevperioeps:4;
+#else
+ uint32_t numdevperioeps:4;
+ uint32_t enablepwropt:1;
+ uint32_t ahbfreq:1;
+ uint32_t reserved_6_13:8;
+ uint32_t phydatawidth:2;
+ uint32_t numctleps:4;
+ uint32_t iddgfltr:1;
+ uint32_t vbusvalidfltr:1;
+ uint32_t avalidfltr:1;
+ uint32_t bvalidfltr:1;
+ uint32_t sessendfltr:1;
+ uint32_t endedtrfifo:1;
+ uint32_t numdevmodinend:4;
+ uint32_t reserved_30_31:2;
+#endif
+ } s;
+ struct cvmx_usbcx_ghwcfg4_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_25_31:7;
+ uint32_t sessendfltr:1;
+ uint32_t bvalidfltr:1;
+ uint32_t avalidfltr:1;
+ uint32_t vbusvalidfltr:1;
+ uint32_t iddgfltr:1;
+ uint32_t numctleps:4;
+ uint32_t phydatawidth:2;
+ uint32_t reserved_6_13:8;
+ uint32_t ahbfreq:1;
+ uint32_t enablepwropt:1;
+ uint32_t numdevperioeps:4;
+#else
+ uint32_t numdevperioeps:4;
+ uint32_t enablepwropt:1;
+ uint32_t ahbfreq:1;
+ uint32_t reserved_6_13:8;
+ uint32_t phydatawidth:2;
+ uint32_t numctleps:4;
+ uint32_t iddgfltr:1;
+ uint32_t vbusvalidfltr:1;
+ uint32_t avalidfltr:1;
+ uint32_t bvalidfltr:1;
+ uint32_t sessendfltr:1;
+ uint32_t reserved_25_31:7;
+#endif
+ } cn30xx;
+ struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx;
+ struct cvmx_usbcx_ghwcfg4_s cn50xx;
+ struct cvmx_usbcx_ghwcfg4_s cn52xx;
+ struct cvmx_usbcx_ghwcfg4_s cn52xxp1;
+ struct cvmx_usbcx_ghwcfg4_s cn56xx;
+ struct cvmx_usbcx_ghwcfg4_s cn56xxp1;
+} cvmx_usbcx_ghwcfg4_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gintmsk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wkupintmsk:1;
+ uint32_t sessreqintmsk:1;
+ uint32_t disconnintmsk:1;
+ uint32_t conidstschngmsk:1;
+ uint32_t reserved_27_27:1;
+ uint32_t ptxfempmsk:1;
+ uint32_t hchintmsk:1;
+ uint32_t prtintmsk:1;
+ uint32_t reserved_23_23:1;
+ uint32_t fetsuspmsk:1;
+ uint32_t incomplpmsk:1;
+ uint32_t incompisoinmsk:1;
+ uint32_t oepintmsk:1;
+ uint32_t inepintmsk:1;
+ uint32_t epmismsk:1;
+ uint32_t reserved_16_16:1;
+ uint32_t eopfmsk:1;
+ uint32_t isooutdropmsk:1;
+ uint32_t enumdonemsk:1;
+ uint32_t usbrstmsk:1;
+ uint32_t usbsuspmsk:1;
+ uint32_t erlysuspmsk:1;
+ uint32_t i2cint:1;
+ uint32_t ulpickintmsk:1;
+ uint32_t goutnakeffmsk:1;
+ uint32_t ginnakeffmsk:1;
+ uint32_t nptxfempmsk:1;
+ uint32_t rxflvlmsk:1;
+ uint32_t sofmsk:1;
+ uint32_t otgintmsk:1;
+ uint32_t modemismsk:1;
+ uint32_t reserved_0_0:1;
+#else
+ uint32_t reserved_0_0:1;
+ uint32_t modemismsk:1;
+ uint32_t otgintmsk:1;
+ uint32_t sofmsk:1;
+ uint32_t rxflvlmsk:1;
+ uint32_t nptxfempmsk:1;
+ uint32_t ginnakeffmsk:1;
+ uint32_t goutnakeffmsk:1;
+ uint32_t ulpickintmsk:1;
+ uint32_t i2cint:1;
+ uint32_t erlysuspmsk:1;
+ uint32_t usbsuspmsk:1;
+ uint32_t usbrstmsk:1;
+ uint32_t enumdonemsk:1;
+ uint32_t isooutdropmsk:1;
+ uint32_t eopfmsk:1;
+ uint32_t reserved_16_16:1;
+ uint32_t epmismsk:1;
+ uint32_t inepintmsk:1;
+ uint32_t oepintmsk:1;
+ uint32_t incompisoinmsk:1;
+ uint32_t incomplpmsk:1;
+ uint32_t fetsuspmsk:1;
+ uint32_t reserved_23_23:1;
+ uint32_t prtintmsk:1;
+ uint32_t hchintmsk:1;
+ uint32_t ptxfempmsk:1;
+ uint32_t reserved_27_27:1;
+ uint32_t conidstschngmsk:1;
+ uint32_t disconnintmsk:1;
+ uint32_t sessreqintmsk:1;
+ uint32_t wkupintmsk:1;
+#endif
+ } s;
+ struct cvmx_usbcx_gintmsk_s cn30xx;
+ struct cvmx_usbcx_gintmsk_s cn31xx;
+ struct cvmx_usbcx_gintmsk_s cn50xx;
+ struct cvmx_usbcx_gintmsk_s cn52xx;
+ struct cvmx_usbcx_gintmsk_s cn52xxp1;
+ struct cvmx_usbcx_gintmsk_s cn56xx;
+ struct cvmx_usbcx_gintmsk_s cn56xxp1;
+} cvmx_usbcx_gintmsk_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gintsts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t wkupint:1;
+ uint32_t sessreqint:1;
+ uint32_t disconnint:1;
+ uint32_t conidstschng:1;
+ uint32_t reserved_27_27:1;
+ uint32_t ptxfemp:1;
+ uint32_t hchint:1;
+ uint32_t prtint:1;
+ uint32_t reserved_23_23:1;
+ uint32_t fetsusp:1;
+ uint32_t incomplp:1;
+ uint32_t incompisoin:1;
+ uint32_t oepint:1;
+ uint32_t iepint:1;
+ uint32_t epmis:1;
+ uint32_t reserved_16_16:1;
+ uint32_t eopf:1;
+ uint32_t isooutdrop:1;
+ uint32_t enumdone:1;
+ uint32_t usbrst:1;
+ uint32_t usbsusp:1;
+ uint32_t erlysusp:1;
+ uint32_t i2cint:1;
+ uint32_t ulpickint:1;
+ uint32_t goutnakeff:1;
+ uint32_t ginnakeff:1;
+ uint32_t nptxfemp:1;
+ uint32_t rxflvl:1;
+ uint32_t sof:1;
+ uint32_t otgint:1;
+ uint32_t modemis:1;
+ uint32_t curmod:1;
+#else
+ uint32_t curmod:1;
+ uint32_t modemis:1;
+ uint32_t otgint:1;
+ uint32_t sof:1;
+ uint32_t rxflvl:1;
+ uint32_t nptxfemp:1;
+ uint32_t ginnakeff:1;
+ uint32_t goutnakeff:1;
+ uint32_t ulpickint:1;
+ uint32_t i2cint:1;
+ uint32_t erlysusp:1;
+ uint32_t usbsusp:1;
+ uint32_t usbrst:1;
+ uint32_t enumdone:1;
+ uint32_t isooutdrop:1;
+ uint32_t eopf:1;
+ uint32_t reserved_16_16:1;
+ uint32_t epmis:1;
+ uint32_t iepint:1;
+ uint32_t oepint:1;
+ uint32_t incompisoin:1;
+ uint32_t incomplp:1;
+ uint32_t fetsusp:1;
+ uint32_t reserved_23_23:1;
+ uint32_t prtint:1;
+ uint32_t hchint:1;
+ uint32_t ptxfemp:1;
+ uint32_t reserved_27_27:1;
+ uint32_t conidstschng:1;
+ uint32_t disconnint:1;
+ uint32_t sessreqint:1;
+ uint32_t wkupint:1;
+#endif
+ } s;
+ struct cvmx_usbcx_gintsts_s cn30xx;
+ struct cvmx_usbcx_gintsts_s cn31xx;
+ struct cvmx_usbcx_gintsts_s cn50xx;
+ struct cvmx_usbcx_gintsts_s cn52xx;
+ struct cvmx_usbcx_gintsts_s cn52xxp1;
+ struct cvmx_usbcx_gintsts_s cn56xx;
+ struct cvmx_usbcx_gintsts_s cn56xxp1;
+} cvmx_usbcx_gintsts_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gnptxfsiz_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t nptxfdep:16;
+ uint32_t nptxfstaddr:16;
+#else
+ uint32_t nptxfstaddr:16;
+ uint32_t nptxfdep:16;
+#endif
+ } s;
+ struct cvmx_usbcx_gnptxfsiz_s cn30xx;
+ struct cvmx_usbcx_gnptxfsiz_s cn31xx;
+ struct cvmx_usbcx_gnptxfsiz_s cn50xx;
+ struct cvmx_usbcx_gnptxfsiz_s cn52xx;
+ struct cvmx_usbcx_gnptxfsiz_s cn52xxp1;
+ struct cvmx_usbcx_gnptxfsiz_s cn56xx;
+ struct cvmx_usbcx_gnptxfsiz_s cn56xxp1;
+} cvmx_usbcx_gnptxfsiz_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gnptxsts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_31_31:1;
+ uint32_t nptxqtop:7;
+ uint32_t nptxqspcavail:8;
+ uint32_t nptxfspcavail:16;
+#else
+ uint32_t nptxfspcavail:16;
+ uint32_t nptxqspcavail:8;
+ uint32_t nptxqtop:7;
+ uint32_t reserved_31_31:1;
+#endif
+ } s;
+ struct cvmx_usbcx_gnptxsts_s cn30xx;
+ struct cvmx_usbcx_gnptxsts_s cn31xx;
+ struct cvmx_usbcx_gnptxsts_s cn50xx;
+ struct cvmx_usbcx_gnptxsts_s cn52xx;
+ struct cvmx_usbcx_gnptxsts_s cn52xxp1;
+ struct cvmx_usbcx_gnptxsts_s cn56xx;
+ struct cvmx_usbcx_gnptxsts_s cn56xxp1;
+} cvmx_usbcx_gnptxsts_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gotgctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t bsesvld:1;
+ uint32_t asesvld:1;
+ uint32_t dbnctime:1;
+ uint32_t conidsts:1;
+ uint32_t reserved_12_15:4;
+ uint32_t devhnpen:1;
+ uint32_t hstsethnpen:1;
+ uint32_t hnpreq:1;
+ uint32_t hstnegscs:1;
+ uint32_t reserved_2_7:6;
+ uint32_t sesreq:1;
+ uint32_t sesreqscs:1;
+#else
+ uint32_t sesreqscs:1;
+ uint32_t sesreq:1;
+ uint32_t reserved_2_7:6;
+ uint32_t hstnegscs:1;
+ uint32_t hnpreq:1;
+ uint32_t hstsethnpen:1;
+ uint32_t devhnpen:1;
+ uint32_t reserved_12_15:4;
+ uint32_t conidsts:1;
+ uint32_t dbnctime:1;
+ uint32_t asesvld:1;
+ uint32_t bsesvld:1;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_usbcx_gotgctl_s cn30xx;
+ struct cvmx_usbcx_gotgctl_s cn31xx;
+ struct cvmx_usbcx_gotgctl_s cn50xx;
+ struct cvmx_usbcx_gotgctl_s cn52xx;
+ struct cvmx_usbcx_gotgctl_s cn52xxp1;
+ struct cvmx_usbcx_gotgctl_s cn56xx;
+ struct cvmx_usbcx_gotgctl_s cn56xxp1;
+} cvmx_usbcx_gotgctl_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gotgint_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_20_31:12;
+ uint32_t dbncedone:1;
+ uint32_t adevtoutchg:1;
+ uint32_t hstnegdet:1;
+ uint32_t reserved_10_16:7;
+ uint32_t hstnegsucstschng:1;
+ uint32_t sesreqsucstschng:1;
+ uint32_t reserved_3_7:5;
+ uint32_t sesenddet:1;
+ uint32_t reserved_0_1:2;
+#else
+ uint32_t reserved_0_1:2;
+ uint32_t sesenddet:1;
+ uint32_t reserved_3_7:5;
+ uint32_t sesreqsucstschng:1;
+ uint32_t hstnegsucstschng:1;
+ uint32_t reserved_10_16:7;
+ uint32_t hstnegdet:1;
+ uint32_t adevtoutchg:1;
+ uint32_t dbncedone:1;
+ uint32_t reserved_20_31:12;
+#endif
+ } s;
+ struct cvmx_usbcx_gotgint_s cn30xx;
+ struct cvmx_usbcx_gotgint_s cn31xx;
+ struct cvmx_usbcx_gotgint_s cn50xx;
+ struct cvmx_usbcx_gotgint_s cn52xx;
+ struct cvmx_usbcx_gotgint_s cn52xxp1;
+ struct cvmx_usbcx_gotgint_s cn56xx;
+ struct cvmx_usbcx_gotgint_s cn56xxp1;
+} cvmx_usbcx_gotgint_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grstctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ahbidle:1;
+ uint32_t dmareq:1;
+ uint32_t reserved_11_29:19;
+ uint32_t txfnum:5;
+ uint32_t txfflsh:1;
+ uint32_t rxfflsh:1;
+ uint32_t intknqflsh:1;
+ uint32_t frmcntrrst:1;
+ uint32_t hsftrst:1;
+ uint32_t csftrst:1;
+#else
+ uint32_t csftrst:1;
+ uint32_t hsftrst:1;
+ uint32_t frmcntrrst:1;
+ uint32_t intknqflsh:1;
+ uint32_t rxfflsh:1;
+ uint32_t txfflsh:1;
+ uint32_t txfnum:5;
+ uint32_t reserved_11_29:19;
+ uint32_t dmareq:1;
+ uint32_t ahbidle:1;
+#endif
+ } s;
+ struct cvmx_usbcx_grstctl_s cn30xx;
+ struct cvmx_usbcx_grstctl_s cn31xx;
+ struct cvmx_usbcx_grstctl_s cn50xx;
+ struct cvmx_usbcx_grstctl_s cn52xx;
+ struct cvmx_usbcx_grstctl_s cn52xxp1;
+ struct cvmx_usbcx_grstctl_s cn56xx;
+ struct cvmx_usbcx_grstctl_s cn56xxp1;
+} cvmx_usbcx_grstctl_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grxfsiz_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t rxfdep:16;
+#else
+ uint32_t rxfdep:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_usbcx_grxfsiz_s cn30xx;
+ struct cvmx_usbcx_grxfsiz_s cn31xx;
+ struct cvmx_usbcx_grxfsiz_s cn50xx;
+ struct cvmx_usbcx_grxfsiz_s cn52xx;
+ struct cvmx_usbcx_grxfsiz_s cn52xxp1;
+ struct cvmx_usbcx_grxfsiz_s cn56xx;
+ struct cvmx_usbcx_grxfsiz_s cn56xxp1;
+} cvmx_usbcx_grxfsiz_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grxstspd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_25_31:7;
+ uint32_t fn:4;
+ uint32_t pktsts:4;
+ uint32_t dpid:2;
+ uint32_t bcnt:11;
+ uint32_t epnum:4;
+#else
+ uint32_t epnum:4;
+ uint32_t bcnt:11;
+ uint32_t dpid:2;
+ uint32_t pktsts:4;
+ uint32_t fn:4;
+ uint32_t reserved_25_31:7;
+#endif
+ } s;
+ struct cvmx_usbcx_grxstspd_s cn30xx;
+ struct cvmx_usbcx_grxstspd_s cn31xx;
+ struct cvmx_usbcx_grxstspd_s cn50xx;
+ struct cvmx_usbcx_grxstspd_s cn52xx;
+ struct cvmx_usbcx_grxstspd_s cn52xxp1;
+ struct cvmx_usbcx_grxstspd_s cn56xx;
+ struct cvmx_usbcx_grxstspd_s cn56xxp1;
+} cvmx_usbcx_grxstspd_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grxstsph_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t pktsts:4;
+ uint32_t dpid:2;
+ uint32_t bcnt:11;
+ uint32_t chnum:4;
+#else
+ uint32_t chnum:4;
+ uint32_t bcnt:11;
+ uint32_t dpid:2;
+ uint32_t pktsts:4;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_usbcx_grxstsph_s cn30xx;
+ struct cvmx_usbcx_grxstsph_s cn31xx;
+ struct cvmx_usbcx_grxstsph_s cn50xx;
+ struct cvmx_usbcx_grxstsph_s cn52xx;
+ struct cvmx_usbcx_grxstsph_s cn52xxp1;
+ struct cvmx_usbcx_grxstsph_s cn56xx;
+ struct cvmx_usbcx_grxstsph_s cn56xxp1;
+} cvmx_usbcx_grxstsph_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grxstsrd_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_25_31:7;
+ uint32_t fn:4;
+ uint32_t pktsts:4;
+ uint32_t dpid:2;
+ uint32_t bcnt:11;
+ uint32_t epnum:4;
+#else
+ uint32_t epnum:4;
+ uint32_t bcnt:11;
+ uint32_t dpid:2;
+ uint32_t pktsts:4;
+ uint32_t fn:4;
+ uint32_t reserved_25_31:7;
+#endif
+ } s;
+ struct cvmx_usbcx_grxstsrd_s cn30xx;
+ struct cvmx_usbcx_grxstsrd_s cn31xx;
+ struct cvmx_usbcx_grxstsrd_s cn50xx;
+ struct cvmx_usbcx_grxstsrd_s cn52xx;
+ struct cvmx_usbcx_grxstsrd_s cn52xxp1;
+ struct cvmx_usbcx_grxstsrd_s cn56xx;
+ struct cvmx_usbcx_grxstsrd_s cn56xxp1;
+} cvmx_usbcx_grxstsrd_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_grxstsrh_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_21_31:11;
+ uint32_t pktsts:4;
+ uint32_t dpid:2;
+ uint32_t bcnt:11;
+ uint32_t chnum:4;
+#else
+ uint32_t chnum:4;
+ uint32_t bcnt:11;
+ uint32_t dpid:2;
+ uint32_t pktsts:4;
+ uint32_t reserved_21_31:11;
+#endif
+ } s;
+ struct cvmx_usbcx_grxstsrh_s cn30xx;
+ struct cvmx_usbcx_grxstsrh_s cn31xx;
+ struct cvmx_usbcx_grxstsrh_s cn50xx;
+ struct cvmx_usbcx_grxstsrh_s cn52xx;
+ struct cvmx_usbcx_grxstsrh_s cn52xxp1;
+ struct cvmx_usbcx_grxstsrh_s cn56xx;
+ struct cvmx_usbcx_grxstsrh_s cn56xxp1;
+} cvmx_usbcx_grxstsrh_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gsnpsid_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t synopsysid:32;
+#else
+ uint32_t synopsysid:32;
+#endif
+ } s;
+ struct cvmx_usbcx_gsnpsid_s cn30xx;
+ struct cvmx_usbcx_gsnpsid_s cn31xx;
+ struct cvmx_usbcx_gsnpsid_s cn50xx;
+ struct cvmx_usbcx_gsnpsid_s cn52xx;
+ struct cvmx_usbcx_gsnpsid_s cn52xxp1;
+ struct cvmx_usbcx_gsnpsid_s cn56xx;
+ struct cvmx_usbcx_gsnpsid_s cn56xxp1;
+} cvmx_usbcx_gsnpsid_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_gusbcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_17_31:15;
+ uint32_t otgi2csel:1;
+ uint32_t phylpwrclksel:1;
+ uint32_t reserved_14_14:1;
+ uint32_t usbtrdtim:4;
+ uint32_t hnpcap:1;
+ uint32_t srpcap:1;
+ uint32_t ddrsel:1;
+ uint32_t physel:1;
+ uint32_t fsintf:1;
+ uint32_t ulpi_utmi_sel:1;
+ uint32_t phyif:1;
+ uint32_t toutcal:3;
+#else
+ uint32_t toutcal:3;
+ uint32_t phyif:1;
+ uint32_t ulpi_utmi_sel:1;
+ uint32_t fsintf:1;
+ uint32_t physel:1;
+ uint32_t ddrsel:1;
+ uint32_t srpcap:1;
+ uint32_t hnpcap:1;
+ uint32_t usbtrdtim:4;
+ uint32_t reserved_14_14:1;
+ uint32_t phylpwrclksel:1;
+ uint32_t otgi2csel:1;
+ uint32_t reserved_17_31:15;
+#endif
+ } s;
+ struct cvmx_usbcx_gusbcfg_s cn30xx;
+ struct cvmx_usbcx_gusbcfg_s cn31xx;
+ struct cvmx_usbcx_gusbcfg_s cn50xx;
+ struct cvmx_usbcx_gusbcfg_s cn52xx;
+ struct cvmx_usbcx_gusbcfg_s cn52xxp1;
+ struct cvmx_usbcx_gusbcfg_s cn56xx;
+ struct cvmx_usbcx_gusbcfg_s cn56xxp1;
+} cvmx_usbcx_gusbcfg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_haint_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t haint:16;
+#else
+ uint32_t haint:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_usbcx_haint_s cn30xx;
+ struct cvmx_usbcx_haint_s cn31xx;
+ struct cvmx_usbcx_haint_s cn50xx;
+ struct cvmx_usbcx_haint_s cn52xx;
+ struct cvmx_usbcx_haint_s cn52xxp1;
+ struct cvmx_usbcx_haint_s cn56xx;
+ struct cvmx_usbcx_haint_s cn56xxp1;
+} cvmx_usbcx_haint_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_haintmsk_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t haintmsk:16;
+#else
+ uint32_t haintmsk:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_usbcx_haintmsk_s cn30xx;
+ struct cvmx_usbcx_haintmsk_s cn31xx;
+ struct cvmx_usbcx_haintmsk_s cn50xx;
+ struct cvmx_usbcx_haintmsk_s cn52xx;
+ struct cvmx_usbcx_haintmsk_s cn52xxp1;
+ struct cvmx_usbcx_haintmsk_s cn56xx;
+ struct cvmx_usbcx_haintmsk_s cn56xxp1;
+} cvmx_usbcx_haintmsk_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hccharx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t chena:1;
+ uint32_t chdis:1;
+ uint32_t oddfrm:1;
+ uint32_t devaddr:7;
+ uint32_t ec:2;
+ uint32_t eptype:2;
+ uint32_t lspddev:1;
+ uint32_t reserved_16_16:1;
+ uint32_t epdir:1;
+ uint32_t epnum:4;
+ uint32_t mps:11;
+#else
+ uint32_t mps:11;
+ uint32_t epnum:4;
+ uint32_t epdir:1;
+ uint32_t reserved_16_16:1;
+ uint32_t lspddev:1;
+ uint32_t eptype:2;
+ uint32_t ec:2;
+ uint32_t devaddr:7;
+ uint32_t oddfrm:1;
+ uint32_t chdis:1;
+ uint32_t chena:1;
+#endif
+ } s;
+ struct cvmx_usbcx_hccharx_s cn30xx;
+ struct cvmx_usbcx_hccharx_s cn31xx;
+ struct cvmx_usbcx_hccharx_s cn50xx;
+ struct cvmx_usbcx_hccharx_s cn52xx;
+ struct cvmx_usbcx_hccharx_s cn52xxp1;
+ struct cvmx_usbcx_hccharx_s cn56xx;
+ struct cvmx_usbcx_hccharx_s cn56xxp1;
+} cvmx_usbcx_hccharx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hcfg_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_3_31:29;
+ uint32_t fslssupp:1;
+ uint32_t fslspclksel:2;
+#else
+ uint32_t fslspclksel:2;
+ uint32_t fslssupp:1;
+ uint32_t reserved_3_31:29;
+#endif
+ } s;
+ struct cvmx_usbcx_hcfg_s cn30xx;
+ struct cvmx_usbcx_hcfg_s cn31xx;
+ struct cvmx_usbcx_hcfg_s cn50xx;
+ struct cvmx_usbcx_hcfg_s cn52xx;
+ struct cvmx_usbcx_hcfg_s cn52xxp1;
+ struct cvmx_usbcx_hcfg_s cn56xx;
+ struct cvmx_usbcx_hcfg_s cn56xxp1;
+} cvmx_usbcx_hcfg_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hcintx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_11_31:21;
+ uint32_t datatglerr:1;
+ uint32_t frmovrun:1;
+ uint32_t bblerr:1;
+ uint32_t xacterr:1;
+ uint32_t nyet:1;
+ uint32_t ack:1;
+ uint32_t nak:1;
+ uint32_t stall:1;
+ uint32_t ahberr:1;
+ uint32_t chhltd:1;
+ uint32_t xfercompl:1;
+#else
+ uint32_t xfercompl:1;
+ uint32_t chhltd:1;
+ uint32_t ahberr:1;
+ uint32_t stall:1;
+ uint32_t nak:1;
+ uint32_t ack:1;
+ uint32_t nyet:1;
+ uint32_t xacterr:1;
+ uint32_t bblerr:1;
+ uint32_t frmovrun:1;
+ uint32_t datatglerr:1;
+ uint32_t reserved_11_31:21;
+#endif
+ } s;
+ struct cvmx_usbcx_hcintx_s cn30xx;
+ struct cvmx_usbcx_hcintx_s cn31xx;
+ struct cvmx_usbcx_hcintx_s cn50xx;
+ struct cvmx_usbcx_hcintx_s cn52xx;
+ struct cvmx_usbcx_hcintx_s cn52xxp1;
+ struct cvmx_usbcx_hcintx_s cn56xx;
+ struct cvmx_usbcx_hcintx_s cn56xxp1;
+} cvmx_usbcx_hcintx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hcintmskx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_11_31:21;
+ uint32_t datatglerrmsk:1;
+ uint32_t frmovrunmsk:1;
+ uint32_t bblerrmsk:1;
+ uint32_t xacterrmsk:1;
+ uint32_t nyetmsk:1;
+ uint32_t ackmsk:1;
+ uint32_t nakmsk:1;
+ uint32_t stallmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t chhltdmsk:1;
+ uint32_t xfercomplmsk:1;
+#else
+ uint32_t xfercomplmsk:1;
+ uint32_t chhltdmsk:1;
+ uint32_t ahberrmsk:1;
+ uint32_t stallmsk:1;
+ uint32_t nakmsk:1;
+ uint32_t ackmsk:1;
+ uint32_t nyetmsk:1;
+ uint32_t xacterrmsk:1;
+ uint32_t bblerrmsk:1;
+ uint32_t frmovrunmsk:1;
+ uint32_t datatglerrmsk:1;
+ uint32_t reserved_11_31:21;
+#endif
+ } s;
+ struct cvmx_usbcx_hcintmskx_s cn30xx;
+ struct cvmx_usbcx_hcintmskx_s cn31xx;
+ struct cvmx_usbcx_hcintmskx_s cn50xx;
+ struct cvmx_usbcx_hcintmskx_s cn52xx;
+ struct cvmx_usbcx_hcintmskx_s cn52xxp1;
+ struct cvmx_usbcx_hcintmskx_s cn56xx;
+ struct cvmx_usbcx_hcintmskx_s cn56xxp1;
+} cvmx_usbcx_hcintmskx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hcspltx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t spltena:1;
+ uint32_t reserved_17_30:14;
+ uint32_t compsplt:1;
+ uint32_t xactpos:2;
+ uint32_t hubaddr:7;
+ uint32_t prtaddr:7;
+#else
+ uint32_t prtaddr:7;
+ uint32_t hubaddr:7;
+ uint32_t xactpos:2;
+ uint32_t compsplt:1;
+ uint32_t reserved_17_30:14;
+ uint32_t spltena:1;
+#endif
+ } s;
+ struct cvmx_usbcx_hcspltx_s cn30xx;
+ struct cvmx_usbcx_hcspltx_s cn31xx;
+ struct cvmx_usbcx_hcspltx_s cn50xx;
+ struct cvmx_usbcx_hcspltx_s cn52xx;
+ struct cvmx_usbcx_hcspltx_s cn52xxp1;
+ struct cvmx_usbcx_hcspltx_s cn56xx;
+ struct cvmx_usbcx_hcspltx_s cn56xxp1;
+} cvmx_usbcx_hcspltx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hctsizx_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t dopng:1;
+ uint32_t pid:2;
+ uint32_t pktcnt:10;
+ uint32_t xfersize:19;
+#else
+ uint32_t xfersize:19;
+ uint32_t pktcnt:10;
+ uint32_t pid:2;
+ uint32_t dopng:1;
+#endif
+ } s;
+ struct cvmx_usbcx_hctsizx_s cn30xx;
+ struct cvmx_usbcx_hctsizx_s cn31xx;
+ struct cvmx_usbcx_hctsizx_s cn50xx;
+ struct cvmx_usbcx_hctsizx_s cn52xx;
+ struct cvmx_usbcx_hctsizx_s cn52xxp1;
+ struct cvmx_usbcx_hctsizx_s cn56xx;
+ struct cvmx_usbcx_hctsizx_s cn56xxp1;
+} cvmx_usbcx_hctsizx_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hfir_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_16_31:16;
+ uint32_t frint:16;
+#else
+ uint32_t frint:16;
+ uint32_t reserved_16_31:16;
+#endif
+ } s;
+ struct cvmx_usbcx_hfir_s cn30xx;
+ struct cvmx_usbcx_hfir_s cn31xx;
+ struct cvmx_usbcx_hfir_s cn50xx;
+ struct cvmx_usbcx_hfir_s cn52xx;
+ struct cvmx_usbcx_hfir_s cn52xxp1;
+ struct cvmx_usbcx_hfir_s cn56xx;
+ struct cvmx_usbcx_hfir_s cn56xxp1;
+} cvmx_usbcx_hfir_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hfnum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t frrem:16;
+ uint32_t frnum:16;
+#else
+ uint32_t frnum:16;
+ uint32_t frrem:16;
+#endif
+ } s;
+ struct cvmx_usbcx_hfnum_s cn30xx;
+ struct cvmx_usbcx_hfnum_s cn31xx;
+ struct cvmx_usbcx_hfnum_s cn50xx;
+ struct cvmx_usbcx_hfnum_s cn52xx;
+ struct cvmx_usbcx_hfnum_s cn52xxp1;
+ struct cvmx_usbcx_hfnum_s cn56xx;
+ struct cvmx_usbcx_hfnum_s cn56xxp1;
+} cvmx_usbcx_hfnum_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hprt_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_19_31:13;
+ uint32_t prtspd:2;
+ uint32_t prttstctl:4;
+ uint32_t prtpwr:1;
+ uint32_t prtlnsts:2;
+ uint32_t reserved_9_9:1;
+ uint32_t prtrst:1;
+ uint32_t prtsusp:1;
+ uint32_t prtres:1;
+ uint32_t prtovrcurrchng:1;
+ uint32_t prtovrcurract:1;
+ uint32_t prtenchng:1;
+ uint32_t prtena:1;
+ uint32_t prtconndet:1;
+ uint32_t prtconnsts:1;
+#else
+ uint32_t prtconnsts:1;
+ uint32_t prtconndet:1;
+ uint32_t prtena:1;
+ uint32_t prtenchng:1;
+ uint32_t prtovrcurract:1;
+ uint32_t prtovrcurrchng:1;
+ uint32_t prtres:1;
+ uint32_t prtsusp:1;
+ uint32_t prtrst:1;
+ uint32_t reserved_9_9:1;
+ uint32_t prtlnsts:2;
+ uint32_t prtpwr:1;
+ uint32_t prttstctl:4;
+ uint32_t prtspd:2;
+ uint32_t reserved_19_31:13;
+#endif
+ } s;
+ struct cvmx_usbcx_hprt_s cn30xx;
+ struct cvmx_usbcx_hprt_s cn31xx;
+ struct cvmx_usbcx_hprt_s cn50xx;
+ struct cvmx_usbcx_hprt_s cn52xx;
+ struct cvmx_usbcx_hprt_s cn52xxp1;
+ struct cvmx_usbcx_hprt_s cn56xx;
+ struct cvmx_usbcx_hprt_s cn56xxp1;
+} cvmx_usbcx_hprt_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hptxfsiz_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ptxfsize:16;
+ uint32_t ptxfstaddr:16;
+#else
+ uint32_t ptxfstaddr:16;
+ uint32_t ptxfsize:16;
+#endif
+ } s;
+ struct cvmx_usbcx_hptxfsiz_s cn30xx;
+ struct cvmx_usbcx_hptxfsiz_s cn31xx;
+ struct cvmx_usbcx_hptxfsiz_s cn50xx;
+ struct cvmx_usbcx_hptxfsiz_s cn52xx;
+ struct cvmx_usbcx_hptxfsiz_s cn52xxp1;
+ struct cvmx_usbcx_hptxfsiz_s cn56xx;
+ struct cvmx_usbcx_hptxfsiz_s cn56xxp1;
+} cvmx_usbcx_hptxfsiz_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_hptxsts_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t ptxqtop:8;
+ uint32_t ptxqspcavail:8;
+ uint32_t ptxfspcavail:16;
+#else
+ uint32_t ptxfspcavail:16;
+ uint32_t ptxqspcavail:8;
+ uint32_t ptxqtop:8;
+#endif
+ } s;
+ struct cvmx_usbcx_hptxsts_s cn30xx;
+ struct cvmx_usbcx_hptxsts_s cn31xx;
+ struct cvmx_usbcx_hptxsts_s cn50xx;
+ struct cvmx_usbcx_hptxsts_s cn52xx;
+ struct cvmx_usbcx_hptxsts_s cn52xxp1;
+ struct cvmx_usbcx_hptxsts_s cn56xx;
+ struct cvmx_usbcx_hptxsts_s cn56xxp1;
+} cvmx_usbcx_hptxsts_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_nptxdfifox_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t data:32;
+#else
+ uint32_t data:32;
+#endif
+ } s;
+ struct cvmx_usbcx_nptxdfifox_s cn30xx;
+ struct cvmx_usbcx_nptxdfifox_s cn31xx;
+ struct cvmx_usbcx_nptxdfifox_s cn50xx;
+ struct cvmx_usbcx_nptxdfifox_s cn52xx;
+ struct cvmx_usbcx_nptxdfifox_s cn52xxp1;
+ struct cvmx_usbcx_nptxdfifox_s cn56xx;
+ struct cvmx_usbcx_nptxdfifox_s cn56xxp1;
+} cvmx_usbcx_nptxdfifox_t;
+
+typedef union {
+ uint32_t u32;
+ struct cvmx_usbcx_pcgcctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint32_t reserved_5_31:27;
+ uint32_t physuspended:1;
+ uint32_t rstpdwnmodule:1;
+ uint32_t pwrclmp:1;
+ uint32_t gatehclk:1;
+ uint32_t stoppclk:1;
+#else
+ uint32_t stoppclk:1;
+ uint32_t gatehclk:1;
+ uint32_t pwrclmp:1;
+ uint32_t rstpdwnmodule:1;
+ uint32_t physuspended:1;
+ uint32_t reserved_5_31:27;
+#endif
+ } s;
+ struct cvmx_usbcx_pcgcctl_s cn30xx;
+ struct cvmx_usbcx_pcgcctl_s cn31xx;
+ struct cvmx_usbcx_pcgcctl_s cn50xx;
+ struct cvmx_usbcx_pcgcctl_s cn52xx;
+ struct cvmx_usbcx_pcgcctl_s cn52xxp1;
+ struct cvmx_usbcx_pcgcctl_s cn56xx;
+ struct cvmx_usbcx_pcgcctl_s cn56xxp1;
+} cvmx_usbcx_pcgcctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_bist_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_7_63:57;
+ uint64_t u2nc_bis:1;
+ uint64_t u2nf_bis:1;
+ uint64_t e2hc_bis:1;
+ uint64_t n2uf_bis:1;
+ uint64_t usbc_bis:1;
+ uint64_t nif_bis:1;
+ uint64_t nof_bis:1;
+#else
+ uint64_t nof_bis:1;
+ uint64_t nif_bis:1;
+ uint64_t usbc_bis:1;
+ uint64_t n2uf_bis:1;
+ uint64_t e2hc_bis:1;
+ uint64_t u2nf_bis:1;
+ uint64_t u2nc_bis:1;
+ uint64_t reserved_7_63:57;
+#endif
+ } s;
+ struct cvmx_usbnx_bist_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_3_63:61;
+ uint64_t usbc_bis:1;
+ uint64_t nif_bis:1;
+ uint64_t nof_bis:1;
+#else
+ uint64_t nof_bis:1;
+ uint64_t nif_bis:1;
+ uint64_t usbc_bis:1;
+ uint64_t reserved_3_63:61;
+#endif
+ } cn30xx;
+ struct cvmx_usbnx_bist_status_cn30xx cn31xx;
+ struct cvmx_usbnx_bist_status_s cn50xx;
+ struct cvmx_usbnx_bist_status_s cn52xx;
+ struct cvmx_usbnx_bist_status_s cn52xxp1;
+ struct cvmx_usbnx_bist_status_s cn56xx;
+ struct cvmx_usbnx_bist_status_s cn56xxp1;
+} cvmx_usbnx_bist_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_clk_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t divide2:2;
+ uint64_t hclk_rst:1;
+ uint64_t p_x_on:1;
+ uint64_t reserved_14_15:2;
+ uint64_t p_com_on:1;
+ uint64_t p_c_sel:2;
+ uint64_t cdiv_byp:1;
+ uint64_t sd_mode:2;
+ uint64_t s_bist:1;
+ uint64_t por:1;
+ uint64_t enable:1;
+ uint64_t prst:1;
+ uint64_t hrst:1;
+ uint64_t divide:3;
+#else
+ uint64_t divide:3;
+ uint64_t hrst:1;
+ uint64_t prst:1;
+ uint64_t enable:1;
+ uint64_t por:1;
+ uint64_t s_bist:1;
+ uint64_t sd_mode:2;
+ uint64_t cdiv_byp:1;
+ uint64_t p_c_sel:2;
+ uint64_t p_com_on:1;
+ uint64_t reserved_14_15:2;
+ uint64_t p_x_on:1;
+ uint64_t hclk_rst:1;
+ uint64_t divide2:2;
+ uint64_t reserved_20_63:44;
+#endif
+ } s;
+ struct cvmx_usbnx_clk_ctl_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_18_63:46;
+ uint64_t hclk_rst:1;
+ uint64_t p_x_on:1;
+ uint64_t p_rclk:1;
+ uint64_t p_xenbn:1;
+ uint64_t p_com_on:1;
+ uint64_t p_c_sel:2;
+ uint64_t cdiv_byp:1;
+ uint64_t sd_mode:2;
+ uint64_t s_bist:1;
+ uint64_t por:1;
+ uint64_t enable:1;
+ uint64_t prst:1;
+ uint64_t hrst:1;
+ uint64_t divide:3;
+#else
+ uint64_t divide:3;
+ uint64_t hrst:1;
+ uint64_t prst:1;
+ uint64_t enable:1;
+ uint64_t por:1;
+ uint64_t s_bist:1;
+ uint64_t sd_mode:2;
+ uint64_t cdiv_byp:1;
+ uint64_t p_c_sel:2;
+ uint64_t p_com_on:1;
+ uint64_t p_xenbn:1;
+ uint64_t p_rclk:1;
+ uint64_t p_x_on:1;
+ uint64_t hclk_rst:1;
+ uint64_t reserved_18_63:46;
+#endif
+ } cn30xx;
+ struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
+ struct cvmx_usbnx_clk_ctl_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_20_63:44;
+ uint64_t divide2:2;
+ uint64_t hclk_rst:1;
+ uint64_t reserved_16_16:1;
+ uint64_t p_rtype:2;
+ uint64_t p_com_on:1;
+ uint64_t p_c_sel:2;
+ uint64_t cdiv_byp:1;
+ uint64_t sd_mode:2;
+ uint64_t s_bist:1;
+ uint64_t por:1;
+ uint64_t enable:1;
+ uint64_t prst:1;
+ uint64_t hrst:1;
+ uint64_t divide:3;
+#else
+ uint64_t divide:3;
+ uint64_t hrst:1;
+ uint64_t prst:1;
+ uint64_t enable:1;
+ uint64_t por:1;
+ uint64_t s_bist:1;
+ uint64_t sd_mode:2;
+ uint64_t cdiv_byp:1;
+ uint64_t p_c_sel:2;
+ uint64_t p_com_on:1;
+ uint64_t p_rtype:2;
+ uint64_t reserved_16_16:1;
+ uint64_t hclk_rst:1;
+ uint64_t divide2:2;
+ uint64_t reserved_20_63:44;
+#endif
+ } cn50xx;
+ struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
+ struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1;
+ struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
+ struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1;
+} cvmx_usbnx_clk_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_6_63:58;
+ uint64_t dma_0pag:1;
+ uint64_t dma_stt:1;
+ uint64_t dma_test:1;
+ uint64_t inv_a2:1;
+ uint64_t l2c_emod:2;
+#else
+ uint64_t l2c_emod:2;
+ uint64_t inv_a2:1;
+ uint64_t dma_test:1;
+ uint64_t dma_stt:1;
+ uint64_t dma_0pag:1;
+ uint64_t reserved_6_63:58;
+#endif
+ } s;
+ struct cvmx_usbnx_ctl_status_s cn30xx;
+ struct cvmx_usbnx_ctl_status_s cn31xx;
+ struct cvmx_usbnx_ctl_status_s cn50xx;
+ struct cvmx_usbnx_ctl_status_s cn52xx;
+ struct cvmx_usbnx_ctl_status_s cn52xxp1;
+ struct cvmx_usbnx_ctl_status_s cn56xx;
+ struct cvmx_usbnx_ctl_status_s cn56xxp1;
+} cvmx_usbnx_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_inb_chn7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn30xx;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn31xx;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn50xx;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn52xx;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn56xx;
+ struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn1_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn1_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn2_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn2_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn3_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn3_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn4_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn4_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn5_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn5_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn6_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn6_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma0_outb_chn7_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+#else
+ uint64_t addr:36;
+ uint64_t reserved_36_63:28;
+#endif
+ } s;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn30xx;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn31xx;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn50xx;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn52xx;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn56xx;
+ struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn7_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_dma_test_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_40_63:24;
+ uint64_t done:1;
+ uint64_t req:1;
+ uint64_t f_addr:18;
+ uint64_t count:11;
+ uint64_t channel:5;
+ uint64_t burst:4;
+#else
+ uint64_t burst:4;
+ uint64_t channel:5;
+ uint64_t count:11;
+ uint64_t f_addr:18;
+ uint64_t req:1;
+ uint64_t done:1;
+ uint64_t reserved_40_63:24;
+#endif
+ } s;
+ struct cvmx_usbnx_dma_test_s cn30xx;
+ struct cvmx_usbnx_dma_test_s cn31xx;
+ struct cvmx_usbnx_dma_test_s cn50xx;
+ struct cvmx_usbnx_dma_test_s cn52xx;
+ struct cvmx_usbnx_dma_test_s cn52xxp1;
+ struct cvmx_usbnx_dma_test_s cn56xx;
+ struct cvmx_usbnx_dma_test_s cn56xxp1;
+} cvmx_usbnx_dma_test_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_int_enb_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t nd4o_dpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t u2n_c_pe:1;
+ uint64_t u2n_c_pf:1;
+ uint64_t u2n_d_pf:1;
+ uint64_t u2n_d_pe:1;
+ uint64_t n2u_pe:1;
+ uint64_t n2u_pf:1;
+ uint64_t uod_pf:1;
+ uint64_t uod_pe:1;
+ uint64_t rq_q3_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t l2_fi_f:1;
+ uint64_t l2_fi_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t dcred_f:1;
+ uint64_t dcred_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t pr_po_e:1;
+#else
+ uint64_t pr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t dcred_e:1;
+ uint64_t dcred_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2_fi_e:1;
+ uint64_t l2_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q3_e:1;
+ uint64_t uod_pe:1;
+ uint64_t uod_pf:1;
+ uint64_t n2u_pf:1;
+ uint64_t n2u_pe:1;
+ uint64_t u2n_d_pe:1;
+ uint64_t u2n_d_pf:1;
+ uint64_t u2n_c_pf:1;
+ uint64_t u2n_c_pe:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_dpf:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_usbnx_int_enb_s cn30xx;
+ struct cvmx_usbnx_int_enb_s cn31xx;
+ struct cvmx_usbnx_int_enb_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t nd4o_dpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t reserved_26_31:6;
+ uint64_t uod_pf:1;
+ uint64_t uod_pe:1;
+ uint64_t rq_q3_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t l2_fi_f:1;
+ uint64_t l2_fi_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t dcred_f:1;
+ uint64_t dcred_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t pr_po_e:1;
+#else
+ uint64_t pr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t dcred_e:1;
+ uint64_t dcred_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2_fi_e:1;
+ uint64_t l2_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q3_e:1;
+ uint64_t uod_pe:1;
+ uint64_t uod_pf:1;
+ uint64_t reserved_26_31:6;
+ uint64_t ltl_f_pe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_dpf:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } cn50xx;
+ struct cvmx_usbnx_int_enb_cn50xx cn52xx;
+ struct cvmx_usbnx_int_enb_cn50xx cn52xxp1;
+ struct cvmx_usbnx_int_enb_cn50xx cn56xx;
+ struct cvmx_usbnx_int_enb_cn50xx cn56xxp1;
+} cvmx_usbnx_int_enb_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_int_sum_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t nd4o_dpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t u2n_c_pe:1;
+ uint64_t u2n_c_pf:1;
+ uint64_t u2n_d_pf:1;
+ uint64_t u2n_d_pe:1;
+ uint64_t n2u_pe:1;
+ uint64_t n2u_pf:1;
+ uint64_t uod_pf:1;
+ uint64_t uod_pe:1;
+ uint64_t rq_q3_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t lt_fi_f:1;
+ uint64_t lt_fi_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t dcred_f:1;
+ uint64_t dcred_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t pr_po_e:1;
+#else
+ uint64_t pr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t dcred_e:1;
+ uint64_t dcred_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t lt_fi_e:1;
+ uint64_t lt_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q3_e:1;
+ uint64_t uod_pe:1;
+ uint64_t uod_pf:1;
+ uint64_t n2u_pf:1;
+ uint64_t n2u_pe:1;
+ uint64_t u2n_d_pe:1;
+ uint64_t u2n_d_pf:1;
+ uint64_t u2n_c_pf:1;
+ uint64_t u2n_c_pe:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_dpf:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } s;
+ struct cvmx_usbnx_int_sum_s cn30xx;
+ struct cvmx_usbnx_int_sum_s cn31xx;
+ struct cvmx_usbnx_int_sum_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t nd4o_dpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t ltl_f_pe:1;
+ uint64_t reserved_26_31:6;
+ uint64_t uod_pf:1;
+ uint64_t uod_pe:1;
+ uint64_t rq_q3_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t lt_fi_f:1;
+ uint64_t lt_fi_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t dcred_f:1;
+ uint64_t dcred_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t pr_po_e:1;
+#else
+ uint64_t pr_po_e:1;
+ uint64_t pr_pu_f:1;
+ uint64_t nr_po_e:1;
+ uint64_t nr_pu_f:1;
+ uint64_t lr_po_e:1;
+ uint64_t lr_pu_f:1;
+ uint64_t pt_po_e:1;
+ uint64_t pt_pu_f:1;
+ uint64_t nt_po_e:1;
+ uint64_t nt_pu_f:1;
+ uint64_t lt_po_e:1;
+ uint64_t lt_pu_f:1;
+ uint64_t dcred_e:1;
+ uint64_t dcred_f:1;
+ uint64_t l2c_s_e:1;
+ uint64_t l2c_a_f:1;
+ uint64_t lt_fi_e:1;
+ uint64_t lt_fi_f:1;
+ uint64_t rg_fi_e:1;
+ uint64_t rg_fi_f:1;
+ uint64_t rq_q2_f:1;
+ uint64_t rq_q2_e:1;
+ uint64_t rq_q3_f:1;
+ uint64_t rq_q3_e:1;
+ uint64_t uod_pe:1;
+ uint64_t uod_pf:1;
+ uint64_t reserved_26_31:6;
+ uint64_t ltl_f_pe:1;
+ uint64_t ltl_f_pf:1;
+ uint64_t nd4o_rpe:1;
+ uint64_t nd4o_rpf:1;
+ uint64_t nd4o_dpe:1;
+ uint64_t nd4o_dpf:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } cn50xx;
+ struct cvmx_usbnx_int_sum_cn50xx cn52xx;
+ struct cvmx_usbnx_int_sum_cn50xx cn52xxp1;
+ struct cvmx_usbnx_int_sum_cn50xx cn56xx;
+ struct cvmx_usbnx_int_sum_cn50xx cn56xxp1;
+} cvmx_usbnx_int_sum_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_usbnx_usbp_ctl_status_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t txrisetune:1;
+ uint64_t txvreftune:4;
+ uint64_t txfslstune:4;
+ uint64_t txhsxvtune:2;
+ uint64_t sqrxtune:3;
+ uint64_t compdistune:3;
+ uint64_t otgtune:3;
+ uint64_t otgdisable:1;
+ uint64_t portreset:1;
+ uint64_t drvvbus:1;
+ uint64_t lsbist:1;
+ uint64_t fsbist:1;
+ uint64_t hsbist:1;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t tdata_out:4;
+ uint64_t siddq:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t dma_bmode:1;
+ uint64_t usbc_end:1;
+ uint64_t usbp_bist:1;
+ uint64_t tclk:1;
+ uint64_t dp_pulld:1;
+ uint64_t dm_pulld:1;
+ uint64_t hst_mode:1;
+ uint64_t tuning:4;
+ uint64_t tx_bs_enh:1;
+ uint64_t tx_bs_en:1;
+ uint64_t loop_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t bist_enb:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ uint64_t ate_reset:1;
+#else
+ uint64_t ate_reset:1;
+ uint64_t tdata_in:8;
+ uint64_t taddr_in:4;
+ uint64_t tdata_sel:1;
+ uint64_t bist_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t loop_enb:1;
+ uint64_t tx_bs_en:1;
+ uint64_t tx_bs_enh:1;
+ uint64_t tuning:4;
+ uint64_t hst_mode:1;
+ uint64_t dm_pulld:1;
+ uint64_t dp_pulld:1;
+ uint64_t tclk:1;
+ uint64_t usbp_bist:1;
+ uint64_t usbc_end:1;
+ uint64_t dma_bmode:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t siddq:1;
+ uint64_t tdata_out:4;
+ uint64_t bist_err:1;
+ uint64_t bist_done:1;
+ uint64_t hsbist:1;
+ uint64_t fsbist:1;
+ uint64_t lsbist:1;
+ uint64_t drvvbus:1;
+ uint64_t portreset:1;
+ uint64_t otgdisable:1;
+ uint64_t otgtune:3;
+ uint64_t compdistune:3;
+ uint64_t sqrxtune:3;
+ uint64_t txhsxvtune:2;
+ uint64_t txfslstune:4;
+ uint64_t txvreftune:4;
+ uint64_t txrisetune:1;
+#endif
+ } s;
+ struct cvmx_usbnx_usbp_ctl_status_cn30xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_38_63:26;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t tdata_out:4;
+ uint64_t reserved_30_31:2;
+ uint64_t dma_bmode:1;
+ uint64_t usbc_end:1;
+ uint64_t usbp_bist:1;
+ uint64_t tclk:1;
+ uint64_t dp_pulld:1;
+ uint64_t dm_pulld:1;
+ uint64_t hst_mode:1;
+ uint64_t tuning:4;
+ uint64_t tx_bs_enh:1;
+ uint64_t tx_bs_en:1;
+ uint64_t loop_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t bist_enb:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ uint64_t ate_reset:1;
+#else
+ uint64_t ate_reset:1;
+ uint64_t tdata_in:8;
+ uint64_t taddr_in:4;
+ uint64_t tdata_sel:1;
+ uint64_t bist_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t loop_enb:1;
+ uint64_t tx_bs_en:1;
+ uint64_t tx_bs_enh:1;
+ uint64_t tuning:4;
+ uint64_t hst_mode:1;
+ uint64_t dm_pulld:1;
+ uint64_t dp_pulld:1;
+ uint64_t tclk:1;
+ uint64_t usbp_bist:1;
+ uint64_t usbc_end:1;
+ uint64_t dma_bmode:1;
+ uint64_t reserved_30_31:2;
+ uint64_t tdata_out:4;
+ uint64_t bist_err:1;
+ uint64_t bist_done:1;
+ uint64_t reserved_38_63:26;
+#endif
+ } cn30xx;
+ struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
+ struct cvmx_usbnx_usbp_ctl_status_cn50xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t txrisetune:1;
+ uint64_t txvreftune:4;
+ uint64_t txfslstune:4;
+ uint64_t txhsxvtune:2;
+ uint64_t sqrxtune:3;
+ uint64_t compdistune:3;
+ uint64_t otgtune:3;
+ uint64_t otgdisable:1;
+ uint64_t portreset:1;
+ uint64_t drvvbus:1;
+ uint64_t lsbist:1;
+ uint64_t fsbist:1;
+ uint64_t hsbist:1;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t tdata_out:4;
+ uint64_t reserved_31_31:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t dma_bmode:1;
+ uint64_t usbc_end:1;
+ uint64_t usbp_bist:1;
+ uint64_t tclk:1;
+ uint64_t dp_pulld:1;
+ uint64_t dm_pulld:1;
+ uint64_t hst_mode:1;
+ uint64_t reserved_19_22:4;
+ uint64_t tx_bs_enh:1;
+ uint64_t tx_bs_en:1;
+ uint64_t loop_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t bist_enb:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ uint64_t ate_reset:1;
+#else
+ uint64_t ate_reset:1;
+ uint64_t tdata_in:8;
+ uint64_t taddr_in:4;
+ uint64_t tdata_sel:1;
+ uint64_t bist_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t loop_enb:1;
+ uint64_t tx_bs_en:1;
+ uint64_t tx_bs_enh:1;
+ uint64_t reserved_19_22:4;
+ uint64_t hst_mode:1;
+ uint64_t dm_pulld:1;
+ uint64_t dp_pulld:1;
+ uint64_t tclk:1;
+ uint64_t usbp_bist:1;
+ uint64_t usbc_end:1;
+ uint64_t dma_bmode:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t reserved_31_31:1;
+ uint64_t tdata_out:4;
+ uint64_t bist_err:1;
+ uint64_t bist_done:1;
+ uint64_t hsbist:1;
+ uint64_t fsbist:1;
+ uint64_t lsbist:1;
+ uint64_t drvvbus:1;
+ uint64_t portreset:1;
+ uint64_t otgdisable:1;
+ uint64_t otgtune:3;
+ uint64_t compdistune:3;
+ uint64_t sqrxtune:3;
+ uint64_t txhsxvtune:2;
+ uint64_t txfslstune:4;
+ uint64_t txvreftune:4;
+ uint64_t txrisetune:1;
+#endif
+ } cn50xx;
+ struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xx;
+ struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
+ struct cvmx_usbnx_usbp_ctl_status_cn56xx {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t txrisetune:1;
+ uint64_t txvreftune:4;
+ uint64_t txfslstune:4;
+ uint64_t txhsxvtune:2;
+ uint64_t sqrxtune:3;
+ uint64_t compdistune:3;
+ uint64_t otgtune:3;
+ uint64_t otgdisable:1;
+ uint64_t portreset:1;
+ uint64_t drvvbus:1;
+ uint64_t lsbist:1;
+ uint64_t fsbist:1;
+ uint64_t hsbist:1;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t tdata_out:4;
+ uint64_t siddq:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t dma_bmode:1;
+ uint64_t usbc_end:1;
+ uint64_t usbp_bist:1;
+ uint64_t tclk:1;
+ uint64_t dp_pulld:1;
+ uint64_t dm_pulld:1;
+ uint64_t hst_mode:1;
+ uint64_t reserved_19_22:4;
+ uint64_t tx_bs_enh:1;
+ uint64_t tx_bs_en:1;
+ uint64_t loop_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t bist_enb:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ uint64_t ate_reset:1;
+#else
+ uint64_t ate_reset:1;
+ uint64_t tdata_in:8;
+ uint64_t taddr_in:4;
+ uint64_t tdata_sel:1;
+ uint64_t bist_enb:1;
+ uint64_t vtest_enb:1;
+ uint64_t loop_enb:1;
+ uint64_t tx_bs_en:1;
+ uint64_t tx_bs_enh:1;
+ uint64_t reserved_19_22:4;
+ uint64_t hst_mode:1;
+ uint64_t dm_pulld:1;
+ uint64_t dp_pulld:1;
+ uint64_t tclk:1;
+ uint64_t usbp_bist:1;
+ uint64_t usbc_end:1;
+ uint64_t dma_bmode:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t siddq:1;
+ uint64_t tdata_out:4;
+ uint64_t bist_err:1;
+ uint64_t bist_done:1;
+ uint64_t hsbist:1;
+ uint64_t fsbist:1;
+ uint64_t lsbist:1;
+ uint64_t drvvbus:1;
+ uint64_t portreset:1;
+ uint64_t otgdisable:1;
+ uint64_t otgtune:3;
+ uint64_t compdistune:3;
+ uint64_t sqrxtune:3;
+ uint64_t txhsxvtune:2;
+ uint64_t txfslstune:4;
+ uint64_t txvreftune:4;
+ uint64_t txrisetune:1;
+#endif
+ } cn56xx;
+ struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
+} cvmx_usbnx_usbp_ctl_status_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_cmd_bist_result_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_31_63:33;
+ uint64_t zip_core:27;
+ uint64_t zip_ctl:4;
+#else
+ uint64_t zip_ctl:4;
+ uint64_t zip_core:27;
+ uint64_t reserved_31_63:33;
+#endif
+ } s;
+ struct cvmx_zip_cmd_bist_result_s cn31xx;
+ struct cvmx_zip_cmd_bist_result_s cn38xx;
+ struct cvmx_zip_cmd_bist_result_s cn38xxp2;
+ struct cvmx_zip_cmd_bist_result_s cn56xx;
+ struct cvmx_zip_cmd_bist_result_s cn56xxp1;
+ struct cvmx_zip_cmd_bist_result_s cn58xx;
+ struct cvmx_zip_cmd_bist_result_s cn58xxp1;
+} cvmx_zip_cmd_bist_result_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_cmd_buf_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_58_63:6;
+ uint64_t dwb:9;
+ uint64_t pool:3;
+ uint64_t size:13;
+ uint64_t ptr:33;
+#else
+ uint64_t ptr:33;
+ uint64_t size:13;
+ uint64_t pool:3;
+ uint64_t dwb:9;
+ uint64_t reserved_58_63:6;
+#endif
+ } s;
+ struct cvmx_zip_cmd_buf_s cn31xx;
+ struct cvmx_zip_cmd_buf_s cn38xx;
+ struct cvmx_zip_cmd_buf_s cn38xxp2;
+ struct cvmx_zip_cmd_buf_s cn56xx;
+ struct cvmx_zip_cmd_buf_s cn56xxp1;
+ struct cvmx_zip_cmd_buf_s cn58xx;
+ struct cvmx_zip_cmd_buf_s cn58xxp1;
+} cvmx_zip_cmd_buf_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_cmd_ctl_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_2_63:62;
+ uint64_t forceclk:1;
+ uint64_t reset:1;
+#else
+ uint64_t reset:1;
+ uint64_t forceclk:1;
+ uint64_t reserved_2_63:62;
+#endif
+ } s;
+ struct cvmx_zip_cmd_ctl_s cn31xx;
+ struct cvmx_zip_cmd_ctl_s cn38xx;
+ struct cvmx_zip_cmd_ctl_s cn38xxp2;
+ struct cvmx_zip_cmd_ctl_s cn56xx;
+ struct cvmx_zip_cmd_ctl_s cn56xxp1;
+ struct cvmx_zip_cmd_ctl_s cn58xx;
+ struct cvmx_zip_cmd_ctl_s cn58xxp1;
+} cvmx_zip_cmd_ctl_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_constants_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_48_63:16;
+ uint64_t depth:16;
+ uint64_t onfsize:12;
+ uint64_t ctxsize:12;
+ uint64_t reserved_1_7:7;
+ uint64_t disabled:1;
+#else
+ uint64_t disabled:1;
+ uint64_t reserved_1_7:7;
+ uint64_t ctxsize:12;
+ uint64_t onfsize:12;
+ uint64_t depth:16;
+ uint64_t reserved_48_63:16;
+#endif
+ } s;
+ struct cvmx_zip_constants_s cn31xx;
+ struct cvmx_zip_constants_s cn38xx;
+ struct cvmx_zip_constants_s cn38xxp2;
+ struct cvmx_zip_constants_s cn56xx;
+ struct cvmx_zip_constants_s cn56xxp1;
+ struct cvmx_zip_constants_s cn58xx;
+ struct cvmx_zip_constants_s cn58xxp1;
+} cvmx_zip_constants_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_debug0_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_14_63:50;
+ uint64_t asserts:14;
+#else
+ uint64_t asserts:14;
+ uint64_t reserved_14_63:50;
+#endif
+ } s;
+ struct cvmx_zip_debug0_s cn31xx;
+ struct cvmx_zip_debug0_s cn38xx;
+ struct cvmx_zip_debug0_s cn38xxp2;
+ struct cvmx_zip_debug0_s cn56xx;
+ struct cvmx_zip_debug0_s cn56xxp1;
+ struct cvmx_zip_debug0_s cn58xx;
+ struct cvmx_zip_debug0_s cn58xxp1;
+} cvmx_zip_debug0_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_error_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t doorbell:1;
+#else
+ uint64_t doorbell:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_zip_error_s cn31xx;
+ struct cvmx_zip_error_s cn38xx;
+ struct cvmx_zip_error_s cn38xxp2;
+ struct cvmx_zip_error_s cn56xx;
+ struct cvmx_zip_error_s cn56xxp1;
+ struct cvmx_zip_error_s cn58xx;
+ struct cvmx_zip_error_s cn58xxp1;
+} cvmx_zip_error_t;
+
+typedef union {
+ uint64_t u64;
+ struct cvmx_zip_int_mask_s {
+#if __BYTE_ORDER == __BIG_ENDIAN
+ uint64_t reserved_1_63:63;
+ uint64_t doorbell:1;
+#else
+ uint64_t doorbell:1;
+ uint64_t reserved_1_63:63;
+#endif
+ } s;
+ struct cvmx_zip_int_mask_s cn31xx;
+ struct cvmx_zip_int_mask_s cn38xx;
+ struct cvmx_zip_int_mask_s cn38xxp2;
+ struct cvmx_zip_int_mask_s cn56xx;
+ struct cvmx_zip_int_mask_s cn56xxp1;
+ struct cvmx_zip_int_mask_s cn58xx;
+ struct cvmx_zip_int_mask_s cn58xxp1;
+} cvmx_zip_int_mask_t;
+#endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-csr.h b/arch/mips/cavium-octeon/executive/cvmx-csr.h
new file mode 100644
index 0000000..9a5750a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-csr.h
@@ -0,0 +1,202 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * Octoen.
+ *
+ */
+#ifndef __CVMX_CSR_H__
+#define __CVMX_CSR_H__
+
+#ifndef CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENABLE_CSR_ADDRESS_CHECKING 0
+#endif
+
+#include "cvmx-platform.h"
+#include "cvmx-csr-enums.h"
+#include "cvmx-csr-addresses.h"
+#include "cvmx-csr-typedefs.h"
+
+/* Map the HW names to the SDK historical names */
+typedef cvmx_ciu_intx_en1_t cvmx_ciu_int1_t;
+typedef cvmx_ciu_intx_sum0_t cvmx_ciu_intx0_t;
+typedef cvmx_ciu_mbox_setx_t cvmx_ciu_mbox_t;
+typedef cvmx_fpa_fpfx_marks_t cvmx_fpa_fpf_marks_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que0_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que1_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que2_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que3_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que4_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que5_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que6_page_index_t;
+typedef cvmx_fpa_quex_page_index_t cvmx_fpa_que7_page_index_t;
+typedef cvmx_ipd_1st_mbuff_skip_t cvmx_ipd_mbuff_first_skip_t;
+typedef cvmx_ipd_1st_next_ptr_back_t cvmx_ipd_first_next_ptr_back_t;
+typedef cvmx_ipd_packet_mbuff_size_t cvmx_ipd_mbuff_size_t;
+typedef cvmx_ipd_qosx_red_marks_t cvmx_ipd_qos_red_marks_t;
+typedef cvmx_ipd_wqe_fpa_queue_t cvmx_ipd_wqe_fpa_pool_t;
+typedef cvmx_l2c_pfcx_t cvmx_l2c_pfc0_t;
+typedef cvmx_l2c_pfcx_t cvmx_l2c_pfc1_t;
+typedef cvmx_l2c_pfcx_t cvmx_l2c_pfc2_t;
+typedef cvmx_l2c_pfcx_t cvmx_l2c_pfc3_t;
+typedef cvmx_lmcx_bist_ctl_t cvmx_lmc_bist_ctl_t;
+typedef cvmx_lmcx_bist_result_t cvmx_lmc_bist_result_t;
+typedef cvmx_lmcx_comp_ctl_t cvmx_lmc_comp_ctl_t;
+typedef cvmx_lmcx_ctl_t cvmx_lmc_ctl_t;
+typedef cvmx_lmcx_ctl1_t cvmx_lmc_ctl1_t;
+typedef cvmx_lmcx_dclk_cnt_hi_t cvmx_lmc_dclk_cnt_hi_t;
+typedef cvmx_lmcx_dclk_cnt_lo_t cvmx_lmc_dclk_cnt_lo_t;
+typedef cvmx_lmcx_dclk_ctl_t cvmx_lmc_dclk_ctl_t;
+typedef cvmx_lmcx_ddr2_ctl_t cvmx_lmc_ddr2_ctl_t;
+typedef cvmx_lmcx_delay_cfg_t cvmx_lmc_delay_cfg_t;
+typedef cvmx_lmcx_dll_ctl_t cvmx_lmc_dll_ctl_t;
+typedef cvmx_lmcx_dual_memcfg_t cvmx_lmc_dual_memcfg_t;
+typedef cvmx_lmcx_ecc_synd_t cvmx_lmc_ecc_synd_t;
+typedef cvmx_lmcx_fadr_t cvmx_lmc_fadr_t;
+typedef cvmx_lmcx_ifb_cnt_hi_t cvmx_lmc_ifb_cnt_hi_t;
+typedef cvmx_lmcx_ifb_cnt_lo_t cvmx_lmc_ifb_cnt_lo_t;
+typedef cvmx_lmcx_mem_cfg0_t cvmx_lmc_mem_cfg0_t;
+typedef cvmx_lmcx_mem_cfg1_t cvmx_lmc_mem_cfg1_t;
+typedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_odt_ctl_t;
+typedef cvmx_lmcx_ops_cnt_hi_t cvmx_lmc_ops_cnt_hi_t;
+typedef cvmx_lmcx_ops_cnt_lo_t cvmx_lmc_ops_cnt_lo_t;
+typedef cvmx_lmcx_pll_bwctl_t cvmx_lmc_pll_bwctl_t;
+typedef cvmx_lmcx_pll_ctl_t cvmx_lmc_pll_ctl_t;
+typedef cvmx_lmcx_pll_status_t cvmx_lmc_pll_status_t;
+typedef cvmx_lmcx_read_level_ctl_t cvmx_lmc_read_level_ctl_t;
+typedef cvmx_lmcx_read_level_dbg_t cvmx_lmc_read_level_dbg_t;
+typedef cvmx_lmcx_read_level_rankx_t cvmx_lmc_read_level_rankx_t;
+typedef cvmx_lmcx_rodt_comp_ctl_t cvmx_lmc_rodt_comp_ctl_t;
+typedef cvmx_lmcx_rodt_ctl_t cvmx_lmc_rodt_ctl_t;
+typedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_wodt_ctl_t;
+typedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_wodt_ctl0_t;
+typedef cvmx_lmcx_wodt_ctl1_t cvmx_lmc_wodt_ctl1_t;
+typedef cvmx_mio_boot_reg_cfgx_t cvmx_mio_boot_reg_cfg0_t;
+typedef cvmx_mio_boot_reg_timx_t cvmx_mio_boot_reg_tim0_t;
+typedef cvmx_mio_twsx_int_t cvmx_mio_tws_int_t;
+typedef cvmx_mio_twsx_sw_twsi_t cvmx_mio_tws_sw_twsi_t;
+typedef cvmx_mio_twsx_sw_twsi_ext_t cvmx_mio_tws_sw_twsi_ext_t;
+typedef cvmx_mio_twsx_twsi_sw_t cvmx_mio_tws_twsi_sw_t;
+typedef cvmx_npi_base_addr_inputx_t cvmx_npi_base_addr_input_t;
+typedef cvmx_npi_base_addr_outputx_t cvmx_npi_base_addr_output_t;
+typedef cvmx_npi_buff_size_outputx_t cvmx_npi_buff_size_output_t;
+typedef cvmx_npi_dma_highp_counts_t cvmx_npi_dma_counts_t;
+typedef cvmx_npi_dma_highp_naddr_t cvmx_npi_dma_naddr_t;
+typedef cvmx_npi_highp_dbell_t cvmx_npi_dbell_t;
+typedef cvmx_npi_highp_ibuff_saddr_t cvmx_npi_dma_ibuff_saddr_t;
+typedef cvmx_npi_mem_access_subidx_t cvmx_npi_mem_access_subid_t;
+typedef cvmx_npi_num_desc_outputx_t cvmx_npi_num_desc_output_t;
+typedef cvmx_npi_px_dbpair_addr_t cvmx_npi_dbpair_addr_t;
+typedef cvmx_npi_px_instr_addr_t cvmx_npi_instr_addr_t;
+typedef cvmx_npi_px_instr_cnts_t cvmx_npi_instr_cnts_t;
+typedef cvmx_npi_px_pair_cnts_t cvmx_npi_pair_cnts_t;
+typedef cvmx_npi_size_inputx_t cvmx_npi_size_input_t;
+typedef cvmx_pci_dbellx_t cvmx_pci_dbell_t;
+typedef cvmx_pci_dma_cntx_t cvmx_pci_dma_cnt_t;
+typedef cvmx_pci_dma_int_levx_t cvmx_pci_dma_int_lev_t;
+typedef cvmx_pci_dma_timex_t cvmx_pci_dma_time_t;
+typedef cvmx_pci_instr_countx_t cvmx_pci_instr_count_t;
+typedef cvmx_pci_pkt_creditsx_t cvmx_pci_pkt_credits_t;
+typedef cvmx_pci_pkts_sent_int_levx_t cvmx_pci_pkts_sent_int_lev_t;
+typedef cvmx_pci_pkts_sent_timex_t cvmx_pci_pkts_sent_time_t;
+typedef cvmx_pci_pkts_sentx_t cvmx_pci_pkts_sent_t;
+typedef cvmx_pip_prt_cfgx_t cvmx_pip_port_cfg_t;
+typedef cvmx_pip_prt_tagx_t cvmx_pip_port_tag_cfg_t;
+typedef cvmx_pip_qos_watchx_t cvmx_pip_port_watcher_cfg_t;
+typedef cvmx_pko_mem_queue_ptrs_t cvmx_pko_queue_cfg_t;
+typedef cvmx_pko_reg_cmd_buf_t cvmx_pko_pool_cfg_t;
+typedef cvmx_smix_clk_t cvmx_smi_clk_t;
+typedef cvmx_smix_cmd_t cvmx_smi_cmd_t;
+typedef cvmx_smix_en_t cvmx_smi_en_t;
+typedef cvmx_smix_rd_dat_t cvmx_smi_rd_dat_t;
+typedef cvmx_smix_wr_dat_t cvmx_smi_wr_dat_t;
+typedef cvmx_tim_reg_flags_t cvmx_tim_control_t;
+
+/* The CSRs for bootbus region zero used to be independent of the
+ other 1-7. As of SDK 1.7.0 these were combined. These macros
+ are for backwards compactability */
+#define CVMX_MIO_BOOT_REG_CFG0 CVMX_MIO_BOOT_REG_CFGX(0)
+#define CVMX_MIO_BOOT_REG_TIM0 CVMX_MIO_BOOT_REG_TIMX(0)
+
+/* The CN3XXX and CN58XX chips use to not have a LMC number
+ passed to the address macros. These are here to supply backwards
+ compatability with old code. Code should really use the new addresses
+ with bus arguments for support on other chips */
+#define CVMX_LMC_BIST_CTL CVMX_LMCX_BIST_CTL(0)
+#define CVMX_LMC_BIST_RESULT CVMX_LMCX_BIST_RESULT(0)
+#define CVMX_LMC_COMP_CTL CVMX_LMCX_COMP_CTL(0)
+#define CVMX_LMC_CTL CVMX_LMCX_CTL(0)
+#define CVMX_LMC_CTL1 CVMX_LMCX_CTL1(0)
+#define CVMX_LMC_DCLK_CNT_HI CVMX_LMCX_DCLK_CNT_HI(0)
+#define CVMX_LMC_DCLK_CNT_LO CVMX_LMCX_DCLK_CNT_LO(0)
+#define CVMX_LMC_DCLK_CTL CVMX_LMCX_DCLK_CTL(0)
+#define CVMX_LMC_DDR2_CTL CVMX_LMCX_DDR2_CTL(0)
+#define CVMX_LMC_DELAY_CFG CVMX_LMCX_DELAY_CFG(0)
+#define CVMX_LMC_DLL_CTL CVMX_LMCX_DLL_CTL(0)
+#define CVMX_LMC_DUAL_MEMCFG CVMX_LMCX_DUAL_MEMCFG(0)
+#define CVMX_LMC_ECC_SYND CVMX_LMCX_ECC_SYND(0)
+#define CVMX_LMC_FADR CVMX_LMCX_FADR(0)
+#define CVMX_LMC_IFB_CNT_HI CVMX_LMCX_IFB_CNT_HI(0)
+#define CVMX_LMC_IFB_CNT_LO CVMX_LMCX_IFB_CNT_LO(0)
+#define CVMX_LMC_MEM_CFG0 CVMX_LMCX_MEM_CFG0(0)
+#define CVMX_LMC_MEM_CFG1 CVMX_LMCX_MEM_CFG1(0)
+#define CVMX_LMC_OPS_CNT_HI CVMX_LMCX_OPS_CNT_HI(0)
+#define CVMX_LMC_OPS_CNT_LO CVMX_LMCX_OPS_CNT_LO(0)
+#define CVMX_LMC_PLL_BWCTL CVMX_LMCX_PLL_BWCTL(0)
+#define CVMX_LMC_PLL_CTL CVMX_LMCX_PLL_CTL(0)
+#define CVMX_LMC_PLL_STATUS CVMX_LMCX_PLL_STATUS(0)
+#define CVMX_LMC_READ_LEVEL_CTL CVMX_LMCX_READ_LEVEL_CTL(0)
+#define CVMX_LMC_READ_LEVEL_DBG CVMX_LMCX_READ_LEVEL_DBG(0)
+#define CVMX_LMC_READ_LEVEL_RANKX CVMX_LMCX_READ_LEVEL_RANKX(0)
+#define CVMX_LMC_RODT_COMP_CTL CVMX_LMCX_RODT_COMP_CTL(0)
+#define CVMX_LMC_RODT_CTL CVMX_LMCX_RODT_CTL(0)
+#define CVMX_LMC_WODT_CTL CVMX_LMCX_WODT_CTL0(0)
+#define CVMX_LMC_WODT_CTL0 CVMX_LMCX_WODT_CTL0(0)
+#define CVMX_LMC_WODT_CTL1 CVMX_LMCX_WODT_CTL1(0)
+
+/* The CN3XXX and CN58XX chips use to not have a TWSI bus number
+ passed to the address macros. These are here to supply backwards
+ compatability with old code. Code should really use the new addresses
+ with bus arguments for support on other chips */
+#define CVMX_MIO_TWS_INT CVMX_MIO_TWSX_INT(0)
+#define CVMX_MIO_TWS_SW_TWSI CVMX_MIO_TWSX_SW_TWSI(0)
+#define CVMX_MIO_TWS_SW_TWSI_EXT CVMX_MIO_TWSX_SW_TWSI_EXT(0)
+#define CVMX_MIO_TWS_TWSI_SW CVMX_MIO_TWSX_TWSI_SW(0)
+
+/* The CN3XXX and CN58XX chips use to not have a SMI/MDIO bus number
+ passed to the address macros. These are here to supply backwards
+ compatability with old code. Code should really use the new addresses
+ with bus arguments for support on other chips */
+#define CVMX_SMI_CLK CVMX_SMIX_CLK(0)
+#define CVMX_SMI_CMD CVMX_SMIX_CMD(0)
+#define CVMX_SMI_EN CVMX_SMIX_EN(0)
+#define CVMX_SMI_RD_DAT CVMX_SMIX_RD_DAT(0)
+#define CVMX_SMI_WR_DAT CVMX_SMIX_WR_DAT(0)
+
+#endif /* __CVMX_CSR_H__ */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 07/37] Don't assume boot CPU is CPU0 if MIPS_DISABLE_BOOT_CPU_ZERO set.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (5 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 06/37] Add Cavium OCTEON processor CSR definitions ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 08/37] For Cavium OCTEON handle hazzards as per the R10000 handling ddaney
` (29 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
MIPS SMP code currently assumes that the boot CPU will be CPU0
of the system. For some systems, this may not be the case.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
---
arch/mips/Kconfig | 4 ++++
arch/mips/kernel/smp.c | 2 ++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b905744..5f832ee 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -746,6 +746,10 @@ config HOTPLUG_CPU
bool
default n
+config MIPS_DISABLE_BOOT_CPU_ZERO
+ bool
+ default n
+
config I8259
bool
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index b79ea70..e2597ef 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -195,12 +195,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
/* preload SMP state for boot cpu */
void __devinit smp_prepare_boot_cpu(void)
{
+#ifndef MIPS_DISABLE_BOOT_CPU_ZERO
/*
* This assumes that bootup is always handled by the processor
* with the logic and physical number 0.
*/
__cpu_number_map[0] = 0;
__cpu_logical_map[0] = 0;
+#endif
cpu_set(0, phys_cpu_present_map);
cpu_set(0, cpu_online_map);
cpu_set(0, cpu_callin_map);
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 08/37] For Cavium OCTEON handle hazzards as per the R10000 handling.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (6 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 07/37] Don't assume boot CPU is CPU0 if MIPS_DISABLE_BOOT_CPU_ZERO set ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 10:46 ` Sergei Shtylyov
2008-10-24 0:56 ` [PATCH 09/37] Enable mips32 style bitops for Cavium OCTEON ddaney
` (28 subsequent siblings)
36 siblings, 1 reply; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
For Cavium CPU, we treat the same as R10000, in that all hazzards
are dealt with in hardware.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/hazards.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f..43baed1 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
/*
* TLB hazards
*/
-#if defined(CONFIG_CPU_MIPSR2)
+#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \
__instruction_hazard(); \
} while (0)
-#elif defined(CONFIG_CPU_R10000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 09/37] Enable mips32 style bitops for Cavium OCTEON.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (7 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 08/37] For Cavium OCTEON handle hazzards as per the R10000 handling ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 10/37] Cavium OCTEON: Set hwrena and lazily restore CP2 state ddaney
` (27 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Enable the basic bitops like __ffs and so forth that would normally be
on if we were MIPS32 or MIPS64, but aren't since Cavium sets neither.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney<ddaney@caviumnetworks.com>
---
arch/mips/include/asm/bitops.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4..6f5f225 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -558,7 +558,8 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
__clear_bit(nr, addr);
}
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) \
+ || defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 10/37] Cavium OCTEON: Set hwrena and lazily restore CP2 state.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (8 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 09/37] Enable mips32 style bitops for Cavium OCTEON ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE ddaney
` (26 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
If on Cavium, then be aware of cop2 and hwrena during do_cpu().
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/traps.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80b9e07..8e40795 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -46,6 +46,7 @@
#include <asm/mmu_context.h>
#include <asm/types.h>
#include <asm/stacktrace.h>
+#include <asm/irq.h>
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
@@ -77,6 +78,10 @@ extern asmlinkage void handle_reserved(void);
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_struct *ctx, int has_fpu);
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
+#endif
+
void (*board_be_init)(void);
int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
void (*board_nmi_handler_setup)(void);
@@ -844,6 +849,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
unsigned int opcode;
unsigned int cpid;
int status;
+ unsigned long __maybe_unused flags;
die_if_kernel("do_cpu invoked from kernel context!", regs);
@@ -899,6 +905,17 @@ asmlinkage void do_cpu(struct pt_regs *regs)
return;
case 2:
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ prefetch(¤t->thread.cp2);
+ local_irq_save(flags);
+ KSTK_STATUS(current) |= ST0_CU2;
+ status = read_c0_status();
+ write_c0_status(status | ST0_CU2);
+ octeon_cop2_restore(&(current->thread.cp2));
+ write_c0_status(status & ~ST0_CU2);
+ local_irq_restore(flags);
+ return;
+#endif
case 3:
break;
}
@@ -1472,6 +1489,10 @@ void __cpuinit per_cpu_trap_init(void)
write_c0_hwrena(enable);
}
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
+#endif
+
#ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) {
#endif /* CONFIG_MIPS_MT_SMTC */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (9 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 10/37] Cavium OCTEON: Set hwrena and lazily restore CP2 state ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 19:56 ` Maciej W. Rozycki
2008-10-24 0:56 ` [PATCH 12/37] Add Cavium OCTEON to arch/mips/Kconfig ddaney
` (25 subsequent siblings)
36 siblings, 1 reply; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
On Cavium, the ebase isn't just CAC_BASE, but also the part of
read_c0_ebase() too.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/traps.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8e40795..91c7aa2 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1610,7 +1610,11 @@ void __init trap_init(void)
if (cpu_has_veic || cpu_has_vint)
ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
else
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ ebase = CAC_BASE + (read_c0_ebase() & 0x3ffff000);
+#else
ebase = CAC_BASE;
+#endif
per_cpu_trap_init();
@@ -1718,11 +1722,11 @@ void __init trap_init(void)
if (cpu_has_vce)
/* Special exception: R4[04]00 uses also the divec space. */
- memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
+ memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
else if (cpu_has_4kex)
- memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
+ memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
else
- memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
+ memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
signal_init();
#ifdef CONFIG_MIPS32_COMPAT
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE
2008-10-24 0:56 ` [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE ddaney
@ 2008-10-24 19:56 ` Maciej W. Rozycki
2008-10-24 20:12 ` David Daney
0 siblings, 1 reply; 53+ messages in thread
From: Maciej W. Rozycki @ 2008-10-24 19:56 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips, Tomaso Paoletti
On Thu, 23 Oct 2008, ddaney@caviumnetworks.com wrote:
> From: David Daney <ddaney@caviumnetworks.com>
>
> On Cavium, the ebase isn't just CAC_BASE, but also the part of
> read_c0_ebase() too.
How is that unique to CONFIG_CPU_CAVIUM_OCTEON? That's a general feature
of the MIPS revision 2 architecture, so please make it right from the
beginning. You'll avoid an ugly #ifdef this way too.
Maciej
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE
2008-10-24 19:56 ` Maciej W. Rozycki
@ 2008-10-24 20:12 ` David Daney
0 siblings, 0 replies; 53+ messages in thread
From: David Daney @ 2008-10-24 20:12 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips, Tomaso Paoletti
Maciej W. Rozycki wrote:
> On Thu, 23 Oct 2008, ddaney@caviumnetworks.com wrote:
>
>> From: David Daney <ddaney@caviumnetworks.com>
>>
>> On Cavium, the ebase isn't just CAC_BASE, but also the part of
>> read_c0_ebase() too.
>
> How is that unique to CONFIG_CPU_CAVIUM_OCTEON? That's a general feature
> of the MIPS revision 2 architecture, so please make it right from the
> beginning. You'll avoid an ugly #ifdef this way too.
>
Thanks for the feedback. We will submit a patch that uses the runtime
value of mipsr2 to do the adjustment.
David Daney
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 12/37] Add Cavium OCTEON to arch/mips/Kconfig
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (10 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 13/37] Add Cavium OCTEON processor constants ddaney
` (24 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/Kconfig | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5f832ee..70b16ad 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -597,6 +597,50 @@ config WR_PPMC
This enables support for the Wind River MIPS32 4KC PPMC evaluation
board, which is based on GT64120 bridge chip.
+config CAVIUM_OCTEON_SIMULATOR
+ bool "Support for the Cavium Networks Octeon Simulator"
+ select CEVT_R4K
+ select CSRC_R4K
+ select 64BIT_PHYS_ADDR
+ select DMA_COHERENT
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select CPU_CAVIUM_OCTEON
+ help
+ The Octeon simulator is software performance model of the Cavium
+ Octeon Processor. It supports simulating Octeon processors on x86
+ hardware.
+
+config CAVIUM_OCTEON_REFERENCE_BOARD
+ bool "Support for the Cavium Networks Octeon reference board"
+ select CEVT_R4K
+ select CSRC_R4K
+ select 64BIT_PHYS_ADDR
+ select DMA_COHERENT
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+ select CPU_CAVIUM_OCTEON
+ select SWAP_IO_SPACE
+ select ISA
+ select GENERIC_ISA_DMA
+ select ARCH_MAY_HAVE_PC_FDC
+ help
+ This option supports all of the Octeon reference boards from Cavium
+ Networks. It builds a kernel that dynamically determines the Octeon
+ CPU type and supports all known board reference implementations.
+ Some of the supported boards are:
+ EBT3000
+ EBH3000
+ EBH3100
+ Asus NA-038
+ Thunder
+ Kodama
+ Hikari
+ Say Y here for most Octeon reference boards.
+
endchoice
source "arch/mips/alchemy/Kconfig"
@@ -608,6 +652,7 @@ source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
+source "arch/mips/cavium-octeon/Kconfig"
endmenu
@@ -840,6 +885,9 @@ config IRQ_GT641XX
config IRQ_GIC
bool
+config IRQ_CPU_OCTEON
+ bool
+
config MIPS_BOARDS_GEN
bool
@@ -914,7 +962,7 @@ config BOOT_ELF32
config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION || MIKROTIK_RB532
- default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
+ default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
default "4" if PMC_MSP4200_EVAL
default "5"
@@ -1165,6 +1213,24 @@ config CPU_SB1
select CPU_SUPPORTS_HIGHMEM
select WEAK_ORDERING
+config CPU_CAVIUM_OCTEON
+ bool "Cavium Octeon processor"
+ select IRQ_CPU
+ select IRQ_CPU_OCTEON
+ select CPU_HAS_PREFETCH
+ select CPU_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_SMP
+ select NR_CPUS_DEFAULT_16
+ select WEAK_ORDERING
+ select WEAK_REORDERING_BEYOND_LLSC
+ select CPU_SUPPORTS_HIGHMEM
+ select MIPS_DISABLE_BOOT_CPU_ZERO
+ help
+ The Cavium Octeon processor is a highly integrated chip containing
+ many ethernet hardware widgets for networking tasks. The processor
+ can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
+ Full details can be found at http://www.caviumnetworks.com.
+
endchoice
config SYS_HAS_CPU_LOONGSON2
@@ -1262,7 +1328,7 @@ config CPU_MIPSR1
config CPU_MIPSR2
bool
- default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
+ default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
config SYS_SUPPORTS_32BIT_KERNEL
bool
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 13/37] Add Cavium OCTEON processor constants.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (11 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 12/37] Add Cavium OCTEON to arch/mips/Kconfig ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 14/37] Rewrite cpu_to_name so it has one statement per line ddaney
` (23 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/cpu.h | 14 ++++++++++++++
arch/mips/include/asm/module.h | 2 ++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786..c018727 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
#define PRID_COMP_TOSHIBA 0x070000
#define PRID_COMP_LSI 0x080000
#define PRID_COMP_LEXRA 0x0b0000
+#define PRID_COMP_CAVIUM 0x0d0000
/*
@@ -114,6 +115,18 @@
#define PRID_IMP_BCM3302 0x9000
/*
+ * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
+ */
+
+#define PRID_IMP_CAVIUM_CN38XX 0x0000
+#define PRID_IMP_CAVIUM_CN31XX 0x0100
+#define PRID_IMP_CAVIUM_CN30XX 0x0200
+#define PRID_IMP_CAVIUM_CN58XX 0x0300
+#define PRID_IMP_CAVIUM_CN56XX 0x0400
+#define PRID_IMP_CAVIUM_CN50XX 0x0600
+#define PRID_IMP_CAVIUM_CN52XX 0x0700
+
+/*
* Definitions for 7:0 on legacy processors
*/
@@ -203,6 +216,7 @@ enum cpu_type_enum {
* MIPS64 class processors
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+ CPU_CAVIUM_OCTEON,
CPU_LAST
};
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index de6d09e..7b24183 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -114,6 +114,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "SB1 "
#elif defined CONFIG_CPU_LOONGSON2
#define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_CAVIUM_OCTEON
+#define MODULE_PROC_FAMILY "OCTEON "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 14/37] Rewrite cpu_to_name so it has one statement per line.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (12 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 13/37] Add Cavium OCTEON processor constants ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 15/37] Probe for Cavium OCTEON CPUs ddaney
` (22 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney
From: David Daney <ddaney@caviumnetworks.com>
Future changes can now pass checkpatch.pl
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
---
arch/mips/kernel/cpu-probe.c | 156 +++++++++++++++++++++--------------------
1 files changed, 80 insertions(+), 76 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0cf1545..30f7e8c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -820,86 +820,90 @@ const char *__cpu_name[NR_CPUS];
/*
* Name a CPU
*/
+static const char *mips_cpu_names[] = {
+ [CPU_UNKNOWN] = "unknown",
+ [CPU_R2000] = "R2000",
+ [CPU_R3000] = "R3000",
+ [CPU_R3000A] = "R3000A",
+ [CPU_R3041] = "R3041",
+ [CPU_R3051] = "R3051",
+ [CPU_R3052] = "R3052",
+ [CPU_R3081] = "R3081",
+ [CPU_R3081E] = "R3081E",
+ [CPU_R4000PC] = "R4000PC",
+ [CPU_R4000SC] = "R4000SC",
+ [CPU_R4000MC] = "R4000MC",
+ [CPU_R4200] = "R4200",
+ [CPU_R4400PC] = "R4400PC",
+ [CPU_R4400SC] = "R4400SC",
+ [CPU_R4400MC] = "R4400MC",
+ [CPU_R4600] = "R4600",
+ [CPU_R6000] = "R6000",
+ [CPU_R6000A] = "R6000A",
+ [CPU_R8000] = "R8000",
+ [CPU_R10000] = "R10000",
+ [CPU_R12000] = "R12000",
+ [CPU_R14000] = "R14000",
+ [CPU_R4300] = "R4300",
+ [CPU_R4650] = "R4650",
+ [CPU_R4700] = "R4700",
+ [CPU_R5000] = "R5000",
+ [CPU_R5000A] = "R5000A",
+ [CPU_R4640] = "R4640",
+ [CPU_NEVADA] = "Nevada",
+ [CPU_RM7000] = "RM7000",
+ [CPU_RM9000] = "RM9000",
+ [CPU_R5432] = "R5432",
+ [CPU_4KC] = "MIPS 4Kc",
+ [CPU_5KC] = "MIPS 5Kc",
+ [CPU_R4310] = "R4310",
+ [CPU_SB1] = "SiByte SB1",
+ [CPU_SB1A] = "SiByte SB1A",
+ [CPU_TX3912] = "TX3912",
+ [CPU_TX3922] = "TX3922",
+ [CPU_TX3927] = "TX3927",
+ [CPU_AU1000] = "Au1000",
+ [CPU_AU1500] = "Au1500",
+ [CPU_AU1100] = "Au1100",
+ [CPU_AU1550] = "Au1550",
+ [CPU_AU1200] = "Au1200",
+ [CPU_AU1210] = "Au1210",
+ [CPU_AU1250] = "Au1250",
+ [CPU_4KEC] = "MIPS 4KEc",
+ [CPU_4KSC] = "MIPS 4KSc",
+ [CPU_VR41XX] = "NEC Vr41xx",
+ [CPU_R5500] = "R5500",
+ [CPU_TX49XX] = "TX49xx",
+ [CPU_20KC] = "MIPS 20Kc",
+ [CPU_24K] = "MIPS 24K",
+ [CPU_25KF] = "MIPS 25Kf",
+ [CPU_34K] = "MIPS 34K",
+ [CPU_1004K] = "MIPS 1004K",
+ [CPU_74K] = "MIPS 74K",
+ [CPU_VR4111] = "NEC VR4111",
+ [CPU_VR4121] = "NEC VR4121",
+ [CPU_VR4122] = "NEC VR4122",
+ [CPU_VR4131] = "NEC VR4131",
+ [CPU_VR4133] = "NEC VR4133",
+ [CPU_VR4181] = "NEC VR4181",
+ [CPU_VR4181A] = "NEC VR4181A",
+ [CPU_SR71000] = "Sandcraft SR71000",
+ [CPU_BCM3302] = "Broadcom BCM3302",
+ [CPU_BCM4710] = "Broadcom BCM4710",
+ [CPU_PR4450] = "Philips PR4450",
+ [CPU_LOONGSON2] = "ICT Loongson-2",
+ [CPU_LAST] = NULL
+};
+
static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
{
- const char *name = NULL;
+ const char *name;
- switch (c->cputype) {
- case CPU_UNKNOWN: name = "unknown"; break;
- case CPU_R2000: name = "R2000"; break;
- case CPU_R3000: name = "R3000"; break;
- case CPU_R3000A: name = "R3000A"; break;
- case CPU_R3041: name = "R3041"; break;
- case CPU_R3051: name = "R3051"; break;
- case CPU_R3052: name = "R3052"; break;
- case CPU_R3081: name = "R3081"; break;
- case CPU_R3081E: name = "R3081E"; break;
- case CPU_R4000PC: name = "R4000PC"; break;
- case CPU_R4000SC: name = "R4000SC"; break;
- case CPU_R4000MC: name = "R4000MC"; break;
- case CPU_R4200: name = "R4200"; break;
- case CPU_R4400PC: name = "R4400PC"; break;
- case CPU_R4400SC: name = "R4400SC"; break;
- case CPU_R4400MC: name = "R4400MC"; break;
- case CPU_R4600: name = "R4600"; break;
- case CPU_R6000: name = "R6000"; break;
- case CPU_R6000A: name = "R6000A"; break;
- case CPU_R8000: name = "R8000"; break;
- case CPU_R10000: name = "R10000"; break;
- case CPU_R12000: name = "R12000"; break;
- case CPU_R14000: name = "R14000"; break;
- case CPU_R4300: name = "R4300"; break;
- case CPU_R4650: name = "R4650"; break;
- case CPU_R4700: name = "R4700"; break;
- case CPU_R5000: name = "R5000"; break;
- case CPU_R5000A: name = "R5000A"; break;
- case CPU_R4640: name = "R4640"; break;
- case CPU_NEVADA: name = "Nevada"; break;
- case CPU_RM7000: name = "RM7000"; break;
- case CPU_RM9000: name = "RM9000"; break;
- case CPU_R5432: name = "R5432"; break;
- case CPU_4KC: name = "MIPS 4Kc"; break;
- case CPU_5KC: name = "MIPS 5Kc"; break;
- case CPU_R4310: name = "R4310"; break;
- case CPU_SB1: name = "SiByte SB1"; break;
- case CPU_SB1A: name = "SiByte SB1A"; break;
- case CPU_TX3912: name = "TX3912"; break;
- case CPU_TX3922: name = "TX3922"; break;
- case CPU_TX3927: name = "TX3927"; break;
- case CPU_AU1000: name = "Au1000"; break;
- case CPU_AU1500: name = "Au1500"; break;
- case CPU_AU1100: name = "Au1100"; break;
- case CPU_AU1550: name = "Au1550"; break;
- case CPU_AU1200: name = "Au1200"; break;
- case CPU_AU1210: name = "Au1210"; break;
- case CPU_AU1250: name = "Au1250"; break;
- case CPU_4KEC: name = "MIPS 4KEc"; break;
- case CPU_4KSC: name = "MIPS 4KSc"; break;
- case CPU_VR41XX: name = "NEC Vr41xx"; break;
- case CPU_R5500: name = "R5500"; break;
- case CPU_TX49XX: name = "TX49xx"; break;
- case CPU_20KC: name = "MIPS 20Kc"; break;
- case CPU_24K: name = "MIPS 24K"; break;
- case CPU_25KF: name = "MIPS 25Kf"; break;
- case CPU_34K: name = "MIPS 34K"; break;
- case CPU_1004K: name = "MIPS 1004K"; break;
- case CPU_74K: name = "MIPS 74K"; break;
- case CPU_VR4111: name = "NEC VR4111"; break;
- case CPU_VR4121: name = "NEC VR4121"; break;
- case CPU_VR4122: name = "NEC VR4122"; break;
- case CPU_VR4131: name = "NEC VR4131"; break;
- case CPU_VR4133: name = "NEC VR4133"; break;
- case CPU_VR4181: name = "NEC VR4181"; break;
- case CPU_VR4181A: name = "NEC VR4181A"; break;
- case CPU_SR71000: name = "Sandcraft SR71000"; break;
- case CPU_BCM3302: name = "Broadcom BCM3302"; break;
- case CPU_BCM4710: name = "Broadcom BCM4710"; break;
- case CPU_PR4450: name = "Philips PR4450"; break;
- case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
- default:
+ if (c->cputype > CPU_LAST)
+ BUG();
+ name = mips_cpu_names[c->cputype];
+ if (!name)
BUG();
- }
-
return name;
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 15/37] Probe for Cavium OCTEON CPUs.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (13 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 14/37] Rewrite cpu_to_name so it has one statement per line ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 16/37] MIPS: Hook Cavium OCTEON cache init into cache.c ddaney
` (21 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Add probe function for Cavium OCTEON CPUs and hook it up.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/cpu-probe.c | 26 ++++++++++++++++++++++++++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 30f7e8c..fc2403c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -154,6 +154,7 @@ void __init check_wait(void)
case CPU_25KF:
case CPU_PR4450:
case CPU_BCM3302:
+ case CPU_CAVIUM_OCTEON:
cpu_wait = r4k_wait;
break;
@@ -815,6 +816,27 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
}
}
+static inline void cpu_probe_cavium(struct cpuinfo_mips *c)
+{
+ decode_configs(c);
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_CAVIUM_CN38XX:
+ case PRID_IMP_CAVIUM_CN31XX:
+ case PRID_IMP_CAVIUM_CN30XX:
+ case PRID_IMP_CAVIUM_CN58XX:
+ case PRID_IMP_CAVIUM_CN56XX:
+ case PRID_IMP_CAVIUM_CN50XX:
+ case PRID_IMP_CAVIUM_CN52XX:
+ c->cputype = CPU_CAVIUM_OCTEON;
+ break;
+ default:
+ printk(KERN_INFO "Unknown Octeon chip!\n");
+ c->cputype = CPU_UNKNOWN;
+ break;
+ }
+ mips_probe_watch_registers(c);
+}
+
const char *__cpu_name[NR_CPUS];
/*
@@ -892,6 +914,7 @@ static const char *mips_cpu_names[] = {
[CPU_BCM4710] = "Broadcom BCM4710",
[CPU_PR4450] = "Philips PR4450",
[CPU_LOONGSON2] = "ICT Loongson-2",
+ [CPU_CAVIUM_OCTEON] = "Cavium Octeon",
[CPU_LAST] = NULL
};
@@ -939,6 +962,9 @@ __cpuinit void cpu_probe(void)
case PRID_COMP_NXP:
cpu_probe_nxp(c);
break;
+ case PRID_COMP_CAVIUM:
+ cpu_probe_cavium(c);
+ break;
default:
c->cputype = CPU_UNKNOWN;
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 16/37] MIPS: Hook Cavium OCTEON cache init into cache.c
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (14 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 15/37] Probe for Cavium OCTEON CPUs ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 17/37] cavium: Hook Cavium specifics into main arch/mips dir ddaney
` (20 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Follow precedent of other boards, and hook-up the CPU specific cache
init.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/cpu-features.h | 3 +++
arch/mips/mm/cache.c | 6 ++++++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701f..4b3761b 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
+#ifndef cpu_has_octeon_cache
+#define cpu_has_octeon_cache 0
+#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71..98ad0a8 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
tx39_cache_init();
}
+ if (cpu_has_octeon_cache) {
+ extern void __weak octeon_cache_init(void);
+
+ octeon_cache_init();
+ }
+
setup_protection_map();
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 17/37] cavium: Hook Cavium specifics into main arch/mips dir
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (15 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 16/37] MIPS: Hook Cavium OCTEON cache init into cache.c ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 18/37] Cavium OCTEON modify core io.h macros to account for the Octeon Errata Core-301 ddaney
` (19 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Take all the cavium specific files that were added and hook
them into the build system for the arch/mips.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/Makefile | 13 +++++++++++++
arch/mips/kernel/Makefile | 9 +++++++++
arch/mips/lib/Makefile | 1 +
arch/mips/mm/Makefile | 5 +++++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 7f39fd8..9d487ea 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -142,6 +142,7 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
-Wa,--trap
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
@@ -573,6 +574,18 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
+#
+# Cavium Octeon
+#
+core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
+core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/
+ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
+else
+load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
+endif
+
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
drivers-$(CONFIG_PCI) += arch/mips/pci/
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d9da711..3174b56 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
@@ -65,6 +66,7 @@ obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
obj-$(CONFIG_IRQ_GIC) += irq-gic.o
+obj-$(CONFIG_IRQ_CPU_OCTEON) += irq-octeon.o
obj-$(CONFIG_32BIT) += scall32-o32.o
obj-$(CONFIG_64BIT) += scall64-64.o
@@ -89,3 +91,10 @@ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
EXTRA_CFLAGS += -Werror
+
+ifdef CONFIG_CPU_CAVIUM_OCTEON
+OCTEON_ROOT = $(srctree)/arch/mips/cavium-octeon
+
+CFLAGS_irq-octeon.o = -I$(OCTEON_ROOT)/executive
+CFLAGS_ptrace.o = -I$(OCTEON_ROOT)/executive
+endif
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 8810dfb..872aae3 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o
obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
# libgcc-style stuff needed in the kernel
obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 44e8dd8..6032f5c 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
@@ -33,3 +34,7 @@ obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
EXTRA_CFLAGS += -Werror
+
+OCTEON_ROOT = $(srctree)/arch/mips/cavium-octeon
+CFLAGS_c-octeon.o = -I$(OCTEON_ROOT)/executive
+
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 18/37] Cavium OCTEON modify core io.h macros to account for the Octeon Errata Core-301.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (16 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 17/37] cavium: Hook Cavium specifics into main arch/mips dir ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 19/37] Cavium OCTEON: increase MAX_DMA address ddaney
` (18 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/io.h | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 501a40b..436878e 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
#undef __IS_KSEG1
}
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb() wmb()
+#else
+#define war_octeon_io_reorder_wmb() do { } while (0)
+#endif
+
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
\
static inline void pfx##write##bwlq(type val, \
@@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \
volatile type *__mem; \
type __val; \
\
+ war_octeon_io_reorder_wmb(); \
+ \
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
\
__val = pfx##ioswab##bwlq(__mem, val); \
@@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
volatile type *__addr; \
type __val; \
\
+ war_octeon_io_reorder_wmb(); \
+ \
__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
\
__val = pfx##ioswab##bwlq(__addr, val); \
@@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
#endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
/* Depends on MIPS II instruction set */
#define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 19/37] Cavium OCTEON: increase MAX_DMA address.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (17 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 18/37] Cavium OCTEON modify core io.h macros to account for the Octeon Errata Core-301 ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 20/37] Cavium OCTEON: add in icache and dcache error functions ddaney
` (17 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
There is not a fundamental limit like an old ISA board where DMA can
be only to an address < 16M, so set the MAX_DMA_ADDRESS accordingly.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/dma.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index 1353c81..1706089 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -87,6 +87,13 @@
#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
#define MAX_DMA_ADDRESS PAGE_OFFSET
+#elif defined(CONFIG_CPU_CAVIUM_OCTEON)
+/* Octeon can support DMA to any memory installed */
+#ifdef CONFIG_64BIT
+#define MAX_DMA_ADDRESS (PAGE_OFFSET + (1ull<<32))
+#else
+#define MAX_DMA_ADDRESS (PAGE_OFFSET + (1ul<<30))
+#endif
#else
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 20/37] Cavium OCTEON: add in icache and dcache error functions.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (18 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 19/37] Cavium OCTEON: increase MAX_DMA address ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 21/37] Cavium OCTEON: Add cop2/cvmseg state entries to processor.h ddaney
` (16 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
If there is an icache or dcache error, there is additional data to
be had from the 64bit read of c0 @ $27.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/mipsregs.h | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9798660..4a1feb5 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -966,7 +966,12 @@ do { \
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define read_c0_cacheerr() __read_64bit_c0_register($27, 0)
+#define write_c0_cacheerr(val) __write_64bit_c0_register($27, 0, val)
+#else
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
+#endif
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 21/37] Cavium OCTEON: Add cop2/cvmseg state entries to processor.h.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (19 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 20/37] Cavium OCTEON: add in icache and dcache error functions ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 22/37] Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c ddaney
` (15 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Add in the cop2 and cvmseg state info to the known proc reg
data for Cavium so that it can be tracked, saved, restored...
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/processor.h | 71 +++++++++++++++++++++++++++++++++++++
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 18ee58e..b6b02f2 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -118,6 +118,61 @@ union mips_watch_reg_state {
struct mips3264_watch_reg_state mips3264;
};
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+
+struct octeon_cop2_state {
+ /* DMFC2 rt, 0x0201 */
+ unsigned long cop2_crc_iv;
+ /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
+ unsigned long cop2_crc_length;
+ /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
+ unsigned long cop2_crc_poly;
+ /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
+ unsigned long cop2_llm_dat[2];
+ /* DMFC2 rt, 0x0084 */
+ unsigned long cop2_3des_iv;
+ /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
+ unsigned long cop2_3des_key[3];
+ /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
+ unsigned long cop2_3des_result;
+ /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
+ unsigned long cop2_aes_inp0;
+ /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
+ unsigned long cop2_aes_iv[2];
+ /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
+ * rt, 0x0107 */
+ unsigned long cop2_aes_key[4];
+ /* DMFC2 rt, 0x0110 */
+ unsigned long cop2_aes_keylen;
+ /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
+ unsigned long cop2_aes_result[2];
+ /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
+ * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
+ * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
+ * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
+ * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
+ unsigned long cop2_hsh_datw[15];
+ /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
+ * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
+ * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
+ unsigned long cop2_hsh_ivw[8];
+ /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
+ unsigned long cop2_gfm_mult[2];
+ /* DMFC2 rt, 0x025E - Pass2 */
+ unsigned long cop2_gfm_poly;
+ /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
+ unsigned long cop2_gfm_result[2];
+};
+#define INIT_OCTEON_COP2 {0,}
+
+struct octeon_cvmseg_state {
+ unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
+ [cpu_dcache_line_size() / sizeof(unsigned long)];
+};
+#define INIT_OCTEON_CVMSEG {{{0,},}}
+
+#endif
+
typedef struct {
unsigned long seg;
} mm_segment_t;
@@ -160,6 +215,10 @@ struct thread_struct {
unsigned long trap_no;
unsigned long irix_trampoline; /* Wheee... */
unsigned long irix_oldctx;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
+ struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
+#endif
struct mips_abi *abi;
};
@@ -171,6 +230,14 @@ struct thread_struct {
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define OCTEON_INIT \
+ .cp2 = INIT_OCTEON_COP2, \
+ .cvmseg = INIT_OCTEON_CVMSEG,
+#else
+#define OCTEON_INIT
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
+
#define INIT_THREAD { \
/* \
* Saved main processor registers \
@@ -221,6 +288,10 @@ struct thread_struct {
.trap_no = 0, \
.irix_trampoline = 0, \
.irix_oldctx = 0, \
+ /* \
+ * Cavium Octeon specifics (null if not Octeon) \
+ */ \
+ OCTEON_INIT \
}
struct task_struct;
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 22/37] Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (20 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 21/37] Cavium OCTEON: Add cop2/cvmseg state entries to processor.h ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 23/37] Add SMP_ICACHE_FLUSH for the Cavium CPU family ddaney
` (14 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
arch/mips/include/asm/ptrace.h | 4 ++++
arch/mips/kernel/asm-offsets.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9c22571..3356873 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -52,6 +52,10 @@ struct pt_regs {
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long cp0_tcstatus;
#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[3]; /* MTM{0,1,2} */
+ unsigned long long mtp[3]; /* MTP{0,1,2} */
+#endif
} __attribute__ ((aligned (8)));
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 7294222..c901c22 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -64,6 +64,10 @@ void output_ptreg_defines(void)
#ifdef CONFIG_MIPS_MT_SMTC
OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ OFFSET(PT_MPL, pt_regs, mpl);
+ OFFSET(PT_MTP, pt_regs, mtp);
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
DEFINE(PT_SIZE, sizeof(struct pt_regs));
BLANK();
}
@@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void)
DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));
BLANK();
}
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+void output_octeon_cop2_state_defines(void)
+{
+ COMMENT("Octeon specific octeon_cop2_state offsets.");
+ OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
+ OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
+ OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
+ OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
+ OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
+ OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
+ OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
+ OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
+ OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
+ OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
+ OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
+ OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
+ OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
+ OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
+ OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
+ OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
+ OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
+ OFFSET(THREAD_CP2, task_struct, thread.cp2);
+ OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
+ BLANK();
+}
+#endif
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 23/37] Add SMP_ICACHE_FLUSH for the Cavium CPU family.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (21 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 22/37] Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 24/37] Cavium OCTEON: PT vs MFC0 reorder, multiplier state preservation ddaney
` (13 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/smp.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 0ff5b52..e6f419f 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
#define SMP_CALL_FUNCTION 0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH 0x4
+
extern cpumask_t phys_cpu_present_map;
#define cpu_possible_map phys_cpu_present_map
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 24/37] Cavium OCTEON: PT vs MFC0 reorder, multiplier state preservation.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (22 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 23/37] Add SMP_ICACHE_FLUSH for the Cavium CPU family ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 25/37] Add Cavium OCTEON irq hazard in asmmacro.h ddaney
` (12 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
For cavium, reorder PT ops to be after mfc0 and not before.
Also implement a save and restore of the multiplier state
so that if it gets corrupted, it will not impact things.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/stackframe.h | 46 ++++++++++++++++++++++++++++++++++++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4c37c4e..bcaac81 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,10 +51,12 @@
LONG_S v1, PT_ACX(sp)
#else
mfhi v1
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
LONG_S v1, PT_HI(sp)
mflo v1
LONG_S v1, PT_LO(sp)
#endif
+#endif
#ifdef CONFIG_32BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
@@ -62,10 +64,17 @@
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S $12, PT_R12(sp)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ LONG_S v1, PT_HI(sp)
+ mflo v1
+#endif
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ LONG_S v1, PT_LO(sp)
+#endif
.endm
.macro SAVE_STATIC
@@ -166,7 +175,9 @@
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
LONG_S v1, PT_STATUS(sp)
+#endif
#ifdef CONFIG_MIPS_MT_SMTC
/*
* Ideally, these instructions would be shuffled in
@@ -178,22 +189,53 @@
LONG_S v1, PT_TCSTATUS(sp)
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_S $4, PT_R4(sp)
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
mfc0 v1, CP0_CAUSE
+#endif
LONG_S $5, PT_R5(sp)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ LONG_S v1, PT_STATUS(sp)
+ mfc0 v1, CP0_CAUSE
+#else
LONG_S v1, PT_CAUSE(sp)
+#endif
LONG_S $6, PT_R6(sp)
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
MFC0 v1, CP0_EPC
+#endif
LONG_S $7, PT_R7(sp)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ LONG_S v1, PT_CAUSE(sp)
+ MFC0 v1, CP0_EPC
+#endif
#ifdef CONFIG_64BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
#endif
+#ifndef CONFIG_CPU_CAVIUM_OCTEON
LONG_S v1, PT_EPC(sp)
+#endif
LONG_S $25, PT_R25(sp)
LONG_S $28, PT_R28(sp)
LONG_S $31, PT_R31(sp)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ LONG_S v1, PT_EPC(sp)
+#endif
ori $28, sp, _THREAD_MASK
xori $28, _THREAD_MASK
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ .set mips64
+ pref 0, 0($28) /* Prefetch the current pointer */
+ pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
+ /* The Octeon multiplier state is affected by general multiply
+ instructions. It must be saved before and kernel code might
+ corrupt it */
+ jal octeon_mult_save
+ LONG_L v1, 0($28) /* Load the current pointer */
+ /* Restore $31(ra) that was changed by the jal */
+ LONG_L ra, PT_R31(sp)
+ pref 0, 0(v1) /* Prefetch the current thread */
+#endif
.set pop
.endm
@@ -324,6 +366,10 @@
DVPE 5 # dvpe a1
jal mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ /* Restore the Octeon multiplier state */
+ jal octeon_mult_restore
+#endif
mfc0 a0, CP0_STATUS
ori a0, STATMASK
xori a0, STATMASK
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 25/37] Add Cavium OCTEON irq hazard in asmmacro.h.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (23 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 24/37] Cavium OCTEON: PT vs MFC0 reorder, multiplier state preservation ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 26/37] Compute branch returns for Cavium OCTEON specific branch instructions ddaney
` (11 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Place irq_enable_hazard and irq_disable_hazard into asmmacro.h
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/asmmacro.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 7a88175..5408149 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -35,6 +35,16 @@
mtc0 \reg, CP0_TCSTATUS
_ehb
.endm
+#elif defined(CONFIG_CPU_CAVIUM_OCTEON)
+ .macro local_irq_enable reg=t0
+ ei
+ irq_enable_hazard
+ .endm
+
+ .macro local_irq_disable reg=t0
+ di
+ irq_disable_hazard
+ .endm
#else
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 26/37] Compute branch returns for Cavium OCTEON specific branch instructions.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (24 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 25/37] Add Cavium OCTEON irq hazard in asmmacro.h ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 27/37] Add Cavium OCTEON slot into proper tlb category ddaney
` (10 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
For cavium, compute the return epc value in the fashion specific to
the OCTEON.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/branch.c | 33 +++++++++++++++++++++++++++++++++
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 6b5df8b..0176ed0 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -205,6 +205,39 @@ int __compute_return_epc(struct pt_regs *regs)
break;
}
break;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ case lwc2_op: /* This is bbit0 on Octeon */
+ if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
+ == 0)
+ epc = epc + 4 + (insn.i_format.simmediate << 2);
+ else
+ epc += 8;
+ regs->cp0_epc = epc;
+ break;
+ case ldc2_op: /* This is bbit032 on Octeon */
+ if ((regs->regs[insn.i_format.rs] &
+ (1ull<<(insn.i_format.rt+32))) == 0)
+ epc = epc + 4 + (insn.i_format.simmediate << 2);
+ else
+ epc += 8;
+ regs->cp0_epc = epc;
+ break;
+ case swc2_op: /* This is bbit1 on Octeon */
+ if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
+ epc = epc + 4 + (insn.i_format.simmediate << 2);
+ else
+ epc += 8;
+ regs->cp0_epc = epc;
+ break;
+ case sdc2_op: /* This is bbit132 on Octeon */
+ if (regs->regs[insn.i_format.rs] &
+ (1ull<<(insn.i_format.rt+32)))
+ epc = epc + 4 + (insn.i_format.simmediate << 2);
+ else
+ epc += 8;
+ regs->cp0_epc = epc;
+ break;
+#endif
}
return 0;
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 27/37] Add Cavium OCTEON slot into proper tlb category.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (25 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 26/37] Compute branch returns for Cavium OCTEON specific branch instructions ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception ddaney
` (9 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/mm/tlbex.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf91..4294203 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BCM3302:
case CPU_BCM4710:
case CPU_LOONGSON2:
+ case CPU_CAVIUM_OCTEON:
if (m4kc_tlbp_war())
uasm_i_nop(p);
tlbw(p);
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (26 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 27/37] Add Cavium OCTEON slot into proper tlb category ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 10:39 ` Sergei Shtylyov
2008-10-24 0:56 ` [PATCH 29/37] Don't clobber spinlocks in 8250 ddaney
` (8 subsequent siblings)
36 siblings, 1 reply; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
The FPU exceptions come in as TLB exceptions -- see if this is
one of them, and act accordingly.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/mm/fault.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index fa636fc..9ce503a 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -47,6 +47,21 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
field, regs->cp0_epc);
#endif
+#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
+ /*
+ * Normally the FPU emulator uses a load word from address one
+ * to retake control of the CPU after executing the
+ * instruction in the delay slot of an emulated branch. The
+ * Octeon hardware unaligned access fix changes this from an
+ * address exception into a TLB exception. This code checks to
+ * see if this page fault was caused by an FPU emulation.
+ *
+ * Terminate if exception was recognized as a delay slot return */
+ extern int do_dsemulret(struct pt_regs *);
+ if (do_dsemulret(regs))
+ return;
+#endif
+
info.si_code = SEGV_MAPERR;
/*
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception
2008-10-24 0:56 ` [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception ddaney
@ 2008-10-24 10:39 ` Sergei Shtylyov
2008-10-24 13:11 ` Paul Gortmaker
2008-10-24 17:01 ` David Daney
0 siblings, 2 replies; 53+ messages in thread
From: Sergei Shtylyov @ 2008-10-24 10:39 UTC (permalink / raw)
To: ddaney; +Cc: linux-mips, Tomaso Paoletti, Paul Gortmaker
Hello.
ddaney@caviumnetworks.com wrote:
> The FPU exceptions come in as TLB exceptions -- see if this is
> one of them, and act accordingly.
>
> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/mm/fault.c | 15 +++++++++++++++
> 1 files changed, 15 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
> index fa636fc..9ce503a 100644
> --- a/arch/mips/mm/fault.c
> +++ b/arch/mips/mm/fault.c
> @@ -47,6 +47,21 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
> field, regs->cp0_epc);
> #endif
>
> +#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
>
Why this is not in the same patch that introduces this option?
> + /*
> + * Normally the FPU emulator uses a load word from address one
> + * to retake control of the CPU after executing the
> + * instruction in the delay slot of an emulated branch. The
> + * Octeon hardware unaligned access fix changes this from an
> + * address exception into a TLB exception. This code checks to
> + * see if this page fault was caused by an FPU emulation.
> + *
> + * Terminate if exception was recognized as a delay slot return */
>
I'm back to nitpicking again, see chapter 8 for the preferred
multiuline comment style (you almost got it right :-).
> + extern int do_dsemulret(struct pt_regs *);
>
Won't this cause a warning about the declaration amidst of code? You
should be able to put it in this function's declaration block painlessly...
WBR. Sergei
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception
2008-10-24 10:39 ` Sergei Shtylyov
@ 2008-10-24 13:11 ` Paul Gortmaker
2008-10-24 17:01 ` David Daney
1 sibling, 0 replies; 53+ messages in thread
From: Paul Gortmaker @ 2008-10-24 13:11 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: ddaney, linux-mips, Tomaso Paoletti
Sergei Shtylyov wrote:
> Hello.
>
> ddaney@caviumnetworks.com wrote:
>
>
>
>> + extern int do_dsemulret(struct pt_regs *);
>>
>
> Won't this cause a warning about the declaration amidst of code? You
> should be able to put it in this function's declaration block
> painlessly...
Yep, I gave David the heads up on this yesterday as well, so I'm
sure he'll squirrel it away in a more appropriate place and resend.
Thanks,
Paul.
>
> WBR. Sergei
>
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception
2008-10-24 10:39 ` Sergei Shtylyov
2008-10-24 13:11 ` Paul Gortmaker
@ 2008-10-24 17:01 ` David Daney
1 sibling, 0 replies; 53+ messages in thread
From: David Daney @ 2008-10-24 17:01 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: linux-mips, Tomaso Paoletti, Paul Gortmaker
Sergei Shtylyov wrote:
> Hello.
>
> ddaney@caviumnetworks.com wrote:
>
>> The FPU exceptions come in as TLB exceptions -- see if this is
>> one of them, and act accordingly.
>>
>> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
>> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
>> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
>> ---
>> arch/mips/mm/fault.c | 15 +++++++++++++++
>> 1 files changed, 15 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
>> index fa636fc..9ce503a 100644
>> --- a/arch/mips/mm/fault.c
>> +++ b/arch/mips/mm/fault.c
>> @@ -47,6 +47,21 @@ asmlinkage void do_page_fault(struct pt_regs *regs,
>> unsigned long write,
>> field, regs->cp0_epc);
>> #endif
>>
>> +#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
>>
>
> Why this is not in the same patch that introduces this option?
Because the option was introduced in patch 01/37 along with all the rest
of the new files. I decided to add the Kconfig for the entire patch set
in a single go. For an incremental patch, certainly Kconfig changes
would probably be in the patch that adds their use. But I think
rigorous orthodoxy on this point in the initial patch set might make
things less clear rather than improving the situation.
>
>> + /*
>> + * Normally the FPU emulator uses a load word from address one
>> + * to retake control of the CPU after executing the
>> + * instruction in the delay slot of an emulated branch. The
>> + * Octeon hardware unaligned access fix changes this from an
>> + * address exception into a TLB exception. This code checks to
>> + * see if this page fault was caused by an FPU emulation.
>> + *
>> + * Terminate if exception was recognized as a delay slot return */
>>
>
> I'm back to nitpicking again, see chapter 8 for the preferred
> multiuline comment style (you almost got it right :-).
>
>> + extern int do_dsemulret(struct pt_regs *);
>>
>
> Won't this cause a warning about the declaration amidst of code? You
> should be able to put it in this function's declaration block painlessly...
>
Both of these last point will be addressed.
David Daney
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 29/37] Don't clobber spinlocks in 8250.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (27 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 28/37] Cavium OCTEON FPU EMU exception as TLB exception ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 20:12 ` Maciej W. Rozycki
2008-10-24 0:56 ` [PATCH 30/37] Generic 8250 serial driver changes to support future OCTEON serial patches ddaney
` (7 subsequent siblings)
36 siblings, 1 reply; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
In serial8250_isa_init_ports(), the port's lock is initialized. We
should not overwrite it. Only copy in the fields we need.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
drivers/serial/8250.c | 15 +++++++++++++--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 1528de2..d339ac1 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -2706,12 +2706,23 @@ static struct uart_driver serial8250_reg = {
*/
int __init early_serial_setup(struct uart_port *port)
{
+ struct uart_port *p;
+
if (port->line >= ARRAY_SIZE(serial8250_ports))
return -ENODEV;
serial8250_isa_init_ports();
- serial8250_ports[port->line].port = *port;
- serial8250_ports[port->line].port.ops = &serial8250_pops;
+ p = &serial8250_ports[port->line].port;
+ p->iobase = port->iobase;
+ p->membase = port->membase;
+ p->irq = port->irq;
+ p->uartclk = port->uartclk;
+ p->fifosize = port->fifosize;
+ p->regshift = port->regshift;
+ p->iotype = port->iotype;
+ p->flags = port->flags;
+ p->mapbase = port->mapbase;
+ p->private_data = port->private_data;
return 0;
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 29/37] Don't clobber spinlocks in 8250.
2008-10-24 0:56 ` [PATCH 29/37] Don't clobber spinlocks in 8250 ddaney
@ 2008-10-24 20:12 ` Maciej W. Rozycki
2008-10-24 20:16 ` David Daney
0 siblings, 1 reply; 53+ messages in thread
From: Maciej W. Rozycki @ 2008-10-24 20:12 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips, Tomaso Paoletti
On Thu, 23 Oct 2008, ddaney@caviumnetworks.com wrote:
> From: David Daney <ddaney@caviumnetworks.com>
>
> In serial8250_isa_init_ports(), the port's lock is initialized. We
> should not overwrite it. Only copy in the fields we need.
I suggest you to send all the 8250 patches to
linux-serial@vger.kernel.org and most probably the LKML. I don't think
the relevant maintainers read this list -- note that they will be the
general Linux maintainers as the serial subsystem doesn't have a dedicated
one at the moment. Please always consult the MAINTAINERS file before
posting patches (see Documentation/SubmittingPatches too).
Maciej
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 29/37] Don't clobber spinlocks in 8250.
2008-10-24 20:12 ` Maciej W. Rozycki
@ 2008-10-24 20:16 ` David Daney
0 siblings, 0 replies; 53+ messages in thread
From: David Daney @ 2008-10-24 20:16 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips, Tomaso Paoletti
Maciej W. Rozycki wrote:
> On Thu, 23 Oct 2008, ddaney@caviumnetworks.com wrote:
>
>> From: David Daney <ddaney@caviumnetworks.com>
>>
>> In serial8250_isa_init_ports(), the port's lock is initialized. We
>> should not overwrite it. Only copy in the fields we need.
>
> I suggest you to send all the 8250 patches to
> linux-serial@vger.kernel.org and most probably the LKML. I don't think
> the relevant maintainers read this list -- note that they will be the
> general Linux maintainers as the serial subsystem doesn't have a dedicated
> one at the moment. Please always consult the MAINTAINERS file before
> posting patches (see Documentation/SubmittingPatches too).
Thanks, we are aware of this. All the serial patches had been
previously sent as you suggest.
The next revision of this patch set will go to a wider audience,
including linux-serial@ as appropriate.
David Daney
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 30/37] Generic 8250 serial driver changes to support future OCTEON serial patches.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (28 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 29/37] Don't clobber spinlocks in 8250 ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 31/37] Allow port type to be specified when calling serial8250_register_port ddaney
` (6 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
In order to use Cavium OCTEON specific serial i/o drivers, we first patch
the 8250 driver to use replaceable i/o functions.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
drivers/serial/8250.c | 192 ++++++++++++++++++++++++++++++-------------
include/linux/serial_8250.h | 2 +
include/linux/serial_core.h | 2 +
3 files changed, 138 insertions(+), 58 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index d339ac1..7b7850b 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -299,16 +299,16 @@ static const u8 au_io_out_map[] = {
};
/* sane hardware needs no mapping */
-static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
+static inline int map_8250_in_reg(struct uart_port *p, int offset)
{
- if (up->port.iotype != UPIO_AU)
+ if (p->iotype != UPIO_AU)
return offset;
return au_io_in_map[offset];
}
-static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
+static inline int map_8250_out_reg(struct uart_port *p, int offset)
{
- if (up->port.iotype != UPIO_AU)
+ if (p->iotype != UPIO_AU)
return offset;
return au_io_out_map[offset];
}
@@ -337,16 +337,16 @@ static const u8
[UART_SCR] = 0x2c
};
-static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
+static inline int map_8250_in_reg(struct uart_port *p, int offset)
{
- if (up->port.iotype != UPIO_RM9000)
+ if (p->iotype != UPIO_RM9000)
return offset;
return regmap_in[offset];
}
-static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
+static inline int map_8250_out_reg(struct uart_port *p, int offset)
{
- if (up->port.iotype != UPIO_RM9000)
+ if (p->iotype != UPIO_RM9000)
return offset;
return regmap_out[offset];
}
@@ -359,108 +359,170 @@ static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
#endif
-static unsigned int serial_in(struct uart_8250_port *up, int offset)
+static unsigned int hub6_serial_in_fn(struct uart_port *p, int offset)
{
- unsigned int tmp;
- offset = map_8250_in_reg(up, offset) << up->port.regshift;
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ outb(p->hub6 - 1 + offset, p->iobase);
+ return inb(p->iobase + 1);
+}
- switch (up->port.iotype) {
- case UPIO_HUB6:
- outb(up->port.hub6 - 1 + offset, up->port.iobase);
- return inb(up->port.iobase + 1);
+static void hub6_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ outb(p->hub6 - 1 + offset, p->iobase);
+ outb(value, p->iobase + 1);
+}
- case UPIO_MEM:
- case UPIO_DWAPB:
- return readb(up->port.membase + offset);
+static unsigned int mem_serial_in_fn(struct uart_port *p, int offset)
+{
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ return readb(p->membase + offset);
+}
- case UPIO_RM9000:
- case UPIO_MEM32:
- return readl(up->port.membase + offset);
+static void mem_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ writeb(value, p->membase + offset);
+}
+
+static void mem32_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ writel(value, p->membase + offset);
+}
+
+static unsigned int mem32_serial_in_fn(struct uart_port *p, int offset)
+{
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ return readl(p->membase + offset);
+}
#ifdef CONFIG_SERIAL_8250_AU1X00
- case UPIO_AU:
- return __raw_readl(up->port.membase + offset);
+static unsigned int au_serial_in_fn(struct uart_port *p, int offset)
+{
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ return __raw_readl(p->membase + offset);
+}
+
+static void au_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ __raw_writel(value, p->membase + offset);
+}
#endif
- case UPIO_TSI:
- if (offset == UART_IIR) {
- tmp = readl(up->port.membase + (UART_IIR & ~3));
- return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
- } else
- return readb(up->port.membase + offset);
+static unsigned int tsi_serial_in_fn(struct uart_port *p, int offset)
+{
+ unsigned int tmp;
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ if (offset == UART_IIR) {
+ tmp = readl(p->membase + (UART_IIR & ~3));
+ return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
+ } else
+ return readb(p->membase + offset);
+}
- default:
- return inb(up->port.iobase + offset);
- }
+static void tsi_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ if (!((offset == UART_IER) && (value & UART_IER_UUE)))
+ writeb(value, p->membase + offset);
}
-static void
-serial_out(struct uart_8250_port *up, int offset, int value)
+static void dwapb_serial_out_fn(struct uart_port *p, int offset, int value)
{
- /* Save the offset before it's remapped */
int save_offset = offset;
- offset = map_8250_out_reg(up, offset) << up->port.regshift;
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ /* Save the LCR value so it can be re-written when a
+ * Busy Detect interrupt occurs. */
+ if (save_offset == UART_LCR) {
+ struct uart_8250_port *up = (struct uart_8250_port *)p;
+ up->lcr = value;
+ }
+ writeb(value, p->membase + offset);
+ /* Read the IER to ensure any interrupt is cleared before
+ * returning from ISR. */
+ if (save_offset == UART_TX || save_offset == UART_IER)
+ value = p->serial_in_fn(p, UART_IER);
+}
- switch (up->port.iotype) {
+static unsigned int io_serial_in_fn(struct uart_port *p, int offset)
+{
+ offset = map_8250_in_reg(p, offset) << p->regshift;
+ return inb(p->iobase + offset);
+}
+
+static void io_serial_out_fn(struct uart_port *p, int offset, int value)
+{
+ offset = map_8250_out_reg(p, offset) << p->regshift;
+ outb(value, p->iobase + offset);
+}
+
+static void set_io_fns_from_upio(struct uart_port *p)
+{
+ switch (p->iotype) {
case UPIO_HUB6:
- outb(up->port.hub6 - 1 + offset, up->port.iobase);
- outb(value, up->port.iobase + 1);
+ p->serial_in_fn = hub6_serial_in_fn;
+ p->serial_out_fn = hub6_serial_out_fn;
break;
case UPIO_MEM:
- writeb(value, up->port.membase + offset);
+ p->serial_in_fn = mem_serial_in_fn;
+ p->serial_out_fn = mem_serial_out_fn;
break;
case UPIO_RM9000:
case UPIO_MEM32:
- writel(value, up->port.membase + offset);
+ p->serial_in_fn = mem32_serial_in_fn;
+ p->serial_out_fn = mem32_serial_out_fn;
break;
#ifdef CONFIG_SERIAL_8250_AU1X00
case UPIO_AU:
- __raw_writel(value, up->port.membase + offset);
+ p->serial_in_fn = au_serial_in_fn;
+ p->serial_out_fn = au_serial_out_fn;
break;
#endif
case UPIO_TSI:
- if (!((offset == UART_IER) && (value & UART_IER_UUE)))
- writeb(value, up->port.membase + offset);
+ p->serial_in_fn = tsi_serial_in_fn;
+ p->serial_out_fn = tsi_serial_out_fn;
break;
case UPIO_DWAPB:
- /* Save the LCR value so it can be re-written when a
- * Busy Detect interrupt occurs. */
- if (save_offset == UART_LCR)
- up->lcr = value;
- writeb(value, up->port.membase + offset);
- /* Read the IER to ensure any interrupt is cleared before
- * returning from ISR. */
- if (save_offset == UART_TX || save_offset == UART_IER)
- value = serial_in(up, UART_IER);
+ p->serial_in_fn = mem_serial_in_fn;
+ p->serial_out_fn = dwapb_serial_out_fn;
break;
default:
- outb(value, up->port.iobase + offset);
+ p->serial_in_fn = io_serial_in_fn;
+ p->serial_out_fn = io_serial_out_fn;
+ break;
}
}
static void
serial_out_sync(struct uart_8250_port *up, int offset, int value)
{
- switch (up->port.iotype) {
+ struct uart_port *p = &up->port;
+ switch (p->iotype) {
case UPIO_MEM:
case UPIO_MEM32:
#ifdef CONFIG_SERIAL_8250_AU1X00
case UPIO_AU:
#endif
case UPIO_DWAPB:
- serial_out(up, offset, value);
- serial_in(up, UART_LCR); /* safe, no side-effects */
+ p->serial_out_fn(p, offset, value);
+ p->serial_in_fn(p, UART_LCR); /* safe, no side-effects */
break;
default:
- serial_out(up, offset, value);
+ p->serial_out_fn(p, offset, value);
}
}
+#define serial_in(up, offset) \
+ (up->port.serial_in_fn(&(up)->port, (offset)))
+#define serial_out(up, offset, value) \
+ (up->port.serial_out_fn(&(up)->port, (offset), (value)))
/*
* We used to support using pause I/O for certain machines. We
* haven't supported this for a while, but just in case it's badly
@@ -2530,6 +2592,7 @@ static void __init serial8250_isa_init_ports(void)
up->port.membase = old_serial_port[i].iomem_base;
up->port.iotype = old_serial_port[i].io_type;
up->port.regshift = old_serial_port[i].iomem_reg_shift;
+ set_io_fns_from_upio(&up->port);
if (share_irqs)
up->port.flags |= UPF_SHARE_IRQ;
}
@@ -2723,6 +2786,13 @@ int __init early_serial_setup(struct uart_port *port)
p->flags = port->flags;
p->mapbase = port->mapbase;
p->private_data = port->private_data;
+
+ set_io_fns_from_upio(p);
+ if (port->serial_in_fn)
+ p->serial_in_fn = port->serial_in_fn;
+ if (port->serial_out_fn)
+ p->serial_out_fn = port->serial_out_fn;
+
return 0;
}
@@ -2940,6 +3010,12 @@ int serial8250_register_port(struct uart_port *port)
uart->port.private_data = port->private_data;
if (port->dev)
uart->port.dev = port->dev;
+ set_io_fns_from_upio(&uart->port);
+ /* Possibly override default I/O functions. */
+ if (port->serial_in_fn)
+ uart->port.serial_in_fn = port->serial_in_fn;
+ if (port->serial_out_fn)
+ uart->port.serial_out_fn = port->serial_out_fn;
ret = uart_add_one_port(&serial8250_reg, &uart->port);
if (ret == 0)
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index 3d37c94..eb08b04 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -28,6 +28,8 @@ struct plat_serial8250_port {
unsigned char iotype; /* UPIO_* */
unsigned char hub6;
upf_t flags; /* UPF_* flags */
+ unsigned int (*serial_in_fn)(struct uart_port *, int);
+ void (*serial_out_fn)(struct uart_port *, int, int);
};
/*
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index e27f216..40509b0 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -243,6 +243,8 @@ struct uart_port {
spinlock_t lock; /* port lock */
unsigned long iobase; /* in/out[bwl] */
unsigned char __iomem *membase; /* read/write[bwl] */
+ unsigned int (*serial_in_fn)(struct uart_port *, int);
+ void (*serial_out_fn)(struct uart_port *, int, int);
unsigned int irq; /* irq number */
unsigned int uartclk; /* base uart clock */
unsigned int fifosize; /* tx fifo size */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 31/37] Allow port type to be specified when calling serial8250_register_port.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (29 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 30/37] Generic 8250 serial driver changes to support future OCTEON serial patches ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 32/37] Allow port type to specify bugs that are not probed for ddaney
` (5 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney
From: David Daney <ddaney@caviumnetworks.com>
Add flag value UPF_FIXED_TYPE which specifies that the UART type is
known and should not be probed. For this case the UARTs properties
are just copied out of the uart_config entry.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
drivers/serial/8250.c | 8 ++++++++
drivers/serial/serial_core.c | 7 +++++--
include/linux/serial_core.h | 2 ++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 7b7850b..e26c090 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -3010,6 +3010,14 @@ int serial8250_register_port(struct uart_port *port)
uart->port.private_data = port->private_data;
if (port->dev)
uart->port.dev = port->dev;
+
+ if (port->flags & UPF_FIXED_TYPE) {
+ uart->port.type = port->type;
+ uart->port.fifosize = uart_config[port->type].fifo_size;
+ uart->capabilities = uart_config[port->type].flags;
+ uart->tx_loadsz = uart_config[port->type].tx_loadsz;
+ }
+
set_io_fns_from_upio(&uart->port);
/* Possibly override default I/O functions. */
if (port->serial_in_fn)
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index 6bdf336..1f6685e 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -2198,11 +2198,14 @@ uart_configure_port(struct uart_driver *drv, struct uart_state *state,
* Now do the auto configuration stuff. Note that config_port
* is expected to claim the resources and map the port for us.
*/
- flags = UART_CONFIG_TYPE;
+ flags = 0;
if (port->flags & UPF_AUTO_IRQ)
flags |= UART_CONFIG_IRQ;
if (port->flags & UPF_BOOT_AUTOCONF) {
- port->type = PORT_UNKNOWN;
+ if (!(port->flags & UPF_FIXED_TYPE)) {
+ port->type = PORT_UNKNOWN;
+ flags |= UART_CONFIG_TYPE;
+ }
port->ops->config_port(port, flags);
}
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 40509b0..54e0dce 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -290,6 +290,8 @@ struct uart_port {
#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
+/* The exact UART type is known and should not be probed. */
+#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
#define UPF_DEAD ((__force upf_t) (1 << 30))
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 32/37] Allow port type to specify bugs that are not probed for.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (30 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 31/37] Allow port type to be specified when calling serial8250_register_port ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 33/37] 8250 serial driver changes for Cavium OCTEON ddaney
` (4 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney
From: David Daney <ddaney@caviumnetworks.com>
Add a bugs field to the serial8250_config and propagate it to the
port's bugs field when the port is registered and configured.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
drivers/serial/8250.c | 2 ++
drivers/serial/8250.h | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index e26c090..a771554 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -1208,6 +1208,7 @@ static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
up->port.fifosize = uart_config[up->port.type].fifo_size;
up->capabilities = uart_config[up->port.type].flags;
up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
+ up->bugs |= uart_config[up->port.type].bugs;
if (up->port.type == PORT_UNKNOWN)
goto out;
@@ -3016,6 +3017,7 @@ int serial8250_register_port(struct uart_port *port)
uart->port.fifosize = uart_config[port->type].fifo_size;
uart->capabilities = uart_config[port->type].flags;
uart->tx_loadsz = uart_config[port->type].tx_loadsz;
+ uart->bugs = uart_config[port->type].bugs;
}
set_io_fns_from_upio(&uart->port);
diff --git a/drivers/serial/8250.h b/drivers/serial/8250.h
index 5202603..c9b3002 100644
--- a/drivers/serial/8250.h
+++ b/drivers/serial/8250.h
@@ -34,6 +34,7 @@ struct serial8250_config {
const char *name;
unsigned short fifo_size;
unsigned short tx_loadsz;
+ unsigned short bugs;
unsigned char fcr;
unsigned int flags;
};
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 33/37] 8250 serial driver changes for Cavium OCTEON.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (31 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 32/37] Allow port type to specify bugs that are not probed for ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 34/37] Adjust the dma-common.c platform hooks ddaney
` (3 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Cavium UART implementation won't work with the standard 8250 driver
as-is. Define a new uart_config (PORT_OCTEON) and use it to enable
special handling required by the OCTEON's serial port.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
drivers/serial/8250.c | 16 +++++++++++++++-
drivers/serial/8250.h | 2 ++
include/linux/serial_core.h | 3 ++-
include/linux/serial_reg.h | 6 ++++++
4 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index a771554..25cc36e 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -275,6 +275,14 @@ static const struct serial8250_config uart_config[] = {
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO,
},
+ [PORT_OCTEON] = {
+ .name = "OCTEON",
+ .fifo_size = 64,
+ .tx_loadsz = 64,
+ .bugs = UART_BUG_TIMEOUT | UART_BUG_OCTEON_IIR,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+ .flags = UART_CAP_FIFO,
+ },
};
#if defined (CONFIG_SERIAL_8250_AU1X00)
@@ -1550,6 +1558,12 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
up = list_entry(l, struct uart_8250_port, list);
iir = serial_in(up, UART_IIR);
+ if ((up->bugs & UART_BUG_OCTEON_IIR) && (iir & 0xf) == 7) {
+ /* Busy interrupt */
+ serial_in(up, UART_OCTEON_USR);
+ iir = serial_in(up, UART_IIR);
+ }
+
if (!(iir & UART_IIR_NO_INT)) {
serial8250_handle_port(up);
@@ -1668,7 +1682,7 @@ static void serial8250_timeout(unsigned long data)
unsigned int iir;
iir = serial_in(up, UART_IIR);
- if (!(iir & UART_IIR_NO_INT))
+ if (!(iir & UART_IIR_NO_INT) || (up->bugs & UART_BUG_TIMEOUT))
serial8250_handle_port(up);
mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
}
diff --git a/drivers/serial/8250.h b/drivers/serial/8250.h
index c9b3002..56b3cb7 100644
--- a/drivers/serial/8250.h
+++ b/drivers/serial/8250.h
@@ -49,6 +49,8 @@ struct serial8250_config {
#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
+#define UART_BUG_TIMEOUT (1 << 4) /* UART should always handle timeout */
+#define UART_BUG_OCTEON_IIR (1 << 5) /* UART OCTEON IIR workaround */
#define PROBE_RSA (1 << 0)
#define PROBE_ANY (~0)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 54e0dce..c6c7faa 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -40,7 +40,8 @@
#define PORT_NS16550A 14
#define PORT_XSCALE 15
#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
-#define PORT_MAX_8250 16 /* max port ID */
+#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
+#define PORT_MAX_8250 17 /* max port ID */
/*
* ARM specific type numbers. These are not currently guaranteed
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 96c0d93..a96bd50 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -324,5 +324,11 @@
#define UART_OMAP_SYSC 0x15 /* System configuration register */
#define UART_OMAP_SYSS 0x16 /* System status register */
+/*
+ * Extra serial register definitions for the internal UARTs in Cavium
+ * Networks OCTEON processors.
+ */
+#define UART_OCTEON_USR 0x27 /* UART Status Register */
+
#endif /* _LINUX_SERIAL_REG_H */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 34/37] Adjust the dma-common.c platform hooks.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (32 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 33/37] 8250 serial driver changes for Cavium OCTEON ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-24 0:56 ` [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON ddaney
` (2 subsequent siblings)
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney
From: David Daney <ddaney@caviumnetworks.com>
With our impending patch set to add Cavium OCTEON CPU support, we
would like to adjust the platform hooks in dma-common.c.
Other than add a dev parameter to plat_unmap_dma_mem(), and hooks for
plat_dma_supported() and plat_extra_sync_for_device() which should be
nop changes for all existing targets, the only real change is to call
plat_unmap_dma_mem() from dma_free_{,non}coherent(). This is a nop
for all targets except jazz, and I expect that it is needed there.
Really if you map the memory in dma_alloc*, you should unmap it in
dma_free*.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/mach-generic/dma-coherence.h | 26 +++++++++++++++++++-
arch/mips/include/asm/mach-ip27/dma-coherence.h | 26 +++++++++++++++++++-
arch/mips/include/asm/mach-ip32/dma-coherence.h | 26 +++++++++++++++++++-
arch/mips/include/asm/mach-jazz/dma-coherence.h | 26 +++++++++++++++++++-
arch/mips/include/asm/mach-lemote/dma-coherence.h | 26 +++++++++++++++++++-
arch/mips/mm/dma-default.c | 24 ++++++++----------
6 files changed, 136 insertions(+), 18 deletions(-)
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 76e04e7..36c611b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -28,10 +28,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return dma_addr;
}
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
{
}
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s,
+ * so we can't guarantee allocations that must be
+ * within a tighter range than GFP_DMA..
+ */
+ if (mask < DMA_BIT_MASK(24))
+ return 0;
+
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return 0;
+}
+
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index ed7e622..4c21bfc 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -38,10 +38,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return dma_addr & ~(0xffUL << 56);
}
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
{
}
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s,
+ * so we can't guarantee allocations that must be
+ * within a tighter range than GFP_DMA..
+ */
+ if (mask < DMA_BIT_MASK(24))
+ return 0;
+
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return 0;
+}
+
static inline int plat_device_is_coherent(struct device *dev)
{
return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index a5511eb..7ae40f4 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -60,10 +60,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return addr;
}
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
{
}
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s,
+ * so we can't guarantee allocations that must be
+ * within a tighter range than GFP_DMA..
+ */
+ if (mask < DMA_BIT_MASK(24))
+ return 0;
+
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return 0;
+}
+
static inline int plat_device_is_coherent(struct device *dev)
{
return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index d66979a..1c7cd27 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -27,11 +27,35 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return vdma_log2phys(dma_addr);
}
-static void plat_unmap_dma_mem(dma_addr_t dma_addr)
+static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
{
vdma_free(dma_addr);
}
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s,
+ * so we can't guarantee allocations that must be
+ * within a tighter range than GFP_DMA..
+ */
+ if (mask < DMA_BIT_MASK(24))
+ return 0;
+
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return 0;
+}
+
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 7e91477..38fad7d 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -30,10 +30,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
return dma_addr & 0x7fffffff;
}
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
{
}
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s,
+ * so we can't guarantee allocations that must be
+ * within a tighter range than GFP_DMA..
+ */
+ if (mask < DMA_BIT_MASK(24))
+ return 0;
+
+ return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+ dma_addr_t dma_addr)
+{
+ return 0;
+}
+
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 5b98d0e..546e697 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -111,6 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
+ plat_unmap_dma_mem(dev, dma_handle);
free_pages((unsigned long) vaddr, get_order(size));
}
@@ -121,6 +122,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
{
unsigned long addr = (unsigned long) vaddr;
+ plat_unmap_dma_mem(dev, dma_handle);
+
if (!plat_device_is_coherent(dev))
addr = CAC_ADDR(addr);
@@ -170,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
__dma_sync(dma_addr_to_virt(dma_addr), size,
direction);
- plat_unmap_dma_mem(dma_addr);
+ plat_unmap_dma_mem(dev, dma_addr);
}
EXPORT_SYMBOL(dma_unmap_single);
@@ -226,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
dma_cache_wback_inv(addr, size);
}
- plat_unmap_dma_mem(dma_address);
+ plat_unmap_dma_mem(dev, dma_address);
}
EXPORT_SYMBOL(dma_unmap_page);
@@ -246,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
if (addr)
__dma_sync(addr, sg->length, direction);
}
- plat_unmap_dma_mem(sg->dma_address);
+ plat_unmap_dma_mem(dev, sg->dma_address);
}
}
@@ -272,6 +275,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
{
BUG_ON(direction == DMA_NONE);
+ plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev)) {
unsigned long addr;
@@ -302,6 +306,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
{
BUG_ON(direction == DMA_NONE);
+ plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev)) {
unsigned long addr;
@@ -348,22 +353,14 @@ EXPORT_SYMBOL(dma_sync_sg_for_device);
int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
- return 0;
+ return plat_dma_mapping_error(dev, dma_addr);
}
EXPORT_SYMBOL(dma_mapping_error);
int dma_supported(struct device *dev, u64 mask)
{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if (mask < DMA_BIT_MASK(24))
- return 0;
-
- return 1;
+ return plat_dma_supported(dev, mask);
}
EXPORT_SYMBOL(dma_supported);
@@ -380,6 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
{
BUG_ON(direction == DMA_NONE);
+ plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev))
__dma_sync((unsigned long)vaddr, size, direction);
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (33 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 34/37] Adjust the dma-common.c platform hooks ddaney
@ 2008-10-24 0:56 ` ddaney
2008-10-26 12:48 ` Ralf Baechle
2008-10-24 0:57 ` [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val() ddaney
2008-10-24 0:57 ` [PATCH 37/37] Add defconfig for Cavium OCTEON ddaney
36 siblings, 1 reply; 53+ messages in thread
From: ddaney @ 2008-10-24 0:56 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Always set ST0_KX on Octeon since IO addresses are at 64bit addresses.
Keep in mind this also moves the TLB handler.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/head.S | 12 ++++++++++--
arch/mips/kernel/traps.c | 7 +++++++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 492a0a8..dcd0be5 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -106,7 +106,11 @@
.endm
.macro setup_c0_status_pri
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
@@ -114,7 +118,11 @@
.endm
.macro setup_c0_status_sec
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
setup_c0_status ST0_KX ST0_BEV
#else
setup_c0_status 0 ST0_BEV
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 91c7aa2..8bed9a8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1472,6 +1472,13 @@ void __cpuinit per_cpu_trap_init(void)
#ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
+ status_set |= ST0_KX;
+#endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
status_set |= ST0_XX;
if (cpu_has_dsp)
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON.
2008-10-24 0:56 ` [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON ddaney
@ 2008-10-26 12:48 ` Ralf Baechle
2008-10-27 1:33 ` Chad Reese
0 siblings, 1 reply; 53+ messages in thread
From: Ralf Baechle @ 2008-10-26 12:48 UTC (permalink / raw)
To: ddaney; +Cc: linux-mips, Tomaso Paoletti, Paul Gortmaker
On Thu, Oct 23, 2008 at 05:56:59PM -0700, ddaney@caviumnetworks.com wrote:
> Always set ST0_KX on Octeon since IO addresses are at 64bit addresses.
> Keep in mind this also moves the TLB handler.
>
> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
> + /*
> + * Note: We always set ST0_KX on Octeon since IO addresses are at
> + * 64bit addresses. Keep in mind this also moves the TLB handler.
> + */
> setup_c0_status ST0_KX 0
That's a bit odd - on 64-bit kernels KX would be set anyway and on 32-bit
kernels would be corrupted by exceptions or interrupts, so 64-bit
addresses are not safe to use on 32-bit kernels for most part.
32-bit virtual addresses mapped to a non-compat address otoh will work fine
without KX set.
Ralf
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON.
2008-10-26 12:48 ` Ralf Baechle
@ 2008-10-27 1:33 ` Chad Reese
2008-10-26 18:51 ` Maciej W. Rozycki
2008-10-26 22:33 ` Ralf Baechle
0 siblings, 2 replies; 53+ messages in thread
From: Chad Reese @ 2008-10-27 1:33 UTC (permalink / raw)
To: Ralf Baechle; +Cc: ddaney, linux-mips, Tomaso Paoletti, Paul Gortmaker
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
>> + /*
>> + * Note: We always set ST0_KX on Octeon since IO addresses are at
>> + * 64bit addresses. Keep in mind this also moves the TLB handler.
>> + */
>> setup_c0_status ST0_KX 0
>
> That's a bit odd - on 64-bit kernels KX would be set anyway and on 32-bit
> kernels would be corrupted by exceptions or interrupts, so 64-bit
> addresses are not safe to use on 32-bit kernels for most part.
>
> 32-bit virtual addresses mapped to a non-compat address otoh will work fine
> without KX set.
>
> Ralf
The Octeon IO space regions are significantly larger than a 32bit kernel
could tlb map easily. The entire range takes 49 bits to address. As a
not particularly clean, but working alternative, we enable 64bit
addressing in the kernel and used XKPHYS to access IO. Every access was
surrounded by a local_irq_save/local_irq_restore. Since this is ugly to
the extreme, maybe we should drop being able to boot a 32bit kernel on
Octeon until something better is worked out.
Chad
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON.
2008-10-27 1:33 ` Chad Reese
@ 2008-10-26 18:51 ` Maciej W. Rozycki
2008-10-26 22:33 ` Ralf Baechle
1 sibling, 0 replies; 53+ messages in thread
From: Maciej W. Rozycki @ 2008-10-26 18:51 UTC (permalink / raw)
To: Chad Reese
Cc: Ralf Baechle, ddaney, linux-mips, Tomaso Paoletti, Paul Gortmaker
On Sun, 26 Oct 2008, Chad Reese wrote:
> The Octeon IO space regions are significantly larger than a 32bit kernel
> could tlb map easily. The entire range takes 49 bits to address. As a
Do you need them all at once? If not, you may be able to get away with
ioremap() called on demand.
> not particularly clean, but working alternative, we enable 64bit
> addressing in the kernel and used XKPHYS to access IO. Every access was
> surrounded by a local_irq_save/local_irq_restore. Since this is ugly to
> the extreme, maybe we should drop being able to boot a 32bit kernel on
> Octeon until something better is worked out.
Good idea anyway I would say. With 64-bit processors support for a
32-bit kernel may be a nice feature, but really only if it works straight
away with no strange hacks. Otherwise a 64-bit kernel is the obvious
choice providing a superset of the functionality, including but not
limited to support for the same plain 32-bit (o32) userland if need be.
And with the GCC/GAS changes to support -msym32 that happened a while ago
the overhead from using a 64-bit kernel has become quite negligible.
Maciej
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON.
2008-10-27 1:33 ` Chad Reese
2008-10-26 18:51 ` Maciej W. Rozycki
@ 2008-10-26 22:33 ` Ralf Baechle
1 sibling, 0 replies; 53+ messages in thread
From: Ralf Baechle @ 2008-10-26 22:33 UTC (permalink / raw)
To: Chad Reese; +Cc: ddaney, linux-mips, Tomaso Paoletti, Paul Gortmaker
On Sun, Oct 26, 2008 at 06:33:44PM -0700, Chad Reese wrote:
> >> -#ifdef CONFIG_64BIT
> >> +#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
> >> + /*
> >> + * Note: We always set ST0_KX on Octeon since IO addresses are at
> >> + * 64bit addresses. Keep in mind this also moves the TLB handler.
> >> + */
> >> setup_c0_status ST0_KX 0
> >
> > That's a bit odd - on 64-bit kernels KX would be set anyway and on 32-bit
> > kernels would be corrupted by exceptions or interrupts, so 64-bit
> > addresses are not safe to use on 32-bit kernels for most part.
> >
> > 32-bit virtual addresses mapped to a non-compat address otoh will work fine
> > without KX set.
> >
> > Ralf
>
> The Octeon IO space regions are significantly larger than a 32bit kernel
> could tlb map easily. The entire range takes 49 bits to address. As a
> not particularly clean, but working alternative, we enable 64bit
> addressing in the kernel and used XKPHYS to access IO. Every access was
> surrounded by a local_irq_save/local_irq_restore. Since this is ugly to
> the extreme, maybe we should drop being able to boot a 32bit kernel on
> Octeon until something better is worked out.
That address space may be huge but for any given application you're
probably only ever going to access a tiny fraction of it - in particular
one where the kernel model of choice is a 32-bit kernel.
If these assumptions don't hold for the Cavium, then I ditching 32-bit
kernels is the obvious choice. We've given up on 32-bit kernels for the
SGI O2 for example - it was just too ugly, too painful. For very small
configurations of SGI Origins it would have been possible similarly for
small Broadcom Sibyte configs - but in practice these days we use 64-bit
kernels. 32-bit is just so yesterday and the 64-bit Linux/MIPS kernels
are now nearly a decade old.
Ralf
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val().
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (34 preceding siblings ...)
2008-10-24 0:56 ` [PATCH 35/37] Set c0 status for ST0_KX on Cavium OCTEON ddaney
@ 2008-10-24 0:57 ` ddaney
2008-10-24 13:00 ` Paul Gortmaker
2008-10-24 15:12 ` Sergei Shtylyov
2008-10-24 0:57 ` [PATCH 37/37] Add defconfig for Cavium OCTEON ddaney
36 siblings, 2 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:57 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Paul Gortmaker
From: David Daney <ddaney@caviumnetworks.com>
Before marking pmd_val as invalid_pte_table, factor in existing value
for pmd_val.
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/pgtable-64.h | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 943515f..bb93bd5 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -129,7 +129,12 @@ extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
*/
static inline int pmd_none(pmd_t pmd)
{
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ return (pmd_val(pmd) == (unsigned long) invalid_pte_table) ||
+ (!pmd_val(pmd));
+#else
return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+#endif
}
#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val().
2008-10-24 0:57 ` [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val() ddaney
@ 2008-10-24 13:00 ` Paul Gortmaker
2008-10-24 15:55 ` David Daney
2008-10-24 15:12 ` Sergei Shtylyov
1 sibling, 1 reply; 53+ messages in thread
From: Paul Gortmaker @ 2008-10-24 13:00 UTC (permalink / raw)
To: ddaney; +Cc: linux-mips
ddaney@caviumnetworks.com wrote:
> From: David Daney <ddaney@caviumnetworks.com>
>
> Before marking pmd_val as invalid_pte_table, factor in existing value
> for pmd_val.
>
> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/include/asm/pgtable-64.h | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
>
Hi David,
I think you missed my feedback on this patch -- you should be the primary
S.O.B. on this, and at a minimum, it needs a better description of just why
this is required (if it actually is) on Cavium CPUs, but not on other
boards.
Thanks,
Paul.
> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
> index 943515f..bb93bd5 100644
> --- a/arch/mips/include/asm/pgtable-64.h
> +++ b/arch/mips/include/asm/pgtable-64.h
> @@ -129,7 +129,12 @@ extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
> */
> static inline int pmd_none(pmd_t pmd)
> {
> +#ifdef CONFIG_CPU_CAVIUM_OCTEON
> + return (pmd_val(pmd) == (unsigned long) invalid_pte_table) ||
> + (!pmd_val(pmd));
> +#else
> return pmd_val(pmd) == (unsigned long) invalid_pte_table;
> +#endif
> }
>
> #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
>
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val().
2008-10-24 13:00 ` Paul Gortmaker
@ 2008-10-24 15:55 ` David Daney
0 siblings, 0 replies; 53+ messages in thread
From: David Daney @ 2008-10-24 15:55 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linux-mips
Paul Gortmaker wrote:
> ddaney@caviumnetworks.com wrote:
>> From: David Daney <ddaney@caviumnetworks.com>
>>
>> Before marking pmd_val as invalid_pte_table, factor in existing value
>> for pmd_val.
>>
>> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
>> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
>> ---
>> arch/mips/include/asm/pgtable-64.h | 5 +++++
>> 1 files changed, 5 insertions(+), 0 deletions(-)
>>
>
> Hi David,
>
> I think you missed my feedback on this patch -- you should be the primary
> S.O.B. on this, and at a minimum, it needs a better description of just
> why
> this is required (if it actually is) on Cavium CPUs, but not on other
> boards.
>
Indeed, it was a screw-up on my part. I hope to be able to remove this
entire patch in the near future.
David Daney
> Thanks,
> Paul.
>
>> diff --git a/arch/mips/include/asm/pgtable-64.h
>> b/arch/mips/include/asm/pgtable-64.h
>> index 943515f..bb93bd5 100644
>> --- a/arch/mips/include/asm/pgtable-64.h
>> +++ b/arch/mips/include/asm/pgtable-64.h
>> @@ -129,7 +129,12 @@ extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
>> */
>> static inline int pmd_none(pmd_t pmd)
>> {
>> +#ifdef CONFIG_CPU_CAVIUM_OCTEON
>> + return (pmd_val(pmd) == (unsigned long) invalid_pte_table) ||
>> + (!pmd_val(pmd));
>> +#else
>> return pmd_val(pmd) == (unsigned long) invalid_pte_table;
>> +#endif
>> }
>>
>> #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
>>
>
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val().
2008-10-24 0:57 ` [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val() ddaney
2008-10-24 13:00 ` Paul Gortmaker
@ 2008-10-24 15:12 ` Sergei Shtylyov
1 sibling, 0 replies; 53+ messages in thread
From: Sergei Shtylyov @ 2008-10-24 15:12 UTC (permalink / raw)
To: ddaney; +Cc: linux-mips, Paul Gortmaker
Hello.
ddaney@caviumnetworks.com wrote:
> Before marking pmd_val as invalid_pte_table, factor in existing value
> for pmd_val.
I didn't get it -- this function doesn't mark anything.
> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
> index 943515f..bb93bd5 100644
> --- a/arch/mips/include/asm/pgtable-64.h
> +++ b/arch/mips/include/asm/pgtable-64.h
> @@ -129,7 +129,12 @@ extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
> */
> static inline int pmd_none(pmd_t pmd)
> {
> +#ifdef CONFIG_CPU_CAVIUM_OCTEON
> + return (pmd_val(pmd) == (unsigned long) invalid_pte_table) ||
> + (!pmd_val(pmd));
Unneeded parens around !pmd_val(pmd) -- ! operator is higher priority than
any of && and ||.
WBR, Sergei
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 37/37] Add defconfig for Cavium OCTEON.
2008-10-24 0:56 [PATCH 00/37] Add Cavium OCTEON processor support ddaney
` (35 preceding siblings ...)
2008-10-24 0:57 ` [PATCH 36/37] Cavium OCTEON: pmd_none - use pmd_val() in pmd_val() ddaney
@ 2008-10-24 0:57 ` ddaney
36 siblings, 0 replies; 53+ messages in thread
From: ddaney @ 2008-10-24 0:57 UTC (permalink / raw)
To: linux-mips; +Cc: David Daney, Tomaso Paoletti
From: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
---
arch/mips/configs/cavium-octeon_defconfig | 1153 +++++++++++++++++++++++++++++
1 files changed, 1153 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/configs/cavium-octeon_defconfig
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
new file mode 100644
index 0000000..bd758f3
--- /dev/null
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -0,0 +1,1153 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27
+# Thu Oct 23 08:58:51 2008
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+CONFIG_ZONE_DMA=y
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
+CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
+# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
+CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
+CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
+CONFIG_CAVIUM_OCTEON_LOCK_L2=y
+CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
+CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
+CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
+CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
+CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_COHERENT=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_CPU_BIG_ENDIAN=y
+# CONFIG_CPU_LITTLE_ENDIAN is not set
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_CPU_OCTEON=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=7
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_CAVIUM_OCTEON=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+
+#
+# Kernel type
+#
+# CONFIG_32BIT is not set
+CONFIG_64BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS_DEFAULT_16=y
+CONFIG_NR_CPUS=16
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PROBE_INITRD_HEADER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ISA=y
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_BINFMT_ELF32=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+CONFIG_NET_PCI=y
+# CONFIG_AC3200 is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=m
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_CMDLINE=""
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--
1.5.5.1
^ permalink raw reply related [flat|nested] 53+ messages in thread