* [U-Boot] [PATCH 01/42] Blackfin: update lockbox api according to latest documentation
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 02/42] Blackfin: safely flush data caches when in writeback mode Mike Frysinger
` (40 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/asm-blackfin/mach-common/bits/lockbox.h | 70 +++++++++++-----------
1 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/include/asm-blackfin/mach-common/bits/lockbox.h b/include/asm-blackfin/mach-common/bits/lockbox.h
index 8b696f3..77f849e 100644
--- a/include/asm-blackfin/mach-common/bits/lockbox.h
+++ b/include/asm-blackfin/mach-common/bits/lockbox.h
@@ -11,52 +11,52 @@
/* SESR argument structure. Expected to reside at 0xFF900018. */
typedef struct SESR_args {
- unsigned short usFlags; /* security firmware flags */
- unsigned short usIRQMask; /* interrupt mask */
- unsigned long ulMessageSize; /* message length in bytes */
- unsigned long ulSFEntryPoint; /* entry point of secure function */
- unsigned long ulMessagePtr; /* pointer to the buffer containing */
- /* the digital signature and message */
- unsigned long ulReserved1; /* reserved */
- unsigned long ulReserved2; /* reserved */
+ unsigned short usFlags; /* security firmware flags */
+ unsigned short usIRQMask; /* interrupt mask */
+ unsigned long ulMessageSize; /* message length in bytes */
+ unsigned long ulSFEntryPoint; /* entry point of secure function */
+ unsigned long ulMessagePtr; /* pointer to the buffer containing
+ the digital signature and message */
+ unsigned long ulReserved1; /* reserved */
+ unsigned long ulReserved2; /* reserved */
} tSESR_args;
/* Secure Entry Service Routine */
-void (* const sesr)(void) = (void *)_BOOTROM_SESR;
+static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
#endif
-/* SESR flags argument bitfields */
-#define SESR_FLAGS_STAY_AT_NMI 0x0000
-#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
-#define SESR_FLAGS_NO_SF_DMA 0x0000
-#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
-#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
-#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
+/* SESR flags argument bitfields */
+#define SESR_FLAGS_STAY_AT_NMI 0x0000
+#define SESR_FLAGS_DROP_BELOW_NMI 0x0001
+#define SESR_FLAGS_NO_SF_DMA 0x0000
+#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002
+#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000
+#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100
/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL 0x00000001 /* Emulation Disable */
-#define RSTDABL 0x00000002 /* Reset Disable */
-#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
-#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
-#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
-#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x00004000 /* Emulation Override */
-#define OTPSEN 0x00008000 /* OTP Secrets Enable */
-#define L2DABL 0x00070000 /* L2 Memory Disable */
+#define EMUDABL 0x00000001 /* Emulation Disable */
+#define RSTDABL 0x00000002 /* Reset Disable */
+#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */
+#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */
+#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */
+#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */
+#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */
+#define EMUOVR 0x00004000 /* Emulation Override */
+#define OTPSEN 0x00008000 /* OTP Secrets Enable */
+#define L2DABL 0x00070000 /* L2 Memory Disable */
/* Bit masks for SECURE_CONTROL */
-#define SECURE0 0x0001 /* SECURE 0 */
-#define SECURE1 0x0002 /* SECURE 1 */
-#define SECURE2 0x0004 /* SECURE 2 */
-#define SECURE3 0x0008 /* SECURE 3 */
+#define SECURE0 0x0001 /* SECURE 0 */
+#define SECURE1 0x0002 /* SECURE 1 */
+#define SECURE2 0x0004 /* SECURE 2 */
+#define SECURE3 0x0008 /* SECURE 3 */
/* Bit masks for SECURE_STATUS */
-#define SECMODE 0x0003 /* Secured Mode Control State */
-#define NMI 0x0004 /* Non Maskable Interrupt */
-#define AFVALID 0x0008 /* Authentication Firmware Valid */
-#define AFEXIT 0x0010 /* Authentication Firmware Exit */
-#define SECSTAT 0x00e0 /* Secure Status */
+#define SECMODE 0x0003 /* Secured Mode Control State */
+#define NMI 0x0004 /* Non Maskable Interrupt */
+#define AFVALID 0x0008 /* Authentication Firmware Valid */
+#define AFEXIT 0x0010 /* Authentication Firmware Exit */
+#define SECSTAT 0x00e0 /* Secure Status */
#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 02/42] Blackfin: safely flush data caches when in writeback mode
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 01/42] Blackfin: update lockbox api according to latest documentation Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 03/42] Blackfin: add cache_dump commands Mike Frysinger
` (39 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
lib_blackfin/cache.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index 1557864..0a321a4 100644
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -36,6 +36,44 @@ void flush_cache(unsigned long addr, unsigned long size)
blackfin_dcache_flush_range(start_addr, end_addr);
}
+#ifdef CONFIG_DCACHE_WB
+static void flushinv_all_dcache(void)
+{
+ u32 way, bank, subbank, set;
+ u32 status, addr;
+ u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+ for (bank = 0; bank < 2; ++bank) {
+ if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+ continue;
+
+ for (way = 0; way < 2; ++way)
+ for (subbank = 0; subbank < 4; ++subbank)
+ for (set = 0; set < 64; ++set) {
+
+ bfin_write_DTEST_COMMAND(
+ way << 26 |
+ bank << 23 |
+ subbank << 16 |
+ set << 5
+ );
+ CSYNC();
+ status = bfin_read_DTEST_DATA0();
+
+ /* only worry about valid/dirty entries */
+ if ((status & 0x3) != 0x3)
+ continue;
+
+ /* construct the address using the tag */
+ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+ /* flush it */
+ __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
+ }
+ }
+}
+#endif
+
void icache_enable(void)
{
bfin_write_IMEM_CONTROL(IMC | ENICPLB);
@@ -61,6 +99,10 @@ void dcache_enable(void)
void dcache_disable(void)
{
+#ifdef CONFIG_DCACHE_WB
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
+ flushinv_all_dcache();
+#endif
bfin_write_DMEM_CONTROL(0);
SSYNC();
}
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 03/42] Blackfin: add cache_dump commands
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 01/42] Blackfin: update lockbox api according to latest documentation Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 02/42] Blackfin: safely flush data caches when in writeback mode Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 04/42] Blackfin: print out Flash: before checking it Mike Frysinger
` (38 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
A few debug-type commands used to dump the raw icache/dcache data. Useful
when trying to track down cache-related bugs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
lib_blackfin/Makefile | 1 +
lib_blackfin/cmd_cache_dump.c | 145 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 146 insertions(+), 0 deletions(-)
create mode 100644 lib_blackfin/cmd_cache_dump.c
diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile
index 46ef7f3..cbf47f0 100644
--- a/lib_blackfin/Makefile
+++ b/lib_blackfin/Makefile
@@ -40,6 +40,7 @@ COBJS-y += board.o
COBJS-y += boot.o
COBJS-y += cache.o
COBJS-y += clocks.o
+COBJS-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
COBJS-y += muldi3.o
COBJS-$(CONFIG_POST) += post.o tests.o
COBJS-y += string.o
diff --git a/lib_blackfin/cmd_cache_dump.c b/lib_blackfin/cmd_cache_dump.c
new file mode 100644
index 0000000..80446ed
--- /dev/null
+++ b/lib_blackfin/cmd_cache_dump.c
@@ -0,0 +1,145 @@
+/*
+ * U-boot - cmd_cache_dump.c
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
+
+static int check_limit(const char *type, size_t start_limit, size_t end_limit, size_t start, size_t end)
+{
+ if (start >= start_limit && start <= end_limit && \
+ end <= end_limit && end >= start_limit && \
+ start <= end)
+ return 0;
+
+ printf("%s limit violation: %i <= (user:%i) <= (user:%i) <= %i\n",
+ type, start_limit, start, end, end_limit);
+ return 1;
+}
+
+int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int cache_status = icache_status();
+
+ if (cache_status)
+ icache_disable();
+
+ uint32_t cmd_base, tag, cache_upper, cache_lower;
+
+ size_t way, way_start = 0, way_end = 3;
+ size_t sbnk, sbnk_start = 0, sbnk_end = 3;
+ size_t set, set_start = 0, set_end = 31;
+ size_t dw;
+
+ if (argc > 1) {
+ way_start = way_end = simple_strtoul(argv[1], NULL, 10);
+ if (argc > 2) {
+ sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
+ if (argc > 3)
+ set_start = set_end = simple_strtoul(argv[3], NULL, 10);
+ }
+ }
+
+ if (check_limit("way", 0, 3, way_start, way_end) || \
+ check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
+ check_limit("set", 0, 31, set_start, set_end))
+ return 1;
+
+ puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
+
+ for (way = way_start; way <= way_end; ++way) {
+ for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
+ for (set = set_start; set <= set_end; ++set) {
+ printf("%i:%i:%2i: ", way, sbnk, set);
+ for (dw = 0; dw < 4; ++dw) {
+ if (ctrlc())
+ return 1;
+
+ cmd_base = \
+ (way << 26) | \
+ (sbnk << 16) | \
+ (set << 5) | \
+ (dw << 3);
+
+ /* first read the tag */
+ bfin_write_ITEST_COMMAND(cmd_base | 0x0);
+ SSYNC();
+ tag = bfin_read_ITEST_DATA0();
+ printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
+
+ /* grab the data@this loc */
+ bfin_write_ITEST_COMMAND(cmd_base | 0x4);
+ SSYNC();
+ cache_lower = bfin_read_ITEST_DATA0();
+ cache_upper = bfin_read_ITEST_DATA1();
+ printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
+ }
+ puts("\n");
+ }
+ }
+ }
+
+ if (cache_status)
+ icache_enable();
+
+ return 0;
+}
+
+U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
+ "icache_dump - dump current instruction cache\n",
+ "[way] [subbank] [set]");
+
+int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 way, bank, subbank, set;
+ u32 status, addr;
+ u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+ for (bank = 0; bank < 2; ++bank) {
+ if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+ continue;
+
+ for (way = 0; way < 2; ++way)
+ for (subbank = 0; subbank < 4; ++subbank) {
+ printf("%i:%i:%i:\t", bank, way, subbank);
+ for (set = 0; set < 64; ++set) {
+
+ if (ctrlc())
+ return 1;
+
+ /* retrieve a cache tag */
+ bfin_write_DTEST_COMMAND(
+ way << 26 |
+ bank << 23 |
+ subbank << 16 |
+ set << 5
+ );
+ CSYNC();
+ status = bfin_read_DTEST_DATA0();
+
+ /* construct the address using the tag */
+ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+ /* show it */
+ if (set && !(set % 4))
+ puts("\n\t");
+ printf("%c%08x%c%08x%c ", (status & 0x1 ? '[' : '{'), status, (status & 0x2 ? 'd' : ' '), addr, (status & 0x1 ? ']' : '}'));
+ }
+ puts("\n");
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(dcache_dump, 4, 0, do_dcache_dump,
+ "dcache_dump - dump current data cache\n",
+ "[bank] [way] [subbank] [set]");
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 04/42] Blackfin: print out Flash: before checking it
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (2 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 03/42] Blackfin: add cache_dump commands Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 05/42] Blackfin: drop now-unused CONFIG_SYS_BFIN_CMD_XXX Mike Frysinger
` (37 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
If there is some problem in the flash init/checking code, it's nicer to see
the message "Flash:" before crashing. This way the source of the problem
is a bit more straightforward.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
lib_blackfin/board.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index c223711..b3452f8 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -312,8 +312,8 @@ void board_init_r(gd_t * id, ulong dest_addr)
#if !defined(CONFIG_SYS_NO_FLASH)
/* Initialize the flash and protect u-boot by default */
extern flash_info_t flash_info[];
- ulong size = flash_init();
puts("Flash: ");
+ ulong size = flash_init();
print_size(size, "\n");
flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1,
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 05/42] Blackfin: drop now-unused CONFIG_SYS_BFIN_CMD_XXX
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (3 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 04/42] Blackfin: print out Flash: before checking it Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 06/42] Blackfin: unify duplicate CPU port definitions Mike Frysinger
` (36 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
With the new CONFIG_XXX system and CONFIG_CMD_XXX handling, these defines
are no longer used/needed.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/asm-blackfin/blackfin-config-pre.h | 6 ------
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h
index 9df01ad..e973de7 100644
--- a/include/asm-blackfin/blackfin-config-pre.h
+++ b/include/asm-blackfin/blackfin-config-pre.h
@@ -14,12 +14,6 @@
#define MK_STR(x) XMK_STR(x)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-/* Configurable Blackfin-specific monitor commands */
-#define CONFIG_SYS_BFIN_CMD_BOOTLDR 0x01
-#define CONFIG_SYS_BFIN_CMD_CPLBINFO 0x02
-#define CONFIG_SYS_BFIN_CMD_OTP 0x04
-#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08
-
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
* Depending on your cpu, some of these may not be valid, check your HRM.
* The actual values here are meaningless as long as they're unique.
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 06/42] Blackfin: unify duplicate CPU port definitions
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (4 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 05/42] Blackfin: drop now-unused CONFIG_SYS_BFIN_CMD_XXX Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 07/42] Blackfin: drop SPORT_TX read helper macros Mike Frysinger
` (35 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/asm-blackfin/mach-bf527/ports.h | 75 +---------
include/asm-blackfin/mach-bf533/ports.h | 18 +--
include/asm-blackfin/mach-bf537/ports.h | 56 +-------
include/asm-blackfin/mach-bf548/ports.h | 189 ++---------------------
include/asm-blackfin/mach-bf561/def_local.h | 2 +
include/asm-blackfin/mach-bf561/ports.h | 44 ++++++
include/asm-blackfin/mach-common/bits/ports-a.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-b.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-c.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-d.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-e.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-f.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-g.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-h.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-i.h | 25 +++
include/asm-blackfin/mach-common/bits/ports-j.h | 25 +++
16 files changed, 314 insertions(+), 320 deletions(-)
create mode 100644 include/asm-blackfin/mach-bf561/ports.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-a.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-b.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-c.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-d.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-e.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-f.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-g.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-h.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-i.h
create mode 100644 include/asm-blackfin/mach-common/bits/ports-j.h
diff --git a/include/asm-blackfin/mach-bf527/ports.h b/include/asm-blackfin/mach-bf527/ports.h
index c32d69f..e6b1df8 100644
--- a/include/asm-blackfin/mach-bf527/ports.h
+++ b/include/asm-blackfin/mach-bf527/ports.h
@@ -52,76 +52,9 @@
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
-
-/* Port J Masks */
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-#define PJ14 0x4000
-#define PJ15 0x8000
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-j.h"
#endif
diff --git a/include/asm-blackfin/mach-bf533/ports.h b/include/asm-blackfin/mach-bf533/ports.h
index 79bc54d..512d6df 100644
--- a/include/asm-blackfin/mach-bf533/ports.h
+++ b/include/asm-blackfin/mach-bf533/ports.h
@@ -5,22 +5,6 @@
#ifndef __BFIN_PERIPHERAL_PORT__
#define __BFIN_PERIPHERAL_PORT__
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
+#include "../mach-common/bits/ports-f.h"
#endif
diff --git a/include/asm-blackfin/mach-bf537/ports.h b/include/asm-blackfin/mach-bf537/ports.h
index cc28ba3..2f62934 100644
--- a/include/asm-blackfin/mach-bf537/ports.h
+++ b/include/asm-blackfin/mach-bf537/ports.h
@@ -21,58 +21,8 @@
#define PGRE 0x0400
#define PGTE 0x0800
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
#endif
diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h
index 5f0e45e..50054f3 100644
--- a/include/asm-blackfin/mach-bf548/ports.h
+++ b/include/asm-blackfin/mach-bf548/ports.h
@@ -92,184 +92,15 @@
#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
-/* Port A Masks */
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* Port B Masks */
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-#define PB15 0x8000
-
-/* Port C Masks */
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-#define PC14 0x4000
-#define PC15 0x8000
-
-/* Port F Masks */
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* Port F Masks */
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* Port F Masks */
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* Port G Masks */
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* Port H Masks */
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-#define PH14 0x4000
-#define PH15 0x8000
-
-/* Port I Masks */
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* Port I Masks */
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-#define PJ14 0x4000
-#define PJ15 0x8000
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-i.h"
+#include "../mach-common/bits/ports-j.h"
#endif
diff --git a/include/asm-blackfin/mach-bf561/def_local.h b/include/asm-blackfin/mach-bf561/def_local.h
index 3ddd689..597dcec 100644
--- a/include/asm-blackfin/mach-bf561/def_local.h
+++ b/include/asm-blackfin/mach-bf561/def_local.h
@@ -8,3 +8,5 @@
#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
+
+#include "ports.h"
diff --git a/include/asm-blackfin/mach-bf561/ports.h b/include/asm-blackfin/mach-bf561/ports.h
new file mode 100644
index 0000000..194d4a3
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/ports.h
@@ -0,0 +1,44 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-f.h"
+
+/* The non-standard PF16+ */
+#define PF16 (1 << 0)
+#define PF17 (1 << 1)
+#define PF18 (1 << 2)
+#define PF19 (1 << 3)
+#define PF20 (1 << 4)
+#define PF21 (1 << 5)
+#define PF22 (1 << 6)
+#define PF23 (1 << 7)
+#define PF24 (1 << 8)
+#define PF25 (1 << 9)
+#define PF26 (1 << 10)
+#define PF27 (1 << 11)
+#define PF28 (1 << 12)
+#define PF29 (1 << 13)
+#define PF30 (1 << 14)
+#define PF31 (1 << 15)
+#define PF32 (1 << 0)
+#define PF33 (1 << 1)
+#define PF34 (1 << 2)
+#define PF35 (1 << 3)
+#define PF36 (1 << 4)
+#define PF37 (1 << 5)
+#define PF38 (1 << 6)
+#define PF39 (1 << 7)
+#define PF40 (1 << 8)
+#define PF41 (1 << 9)
+#define PF42 (1 << 10)
+#define PF43 (1 << 11)
+#define PF44 (1 << 12)
+#define PF45 (1 << 13)
+#define PF46 (1 << 14)
+#define PF47 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-a.h b/include/asm-blackfin/mach-common/bits/ports-a.h
new file mode 100644
index 0000000..9f78a76
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-a.h
@@ -0,0 +1,25 @@
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0 (1 << 0)
+#define PA1 (1 << 1)
+#define PA2 (1 << 2)
+#define PA3 (1 << 3)
+#define PA4 (1 << 4)
+#define PA5 (1 << 5)
+#define PA6 (1 << 6)
+#define PA7 (1 << 7)
+#define PA8 (1 << 8)
+#define PA9 (1 << 9)
+#define PA10 (1 << 10)
+#define PA11 (1 << 11)
+#define PA12 (1 << 12)
+#define PA13 (1 << 13)
+#define PA14 (1 << 14)
+#define PA15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-b.h b/include/asm-blackfin/mach-common/bits/ports-b.h
new file mode 100644
index 0000000..b81702f
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-b.h
@@ -0,0 +1,25 @@
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0 (1 << 0)
+#define PB1 (1 << 1)
+#define PB2 (1 << 2)
+#define PB3 (1 << 3)
+#define PB4 (1 << 4)
+#define PB5 (1 << 5)
+#define PB6 (1 << 6)
+#define PB7 (1 << 7)
+#define PB8 (1 << 8)
+#define PB9 (1 << 9)
+#define PB10 (1 << 10)
+#define PB11 (1 << 11)
+#define PB12 (1 << 12)
+#define PB13 (1 << 13)
+#define PB14 (1 << 14)
+#define PB15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-c.h b/include/asm-blackfin/mach-common/bits/ports-c.h
new file mode 100644
index 0000000..3cc665e
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-c.h
@@ -0,0 +1,25 @@
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0 (1 << 0)
+#define PC1 (1 << 1)
+#define PC2 (1 << 2)
+#define PC3 (1 << 3)
+#define PC4 (1 << 4)
+#define PC5 (1 << 5)
+#define PC6 (1 << 6)
+#define PC7 (1 << 7)
+#define PC8 (1 << 8)
+#define PC9 (1 << 9)
+#define PC10 (1 << 10)
+#define PC11 (1 << 11)
+#define PC12 (1 << 12)
+#define PC13 (1 << 13)
+#define PC14 (1 << 14)
+#define PC15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-d.h b/include/asm-blackfin/mach-common/bits/ports-d.h
new file mode 100644
index 0000000..868c6a0
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-d.h
@@ -0,0 +1,25 @@
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0 (1 << 0)
+#define PD1 (1 << 1)
+#define PD2 (1 << 2)
+#define PD3 (1 << 3)
+#define PD4 (1 << 4)
+#define PD5 (1 << 5)
+#define PD6 (1 << 6)
+#define PD7 (1 << 7)
+#define PD8 (1 << 8)
+#define PD9 (1 << 9)
+#define PD10 (1 << 10)
+#define PD11 (1 << 11)
+#define PD12 (1 << 12)
+#define PD13 (1 << 13)
+#define PD14 (1 << 14)
+#define PD15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-e.h b/include/asm-blackfin/mach-common/bits/ports-e.h
new file mode 100644
index 0000000..c88b0d0
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-e.h
@@ -0,0 +1,25 @@
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0 (1 << 0)
+#define PE1 (1 << 1)
+#define PE2 (1 << 2)
+#define PE3 (1 << 3)
+#define PE4 (1 << 4)
+#define PE5 (1 << 5)
+#define PE6 (1 << 6)
+#define PE7 (1 << 7)
+#define PE8 (1 << 8)
+#define PE9 (1 << 9)
+#define PE10 (1 << 10)
+#define PE11 (1 << 11)
+#define PE12 (1 << 12)
+#define PE13 (1 << 13)
+#define PE14 (1 << 14)
+#define PE15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-f.h b/include/asm-blackfin/mach-common/bits/ports-f.h
new file mode 100644
index 0000000..d6af206
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-f.h
@@ -0,0 +1,25 @@
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0 (1 << 0)
+#define PF1 (1 << 1)
+#define PF2 (1 << 2)
+#define PF3 (1 << 3)
+#define PF4 (1 << 4)
+#define PF5 (1 << 5)
+#define PF6 (1 << 6)
+#define PF7 (1 << 7)
+#define PF8 (1 << 8)
+#define PF9 (1 << 9)
+#define PF10 (1 << 10)
+#define PF11 (1 << 11)
+#define PF12 (1 << 12)
+#define PF13 (1 << 13)
+#define PF14 (1 << 14)
+#define PF15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-g.h b/include/asm-blackfin/mach-common/bits/ports-g.h
new file mode 100644
index 0000000..09355d3
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-g.h
@@ -0,0 +1,25 @@
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0 (1 << 0)
+#define PG1 (1 << 1)
+#define PG2 (1 << 2)
+#define PG3 (1 << 3)
+#define PG4 (1 << 4)
+#define PG5 (1 << 5)
+#define PG6 (1 << 6)
+#define PG7 (1 << 7)
+#define PG8 (1 << 8)
+#define PG9 (1 << 9)
+#define PG10 (1 << 10)
+#define PG11 (1 << 11)
+#define PG12 (1 << 12)
+#define PG13 (1 << 13)
+#define PG14 (1 << 14)
+#define PG15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-h.h b/include/asm-blackfin/mach-common/bits/ports-h.h
new file mode 100644
index 0000000..fa3910c
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-h.h
@@ -0,0 +1,25 @@
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0 (1 << 0)
+#define PH1 (1 << 1)
+#define PH2 (1 << 2)
+#define PH3 (1 << 3)
+#define PH4 (1 << 4)
+#define PH5 (1 << 5)
+#define PH6 (1 << 6)
+#define PH7 (1 << 7)
+#define PH8 (1 << 8)
+#define PH9 (1 << 9)
+#define PH10 (1 << 10)
+#define PH11 (1 << 11)
+#define PH12 (1 << 12)
+#define PH13 (1 << 13)
+#define PH14 (1 << 14)
+#define PH15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-i.h b/include/asm-blackfin/mach-common/bits/ports-i.h
new file mode 100644
index 0000000..f176f08
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-i.h
@@ -0,0 +1,25 @@
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0 (1 << 0)
+#define PI1 (1 << 1)
+#define PI2 (1 << 2)
+#define PI3 (1 << 3)
+#define PI4 (1 << 4)
+#define PI5 (1 << 5)
+#define PI6 (1 << 6)
+#define PI7 (1 << 7)
+#define PI8 (1 << 8)
+#define PI9 (1 << 9)
+#define PI10 (1 << 10)
+#define PI11 (1 << 11)
+#define PI12 (1 << 12)
+#define PI13 (1 << 13)
+#define PI14 (1 << 14)
+#define PI15 (1 << 15)
+
+#endif
diff --git a/include/asm-blackfin/mach-common/bits/ports-j.h b/include/asm-blackfin/mach-common/bits/ports-j.h
new file mode 100644
index 0000000..924123e
--- /dev/null
+++ b/include/asm-blackfin/mach-common/bits/ports-j.h
@@ -0,0 +1,25 @@
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0 (1 << 0)
+#define PJ1 (1 << 1)
+#define PJ2 (1 << 2)
+#define PJ3 (1 << 3)
+#define PJ4 (1 << 4)
+#define PJ5 (1 << 5)
+#define PJ6 (1 << 6)
+#define PJ7 (1 << 7)
+#define PJ8 (1 << 8)
+#define PJ9 (1 << 9)
+#define PJ10 (1 << 10)
+#define PJ11 (1 << 11)
+#define PJ12 (1 << 12)
+#define PJ13 (1 << 13)
+#define PJ14 (1 << 14)
+#define PJ15 (1 << 15)
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 07/42] Blackfin: drop SPORT_TX read helper macros
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (5 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 06/42] Blackfin: unify duplicate CPU port definitions Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 08/42] Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bits Mike Frysinger
` (34 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
The SPORT_TX registers cannot be read (the hardware will trigger an error),
so drop the read helper macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
.../mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 2 --
.../mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 2 --
.../mach-bf548/ADSP-EDN-BF542-extended_cdef.h | 3 ---
.../mach-bf548/ADSP-EDN-BF544-extended_cdef.h | 3 ---
.../mach-bf548/ADSP-EDN-BF547-extended_cdef.h | 4 ----
.../mach-bf548/ADSP-EDN-BF548-extended_cdef.h | 4 ----
.../mach-bf548/ADSP-EDN-BF549-extended_cdef.h | 4 ----
.../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h | 2 --
.../mach-common/ADSP-EDN-extended_cdef.h | 2 --
9 files changed, 0 insertions(+), 26 deletions(-)
diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
index 85acdd6..dec7c63 100644
--- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -304,7 +304,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
@@ -370,7 +369,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
index b9e4d67..58df301 100644
--- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
@@ -304,7 +304,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
@@ -370,7 +369,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
index e9572a0..51d9cf2 100644
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
@@ -3577,7 +3577,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
@@ -3643,7 +3642,6 @@
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
@@ -3709,7 +3707,6 @@
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
index 968cd3e..4c0fdf5 100644
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
@@ -4678,7 +4678,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
@@ -4744,7 +4743,6 @@
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
@@ -4810,7 +4808,6 @@
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
index bd40f35..e0f76ae 100644
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
@@ -2713,7 +2713,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
@@ -2779,7 +2778,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
@@ -2845,7 +2843,6 @@
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
@@ -2911,7 +2908,6 @@
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
index 77cd5dc..caf2f6f 100644
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
@@ -4885,7 +4885,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
@@ -4951,7 +4950,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
@@ -5017,7 +5015,6 @@
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
@@ -5083,7 +5080,6 @@
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
index c5d3511..af90e4c 100644
--- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
@@ -5233,7 +5233,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
@@ -5299,7 +5298,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
@@ -5365,7 +5363,6 @@
#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
@@ -5431,7 +5428,6 @@
#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
index c0c7e1e..43f3850 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
@@ -1798,7 +1798,6 @@
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
@@ -1861,7 +1860,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX)
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
index 4c439e5..4a3f34c 100644
--- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
@@ -1039,7 +1039,6 @@
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
@@ -1081,7 +1080,6 @@
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 08/42] Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bits
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (6 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 07/42] Blackfin: drop SPORT_TX read helper macros Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 09/42] Blackfin: simplify symbol_lookup() a bit Mike Frysinger
` (33 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
.../mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 6 +++---
.../mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
index dec7c63..f65b439 100644
--- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -6,9 +6,9 @@
#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
-#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
+#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
index 58df301..0700875 100644
--- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
+++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
@@ -27,9 +27,9 @@
#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
+#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 09/42] Blackfin: simplify symbol_lookup() a bit
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (7 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 08/42] Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bits Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 10/42] Blackfin: kill off LDR jump block Mike Frysinger
` (32 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
No need to skip a byte as the symbol table handles this.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
cpu/blackfin/traps.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
index a2c6f1e..2121b0e 100644
--- a/cpu/blackfin/traps.c
+++ b/cpu/blackfin/traps.c
@@ -193,7 +193,7 @@ static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
while (*sym) {
sym_addr = simple_strtoul(sym, &esym, 16);
- sym = esym + 1;
+ sym = esym;
if (sym_addr > addr)
break;
*caddr = sym_addr;
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 10/42] Blackfin: kill off LDR jump block
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (8 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 09/42] Blackfin: simplify symbol_lookup() a bit Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 11/42] Blackfin: handle reboot anomaly 432 Mike Frysinger
` (31 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
The Boot ROM uses EVT1 as the entry point so set that rather than having
to use a tiny jump block in the default EVT1 location.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
blackfin_config.mk | 1 +
board/bf533-ezkit/u-boot.lds.S | 5 ++---
board/bf533-stamp/u-boot.lds.S | 5 ++---
board/bf537-stamp/u-boot.lds.S | 5 ++---
board/bf561-ezkit/u-boot.lds.S | 5 ++---
cpu/blackfin/cpu.c | 8 +-------
cpu/blackfin/initcode.c | 4 ++++
7 files changed, 14 insertions(+), 19 deletions(-)
diff --git a/blackfin_config.mk b/blackfin_config.mk
index f3fcd7a..04a7529 100644
--- a/blackfin_config.mk
+++ b/blackfin_config.mk
@@ -36,6 +36,7 @@ endif
SYM_PREFIX = _
+LDR_FLAGS += -J
LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
LDR_FLAGS += --use-vmas
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S
index da16726..f80f894 100644
--- a/board/bf533-ezkit/u-boot.lds.S
+++ b/board/bf533-ezkit/u-boot.lds.S
@@ -44,12 +44,11 @@
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S
index 76daa75..8ddfa81 100644
--- a/board/bf533-stamp/u-boot.lds.S
+++ b/board/bf533-stamp/u-boot.lds.S
@@ -44,12 +44,11 @@
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S
index 76daa75..8ddfa81 100644
--- a/board/bf537-stamp/u-boot.lds.S
+++ b/board/bf537-stamp/u-boot.lds.S
@@ -44,12 +44,11 @@
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S
index 3d0453e..4220e81 100644
--- a/board/bf561-ezkit/u-boot.lds.S
+++ b/board/bf561-ezkit/u-boot.lds.S
@@ -44,12 +44,11 @@
OUTPUT_ARCH(bfin)
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
- l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c
index 30c214b..c2ff8cd 100644
--- a/cpu/blackfin/cpu.c
+++ b/cpu/blackfin/cpu.c
@@ -25,18 +25,12 @@ ulong bfin_poweron_retx;
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
- /* Build a NOP slide over the LDR jump block. Whee! */
- serial_early_puts("NOP Slide\n");
- char nops[0xC];
- memset(nops, 0x00, sizeof(nops));
- extern char _stext_l1;
- memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
-
if (!loaded_from_ldr) {
/* Relocate sections into L1 if the LDR didn't do it -- don't
* check length because the linker script does the size
* checking at build time.
*/
+ extern char _stext_l1;
serial_early_puts("L1 Relocate\n");
extern char _stext_l1, _etext_l1, _stext_l1_lma;
memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index ae0016d..23d683a 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -371,6 +371,10 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_SIC_IWR(-1);
#endif
+ /* tell the bootrom where our entry point is */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
+ bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
+
serial_putc('>');
serial_putc('\n');
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 11/42] Blackfin: handle reboot anomaly 432
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (9 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 10/42] Blackfin: kill off LDR jump block Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 12/42] Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers Mike Frysinger
` (30 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence. Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
cpu/blackfin/initcode.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 23d683a..5e48564 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -272,8 +272,14 @@ void initcode(ADI_BOOT_DATA *bootstruct)
memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
+#if ANOMALY_05000432
+ bfin_write_SIC_IWR1(0);
+#endif
syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
(CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+#if ANOMALY_05000432
+ bfin_write_SIC_IWR1(-1);
+#endif
} else {
serial_putc('L');
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 12/42] Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (10 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 11/42] Blackfin: handle reboot anomaly 432 Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 13/42] Blackfin: do not program voltage regulator on parts that do not have one Mike Frysinger
` (29 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
cpu/blackfin/initcode.c | 33 +++++++++++++++++++++++++++++++++
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 5e48564..882ec11 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -203,6 +203,39 @@ static inline void serial_putc(char c)
# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
#endif
+#ifndef EBIU_RSTCTL
+/* Blackfin with SDRAM */
+#ifndef CONFIG_EBIU_SDBCTL_VAL
+# if CONFIG_MEM_SIZE == 16
+# define CONFIG_EBSZ_VAL EBSZ_16
+# elif CONFIG_MEM_SIZE == 32
+# define CONFIG_EBSZ_VAL EBSZ_32
+# elif CONFIG_MEM_SIZE == 64
+# define CONFIG_EBSZ_VAL EBSZ_64
+# elif CONFIG_MEM_SIZE == 128
+# define CONFIG_EBSZ_VAL EBSZ_128
+# elif CONFIG_MEM_SIZE == 256
+# define CONFIG_EBSZ_VAL EBSZ_256
+# elif CONFIG_MEM_SIZE == 512
+# define CONFIG_EBSZ_VAL EBSZ_512
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
+# endif
+# if CONFIG_MEM_ADD_WDTH == 8
+# define CONFIG_EBCAW_VAL EBCAW_8
+# elif CONFIG_MEM_ADD_WDTH == 9
+# define CONFIG_EBCAW_VAL EBCAW_9
+# elif CONFIG_MEM_ADD_WDTH == 10
+# define CONFIG_EBCAW_VAL EBCAW_10
+# elif CONFIG_MEM_ADD_WDTH == 11
+# define CONFIG_EBCAW_VAL EBCAW_11
+# else
+# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
+# endif
+# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
+#endif
+#endif
+
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
{
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 13/42] Blackfin: do not program voltage regulator on parts that do not have one
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (11 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 12/42] Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 14/42] Blackfin: put memory into self-refresh before/after programming clocks Mike Frysinger
` (28 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
cpu/blackfin/initcode.c | 23 ++++++++++++++++++++---
1 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 882ec11..231474a 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -203,6 +203,15 @@ static inline void serial_putc(char c)
# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
#endif
+/* some parts do not have an on-chip voltage regulator */
+#if defined(__ADSPBF51x__)
+# define CONFIG_HAS_VR 0
+# undef CONFIG_VR_CTL_VAL
+# define CONFIG_VR_CTL_VAL 0
+#else
+# define CONFIG_HAS_VR 1
+#endif
+
#ifndef EBIU_RSTCTL
/* Blackfin with SDRAM */
#ifndef CONFIG_EBIU_SDBCTL_VAL
@@ -301,15 +310,23 @@ void initcode(ADI_BOOT_DATA *bootstruct)
serial_putc('S');
ADI_SYSCTRL_VALUES memory_settings;
- memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+ uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
+ if (CONFIG_HAS_VR) {
+ actions |= SYSCTRL_VRCTL;
+ if (CONFIG_VR_CTL_VAL & FREQ_MASK)
+ actions |= SYSCTRL_INTVOLTAGE;
+ else
+ actions |= SYSCTRL_EXTVOLTAGE;
+ memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+ } else
+ actions |= SYSCTRL_EXTVOLTAGE;
memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
#if ANOMALY_05000432
bfin_write_SIC_IWR1(0);
#endif
- syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
- (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
+ bfrom_SysControl(actions, &memory_settings, NULL);
#if ANOMALY_05000432
bfin_write_SIC_IWR1(-1);
#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 14/42] Blackfin: put memory into self-refresh before/after programming clocks
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (12 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 13/42] Blackfin: do not program voltage regulator on parts that do not have one Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 15/42] Blackfin: unify common ADI board settings Mike Frysinger
` (27 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
- support suspend-to-RAM with Linux
- reprogram clocks automatically when doing "go" on u-boot.bin in RAM
- make sure settings are stable before flashing new version
- finally fully unify initialize startup code path between LDR/non-LDR
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
cpu/blackfin/initcode.c | 188 +++++++++++++++++++++++++++++++++++------------
cpu/blackfin/start.S | 83 +++++++++++++--------
2 files changed, 190 insertions(+), 81 deletions(-)
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 231474a..7bd4b22 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -12,6 +12,7 @@
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
@@ -257,6 +258,8 @@ void initcode(ADI_BOOT_DATA *bootstruct)
divB = serial_early_get_div();
}
+ serial_putc('A');
+
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
@@ -273,7 +276,23 @@ void initcode(ADI_BOOT_DATA *bootstruct)
}
#endif
- serial_putc('S');
+ serial_putc('B');
+
+ /* If external memory is enabled, put it into self refresh first. */
+ bool put_into_srfs = false;
+#ifdef EBIU_RSTCTL
+ if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
+ put_into_srfs = true;
+ }
+#else
+ if (bfin_read_EBIU_SDBCTL() & EBE) {
+ bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
+ put_into_srfs = true;
+ }
+#endif
+
+ serial_putc('C');
/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
* fast read, so we need to slow down the SPI clock a lot more during
@@ -286,28 +305,26 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
}
- serial_putc('B');
+ serial_putc('D');
- /* Disable all peripheral wakeups except for the PLL event. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(1);
- bfin_write_SIC_IWR1(0);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(0);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(1);
- bfin_write_SICA_IWR1(0);
+ /* If we're entering self refresh, make sure it has happened. */
+ if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+ while (!(bfin_read_EBIU_RSTCTL() & SRACK))
#else
- bfin_write_SIC_IWR(1);
+ while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
#endif
+ continue;
+
+ serial_putc('E');
/* With newer bootroms, we use the helper function to set up
* the memory controller. Older bootroms lacks such helpers
* so we do it ourselves.
*/
- if (BOOTROM_CAPS_SYSCONTROL) {
- serial_putc('S');
+ uint16_t vr_ctl = bfin_read_VR_CTL();
+ if (!ANOMALY_05000386) {
+ serial_putc('F');
ADI_SYSCTRL_VALUES memory_settings;
uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
@@ -331,22 +348,38 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_SIC_IWR1(-1);
#endif
} else {
- serial_putc('L');
+ serial_putc('G');
+
+ /* Disable all peripheral wakeups except for the PLL event. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(1);
+ bfin_write_SIC_IWR1(0);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(0);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(1);
+ bfin_write_SICA_IWR1(0);
+#else
+ bfin_write_SIC_IWR(1);
+#endif
+
+ serial_putc('H');
bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
- serial_putc('A');
+ serial_putc('I');
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
- if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+ if (vr_ctl != CONFIG_VR_CTL_VAL) {
serial_putc('!');
bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
asm("idle;");
}
- serial_putc('C');
+ serial_putc('J');
bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
@@ -360,8 +393,26 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");
}
+
+ serial_putc('L');
+
+ /* Restore all peripheral wakeups. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(-1);
+ bfin_write_SIC_IWR1(-1);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(-1);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(-1);
+ bfin_write_SICA_IWR1(-1);
+#else
+ bfin_write_SIC_IWR(-1);
+#endif
}
+ serial_putc('M');
+
/* Since we've changed the SCLK above, we may need to update
* the UART divisors (UART baud rates are based on SCLK).
* Do the division by hand as there are no native instructions
@@ -379,23 +430,32 @@ void initcode(ADI_BOOT_DATA *bootstruct)
serial_early_put_div(quotient - ANOMALY_05000230);
}
- serial_putc('F');
+ serial_putc('N');
- /* Program the async banks controller. */
- bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
- bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
- bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+ /* Program the external memory controller before we come out of
+ * self-refresh. This only works with our SDRAM controller.
+ */
+#ifndef EBIU_RSTCTL
+ bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
+ bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
+ bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+#endif
-#ifdef EBIU_MODE
- /* Not all parts have these additional MMRs. */
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+ serial_putc('O');
+
+ /* Now that we've reprogrammed, take things out of self refresh. */
+ if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
+#else
+ bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
#endif
- serial_putc('I');
+ serial_putc('P');
- /* Program the external memory controller. */
+ /* Our DDR controller sucks and cannot be programmed while in
+ * self-refresh. So we have to pull it out before programming.
+ */
#ifdef EBIU_RSTCTL
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
@@ -405,28 +465,60 @@ void initcode(ADI_BOOT_DATA *bootstruct)
/* default is disable, so don't need to force this */
bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
# endif
-#else
- bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
- bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
- bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+# ifdef CONFIG_EBIU_DDRQUE_VAL
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
+# endif
#endif
- serial_putc('N');
+ serial_putc('Q');
- /* Restore all peripheral wakeups. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(-1);
- bfin_write_SIC_IWR1(-1);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(-1);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(-1);
- bfin_write_SICA_IWR1(-1);
-#else
- bfin_write_SIC_IWR(-1);
+ /* Are we coming out of hibernate (suspend to memory) ?
+ * The memory layout is:
+ * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
+ * 0x4: return address
+ * 0x8: stack pointer
+ *
+ * SCKELOW is unreliable on older parts (anomaly 307)
+ */
+ if (ANOMALY_05000307 || vr_ctl & 0x8000) {
+ uint32_t *hibernate_magic = 0;
+ __builtin_bfin_ssync(); /* make sure memory controller is done */
+ if (hibernate_magic[0] == 0xDEADBEEF) {
+ serial_putc('R');
+ bfin_write_EVT15(hibernate_magic[1]);
+ bfin_write_IMASK(EVT_IVG15);
+ __asm__ __volatile__ (
+ /* load reti early to avoid anomaly 281 */
+ "reti = %0;"
+ /* clear hibernate magic */
+ "[%0] = %1;"
+ /* load stack pointer */
+ "SP = [%0 + 8];"
+ /* lower ourselves from reset ivg to ivg15 */
+ "raise 15;"
+ "rti;"
+ :
+ : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
+ );
+ }
+ }
+
+ serial_putc('S');
+
+ /* Program the async banks controller. */
+ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+ bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+#ifdef EBIU_MODE
+ /* Not all parts have these additional MMRs. */
+ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+ bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+ bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
#endif
+ serial_putc('T');
+
/* tell the bootrom where our entry point is */
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S
index 6c8def4..506fea5 100644
--- a/cpu/blackfin/start.S
+++ b/cpu/blackfin/start.S
@@ -95,36 +95,64 @@ ENTRY(_start)
/* Save RETX so we can pass it while booting Linux */
r7 = RETX;
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
- /* In bypass mode, we don't have an LDR with an init block
- * so we need to explicitly call it ourselves. This will
- * reprogram our clocks and setup our async banks.
- */
- /* XXX: we should DMA this into L1, put external memory into
- * self refresh, and then jump there ...
+ /* Figure out where we are currently executing so that we can decide
+ * how to best reprogram and relocate things. We'll pass below:
+ * R4: load address of _start
+ * R5: current (not load) address of _start
*/
+ serial_early_puts("Find ourselves");
+
call _get_pc;
- r3 = 0x0;
- r3.h = 0x2000;
- cc = r0 < r3 (iu);
- if cc jump .Lproc_initialized;
+.Loffset:
+ r1.l = .Loffset;
+ r1.h = .Loffset;
+ r4.l = _start;
+ r4.h = _start;
+ r3 = r1 - r4;
+ r5 = r0 - r3;
+
+ /* Inform upper layers if we had to do the relocation ourselves.
+ * This allows us to detect whether we were loaded by 'go 0x1000'
+ * or by the bootrom from an LDR. "R6" is "loaded_from_ldr".
+ */
+ r6 = 1 (x);
+ cc = r4 == r5;
+ if cc jump .Lnorelocate;
+ r6 = 0 (x);
+ /* In bypass mode, we don't have an LDR with an init block
+ * so we need to explicitly call it ourselves. This will
+ * reprogram our clocks, memory, and setup our async banks.
+ */
serial_early_puts("Program Clocks");
+ /* if we're executing >=0x20000000, then we dont need to dma */
+ r3 = 0x0;
+ r3.h = 0x2000;
+ cc = r5 < r3 (iu);
+ if cc jump .Ldma_and_reprogram;
call _initcode;
+ jump .Lprogrammed;
+
+ /* we're sitting in external memory, so dma into L1 and reprogram */
+.Ldma_and_reprogram:
+ r0.l = LO(L1_INST_SRAM);
+ r0.h = HI(L1_INST_SRAM);
+ r1.l = __initcode_start;
+ r1.h = __initcode_start;
+ r2.l = __initcode_end;
+ r2.h = __initcode_end;
+ r2 = r2 - r1; /* convert r2 into length of initcode */
+ r1 = r1 - r4; /* convert r1 from load address of initcode ... */
+ r1 = r1 + r5; /* ... to current (not load) address of initcode */
+ p3 = r0;
+ call _dma_memcpy_nocache;
+ call (p3);
/* Since we reprogrammed SCLK, we need to update the serial divisor */
+.Lprogrammed:
serial_early_set_baud
-.Lproc_initialized:
-#endif
-
- /* Inform upper layers if we had to do the relocation ourselves.
- * This allows us to detect whether we were loaded by 'go 0x1000'
- * or by the bootrom from an LDR. "r6" is "loaded_from_ldr".
- */
- r6 = 1 (x);
-
/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
* monitor location in the end of RAM. We know that memcpy() only
* uses registers, so it is safe to call here. Note that this only
@@ -132,19 +160,8 @@ ENTRY(_start)
* it yet (see "lower to 15" below).
*/
serial_early_puts("Relocate");
- call _get_pc;
-.Loffset:
- r2.l = .Loffset;
- r2.h = .Loffset;
- r3.l = _start;
- r3.h = _start;
- r2 = r2 - r3;
- r1 = r0 - r2;
- cc = r1 == r3;
- if cc jump .Lnorelocate;
- r6 = 0 (x);
-
- r0 = r3;
+ r0 = r4;
+ r1 = r5;
r2.l = LO(CONFIG_SYS_MONITOR_LEN);
r2.h = HI(CONFIG_SYS_MONITOR_LEN);
call _memcpy_ASM;
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 15/42] Blackfin: unify common ADI board settings
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (13 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 14/42] Blackfin: put memory into self-refresh before/after programming clocks Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 16/42] Blackfin: bf533-stamp: rewrite startup LED notifications Mike Frysinger
` (26 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Rather than duplicate the same ADI settings in every ADI board, create a
common ADI config header and have all ADI boards start using that. This
will also make merging the ~10 boards I have to forward port a lot easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/configs/bf533-ezkit.h | 286 ++++++++++---------------
include/configs/bf533-stamp.h | 429 ++++++++++++-------------------------
include/configs/bf537-stamp.h | 421 ++++++++++++------------------------
include/configs/bf561-ezkit.h | 295 ++++++++++----------------
include/configs/bfin_adi_common.h | 197 +++++++++++++++++
5 files changed, 689 insertions(+), 939 deletions(-)
create mode 100644 include/configs/bfin_adi_common.h
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 48c0252..90e2743 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -2,213 +2,155 @@
* U-boot - Configuration file for BF533 EZKIT board
*/
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
+#ifndef __CONFIG_BF533_EZKIT_H__
+#define __CONFIG_BF533_EZKIT_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_LOADADDR 0x01000000 /* default load address */
-#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
-/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20310300
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 27000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 22
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
-#if 0
-#define CONFIG_MII
-#define CONFIG_SYS_DISCOVER_PHY
-#endif
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 22
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE 32
+/* Early EZKITs had 32megs, but later have 64megs */
+#if (CONFIG_MEM_SIZE == 64)
+# define CONFIG_MEM_ADD_WDTH 10
#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+# define CONFIG_MEM_ADD_WDTH 9
#endif
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
+#define CONFIG_EBIU_SDRRC_VAL 0x398
+#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_LOADS_ECHO 1
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
- * BOOTP options
+ * Network Settings
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20310300
+#define SMC91111_EEPROM_INIT() \
+ do { \
+ *pFIO_DIR |= PF1; \
+ *pFIO_FLAG_S = PF1; \
+ SSYNC(); \
+ } while (0)
+#define CONFIG_HOSTNAME bf533-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
- * Command line configuration.
+ * Flash Settings
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_DATE
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
#define CONFIG_SYS_FLASH_BASE 0x20000000
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_FLASH0_BASE 0x20000000
-#define CONFIG_SYS_FLASH1_BASE 0x20200000
-#define CONFIG_SYS_FLASH2_BASE 0x20280000
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_MAX_FLASH_SECT 40
+#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20020000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#define POLL_MODE 1
+#define CONFIG_ENV_SECT_SIZE 0x10000
#define FLASH_TOT_SECT 40
-#define FLASH_SIZE 0x220000
-#define CONFIG_SYS_FLASH_SIZE 0x220000
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
/*
- * I2C settings
+ * I2C Settings
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
*/
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL PF0
-#define PF_SDA PF1
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF0
+#define PF_SDA PF1
+#define I2C_INIT \
+ do { \
+ *pFIO_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO_DIR |= PF_SDA; \
+ *pFIO_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO_DIR &= ~PF_SDA; \
+ *pFIO_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SDA; \
+ else \
+ *pFIO_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SCL; \
+ else \
+ *pFIO_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
+#endif
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-#define CONFIG_EBIU_SDRRC_VAL 0x398
-#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-#define CONFIG_EBIU_SDBCTL_VAL 0x13
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index ee41c7e..0aa4d92 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -2,371 +2,208 @@
* U-boot - Configuration file for BF533 STAMP board
*/
-#ifndef __CONFIG_STAMP_H__
-#define __CONFIG_STAMP_H__
+#ifndef __CONFIG_BF533_STAMP_H__
+#define __CONFIG_BF533_STAMP_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_RTC_BFIN 1
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
/*
- * Board settings
+ * Processor Settings
*/
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20300300
-
-/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 1
+#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/* Is I2C bit-banged? */
-#define CONFIG_SOFT_I2C 1
/*
- * Software (bit-bang) I2C driver configuration
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
-#define PF_SCL PF3
-#define PF_SDA PF2
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 11059200
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 36
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
-/*
- * Video splash screen support
- */
-#define CONFIG_VIDEO 0
/*
- * Clock settings
+ * Memory Settings
*/
+#define CONFIG_MEM_ADD_WDTH 11
+#define CONFIG_MEM_SIZE 128
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 36
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-
-/*
- * Network settings
- */
+#define CONFIG_EBIU_SDRRC_VAL 0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-#if (CONFIG_DRIVER_SMC91111)
-#if 0
-#define CONFIG_MII
-#endif
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-/* network support */
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME STAMP
-#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-/* To remove hardcoding and enable MAC storage in EEPROM */
-/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
-#endif /* CONFIG_DRIVER_SMC91111 */
/*
- * Flash settings
+ * Network Settings
*/
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20300300
+#define SMC91111_EEPROM_INIT() \
+ do { \
+ *pFIO_DIR |= PF1; \
+ *pFIO_FLAG_S = PF1; \
+ SSYNC(); \
+ } while (0)
+#define CONFIG_HOSTNAME bf533-stamp
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 67
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
+#define CONFIG_ENV_OFFSET 0x4000
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#endif
-
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
-#define ENV_IS_EMBEDDED
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
-#define CONFIG_SYS_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
-
-/*
- * following timeouts shall be used once the
- * Flash real protection is enabled
- */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MAX_RAM_SIZE - 0x80000 - 1)
-#define CONFIG_LOADADDR 0x01000000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - 0x40000)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-
-/* Check to make sure everything fits in SDRAM */
-#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
- #error Memory Map does not fit into configuration
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#endif
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
-
-/*
- * Command settings
- */
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-
-#define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
-
-/* configuration lookup from the BOOTP/DHCP server, */
-/* but not try to load any image using TFTP */
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.bin; " \
- "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
- "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
- ""
-
-#ifdef CONFIG_SOFT_I2C
-#if (!CONFIG_SOFT_I2C)
-#undef CONFIG_SOFT_I2C
-#endif
+#define ENV_IS_EMBEDDED_CUSTOM
#endif
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#endif
-
-#if (CONFIG_SOFT_I2C)
-#define CONFIG_CMD_I2C
-#endif
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * Console settings
- */
-
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_LOADS_ECHO 1
/*
- * I2C settings
+ * I2C Settings
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
*/
-#if (CONFIG_SOFT_I2C)
-
-#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
-#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SDA; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SDA; \
- asm("ssync;"); \
- }
-#define I2C_SCL(bit) if(bit) { \
- *pFIO_FLAG_S = PF_SCL; \
- asm("ssync;"); \
- } \
- else { \
- *pFIO_FLAG_C = PF_SCL; \
- asm("ssync;"); \
- }
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF3
+#define PF_SDA PF2
+#define I2C_INIT \
+ do { \
+ *pFIO_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO_DIR |= PF_SDA; \
+ *pFIO_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO_DIR &= ~PF_SDA; \
+ *pFIO_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SDA; \
+ else \
+ *pFIO_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SCL; \
+ else \
+ *pFIO_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
-#endif /* CONFIG_SOFT_I2C */
+#endif
+
/*
- * Compact Flash settings
+ * Compact Flash / IDE / ATA Settings
*/
/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF 1 */
-
-#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
-
-#define CONFIG_MISC_INIT_R 1
+/* #define CONFIG_STAMP_CF */
+#if defined(CONFIG_STAMP_CF)
+#define CONFIG_MISC_INIT_R
#define CONFIG_DOS_PARTITION 1
-/*
- * IDE/ATA stuff
- */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2
+
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
#endif
+
/*
- * Miscellaneous configurable options
+ * Misc Settings
*/
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
-#define CONFIG_SYS_HZ 1000 /* 1ms time tick */
+/* FLASH/ETHERNET uses the same async bank */
+#define SHARED_RESOURCES 1
-#define CONFIG_SYS_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
+/* define to enable splash screen support */
+/* #define CONFIG_VIDEO */
-#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
-
-#define CONFIG_SPI
-
-#ifdef CONFIG_VIDEO
-#if (CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN 1
-#define CONFIG_SILENT_CONSOLE 1
-#else
-#undef CONFIG_VIDEO
-#endif
-#endif
/*
- * FLASH organization and environment definitions
+ * Pull in common ADI header for remaining command/environment setup
*/
-
-#define CONFIG_EBIU_SDRRC_VAL 0x268
-#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-#define CONFIG_EBIU_SDBCTL_VAL 0x37
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 27567fa..e0b107b 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -2,272 +2,124 @@
* U-boot - Configuration file for BF537 STAMP board
*/
-#ifndef __CONFIG_BF537_H__
-#define __CONFIG_BF537_H__
+#ifndef __CONFIG_BF537_STAMP_H__
+#define __CONFIG_BF537_STAMP_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_BAUDRATE 57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTDELAY 5
-/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
-/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
-
-#define CONFIG_PANIC_HANG 1
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-#define CONFIG_BFIN_MAC
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-/* Define if want to do post memory test */
-#undef CONFIG_POST_TEST
-
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL*/
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
-/* Values can range from 1-64 */
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15 */
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC32M8A2_75 1
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_LOADS_ECHO 1
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-/*
- * rarpb, bootp or dhcp commands will perform only a
- * configuration lookup from the BOOTP/DHCP server
- * but not try to load any image using TFTP
- */
-#define CONFIG_SYS_AUTOLOAD "no"
/*
* Network Settings
*/
-/* network support */
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME BF537
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
#endif
-
-#define CONFIG_ROOTPATH /romfs
+#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-
-#if defined(CONFIG_POST_TEST)
-/* POST support */
-#define CONFIG_POST ( CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_UART | \
- CONFIG_SYS_POST_FLASH | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_LED | \
- CONFIG_SYS_POST_BUTTON)
-#else
-#undef CONFIG_POST
-#endif
-#ifdef CONFIG_POST
-#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
-#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
-#endif
-
-/* CF-CARD IDE-HDD Support */
-
-/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
-/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
-/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
-
-#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
-# define CONFIG_BFIN_IDE 1
-#endif
-
-/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
-
-#define CONFIG_NETCONSOLE 1
-#define CONFIG_NET_MULTI 1
/*
- * BOOTP options
+ * Flash Settings
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-
-#ifndef CONFIG_BFIN_MAC
-#undef CONFIG_CMD_NET
-#else
-#define CONFIG_CMD_PING
-#endif
-
-#if defined(CONFIG_BFIN_CF_IDE) \
- || defined(CONFIG_BFIN_HDD_IDE) \
- || defined(CONFIG_BFIN_TRUE_IDE)
-#define CONFIG_CMD_IDE
-#endif
-
-#define CONFIG_CMD_DHCP
-
-#if defined(CONFIG_POST)
-#define CONFIG_CMD_DIAG
-#endif
-
-#ifdef CONFIG_BF537_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#define CONFIG_LOADADDR 0x1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0" \
- "flashboot=bootm 0x20100000\0" \
- "update=tftpboot $(loadaddr) u-boot.bin;" \
- "protect off 0x20000000 0x2007FFFF;" \
- "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
- ""
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-
+/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
+#define CONFIG_SYS_MAX_FLASH_SECT 71
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#define CONFIG_ENV_OFFSET 0x4000
#else
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#endif
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
-
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
/*
- * Stack sizes
+ * I2C Settings
*/
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
-#define POLL_MODE 1
-#define FLASH_TOT_SECT 71
-#define FLASH_SIZE 0x400000
-#define CONFIG_SYS_FLASH_SIZE 0x400000
/*
- * Board NAND Infomation
+ * NAND Settings
*/
+/* #define CONFIG_BF537_NAND */
+#ifdef CONFIG_BF537_NAND
+# define CONFIG_CMD_NAND
+#endif
#define CONFIG_SYS_NAND_ADDR 0x20212000
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
@@ -280,56 +132,35 @@
#define NAND_MAX_FLOORS 1
#define BFIN_NAND_READY PF3
-#define NAND_WAIT_READY(nand) \
- do { \
- int timeout = 0; \
- while(!(*pPORTFIO & PF3)) \
- if (timeout++ > 100000) \
- break; \
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int timeout = 0; \
+ while (!(*pPORTFIO & PF3)) \
+ if (timeout++ > 100000) \
+ break; \
} while (0)
-#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
-#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
+#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
+#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
+#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
+#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
+#define WRITE_NAND(d, adr) bfin_write8(adr, d)
+#define READ_NAND(adr) bfin_read8(adr)
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/*
- * Initialize PSD4256 registers for using I2C
+ * CF-CARD IDE-HDD Support
*/
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
-
-/*
- * I2C settings
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_BFIN_TWI_I2C 1
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x25
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
- ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
- B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
+/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
+/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
-#define AMGCTLVAL 0xFF
-#define AMBCTL0VAL 0x7BB07BB0
-#define AMBCTL1VAL 0xFFC27BB0
+#if defined(CONFIG_BFIN_CF_IDE) || \
+ defined(CONFIG_BFIN_HDD_IDE) || \
+ defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE 1
+# define CONFIG_CMD_IDE
+#endif
#if defined(CONFIG_BFIN_IDE)
@@ -341,11 +172,11 @@
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
-#undef AMBCTL1VAL
-#define AMBCTL1VAL 0xFFC3FFC3
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
#define CONFIG_CF_ATASEL_DIS 0x20311800
#define CONFIG_CF_ATASEL_ENA 0x20311802
@@ -357,34 +188,54 @@
*/
#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
-#endif /* CONFIG_BFIN_TRUE_IDE */
-#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
+#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
-#endif /* CONFIG_BFIN_CF_IDE */
-#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
+#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
-
#undef CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV 8
-#endif /* CONFIG_BFIN_HDD_IDE */
+#endif
+
+#endif
+
-#endif /*CONFIG_BFIN_IDE */
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 320a8c6..ef2019f 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -2,229 +2,152 @@
* U-boot - Configuration file for BF561 EZKIT board
*/
-#ifndef __CONFIG_EZKIT561_H__
-#define __CONFIG_EZKIT561_H__
+#ifndef __CONFIG_BF561_EZKIT_H__
+#define __CONFIG_BF561_EZKIT_H__
#include <asm/blackfin-config-pre.h>
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_BAUDRATE 57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_EZKIT561 1
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
/*
- * Board settings
+ * Processor Settings
*/
-#define CONFIG_DRIVER_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x2C010300
-#define CONFIG_ASYNC_EBIU_BASE CONFIG_SMC91111_BASE & ~(4*1024*1024)
-#define CONFIG_SMC_USE_32_BIT 1
-#define CONFIG_MISC_INIT_R 1
-
-/*
- * Clock settings
- */
-
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 30000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
-/* 1=CLKIN/2 */
-#define CONFIG_CLKIN_HALF 0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/* 1=bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is */
-/* Values can range from 1-64 */
-#define CONFIG_VCO_MULT 20
-/* CONFIG_CCLK_DIV controls what the core clock divider is */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
-/* Values can range from 2-65535 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
-#define CONFIG_SPI_BAUD 2
-#define CONFIG_SPI_BAUD_INITBLOCK 4
+#define CONFIG_BFIN_CPU bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-/*
- * Network settings
- */
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME ezkit561
-#define CONFIG_ROOTPATH /arm-cross-build/BF561/uClinux-dist/romfs
-#endif /* CONFIG_DRIVER_SMC91111 */
/*
- * Flash settings
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 20
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 6
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR 0x20020000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8
/*
- * SDRAM settings & memory map
+ * Memory Settings
*/
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 64
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC16M16A2TG_75 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_LOADADDR 0x01000000 /* default load address */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
/*
- * Command settings
+ * Network Settings
*/
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x2C010300
+#define CONFIG_SMC_USE_32_BIT 1
+#define CONFIG_HOSTNAME bf561-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
-#define CONFIG_SYS_AUTOLOAD "no" /* rarpb, bootp, dhcp commands will */
- /* only perform a configuration */
- /* lookup from the BOOTP/DHCP server */
- /* but not try to load any image */
- /* using TFTP */
-#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, */
- /* currently its disabled */
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
- "$(rootpath) console=ttyBF0,57600\0" \
- "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
- "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux; " \
- "run ramargs; run addip; bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux; " \
- "run nfsargs; run addip; bootelf\0" \
- "update=tftpboot $(loadaddr) u-boot.bin; " \
- "protect off 0x20000000 0x2003FFFF; " \
- "erase 0x20000000 0x2003FFFF; " \
- "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
- ""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
- "flashboot=bootm 0x20100000\0" \
- ""
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
/*
- * Command line configuration.
+ * Flash Settings
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-
-#if defined(CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+/* The BF561-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
#endif
+
/*
- * Console settings
+ * I2C Settings
*/
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SOFT_I2C
+#ifdef CONFIG_SOFT_I2C
+#define PF_SCL PF0
+#define PF_SDA PF1
+#define I2C_INIT \
+ do { \
+ *pFIO0_DIR |= PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_ACTIVE \
+ do { \
+ *pFIO0_DIR |= PF_SDA; \
+ *pFIO0_INEN &= ~PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_TRISTATE \
+ do { \
+ *pFIO0_DIR &= ~PF_SDA; \
+ *pFIO0_INEN |= PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SDA; \
+ else \
+ *pFIO0_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SCL; \
+ else \
+ *pFIO0_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_LOADS_ECHO 1
/*
- * Miscellaneous configurable options
+ * Misc Settings
*/
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
-#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+#define CONFIG_UART_CONSOLE 0
+
/*
- * FLASH organization and environment definitions
+ * Pull in common ADI header for remaining command/environment setup
*/
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x15
-
-#define CONFIG_EBIU_AMGCTL_VAL 0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+#include <configs/bfin_adi_common.h>
#include <asm/blackfin-config-post.h>
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
new file mode 100644
index 0000000..e40bb2c
--- /dev/null
+++ b/include/configs/bfin_adi_common.h
@@ -0,0 +1,197 @@
+/*
+ * U-Boot - Common settings for Analog Devices boards
+ */
+
+#ifndef __CONFIG_BFIN_ADI_COMMON_H__
+#define __CONFIG_BFIN_ADI_COMMON_H__
+
+/*
+ * Command Settings
+ */
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+# if ADI_CMDS_NETWORK
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+# ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_MII
+# endif
+# else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+# endif
+# ifdef CONFIG_LIBATA
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_SATA
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_MMC
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_MMC
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_USB
+# define CONFIG_CMD_EXT2
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_USB
+# define CONFIG_CMD_USB_STORAGE
+# define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_POST
+# define CONFIG_CMD_DIAG
+# endif
+# ifdef CONFIG_RTC_BFIN
+# define CONFIG_CMD_DATE
+# endif
+# ifdef CONFIG_SPI
+# define CONFIG_CMD_EEPROM
+# endif
+# if defined(CONFIG_BFIN_SPI) || defined(CONFIG_SOFT_SPI)
+# define CONFIG_CMD_SPI
+# endif
+# ifdef CONFIG_SPI_FLASH
+# define CONFIG_CMD_SF
+# endif
+# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# define CONFIG_CMD_I2C
+# endif
+# ifdef CONFIG_SYS_NO_FLASH
+# undef CONFIG_CMD_FLASH
+# undef CONFIG_CMD_IMLS
+# else
+# define CONFIG_CMD_JFFS2
+# endif
+# define CONFIG_CMD_BOOTLDR
+# define CONFIG_CMD_CACHE
+# define CONFIG_CMD_CPLBINFO
+# define CONFIG_CMD_ELF
+# define CONFIG_ELF_SIMPLE_LOAD
+# define CONFIG_CMD_REGINFO
+# define CONFIG_CMD_STRINGS
+# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
+# define CONFIG_CMD_OTP
+# endif
+#endif
+
+/*
+ * Console Settings
+ */
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_JTAG_CONSOLE
+#ifndef CONFIG_BAUDRATE
+# define CONFIG_BAUDRATE 57600
+#endif
+
+/*
+ * Debug Settings
+ */
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DEBUG_DUMP 1
+#define CONFIG_DEBUG_DUMP_SYMS 1
+#define CONFIG_PANIC_HANG 1
+
+/*
+ * Env Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+#else
+# define CONFIG_BOOTDELAY 5
+#endif
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#ifdef CONFIG_VIDEO
+# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
+#else
+# define CONFIG_BOOTARGS_VIDEO ""
+#endif
+#define CONFIG_BOOTARGS \
+ "root=/dev/mtdblock0 rw " \
+ "earlyprintk=" \
+ "serial," \
+ "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
+ MK_STR(CONFIG_BAUDRATE) " " \
+ CONFIG_BOOTARGS_VIDEO \
+ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+
+#if defined(CONFIG_CMD_NET)
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+# define UBOOT_ENV_FILE "u-boot.bin"
+# else
+# define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+# ifdef CONFIG_SPI
+# define UBOOT_ENV_UPDATE \
+ "eeprom write $(loadaddr) 0x0 $(filesize)"
+# else
+# define UBOOT_ENV_UPDATE \
+ "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf erase 0 0x40000;" \
+ "sf write $(loadaddr) 0 $(filesize)"
+# endif
+# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define UBOOT_ENV_UPDATE \
+ "nand unlock 0 0x40000;" \
+ "nand erase 0 0x40000;" \
+ "nand write $(loadaddr) 0 0x40000"
+# else
+# define UBOOT_ENV_UPDATE \
+ "protect off 0x20000000 0x2003FFFF;" \
+ "erase 0x20000000 0x2003FFFF;" \
+ "cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
+# define NETWORK_ENV_SETTINGS \
+ "ubootfile=" UBOOT_ENV_FILE "\0" \
+ "update=" \
+ "tftp $(loadaddr) $(ubootfile);" \
+ UBOOT_ENV_UPDATE \
+ "\0" \
+ "addip=set bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
+ "$(hostname):eth0:off" \
+ "\0" \
+ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+ "ramboot=" \
+ "tftp $(loadaddr) uImage;" \
+ "run ramargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0" \
+ "nfsargs=set bootargs " \
+ "root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
+ "\0" \
+ "nfsboot=" \
+ "tftp $(loadaddr) vmImage;" \
+ "run nfsargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+ "flashboot=bootm 0x20100000\0"
+
+/*
+ * Network Settings
+ */
+#ifdef CONFIG_CMD_NET
+# define CONFIG_IPADDR 192.168.0.15
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_GATEWAYIP 192.168.0.1
+# define CONFIG_SERVERIP 192.168.0.2
+# define CONFIG_ROOTPATH /romfs
+# ifdef CONFIG_CMD_DHCP
+# ifndef CONFIG_SYS_AUTOLOAD
+# define CONFIG_SYS_AUTOLOAD "no"
+# endif
+# endif
+#endif
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 16/42] Blackfin: bf533-stamp: rewrite startup LED notifications
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (14 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 15/42] Blackfin: unify common ADI board settings Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 17/42] Blackfin: bf533-stamp: bump up default clocks Mike Frysinger
` (25 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Again, don't clobber pins that we aren't actually using, and use the common
LED framework rather than our own hob-job-but-not-really-working.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
board/bf533-stamp/bf533-stamp.c | 62 ++++++++++++++++++++++++++++++---------
include/configs/bf533-stamp.h | 25 +++++++++++++++
2 files changed, 73 insertions(+), 14 deletions(-)
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 44ebc93..7108dda 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -1,7 +1,7 @@
/*
- * U-boot - stamp.c STAMP board specific routines
+ * U-boot - main board file
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -31,15 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define STATUS_LED_OFF 0
-#define STATUS_LED_ON 1
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
int checkboard(void)
{
printf("Board: ADI BF533 Stamp board\n");
@@ -192,10 +183,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
}
#endif
-void stamp_led_set(int LED1, int LED2, int LED3)
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON 1
+
+static void stamp_led_set(int LED1, int LED2, int LED3)
{
- *pFIO_INEN &= ~(PF2 | PF3 | PF4);
- *pFIO_DIR |= (PF2 | PF3 | PF4);
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
if (LED1 == STATUS_LED_OFF)
*pFIO_FLAG_S = PF2;
@@ -249,3 +245,41 @@ void show_boot_progress(int status)
break;
}
}
+#endif
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+
+static void set_led(int pf, int state)
+{
+ switch (state) {
+ case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break;
+ case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break;
+ case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break;
+ }
+}
+
+static void set_leds(led_id_t mask, int state)
+{
+ if (mask & 0x1) set_led(PF2, state);
+ if (mask & 0x2) set_led(PF3, state);
+ if (mask & 0x4) set_led(PF4, state);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ set_leds(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ set_leds(mask, STATUS_LED_BLINKING);
+}
+
+#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 0aa4d92..ea5cf41 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -196,6 +196,31 @@
/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 1
+/* define to enable boot progress via leds */
+/* #define CONFIG_SHOW_BOOT_PROGRESS */
+
+/* define to enable run status via led */
+/* #define CONFIG_STATUS_LED */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+void __led_init(led_id_t mask, int state);
+void __led_set(led_id_t mask, int state);
+void __led_toggle(led_id_t mask);
+#endif
+/* use LED1 to indicate booting/alive */
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT 1
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
+/* use LED2 to indicate crash */
+#define STATUS_LED_CRASH 1
+#define STATUS_LED_BIT1 2
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#endif
+
/* define to enable splash screen support */
/* #define CONFIG_VIDEO */
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 17/42] Blackfin: bf533-stamp: bump up default clocks
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (15 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 16/42] Blackfin: bf533-stamp: rewrite startup LED notifications Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough Mike Frysinger
` (24 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Since the hardware can handle it, bump the default clocks from 80mhz SCLK
and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/configs/bf533-stamp.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index ea5cf41..b1cdf49 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -30,7 +30,7 @@
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 36
+#define CONFIG_VCO_MULT 45
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (16 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 17/42] Blackfin: bf533-stamp: bump up default clocks Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 17:54 ` Ben Warren
2009-02-10 6:20 ` [U-Boot] [PATCH 19/42] Blackfin: new spibootldr command Mike Frysinger
` (23 subsequent siblings)
41 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
We use things from autoconf.mk in the top level Makefile, so it needs to
exist before doing a top level make. Otherwise, the top level make env
does not get the values in the autoconf.mk.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
Makefile | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index 787c5f2..db77d3b 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,6 +3293,8 @@ BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
+ @$(MAKE) -s -B $(obj)include/autoconf.mk
+ @$(MAKE) -s -B $(obj)include/autoconf.mk
$(BFIN_BOARDS):
$(MAKE) $@_config
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 6:20 ` [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough Mike Frysinger
@ 2009-02-10 17:54 ` Ben Warren
2009-02-10 18:57 ` Mike Frysinger
0 siblings, 1 reply; 58+ messages in thread
From: Ben Warren @ 2009-02-10 17:54 UTC (permalink / raw)
To: u-boot
Hi Mike,
Mike Frysinger wrote:
> We use things from autoconf.mk in the top level Makefile, so it needs to
> exist before doing a top level make. Otherwise, the top level make env
> does not get the values in the autoconf.mk.
>
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> ---
> Makefile | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 787c5f2..db77d3b 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3293,6 +3293,8 @@ BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
>
> $(BFIN_BOARDS:%=%_config) : unconfig
> @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
> + @$(MAKE) -s -B $(obj)include/autoconf.mk
> + @$(MAKE) -s -B $(obj)include/autoconf.mk
>
>
Do you really mean to do this twice?
> $(BFIN_BOARDS):
> $(MAKE) $@_config
>
regards,
Ben
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 17:54 ` Ben Warren
@ 2009-02-10 18:57 ` Mike Frysinger
2009-02-10 19:23 ` Ben Warren
2009-02-10 19:42 ` Wolfgang Denk
0 siblings, 2 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 18:57 UTC (permalink / raw)
To: u-boot
On Tuesday 10 February 2009 12:54:31 Ben Warren wrote:
> Mike Frysinger wrote:
> > We use things from autoconf.mk in the top level Makefile, so it needs to
> > exist before doing a top level make. Otherwise, the top level make env
> > does not get the values in the autoconf.mk.
> >
> > Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> > ---
> > Makefile | 2 ++
> > 1 files changed, 2 insertions(+), 0 deletions(-)
> >
> > diff --git a/Makefile b/Makefile
> > index 787c5f2..db77d3b 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -3293,6 +3293,8 @@ BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp
> > bf561-ezkit
> >
> > $(BFIN_BOARDS:%=%_config) : unconfig
> > @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
> > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > + @$(MAKE) -s -B $(obj)include/autoconf.mk
>
> Do you really mean to do this twice?
unfortunately, yes. since some settings in the board config are turned into
compiler flags and those compiler flags can in turn affect the board config,
we need to do it twice. first is to make sure the proper cpu flags are
propagated into the toplevel build env while the second is to make sure the
autoconf.mk fully reflects the board config.
i guess i could add a one line comment above each one giving hints about why
each is needed ...
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 18:57 ` Mike Frysinger
@ 2009-02-10 19:23 ` Ben Warren
2009-02-10 19:42 ` Wolfgang Denk
1 sibling, 0 replies; 58+ messages in thread
From: Ben Warren @ 2009-02-10 19:23 UTC (permalink / raw)
To: u-boot
Mike Frysinger wrote:
> On Tuesday 10 February 2009 12:54:31 Ben Warren wrote:
>
>> Mike Frysinger wrote:
>>
>>> We use things from autoconf.mk in the top level Makefile, so it needs to
>>> exist before doing a top level make. Otherwise, the top level make env
>>> does not get the values in the autoconf.mk.
>>>
>>> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
>>> ---
>>> Makefile | 2 ++
>>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/Makefile b/Makefile
>>> index 787c5f2..db77d3b 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -3293,6 +3293,8 @@ BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp
>>> bf561-ezkit
>>>
>>> $(BFIN_BOARDS:%=%_config) : unconfig
>>> @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
>>> + @$(MAKE) -s -B $(obj)include/autoconf.mk
>>> + @$(MAKE) -s -B $(obj)include/autoconf.mk
>>>
>> Do you really mean to do this twice?
>>
>
> unfortunately, yes. since some settings in the board config are turned into
> compiler flags and those compiler flags can in turn affect the board config,
> we need to do it twice. first is to make sure the proper cpu flags are
> propagated into the toplevel build env while the second is to make sure the
> autoconf.mk fully reflects the board config.
>
> i guess i could add a one line comment above each one giving hints about why
> each is needed ...
> -mike
>
No problem. Just a sanity check. Turns out you're sane :)
regards,
Ben
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 18:57 ` Mike Frysinger
2009-02-10 19:23 ` Ben Warren
@ 2009-02-10 19:42 ` Wolfgang Denk
2009-02-10 19:49 ` Mike Frysinger
1 sibling, 1 reply; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-10 19:42 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <200902101357.29507.vapier@gentoo.org> you wrote:
>
> > > $(BFIN_BOARDS:%=%_config) : unconfig
> > > @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
> > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> >
> > Do you really mean to do this twice?
>
> unfortunately, yes. since some settings in the board config are turned into
> compiler flags and those compiler flags can in turn affect the board config,
> we need to do it twice. first is to make sure the proper cpu flags are
> propagated into the toplevel build env while the second is to make sure the
> autoconf.mk fully reflects the board config.
Sounds like a design problem to me.
> i guess i could add a one line comment above each one giving hints about why
> each is needed ...
That would be the minimum, but given the fact that the top level
Makefile already includes rules to build autoconf.mk I really wonder
if we must do this so often, and if so, then why this is only the
case for blackfin.
I think you should fix the cuase rather then doctor about the
symptoms.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The joys of love made her human and the agonies of love destroyed
her.
-- Spock, "Requiem for Methuselah", stardate 5842.8
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 19:42 ` Wolfgang Denk
@ 2009-02-10 19:49 ` Mike Frysinger
2009-02-11 21:36 ` Wolfgang Denk
0 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 19:49 UTC (permalink / raw)
To: u-boot
On Tuesday 10 February 2009 14:42:20 Wolfgang Denk wrote:
> Dear Mike Frysinger,
>
> In message <200902101357.29507.vapier@gentoo.org> you wrote:
> > > > $(BFIN_BOARDS:%=%_config) : unconfig
> > > > @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
> > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > >
> > > Do you really mean to do this twice?
> >
> > unfortunately, yes. since some settings in the board config are turned
> > into compiler flags and those compiler flags can in turn affect the board
> > config, we need to do it twice. first is to make sure the proper cpu
> > flags are propagated into the toplevel build env while the second is to
> > make sure the autoconf.mk fully reflects the board config.
>
> Sounds like a design problem to me.
not really. the point is to avoid duplication and considering the method to
attain that, sounds pretty good to me.
> > i guess i could add a one line comment above each one giving hints about
> > why each is needed ...
>
> That would be the minimum, but given the fact that the top level
> Makefile already includes rules to build autoconf.mk I really wonder
> if we must do this so often, and if so, then why this is only the
> case for blackfin.
the top level Makefile includes rules to build it, but it doesnt re-source it
once it's been generated. so anything in the top level cannot use things from
autoconf.mk (like $(arch)_config.mk).
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-10 19:49 ` Mike Frysinger
@ 2009-02-11 21:36 ` Wolfgang Denk
2009-02-11 21:54 ` Mike Frysinger
0 siblings, 1 reply; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-11 21:36 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <200902101449.24108.vapier@gentoo.org> you wrote:
>
> > > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > >
> > > > Do you really mean to do this twice?
> > >
> > > unfortunately, yes. since some settings in the board config are turned
> > > into compiler flags and those compiler flags can in turn affect the board
> > > config, we need to do it twice. first is to make sure the proper cpu
> > > flags are propagated into the toplevel build env while the second is to
> > > make sure the autoconf.mk fully reflects the board config.
> >
> > Sounds like a design problem to me.
>
> not really. the point is to avoid duplication and considering the method to
> attain that, sounds pretty good to me.
Well, no othe rarchitecture seems to need that, and it looks very
strange. I guess 4 out of 5 persons who will see this are tempted to
"clean this up".
> > That would be the minimum, but given the fact that the top level
> > Makefile already includes rules to build autoconf.mk I really wonder
> > if we must do this so often, and if so, then why this is only the
> > case for blackfin.
>
> the top level Makefile includes rules to build it, but it doesnt re-source it
> once it's been generated. so anything in the top level cannot use things from
> autoconf.mk (like $(arch)_config.mk).
To me it seems as if you were rebuilding it twice without re-sourcing
it inbetween, too.
And you fail to explain why BF needs this, while all other
architectures don't.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The software required `Windows 95 or better', so I installed Linux.
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-11 21:36 ` Wolfgang Denk
@ 2009-02-11 21:54 ` Mike Frysinger
2009-02-11 22:16 ` Wolfgang Denk
0 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-11 21:54 UTC (permalink / raw)
To: u-boot
On Wednesday 11 February 2009 16:36:37 Wolfgang Denk wrote:
> Dear Mike Frysinger,
>
> In message <200902101449.24108.vapier@gentoo.org> you wrote:
> > > > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > > > > + @$(MAKE) -s -B $(obj)include/autoconf.mk
> > > > >
> > > > > Do you really mean to do this twice?
> > > >
> > > > unfortunately, yes. since some settings in the board config are
> > > > turned into compiler flags and those compiler flags can in turn
> > > > affect the board config, we need to do it twice. first is to make
> > > > sure the proper cpu flags are propagated into the toplevel build env
> > > > while the second is to make sure the autoconf.mk fully reflects the
> > > > board config.
> > >
> > > Sounds like a design problem to me.
> >
> > not really. the point is to avoid duplication and considering the method
> > to attain that, sounds pretty good to me.
>
> Well, no othe rarchitecture seems to need that, and it looks very
> strange. I guess 4 out of 5 persons who will see this are tempted to
> "clean this up".
that's why i said i would add comments. they're in there now and anyone
touching code that doesnt belong to them while ignoring the comments shouldnt
be doing clean up work in the first place.
> > > That would be the minimum, but given the fact that the top level
> > > Makefile already includes rules to build autoconf.mk I really wonder
> > > if we must do this so often, and if so, then why this is only the
> > > case for blackfin.
> >
> > the top level Makefile includes rules to build it, but it doesnt
> > re-source it once it's been generated. so anything in the top level
> > cannot use things from autoconf.mk (like $(arch)_config.mk).
>
> To me it seems as if you were rebuilding it twice without re-sourcing
> it inbetween, too.
>
> And you fail to explain why BF needs this, while all other
> architectures don't.
i explained it already when Ben asked. the processor variant is selected in
the board config and the board config (and shared settings) can change based
on that selection. and the top level build flags use that processor
selection. first one is to make sure the cpu settings make it from the board
config into the environment while the second is to make sure the board config
has been fully processed by the proper cpu selection.
also, other people dont seem to have a problem sprinkling duplication over the
place until things work. i do.
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-11 21:54 ` Mike Frysinger
@ 2009-02-11 22:16 ` Wolfgang Denk
2009-02-11 22:57 ` Mike Frysinger
0 siblings, 1 reply; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-11 22:16 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <200902111654.20726.vapier@gentoo.org> you wrote:
>
> > And you fail to explain why BF needs this, while all other
> > architectures don't.
>
> i explained it already when Ben asked. the processor variant is selected in
> the board config and the board config (and shared settings) can change based
> on that selection. and the top level build flags use that processor
If you define the processor variant right at the beginning of the
board config file, then why would that not be visible in the
remainder of the board config so you'd have to re-run this?
> selection. first one is to make sure the cpu settings make it from the board
> config into the environment while the second is to make sure the board config
> has been fully processed by the proper cpu selection.
I still don;t get why BF has such a problem while none of the N other
arches has it?
> also, other people dont seem to have a problem sprinkling duplication over the
> place until things work. i do.
What exactly are you referring to here?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
2000 pounds of chinese soup = 1 Won Ton
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-11 22:16 ` Wolfgang Denk
@ 2009-02-11 22:57 ` Mike Frysinger
2009-02-12 0:16 ` Wolfgang Denk
0 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-11 22:57 UTC (permalink / raw)
To: u-boot
On Wednesday 11 February 2009 17:16:38 Wolfgang Denk wrote:
> In message Mike Frysinger you wrote:
> > > And you fail to explain why BF needs this, while all other
> > > architectures don't.
> >
> > i explained it already when Ben asked. the processor variant is selected
> > in the board config and the board config (and shared settings) can change
> > based on that selection. and the top level build flags use that
> > processor
>
> If you define the processor variant right at the beginning of the
> board config file, then why would that not be visible in the
> remainder of the board config so you'd have to re-run this?
that's a string representation that defines (1) the variant and (2) the
silicon revision. that gets turned into CFLAGS via -mcpu=... and the
toolchain itself then sets up the proper defines which everything else uses.
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough
2009-02-11 22:57 ` Mike Frysinger
@ 2009-02-12 0:16 ` Wolfgang Denk
0 siblings, 0 replies; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-12 0:16 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <200902111757.21416.vapier@gentoo.org> you wrote:
>
> > If you define the processor variant right at the beginning of the
> > board config file, then why would that not be visible in the
> > remainder of the board config so you'd have to re-run this?
>
> that's a string representation that defines (1) the variant and (2) the
> silicon revision. that gets turned into CFLAGS via -mcpu=... and the
> toolchain itself then sets up the proper defines which everything else uses.
Sorry, I still fail to see in which way this is different for BF than
for any other architecture?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The glory of creation is in its infinite diversity." "And in the way
our differences combine to create meaning and beauty."
-- Dr. Miranda Jones and Spock, "Is There in Truth No Beauty?",
stardate 5630.8
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 19/42] Blackfin: new spibootldr command
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (17 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 18/42] Blackfin: make sure autoconf.mk is generated early enough Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 20/42] Blackfin: add clkin_hz= to default kernel command line for ADI boards Mike Frysinger
` (22 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Newer Blackfin parts can an on-chip ROM that can boot LDRs over SPI flashes,
so add a new 'spibootldr' command to take advantage of it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
common/Makefile | 1 +
common/cmd_spibootldr.c | 36 +++++++++++++++++++++++
include/asm-blackfin/mach-common/bits/bootrom.h | 27 +++++++++++++++++
include/configs/bfin_adi_common.h | 1 +
4 files changed, 65 insertions(+), 0 deletions(-)
create mode 100644 common/cmd_spibootldr.c
diff --git a/common/Makefile b/common/Makefile
index 93e3963..2a5ab9d 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -126,6 +126,7 @@ COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
+COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
diff --git a/common/cmd_spibootldr.c b/common/cmd_spibootldr.c
new file mode 100644
index 0000000..acd6b43
--- /dev/null
+++ b/common/cmd_spibootldr.c
@@ -0,0 +1,36 @@
+/*
+ * U-boot - spibootldr.c
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
+
+int do_spibootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ s32 addr;
+
+ /* Get the address */
+ if (argc < 2)
+ addr = 0;
+ else
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ printf("## Booting ldr image at SPI offset 0x%x ...\n", addr);
+
+ return bfrom_SpiBoot(addr, BFLAG_PERIPHERAL | 4, 0, NULL);
+}
+
+U_BOOT_CMD(spibootldr, 2, 0, do_spibootldr,
+ "spibootldr - boot ldr image from spi\n",
+ "[offset]\n"
+ " - boot ldr image stored@offset into spi\n");
diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h
index fb97ff8..f537e93 100644
--- a/include/asm-blackfin/mach-common/bits/bootrom.h
+++ b/include/asm-blackfin/mach-common/bits/bootrom.h
@@ -200,6 +200,33 @@ typedef struct ADI_BOOT_DATA {
int32_t dLogByteCount;
} ADI_BOOT_DATA;
+typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *);
+
+#ifndef _BOOTROM_MEMBOOT
+#define _BOOTROM_MEMBOOT 0
+#endif
+static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT;
+
+#ifndef _BOOTROM_TWIBOOT
+#define _BOOTROM_TWIBOOT 0
+#endif
+static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT;
+
+#ifndef _BOOTROM_SPIBOOT
+#define _BOOTROM_SPIBOOT 0
+#endif
+static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT;
+
+#ifndef _BOOTROM_OTPBOOT
+#define _BOOTROM_OTPBOOT 0
+#endif
+static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT;
+
+#ifndef _BOOTROM_NANDBOOT
+#define _BOOTROM_NANDBOOT 0
+#endif
+static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT;
+
#endif /* __ASSEMBLY__ */
/* Bit defines for ADI_BOOT_DATA->dFlags */
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index e40bb2c..b714d32 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -71,6 +71,7 @@
# define CONFIG_CMD_STRINGS
# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
# define CONFIG_CMD_OTP
+# define CONFIG_CMD_SPIBOOTLDR
# endif
#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 20/42] Blackfin: add clkin_hz= to default kernel command line for ADI boards
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (18 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 19/42] Blackfin: new spibootldr command Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:20 ` [U-Boot] [PATCH 21/42] Blackfin: bf537-stamp: bump default SCLK up to 125MHz Mike Frysinger
` (21 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/configs/bfin_adi_common.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index b714d32..c89253d 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -111,6 +111,7 @@
#endif
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
+ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
"uart" MK_STR(CONFIG_UART_CONSOLE) "," \
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 21/42] Blackfin: bf537-stamp: bump default SCLK up to 125MHz
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (19 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 20/42] Blackfin: add clkin_hz= to default kernel command line for ADI boards Mike Frysinger
@ 2009-02-10 6:20 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 22/42] Blackfin: bf537-stamp: increase monitor size Mike Frysinger
` (20 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:20 UTC (permalink / raw)
To: u-boot
Since all of the bf537-stamp and bf537-ezkit boards out there can handle it,
increase the speed of SCLK to 125MHz rather than 100MHz.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/configs/bf537-stamp.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index e0b107b..5be2748 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -36,7 +36,7 @@
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
+#define CONFIG_SCLK_DIV 4
/*
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 22/42] Blackfin: bf537-stamp: increase monitor size
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (20 preceding siblings ...)
2009-02-10 6:20 ` [U-Boot] [PATCH 21/42] Blackfin: bf537-stamp: bump default SCLK up to 125MHz Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 23/42] Blackfin: add hack for crappy m25p80 Mike Frysinger
` (19 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
The new jffs2 code pushed the code size just over the limit, so increase
the limit a bit more.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
include/configs/bf537-stamp.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 5be2748..0339a80 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -52,7 +52,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 23/42] Blackfin: add hack for crappy m25p80
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (21 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 22/42] Blackfin: bf537-stamp: increase monitor size Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 24/42] Blackfin: add support for SST SPI flashes Mike Frysinger
` (18 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
board/bf537-stamp/spi_flash.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index 7b764b4..797daf2 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -51,6 +51,7 @@ static struct flash_info flash_st_serial_flash[] = {
{ "m25p10", 0x2011, 32 * 1024, 4 },
{ "m25p20", 0x2012, 64 * 1024, 4 },
{ "m25p40", 0x2013, 64 * 1024, 8 },
+ { "m25p80", 0x20FF, 64 * 1024, 16 },
{ "m25p16", 0x2015, 64 * 1024, 32 },
{ "m25p32", 0x2016, 64 * 1024, 64 },
{ "m25p64", 0x2017, 64 * 1024, 128 },
@@ -309,6 +310,11 @@ static int spi_detect_part(void)
if (called_init)
return 0;
+#ifdef CONFIG_SPI_FLASH_M25P80
+ flash.manufacturer_id = JED_MANU_ST;
+ flash.device_id1 = 0x20;
+ flash.device_id2 = 0xFF;
+#else
SPI_ON();
/* Send the request for the part identification */
@@ -328,6 +334,7 @@ static int spi_detect_part(void)
flash.device_id2 = spi_write_read_byte(0);
SPI_OFF();
+#endif
dev_id = (flash.device_id1 << 8) | flash.device_id2;
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 24/42] Blackfin: add support for SST SPI flashes
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (22 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 23/42] Blackfin: add hack for crappy m25p80 Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 25/42] Blackfin: overhaul SPI flash handling to speed things up Mike Frysinger
` (17 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
board/bf537-stamp/spi_flash.c | 107 ++++++++++++++++++++++++++++++-----------
1 files changed, 78 insertions(+), 29 deletions(-)
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index 797daf2..a336894 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -59,6 +59,15 @@ static struct flash_info flash_st_serial_flash[] = {
{ NULL, 0, 0, 0 }
};
+/* SPI Speeds: 20 MHz / 40 MHz */
+static struct flash_info flash_sst_serial_flash[] = {
+ { "SST25WF512", 0x2501, 4 * 1024, 128 },
+ { "SST25WF010", 0x2502, 4 * 1024, 256 },
+ { "SST25WF020", 0x2503, 4 * 1024, 512 },
+ { "SST25WF040", 0x2504, 4 * 1024, 1024 },
+ { NULL, 0, 0, 0 }
+};
+
/* SPI Speeds: 66 MHz / 33 MHz */
static struct flash_info flash_atmel_dataflash[] = {
{ "AT45DB011x", 0x0c, 264, 512 },
@@ -98,6 +107,13 @@ static struct flash_ops flash_st_ops = {
.status = 0x05,
};
+static struct flash_ops flash_sst_ops = {
+ .read = OP_READ,
+ .write = 0x02,
+ .erase = 0x20,
+ .status = 0x05,
+};
+
static struct flash_ops flash_atmel_ops = {
.read = OP_READ,
.write = 0x82,
@@ -131,6 +147,7 @@ static struct {
enum {
JED_MANU_SPANSION = 0x01,
JED_MANU_ST = 0x20,
+ JED_MANU_SST = 0xBF,
JED_MANU_ATMEL = 0x1F,
JED_MANU_WINBOND = 0xEF,
};
@@ -149,6 +166,12 @@ static struct manufacturer_info flash_manufacturers[] = {
.ops = &flash_st_ops,
},
{
+ .name = "SST",
+ .id = JED_MANU_SST,
+ .flashes = flash_sst_serial_flash,
+ .ops = &flash_sst_ops,
+ },
+ {
.name = "Atmel",
.id = JED_MANU_ATMEL,
.flashes = flash_atmel_dataflash,
@@ -276,6 +299,7 @@ static int wait_for_ready_status(void)
switch (flash.manufacturer_id) {
case JED_MANU_SPANSION:
case JED_MANU_ST:
+ case JED_MANU_SST:
case JED_MANU_WINBOND:
if (!(read_status_register() & 0x01))
return 0;
@@ -297,6 +321,50 @@ static int wait_for_ready_status(void)
return -1;
}
+static int enable_writing(void)
+{
+ ulong start;
+
+ if (flash.manufacturer_id == JED_MANU_ATMEL)
+ return 0;
+
+ /* A write enable instruction must previously have been executed */
+ SPI_ON();
+ spi_write_read_byte(0x06);
+ SPI_OFF();
+
+ /* The status register will be polled to check the write enable latch "WREN" */
+ start = get_timer(0);
+ while (get_timer(0) - start < TIMEOUT) {
+ if (read_status_register() & 0x02)
+ return 0;
+
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return -1;
+ }
+ }
+
+ puts("Timeout\n");
+ return -1;
+}
+
+static void write_status_register(uint8_t val)
+{
+ if (flash.manufacturer_id != JED_MANU_SST)
+ hang();
+
+ if (enable_writing())
+ return;
+
+ /* send instruction to write status register */
+ SPI_ON();
+ spi_write_read_byte(0x01);
+ /* and clear it! */
+ spi_write_read_byte(val);
+ SPI_OFF();
+}
+
/* Request and read the manufacturer and device id of parts which
* are compatible with the JEDEC standard (JEP106) and use that to
* setup other operating conditions.
@@ -351,6 +419,7 @@ static int spi_detect_part(void)
switch (flash.manufacturer_id) {
case JED_MANU_SPANSION:
case JED_MANU_ST:
+ case JED_MANU_SST:
case JED_MANU_WINBOND:
for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
if (dev_id == flash.manufacturer->flashes[i].id)
@@ -362,7 +431,11 @@ static int spi_detect_part(void)
flash.flash = &flash.manufacturer->flashes[i];
flash.sector_size = flash.flash->sector_size;
flash.num_sectors = flash.flash->num_sectors;
- flash.write_length = 256;
+
+ if (flash.manufacturer_id == JED_MANU_SST)
+ flash.write_length = 1; /* pwnt :( */
+ else
+ flash.write_length = 256;
break;
case JED_MANU_ATMEL: {
@@ -388,6 +461,10 @@ static int spi_detect_part(void)
}
}
+ /* the SST parts power up with software protection enabled by default */
+ if (flash.manufacturer_id == JED_MANU_SST)
+ write_status_register(0);
+
called_init = 1;
return 0;
@@ -572,34 +649,6 @@ static int read_flash(unsigned long address, long count, uchar *buffer)
return 0;
}
-static int enable_writing(void)
-{
- ulong start;
-
- if (flash.manufacturer_id == JED_MANU_ATMEL)
- return 0;
-
- /* A write enable instruction must previously have been executed */
- SPI_ON();
- spi_write_read_byte(0x06);
- SPI_OFF();
-
- /* The status register will be polled to check the write enable latch "WREN" */
- start = get_timer(0);
- while (get_timer(0) - start < TIMEOUT) {
- if (read_status_register() & 0x02)
- return 0;
-
- if (ctrlc()) {
- puts("\nAbort\n");
- return -1;
- }
- }
-
- puts("Timeout\n");
- return -1;
-}
-
static long address_to_sector(unsigned long address)
{
if (address > (flash.num_sectors * flash.sector_size) - 1)
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 25/42] Blackfin: overhaul SPI flash handling to speed things up
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (23 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 24/42] Blackfin: add support for SST SPI flashes Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 26/42] Blackfin: add support for S25FL128 parts Mike Frysinger
` (16 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
board/bf537-stamp/spi_flash.c | 132 +++++++++++++++++++++++++++++++++++++++--
1 files changed, 126 insertions(+), 6 deletions(-)
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index a336894..214981a 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -18,6 +18,7 @@
#include <malloc.h>
#include <asm/io.h>
#include <asm/mach-common/bits/spi.h>
+#include <asm/mach-common/bits/dma.h>
/* Forcibly phase out these */
#ifdef CONFIG_SPI_FLASH_NUM_SECTORS
@@ -185,7 +186,7 @@ static struct manufacturer_info flash_manufacturers[] = {
},
};
-#define TIMEOUT 5000 /* timeout of 5 seconds */
+#define TIMEOUT 5000 /* timeout of 5 seconds */
/* If part has multiple SPI flashes, assume SPI0 as that is
* the one we can boot off of ...
@@ -213,6 +214,7 @@ static void SPI_INIT(void)
/* [#3541] This delay appears to be necessary, but not sure
* exactly why as the history behind it is non-existant.
*/
+ *pSPI_CTL = 0;
udelay(CONFIG_CCLK_HZ / 25000000);
/* enable SPI pins: SSEL, MOSI, MISO, SCK */
@@ -229,14 +231,13 @@ static void SPI_INIT(void)
#endif
/* initate communication upon write of TDBR */
- *pSPI_CTL = (SPE|MSTR|CPHA|CPOL|0x01);
+ *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
*pSPI_BAUD = CONFIG_SPI_BAUD;
}
static void SPI_DEINIT(void)
{
- /* put SPI settings back to reset state */
- *pSPI_CTL = 0x0400;
+ *pSPI_CTL = 0;
*pSPI_BAUD = 0;
SSYNC();
}
@@ -622,9 +623,10 @@ static void transmit_address(uint32_t addr)
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
*/
+#ifdef CONFIG_SPI_READFLASH_NODMA
static int read_flash(unsigned long address, long count, uchar *buffer)
{
- size_t i;
+ size_t i, j;
/* Send the read command to SPI device */
SPI_ON();
@@ -638,16 +640,134 @@ static int read_flash(unsigned long address, long count, uchar *buffer)
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
+ j = flash.sector_size << 1;
for (i = 1; i <= count; ++i) {
*buffer++ = spi_write_read_byte(0);
- if (i % flash.sector_size == 0)
+ if (!j--) {
puts(".");
+ j = flash.sector_size;
+ }
+ }
+
+ SPI_OFF();
+
+ return 0;
+}
+#else
+
+#ifdef __ADSPBF54x__
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG
+#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
+ defined(__ADSPBF538__) || defined(__ADSPBF539__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG
+#elif defined(__ADSPBF561__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
+ defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS
+#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS
+#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR
+#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG
+#else
+#error "Please provide SPI DMA channel defines"
+#endif
+
+struct dmadesc_array {
+ unsigned long start_addr;
+ unsigned short cfg;
+ unsigned short x_count;
+ short x_modify;
+ unsigned short y_count;
+ short y_modify;
+} __attribute__((packed));
+
+/*
+ * Read a value from flash for verify purpose
+ * Inputs: unsigned long ulStart - holds the SPI start address
+ * int pnData - pointer to store value read from flash
+ * long lCount - number of elements to read
+ */
+
+static int read_flash(unsigned long address, long count, uchar *buffer)
+{
+ unsigned int ndsize;
+ struct dmadesc_array dma[2];
+ /* Send the read command to SPI device */
+
+ if (!count)
+ return 0;
+
+ dma[0].start_addr = (unsigned long)buffer;
+ dma[0].x_modify = 1;
+ if (count <= 65536) {
+ blackfin_dcache_flush_invalidate_range(buffer, buffer + count);
+ ndsize = NDSIZE_5;
+ dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
+ dma[0].x_count = count;
+ } else {
+ blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1);
+ ndsize = NDSIZE_7;
+ dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D;
+ dma[0].x_count = 0; /* 2^16 */
+ dma[0].y_count = count >> 16; /* count / 2^16 */
+ dma[0].y_modify = 1;
+ dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF));
+ dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN;
+ dma[1].x_count = count & 0xFFFF; /* count % 2^16 */
+ dma[1].x_modify = 1;
}
+ bfin_write_DMA_SPI_CONFIG(0);
+ bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_DMA_SPI_CURR_DESC_PTR(dma);
+
+ SPI_ON();
+
+ spi_write_read_byte(flash.ops->read);
+ transmit_address(address);
+
+#ifndef CONFIG_SPI_FLASH_SLOW_READ
+ /* Send dummy byte when doing SPI fast reads */
+ spi_write_read_byte(0);
+#endif
+
+ bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN);
+ *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ);
+ SSYNC();
+
+ /*
+ * We already invalidated the first 64k,
+ * now while we just wait invalidate the remaining part.
+ * Its not likely that the DMA is going to overtake
+ */
+ if (count > 65536)
+ blackfin_dcache_flush_invalidate_range(buffer + 65536,
+ buffer + count);
+
+ while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE))
+ if (ctrlc())
+ break;
+
SPI_OFF();
+ *pSPI_CTL = 0;
+
+ bfin_write_DMA_SPI_CONFIG(0);
+
+ *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE);
+
return 0;
}
+#endif
static long address_to_sector(unsigned long address)
{
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 26/42] Blackfin: add support for S25FL128 parts
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (24 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 25/42] Blackfin: overhaul SPI flash handling to speed things up Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 27/42] Blackfin: bf548-ezkit: new board port Mike Frysinger
` (15 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
board/bf537-stamp/spi_flash.c | 85 ++++++++++++++++++++++------------------
1 files changed, 47 insertions(+), 38 deletions(-)
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index 214981a..7b753ad 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -33,63 +33,65 @@
struct flash_info {
char *name;
uint16_t id;
+ uint16_t ext_id;
unsigned sector_size;
unsigned num_sectors;
};
/* SPI Speeds: 50 MHz / 33 MHz */
static struct flash_info flash_spansion_serial_flash[] = {
- { "S25FL016", 0x0215, 64 * 1024, 32 },
- { "S25FL032", 0x0216, 64 * 1024, 64 },
- { "S25FL064", 0x0217, 64 * 1024, 128 },
- { "S25FL0128", 0x0218, 256 * 1024, 64 },
- { NULL, 0, 0, 0 }
+ { "S25FL016", 0x0215, 0, 64 * 1024, 32 },
+ { "S25FL032", 0x0216, 0, 64 * 1024, 64 },
+ { "S25FL064", 0x0217, 0, 64 * 1024, 128 },
+ { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */
+ { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speeds: 50 MHz / 20 MHz */
static struct flash_info flash_st_serial_flash[] = {
- { "m25p05", 0x2010, 32 * 1024, 2 },
- { "m25p10", 0x2011, 32 * 1024, 4 },
- { "m25p20", 0x2012, 64 * 1024, 4 },
- { "m25p40", 0x2013, 64 * 1024, 8 },
- { "m25p80", 0x20FF, 64 * 1024, 16 },
- { "m25p16", 0x2015, 64 * 1024, 32 },
- { "m25p32", 0x2016, 64 * 1024, 64 },
- { "m25p64", 0x2017, 64 * 1024, 128 },
- { "m25p128", 0x2018, 256 * 1024, 64 },
- { NULL, 0, 0, 0 }
+ { "m25p05", 0x2010, 0, 32 * 1024, 2 },
+ { "m25p10", 0x2011, 0, 32 * 1024, 4 },
+ { "m25p20", 0x2012, 0, 64 * 1024, 4 },
+ { "m25p40", 0x2013, 0, 64 * 1024, 8 },
+ { "m25p80", 0x20FF, 0, 64 * 1024, 16 },
+ { "m25p16", 0x2015, 0, 64 * 1024, 32 },
+ { "m25p32", 0x2016, 0, 64 * 1024, 64 },
+ { "m25p64", 0x2017, 0, 64 * 1024, 128 },
+ { "m25p128", 0x2018, 0, 256 * 1024, 64 },
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speeds: 20 MHz / 40 MHz */
static struct flash_info flash_sst_serial_flash[] = {
- { "SST25WF512", 0x2501, 4 * 1024, 128 },
- { "SST25WF010", 0x2502, 4 * 1024, 256 },
- { "SST25WF020", 0x2503, 4 * 1024, 512 },
- { "SST25WF040", 0x2504, 4 * 1024, 1024 },
- { NULL, 0, 0, 0 }
+ { "SST25WF512", 0x2501, 0, 4 * 1024, 128 },
+ { "SST25WF010", 0x2502, 0, 4 * 1024, 256 },
+ { "SST25WF020", 0x2503, 0, 4 * 1024, 512 },
+ { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 },
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speeds: 66 MHz / 33 MHz */
static struct flash_info flash_atmel_dataflash[] = {
- { "AT45DB011x", 0x0c, 264, 512 },
- { "AT45DB021x", 0x14, 264, 1025 },
- { "AT45DB041x", 0x1c, 264, 2048 },
- { "AT45DB081x", 0x24, 264, 4096 },
- { "AT45DB161x", 0x2c, 528, 4096 },
- { "AT45DB321x", 0x34, 528, 8192 },
- { "AT45DB642x", 0x3c, 1056, 8192 },
- { NULL, 0, 0, 0 }
+ { "AT45DB011x", 0x0c, 0, 264, 512 },
+ { "AT45DB021x", 0x14, 0, 264, 1025 },
+ { "AT45DB041x", 0x1c, 0, 264, 2048 },
+ { "AT45DB081x", 0x24, 0, 264, 4096 },
+ { "AT45DB161x", 0x2c, 0, 528, 4096 },
+ { "AT45DB321x", 0x34, 0, 528, 8192 },
+ { "AT45DB642x", 0x3c, 0, 1056, 8192 },
+ { NULL, 0, 0, 0, 0 }
};
/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */
static struct flash_info flash_winbond_serial_flash[] = {
- { "W25X10", 0x3011, 16 * 256, 32 },
- { "W25X20", 0x3012, 16 * 256, 64 },
- { "W25X40", 0x3013, 16 * 256, 128 },
- { "W25X80", 0x3014, 16 * 256, 256 },
- { "W25P80", 0x2014, 256 * 256, 16 },
- { "W25P16", 0x2015, 256 * 256, 32 },
- { NULL, 0, 0, 0 }
+ { "W25X10", 0x3011, 0, 16 * 256, 32 },
+ { "W25X20", 0x3012, 0, 16 * 256, 64 },
+ { "W25X40", 0x3013, 0, 16 * 256, 128 },
+ { "W25X80", 0x3014, 0, 16 * 256, 256 },
+ { "W25P80", 0x2014, 0, 256 * 256, 16 },
+ { "W25P16", 0x2015, 0, 256 * 256, 32 },
+ { NULL, 0, 0, 0, 0 }
};
struct flash_ops {
@@ -140,7 +142,7 @@ static struct {
struct manufacturer_info *manufacturer;
struct flash_info *flash;
struct flash_ops *ops;
- uint8_t manufacturer_id, device_id1, device_id2;
+ uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2;
unsigned int write_length;
unsigned long sector_size, num_sectors;
} flash;
@@ -372,7 +374,7 @@ static void write_status_register(uint8_t val)
*/
static int spi_detect_part(void)
{
- uint16_t dev_id;
+ uint16_t dev_id, dev_extid;
size_t i;
static char called_init;
@@ -402,10 +404,15 @@ static int spi_detect_part(void)
/* Now read in the second device id byte */
flash.device_id2 = spi_write_read_byte(0);
+ /* Read extended device ids */
+ flash.device_extid1 = spi_write_read_byte(0);
+ flash.device_extid2 = spi_write_read_byte(0);
+
SPI_OFF();
#endif
dev_id = (flash.device_id1 << 8) | flash.device_id2;
+ dev_extid = (flash.device_extid1 << 8) | flash.device_extid2;
for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) {
if (flash.manufacturer_id == flash_manufacturers[i].id)
@@ -423,7 +430,9 @@ static int spi_detect_part(void)
case JED_MANU_SST:
case JED_MANU_WINBOND:
for (i = 0; flash.manufacturer->flashes[i].name; ++i) {
- if (dev_id == flash.manufacturer->flashes[i].id)
+ if (dev_id == flash.manufacturer->flashes[i].id &&
+ (flash.manufacturer->flashes[i].ext_id == 0 ||
+ flash.manufacturer->flashes[i].ext_id == dev_extid))
break;
}
if (!flash.manufacturer->flashes[i].name)
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 27/42] Blackfin: bf548-ezkit: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (25 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 26/42] Blackfin: add support for S25FL128 parts Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 28/42] Blackfin: bf527-ezkit: " Mike Frysinger
` (14 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/bf548-ezkit/.gitignore | 1 +
board/bf548-ezkit/Makefile | 59 +++++++
board/bf548-ezkit/bf548-ezkit.c | 79 ++++++++++
board/bf548-ezkit/config.mk | 37 +++++
board/bf548-ezkit/spi_flash.c | 2 +
board/bf548-ezkit/u-boot.lds.S | 124 +++++++++++++++
board/bf548-ezkit/video.c | 327 +++++++++++++++++++++++++++++++++++++++
include/configs/bf548-ezkit.h | 201 ++++++++++++++++++++++++
11 files changed, 834 insertions(+), 2 deletions(-)
create mode 100644 board/bf548-ezkit/.gitignore
create mode 100644 board/bf548-ezkit/Makefile
create mode 100644 board/bf548-ezkit/bf548-ezkit.c
create mode 100644 board/bf548-ezkit/config.mk
create mode 100644 board/bf548-ezkit/spi_flash.c
create mode 100644 board/bf548-ezkit/u-boot.lds.S
create mode 100644 board/bf548-ezkit/video.c
create mode 100644 include/configs/bf548-ezkit.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 38feac8..59da854 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -848,6 +848,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-STAMP BF537
+ BF548-EZKIT BF548
BF561-EZKIT BF561
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index cf05133..3f3170c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -783,6 +783,7 @@ LIST_blackfin=" \
bf533-ezkit \
bf533-stamp \
bf537-stamp \
+ bf548-ezkit \
bf561-ezkit \
"
diff --git a/Makefile b/Makefile
index db77d3b..c209e53 100644
--- a/Makefile
+++ b/Makefile
@@ -3289,7 +3289,7 @@ suzaku_config: unconfig
#========================================================================
# Analog Devices boards
-BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit
+BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3452,7 +3452,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds \
+ $(obj)board/{bf5{33,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf548-ezkit/.gitignore b/board/bf548-ezkit/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf548-ezkit/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
new file mode 100644
index 0000000..e86e19d
--- /dev/null
+++ b/board/bf548-ezkit/Makefile
@@ -0,0 +1,59 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_VIDEO) += video.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
new file mode 100644
index 0000000..74f93ba
--- /dev/null
+++ b/board/bf548-ezkit/bf548-ezkit.c
@@ -0,0 +1,79 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF548 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+int board_early_init_f(void)
+{
+ /* Port H: PH8 - PH13 == A4 - A9
+ * address lines of the parallel asynchronous memory interface
+ */
+
+ /************************************************
+ * configure GPIO *
+ * set port H function enable register *
+ * configure PH8-PH13 as peripheral (not GPIO) *
+ *************************************************/
+ bfin_write_PORTH_FER(0x3F03);
+
+ /************************************************
+ * set port H MUX to configure PH8-PH13 *
+ * 1st Function (MUX = 00) (bits 16-27 == 0) *
+ * Set to address signals A4-A9 *
+ *************************************************/
+ bfin_write_PORTH_MUX(0);
+
+ /************************************************
+ * set port H direction register *
+ * enable PH8-PH13 as outputs *
+ *************************************************/
+ bfin_write_PORTH_DIR_SET(0x3F00);
+
+ /* Port I: PI0 - PH14 == A10 - A24
+ * address lines of the parallel asynchronous memory interface
+ */
+
+ /************************************************
+ * set port I function enable register *
+ * configure PI0-PI14 as peripheral (not GPIO) *
+ *************************************************/
+ bfin_write_PORTI_FER(0x7fff);
+
+ /**************************************************
+ * set PORT I MUX to configure PI14-PI0 as *
+ * 1st Function (MUX=00) - address signals A10-A24 *
+ ***************************************************/
+ bfin_write_PORTI_MUX(0);
+
+ /****************************************
+ * set PORT I direction register *
+ * enable PI0 - PI14 as outputs *
+ *****************************************/
+ bfin_write_PORTI_DIR_SET(0x7fff);
+
+ return 0;
+}
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
new file mode 100644
index 0000000..8b471f6
--- /dev/null
+++ b/board/bf548-ezkit/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART := --dma 1
+LDR_FLAGS-BFIN_BOOT_NAND := --dma 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf548-ezkit/spi_flash.c b/board/bf548-ezkit/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf548-ezkit/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf548-ezkit/u-boot.lds.S b/board/bf548-ezkit/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/bf548-ezkit/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
new file mode 100644
index 0000000..a6f52bd
--- /dev/null
+++ b/board/bf548-ezkit/video.c
@@ -0,0 +1,327 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES 480 /*Horizontal Resolution */
+#define LCD_Y_RES 272 /* Vertical Resolution */
+
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+#define DMA_BUS_SIZE 32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* -- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period TH - 525 - Clock
+ * Pulse width THp - 41 - Clock
+ * Horizontal period THd - 480 - Clock
+ * Back porch THb - 2 - Clock
+ * Front porch THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period TV - 286 - Line
+ * Pulse width TVp - 10 - Line
+ * Vertical period TVd - 272 - Line
+ * Back porch TVb - 2 - Line
+ * Front porch TVf - 2 - Line
+ */
+
+#define LCD_CLK (8*1000*1000) /* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE 525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME 286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL 41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY 43
+
+/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB (EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY 12
+
+#define EPPI_CLIP 0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL (0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+ u32 sclk = get_sclk();
+
+ /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+ return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+ u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+ bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+ bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+ bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+ bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+ bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+ bfin_write_EPPI0_FRAME(EPPI_FRAME);
+ bfin_write_EPPI0_LINE(EPPI_LINE);
+
+ bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+ bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+ bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+ bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+ bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+ bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+ RGB_FMT_EN);
+#else
+ bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+ ~RGB_FMT_EN);
+#endif
+
+}
+
+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+
+#if defined(CONFIG_DEB_DMA_URGENT)
+ *pEBIU_DDRQUE |= DEB2_URGENT;
+#endif
+
+ *pDMA12_START_ADDR = dst;
+
+ /* X count */
+ *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
+ *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* Y count */
+ *pDMA12_Y_COUNT = LCD_Y_RES;
+ *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* DMA Config */
+ *pDMA12_CONFIG =
+ WDSIZE_32 | /* 32 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO; /* autobuffer mode */
+}
+
+void Init_Ports(void)
+{
+ *pPORTF_MUX = 0x00000000;
+ *pPORTF_FER |= 0xFFFF; /* PPI0..15 */
+
+ *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
+ *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */
+
+#if !defined(CONFIG_VIDEO_RGB666)
+ *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
+ *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
+ *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */
+#endif
+
+ *pPORTE_FER &= ~PE3; /* DISP */
+ *pPORTE_DIR_SET = PE3;
+ *pPORTE_SET = PE3;
+
+}
+
+void EnableDMA(void)
+{
+ *pDMA12_CONFIG |= DMAEN;
+}
+
+void DisableDMA(void)
+{
+ *pDMA12_CONFIG &= ~DMAEN;
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ Init_PPI();
+ EnablePPI();
+
+ return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ device_t videodev;
+
+ u8 *dst;
+ u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+ bfin_logo.data = data;
+#endif
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+ videodev.putc = video_putc; /* 'putc' function */
+ videodev.puts = video_puts; /* 'puts' function */
+
+ error = device_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
new file mode 100644
index 0000000..037514b
--- /dev/null
+++ b/include/configs/bf548-ezkit.h
@@ -0,0 +1,201 @@
+/*
+ * U-boot - Configuration file for BF548 STAMP board
+ */
+
+#ifndef __CONFIG_BF548_EZKIT_H__
+#define __CONFIG_BF548_EZKIT_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf548-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
+#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
+#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
+
+/* Default EZ-Kit bank mapping:
+ * Async Bank 0 - 32MB Burst Flash
+ * Async Bank 1 - Ethernet
+ * Async Bank 2 - Nothing
+ * Async Bank 3 - Nothing
+ */
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
+#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
+#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_HOSTNAME bf548-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define ENV_IS_EMBEDDED_CUSTOM
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20002000
+#define CONFIG_ENV_OFFSET 0x2000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_CMD_NAND
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * SATA
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_LIBATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_LBA48
+#define CONFIG_PATA_BFIN
+#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
+#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
+#endif
+
+
+/*
+ * SDH Settings
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+#endif
+
+
+/*
+ * USB Setting
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_USB
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_BLACKFIN
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 1
+
+#ifndef __ADSPBF542__
+/* Don't waste time transferring a logo over the UART */
+# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+# define CONFIG_VIDEO
+# endif
+# define CONFIG_DEB_DMA_URGENT
+#endif
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 28/42] Blackfin: bf527-ezkit: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (26 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 27/42] Blackfin: bf548-ezkit: new board port Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 29/42] Blackfin: bf538f-ezkit: " Mike Frysinger
` (13 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 5 +-
board/bf527-ezkit/.gitignore | 1 +
board/bf527-ezkit/Makefile | 59 +++++++
board/bf527-ezkit/bf527-ezkit.c | 60 ++++++++
board/bf527-ezkit/config.mk | 32 ++++
board/bf527-ezkit/spi_flash.c | 2 +
board/bf527-ezkit/u-boot.lds.S | 124 +++++++++++++++
board/bf527-ezkit/video.c | 317 +++++++++++++++++++++++++++++++++++++++
include/configs/bf527-ezkit.h | 158 +++++++++++++++++++
11 files changed, 758 insertions(+), 2 deletions(-)
create mode 100644 board/bf527-ezkit/.gitignore
create mode 100644 board/bf527-ezkit/Makefile
create mode 100644 board/bf527-ezkit/bf527-ezkit.c
create mode 100644 board/bf527-ezkit/config.mk
create mode 100644 board/bf527-ezkit/spi_flash.c
create mode 100644 board/bf527-ezkit/u-boot.lds.S
create mode 100644 board/bf527-ezkit/video.c
create mode 100644 include/configs/bf527-ezkit.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 59da854..7eda61e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ Yusuke Goda <goda.yusuke@renesas.com>
Mike Frysinger <vapier@gentoo.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+ BF527-EZKIT BF527
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-STAMP BF537
diff --git a/MAKEALL b/MAKEALL
index 3f3170c..c3c8765 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -780,6 +780,7 @@ LIST_avr32=" \
#########################################################################
LIST_blackfin=" \
+ bf527-ezkit \
bf533-ezkit \
bf533-stamp \
bf537-stamp \
diff --git a/Makefile b/Makefile
index c209e53..e6df6cd 100644
--- a/Makefile
+++ b/Makefile
@@ -3289,7 +3289,8 @@ suzaku_config: unconfig
#========================================================================
# Analog Devices boards
-BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit bf561-ezkit
+BFIN_BOARDS = bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit \
+ bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3452,7 +3453,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{bf5{33,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
+ $(obj)board/{bf5{27,33,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf527-ezkit/.gitignore b/board/bf527-ezkit/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf527-ezkit/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
new file mode 100644
index 0000000..e86e19d
--- /dev/null
+++ b/board/bf527-ezkit/Makefile
@@ -0,0 +1,59 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_VIDEO) += video.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
new file mode 100644
index 0000000..4ef2865
--- /dev/null
+++ b/board/bf527-ezkit/bf527-ezkit.c
@@ -0,0 +1,60 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ return;
+ }
+
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/bf527-ezkit/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf527-ezkit/spi_flash.c b/board/bf527-ezkit/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf527-ezkit/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf527-ezkit/u-boot.lds.S b/board/bf527-ezkit/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/bf527-ezkit/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
new file mode 100644
index 0000000..2df6717
--- /dev/null
+++ b/board/bf527-ezkit/video.c
@@ -0,0 +1,317 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/ppi.h>
+#include <asm/mach-common/bits/timer.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES 320 /* Horizontal Resolution */
+#define LCD_Y_RES 240 /* Vertical Resolution */
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+
+#define DMA_BUS_SIZE 16
+#define LCD_CLK (12*1000*1000) /* 12MHz */
+
+#define CLOCKS_PER_PIX 3
+
+/* HS and VS timing parameters (all in number of PPI clk ticks) */
+#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
+#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
+#define H_PULSE 90 /* HS pulse width */
+#define H_START 204 /* first valid pixel */
+
+#define U_LINE 1 /* Blanking Lines */
+
+#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
+#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
+#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
+
+#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
+
+#define PPI_TX_MODE 0x2
+#define PPI_XFER_TYPE_11 0xC
+#define PPI_PORT_CFG_01 0x10
+#define PPI_PACK_EN 0x80
+#define PPI_POLS_1 0x8000
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ *pPPI_CONTROL |= PORT_EN;
+}
+
+void DisablePPI(void)
+{
+ *pPPI_CONTROL &= ~PORT_EN;
+}
+
+void Init_Ports(void)
+{
+ *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
+ *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
+ *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
+
+ *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
+ *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
+ *pPORTG_FER |= PG5;
+}
+
+void Init_PPI(void)
+{
+
+ *pPPI_DELAY = H_START;
+ *pPPI_COUNT = (H_ACTPIX-1);
+ *pPPI_FRAME = 0;
+
+ /* PPI control, to be replaced with definitions */
+ *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
+ PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
+ PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
+ PPI_PACK_EN | /* packing enabled PACK_EN */
+ PPI_POLS_1; /* faling edge syncs POLS */
+}
+
+void Init_DMA(void *dst)
+{
+ *pDMA0_START_ADDR = dst;
+
+ /* X count */
+ *pDMA0_X_COUNT = H_ACTPIX / 2;
+ *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* Y count */
+ *pDMA0_Y_COUNT = V_LINES;
+ *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* DMA Config */
+ *pDMA0_CONFIG =
+ WDSIZE_16 | /* 16 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO; /* autobuffer mode */
+}
+
+
+void EnableDMA(void)
+{
+ *pDMA0_CONFIG |= DMAEN;
+}
+
+void DisableDMA(void)
+{
+ *pDMA0_CONFIG &= ~DMAEN;
+}
+
+
+/* Init TIMER0 as Frame Sync 1 generator */
+void InitTIMER0(void)
+{
+ *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
+ SSYNC();
+ *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
+ SSYNC();
+
+ *pTIMER0_PERIOD = H_PERIOD;
+ SSYNC();
+ *pTIMER0_WIDTH = H_PULSE;
+ SSYNC();
+
+ *pTIMER0_CONFIG = PWM_OUT |
+ PERIOD_CNT |
+ TIN_SEL |
+ CLK_SEL |
+ EMU_RUN;
+ SSYNC();
+}
+
+void EnableTIMER0(void)
+{
+ *pTIMER_ENABLE |= TIMEN0;
+ SSYNC();
+}
+
+void DisableTIMER0(void)
+{
+ *pTIMER_DISABLE |= TIMDIS0;
+ SSYNC();
+}
+
+
+void InitTIMER1(void)
+{
+ *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
+ SSYNC();
+ *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
+ SSYNC();
+
+
+ *pTIMER1_PERIOD = V_PERIOD;
+ SSYNC();
+ *pTIMER1_WIDTH = V_PULSE;
+ SSYNC();
+
+ *pTIMER1_CONFIG = PWM_OUT |
+ PERIOD_CNT |
+ TIN_SEL |
+ CLK_SEL |
+ EMU_RUN;
+ SSYNC();
+}
+
+void EnableTIMER1(void)
+{
+ *pTIMER_ENABLE |= TIMEN1;
+ SSYNC();
+}
+
+void DisableTIMER1(void)
+{
+ *pTIMER_DISABLE |= TIMDIS1;
+ SSYNC();
+}
+
+int video_init(void *dst)
+{
+
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ InitTIMER0();
+ InitTIMER1();
+ Init_PPI();
+ EnablePPI();
+
+ /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
+ EnableTIMER1();
+ /* Add Some Delay ... */
+ SSYNC();
+ SSYNC();
+ SSYNC();
+ SSYNC();
+
+ /* now start frame sync 1 */
+ EnableTIMER0();
+
+ return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ device_t videodev;
+
+ u8 *dst;
+ u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+ bfin_logo.data = data;
+#endif
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+ videodev.putc = video_putc; /* 'putc' function */
+ videodev.puts = video_puts; /* 'puts' function */
+
+ error = device_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
new file mode 100644
index 0000000..14519f2
--- /dev/null
+++ b/include/configs/bf527-ezkit.h
@@ -0,0 +1,158 @@
+/*
+ * U-boot - Configuration file for BF537 STAMP board
+ */
+
+#ifndef __CONFIG_BF527_EZKIT_H__
+#define __CONFIG_BF527_EZKIT_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf527-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x03F6
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used sametime as ethernet)
+ */
+/* #define CONFIG_BFIN_NFC */
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_CMD_NAND
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+ !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME bf527-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED_CUSTOM
+
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * USB Setting
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
+#define CONFIG_USB
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_BLACKFIN
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 1
+
+/* Don't waste time transferring a logo over the UART */
+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+# define CONFIG_VIDEO
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 29/42] Blackfin: bf538f-ezkit: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (27 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 28/42] Blackfin: bf527-ezkit: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 30/42] Blackfin: bf526-ezbrd: " Mike Frysinger
` (12 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 6 +-
board/bf538f-ezkit/.gitignore | 1 +
board/bf538f-ezkit/Makefile | 57 +++++++++++++++
board/bf538f-ezkit/bf538f-ezkit.c | 27 +++++++
board/bf538f-ezkit/config.mk | 33 +++++++++
board/bf538f-ezkit/u-boot.lds.S | 143 +++++++++++++++++++++++++++++++++++++
include/configs/bf538f-ezkit.h | 125 ++++++++++++++++++++++++++++++++
9 files changed, 391 insertions(+), 3 deletions(-)
create mode 100644 board/bf538f-ezkit/.gitignore
create mode 100644 board/bf538f-ezkit/Makefile
create mode 100644 board/bf538f-ezkit/bf538f-ezkit.c
create mode 100644 board/bf538f-ezkit/config.mk
create mode 100644 board/bf538f-ezkit/u-boot.lds.S
create mode 100644 include/configs/bf538f-ezkit.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7eda61e..1abdbd5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -849,6 +849,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-STAMP BF537
+ BF538F-EZKIT BF538
BF548-EZKIT BF548
BF561-EZKIT BF561
diff --git a/MAKEALL b/MAKEALL
index c3c8765..dada5a4 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -784,6 +784,7 @@ LIST_blackfin=" \
bf533-ezkit \
bf533-stamp \
bf537-stamp \
+ bf538f-ezkit \
bf548-ezkit \
bf561-ezkit \
"
diff --git a/Makefile b/Makefile
index e6df6cd..9f7dd36 100644
--- a/Makefile
+++ b/Makefile
@@ -3289,8 +3289,8 @@ suzaku_config: unconfig
#========================================================================
# Analog Devices boards
-BFIN_BOARDS = bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp bf548-ezkit \
- bf561-ezkit
+BFIN_BOARDS = bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp bf538f-ezkit \
+ bf548-ezkit bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3453,7 +3453,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{bf5{27,33,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
+ $(obj)board/{bf5{27,33,38f,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf538f-ezkit/.gitignore b/board/bf538f-ezkit/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf538f-ezkit/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
new file mode 100644
index 0000000..1b21728
--- /dev/null
+++ b/board/bf538f-ezkit/Makefile
@@ -0,0 +1,57 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
new file mode 100644
index 0000000..bbee989
--- /dev/null
+++ b/board/bf538f-ezkit/bf538f-ezkit.c
@@ -0,0 +1,27 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF538F EZ-Kit Lite board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
new file mode 100644
index 0000000..c8b9fb8
--- /dev/null
+++ b/board/bf538f-ezkit/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf538f-ezkit/u-boot.lds.S b/board/bf538f-ezkit/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/bf538f-ezkit/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
new file mode 100644
index 0000000..b731dd4
--- /dev/null
+++ b/include/configs/bf538f-ezkit.h
@@ -0,0 +1,125 @@
+/*
+ * U-boot - Configuration file for BF538F EZ-Kit Lite board
+ */
+
+#ifndef __CONFIG_BF538F_EZKIT_H__
+#define __CONFIG_BF538F_EZKIT_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf538-0.4
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20310300
+#define CONFIG_HOSTNAME bf538f-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 30/42] Blackfin: bf526-ezbrd: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (28 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 29/42] Blackfin: bf538f-ezkit: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 31/42] Blackfin: bf518f-ezbrd: " Mike Frysinger
` (11 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 6 +-
board/bf526-ezbrd/.gitignore | 1 +
board/bf526-ezbrd/Makefile | 58 ++++++++++++++
board/bf526-ezbrd/bf526-ezbrd.c | 109 +++++++++++++++++++++++++
board/bf526-ezbrd/config.mk | 32 ++++++++
board/bf526-ezbrd/spi_flash.c | 2 +
board/bf526-ezbrd/u-boot.lds.S | 124 +++++++++++++++++++++++++++++
include/configs/bf526-ezbrd.h | 166 +++++++++++++++++++++++++++++++++++++++
10 files changed, 497 insertions(+), 3 deletions(-)
create mode 100644 board/bf526-ezbrd/.gitignore
create mode 100644 board/bf526-ezbrd/Makefile
create mode 100644 board/bf526-ezbrd/bf526-ezbrd.c
create mode 100644 board/bf526-ezbrd/config.mk
create mode 100644 board/bf526-ezbrd/spi_flash.c
create mode 100644 board/bf526-ezbrd/u-boot.lds.S
create mode 100644 include/configs/bf526-ezbrd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1abdbd5..7acb22c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ Yusuke Goda <goda.yusuke@renesas.com>
Mike Frysinger <vapier@gentoo.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+ BF526-EZBRD BF526
BF527-EZKIT BF527
BF533-EZKIT BF533
BF533-STAMP BF533
diff --git a/MAKEALL b/MAKEALL
index dada5a4..7862940 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -780,6 +780,7 @@ LIST_avr32=" \
#########################################################################
LIST_blackfin=" \
+ bf526-ezbrd \
bf527-ezkit \
bf533-ezkit \
bf533-stamp \
diff --git a/Makefile b/Makefile
index 9f7dd36..95945a9 100644
--- a/Makefile
+++ b/Makefile
@@ -3289,8 +3289,8 @@ suzaku_config: unconfig
#========================================================================
# Analog Devices boards
-BFIN_BOARDS = bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp bf538f-ezkit \
- bf548-ezkit bf561-ezkit
+BFIN_BOARDS = bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp \
+ bf538f-ezkit bf548-ezkit bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3453,7 +3453,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{bf5{27,33,38f,48,61}-ezkit,bf5{33,37}-stamp}/u-boot.lds \
+ $(obj)board/bf5{26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf526-ezbrd/.gitignore b/board/bf526-ezbrd/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf526-ezbrd/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
new file mode 100644
index 0000000..9e667db
--- /dev/null
+++ b/board/bf526-ezbrd/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c
new file mode 100644
index 0000000..26b6feb
--- /dev/null
+++ b/board/bf526-ezbrd/bf526-ezbrd.c
@@ -0,0 +1,109 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF526 EZ-Board board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ return;
+ }
+
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+
+static void set_led_f(int pf, int state)
+{
+ switch (state) {
+ case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break;
+ case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break;
+ case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break;
+ }
+}
+static void set_led_g(int pf, int state)
+{
+ switch (state) {
+ case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break;
+ case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break;
+ case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break;
+ }
+}
+
+static void set_leds(led_id_t mask, int state)
+{
+ if (mask & 0x1) set_led_f(PF8, state);
+ if (mask & 0x2) set_led_g(PG11, state);
+ if (mask & 0x4) set_led_g(PG12, state);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8));
+ bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12));
+ bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8));
+ bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12));
+ bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8));
+ bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12));
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ set_leds(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ set_leds(mask, STATUS_LED_BLINKING);
+}
+
+#endif
diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/bf526-ezbrd/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf526-ezbrd/spi_flash.c b/board/bf526-ezbrd/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf526-ezbrd/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf526-ezbrd/u-boot.lds.S b/board/bf526-ezbrd/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/bf526-ezbrd/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
new file mode 100644
index 0000000..ddde6bd
--- /dev/null
+++ b/include/configs/bf526-ezbrd.h
@@ -0,0 +1,166 @@
+/*
+ * U-boot - Configuration file for BF526 EZBrd board
+ */
+
+#ifndef __CONFIG_BF526_EZBRD_H__
+#define __CONFIG_BF526_EZBRD_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf526-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 16
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+/* This board has a 64meg MT48H32M16 */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x0267
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used sametime as ethernet)
+ */
+/* #define CONFIG_BFIN_NFC */
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_CMD_NAND
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+ !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME bf526-ezbrd
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED_CUSTOM
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 1
+
+/* define to enable run status via led */
+/* #define CONFIG_STATUS_LED */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+void __led_init(led_id_t mask, int state);
+void __led_set(led_id_t mask, int state);
+void __led_toggle(led_id_t mask);
+#endif
+/* use LED0 to indicate booting/alive */
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT 1
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
+/* use LED1 to indicate crash */
+#define STATUS_LED_CRASH 1
+#define STATUS_LED_BIT1 2
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 31/42] Blackfin: bf518f-ezbrd: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (29 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 30/42] Blackfin: bf526-ezbrd: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 32/42] Blackfin: cm-bf533: " Mike Frysinger
` (10 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 6 +-
board/bf518f-ezbrd/.gitignore | 1 +
board/bf518f-ezbrd/Makefile | 58 ++++++++++++++++
board/bf518f-ezbrd/bf518f-ezbrd.c | 76 ++++++++++++++++++++
board/bf518f-ezbrd/config.mk | 32 +++++++++
board/bf518f-ezbrd/spi_flash.c | 2 +
board/bf518f-ezbrd/u-boot.lds.S | 124 +++++++++++++++++++++++++++++++++
include/configs/bf518f-ezbrd.h | 137 +++++++++++++++++++++++++++++++++++++
10 files changed, 435 insertions(+), 3 deletions(-)
create mode 100644 board/bf518f-ezbrd/.gitignore
create mode 100644 board/bf518f-ezbrd/Makefile
create mode 100644 board/bf518f-ezbrd/bf518f-ezbrd.c
create mode 100644 board/bf518f-ezbrd/config.mk
create mode 100644 board/bf518f-ezbrd/spi_flash.c
create mode 100644 board/bf518f-ezbrd/u-boot.lds.S
create mode 100644 include/configs/bf518f-ezbrd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7acb22c..49a456f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ Yusuke Goda <goda.yusuke@renesas.com>
Mike Frysinger <vapier@gentoo.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+ BF518F-EZBRD BF518
BF526-EZBRD BF526
BF527-EZKIT BF527
BF533-EZKIT BF533
diff --git a/MAKEALL b/MAKEALL
index 7862940..db78210 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -780,6 +780,7 @@ LIST_avr32=" \
#########################################################################
LIST_blackfin=" \
+ bf518f-ezbrd \
bf526-ezbrd \
bf527-ezkit \
bf533-ezkit \
diff --git a/Makefile b/Makefile
index 95945a9..b5eac84 100644
--- a/Makefile
+++ b/Makefile
@@ -3289,8 +3289,8 @@ suzaku_config: unconfig
#========================================================================
# Analog Devices boards
-BFIN_BOARDS = bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp bf537-stamp \
- bf538f-ezkit bf548-ezkit bf561-ezkit
+BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
+ bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3453,7 +3453,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/bf5{26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
+ $(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf518f-ezbrd/.gitignore b/board/bf518f-ezbrd/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf518f-ezbrd/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
new file mode 100644
index 0000000..9e667db
--- /dev/null
+++ b/board/bf518f-ezbrd/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
new file mode 100644
index 0000000..5858078
--- /dev/null
+++ b/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -0,0 +1,76 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF518F EZ-Board board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+#if 0
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ return;
+ }
+#endif
+
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = -1;
+ struct spi_slave *slave = spi_setup_slave(0, 1, 5000000, SPI_MODE_3);
+ if (slave) {
+ if (!spi_claim_bus(slave)) {
+ unsigned char dout[3] = { 2, 1, 1, };
+ unsigned char din[3];
+ ret = spi_xfer(slave, sizeof(dout) * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
+ if (!ret)
+ bfin_EMAC_initialize(bis);
+ spi_release_bus(slave);
+ }
+ spi_free_slave(slave);
+ }
+ return ret;
+}
+#endif
diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/bf518f-ezbrd/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf518f-ezbrd/spi_flash.c b/board/bf518f-ezbrd/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf518f-ezbrd/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf518f-ezbrd/u-boot.lds.S b/board/bf518f-ezbrd/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/bf518f-ezbrd/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
new file mode 100644
index 0000000..cb8a005
--- /dev/null
+++ b/include/configs/bf518f-ezbrd.h
@@ -0,0 +1,137 @@
+/*
+ * U-boot - Configuration file for BF518F EZBrd board
+ */
+
+#ifndef __CONFIG_BF518F_EZBRD_H__
+#define __CONFIG_BF518F_EZBRD_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf518-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 16
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+/* This board has a 64meg MT48H32M16 */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x0096
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME bf518f-ezbrd
+#define CONFIG_PHY_ADDR 3
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE 0x2000
+#endif
+#define ENV_IS_EMBEDDED_CUSTOM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * SDH Settings
+ */
+#if !defined(__ADSPBF512__)
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 32/42] Blackfin: cm-bf533: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (30 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 31/42] Blackfin: bf518f-ezbrd: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-11 21:39 ` Wolfgang Denk
2009-02-10 6:21 ` [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: " Mike Frysinger
` (9 subsequent siblings)
41 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 5 +
MAKEALL | 1 +
Makefile | 4 +
board/cm-bf533/.gitignore | 1 +
board/cm-bf533/Makefile | 57 ++++++++
board/cm-bf533/cm-bf533.c | 25 ++++
board/cm-bf533/config.mk | 33 +++++
board/cm-bf533/flash-defines.h | 49 +++++++
board/cm-bf533/flash.c | 283 ++++++++++++++++++++++++++++++++++++++++
board/cm-bf533/u-boot.lds.S | 143 ++++++++++++++++++++
include/configs/cm-bf533.h | 100 ++++++++++++++
11 files changed, 701 insertions(+), 0 deletions(-)
create mode 100644 board/cm-bf533/.gitignore
create mode 100644 board/cm-bf533/Makefile
create mode 100644 board/cm-bf533/cm-bf533.c
create mode 100644 board/cm-bf533/config.mk
create mode 100644 board/cm-bf533/flash-defines.h
create mode 100644 board/cm-bf533/flash.c
create mode 100644 board/cm-bf533/u-boot.lds.S
create mode 100644 include/configs/cm-bf533.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 49a456f..d5fa707 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -855,6 +855,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF548-EZKIT BF548
BF561-EZKIT BF561
+Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+ CM-BF533 BF533
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index db78210..3074465 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -789,6 +789,7 @@ LIST_blackfin=" \
bf538f-ezkit \
bf548-ezkit \
bf561-ezkit \
+ cm-bf533 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index b5eac84..69e3d83 100644
--- a/Makefile
+++ b/Makefile
@@ -3292,6 +3292,9 @@ suzaku_config: unconfig
BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
+# Bluetechnix tinyboards
+BFIN_BOARDS += cm-bf533
+
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@$(MAKE) -s -B $(obj)include/autoconf.mk
@@ -3453,6 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
+ $(obj)board/cm-bf533/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/cm-bf533/.gitignore b/board/cm-bf533/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/cm-bf533/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
new file mode 100644
index 0000000..6ed3962
--- /dev/null
+++ b/board/cm-bf533/Makefile
@@ -0,0 +1,57 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
new file mode 100644
index 0000000..7eb761d
--- /dev/null
+++ b/board/cm-bf533/cm-bf533.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF533 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
new file mode 100644
index 0000000..c8b9fb8
--- /dev/null
+++ b/board/cm-bf533/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf533/flash-defines.h b/board/cm-bf533/flash-defines.h
new file mode 100644
index 0000000..a5b590a
--- /dev/null
+++ b/board/cm-bf533/flash-defines.h
@@ -0,0 +1,49 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_SECTOR_SIZE 0x20000
+#define MT_MANUFACT_CM_BF533 0x00890016 /* MT manuf. ID in D23..D16, D7..D0 */
+
+int get_codes(void);
+int erase_block_flash(int, unsigned long);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int write_flash(long nOffset, unsigned short nValue);
+int check_sector(unsigned short usSector);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#endif
diff --git a/board/cm-bf533/flash.c b/board/cm-bf533/flash.c
new file mode 100644
index 0000000..f850840
--- /dev/null
+++ b/board/cm-bf533/flash.c
@@ -0,0 +1,283 @@
+/*
+ * U-boot - flash.c Flash driver for MT28F320J3FS-11
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+unsigned long flash_init(void)
+{
+ int i = 0;
+
+ if (CONFIG_SYS_MAX_FLASH_BANKS > 1)
+ printf("Only FLASH bank 0 will be used!");
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ if (get_codes() == MT_MANUFACT_CM_BF533)
+ flash_info[0].flash_id = MT_MANUFACT_CM_BF533;
+ printf("Device ID of the Flash is %lx\n", flash_info[0].flash_id);
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++)
+ flash_info[0].start[i] = (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
+ flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+ flash_info[0].sector_count = FLASH_TOT_SECT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN)
+ printf("## Unknown FLASH on Bank 0\n");
+ else {
+ printf("Memory Map for the Flash\n");
+ printf("0x%x - 0x%x Single Flash Chip\n", CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE);
+ printf("Please type command flinfo for information on Sectors \n");
+ }
+
+ return (CONFIG_SYS_FLASH_SIZE);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case MT_MANUFACT_CM_BF533:
+ printf("MT_MANUFACT_on_CM-BF533");
+ break;
+ default:
+ printf("Unknown Vendor");
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect, i;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect)
+ if (info->protect[sect])
+ prot++;
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n", prot);
+ else
+ printf("\n");
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing \n");
+ return ERR_INVAL;
+ } else
+ printf("Sector %i erased.\n", i);
+ }
+ }
+ return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ long i = 0;
+ unsigned long ulOffset = addr - CONFIG_SYS_FLASH_BASE;
+ int nLeftover = cnt % 4;
+ int iSectors = 0;
+ int iFirst_sector = 0;
+ int iProgress = cnt / (4 * 20);
+
+ iFirst_sector = (int) (ulOffset / FLASH_SECTOR_SIZE);
+ for (iSectors = 1; (iSectors * FLASH_SECTOR_SIZE) < cnt; iSectors++)
+ ;
+
+ printf("Bytes for programming: %li\n", cnt);
+ printf("First sector: %d\n", iFirst_sector);
+ printf("Sectors needed:%d\n", iSectors);
+
+ if (iFirst_sector + iSectors > FLASH_TOT_SECT) {
+ printf("Not enough free flash-sectors!\n");
+ return ERR_INVAL;
+ }
+
+ for (i = iFirst_sector; i < (iFirst_sector + iSectors); i++)
+ if (check_sector(i) == ERR_NOT_ERASED)
+ return ERR_NOT_ERASED;
+
+ printf("[ ]\n[");
+
+ for (i = 0; (i < cnt / 4); i++) {
+ if ((i % iProgress) == 0)
+ printf(".");
+
+ if (write_flash(ulOffset, (((int *)src)[i])) < 0) {
+ printf("Error programming the flash \n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ if (write_flash(ulOffset, (((int *)src)[i] >> 16)) < 0) {
+ printf("Error programming the flash \n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ }
+ if (nLeftover > 0) {
+ if (write_flash(ulOffset, ((int *) src)[i]) < 0) {
+ printf("Error programming the flash \n");
+ return ERR_TIMOUT;
+ }
+ }
+ printf("]\n");
+ return ERR_OK;
+}
+
+int check_sector(unsigned short usSector)
+{
+ long i = 0;
+ int iData;
+ printf("Checking sector %d", usSector);
+ for (i = 0; i < FLASH_SECTOR_SIZE; i += 2) {
+ iData = *((unsigned short *)(CONFIG_SYS_FLASH_BASE + (i + (usSector * FLASH_SECTOR_SIZE))));
+
+ if (iData != 0xFFFF) {
+ printf(" ... not empty!\n");
+ return ERR_NOT_ERASED;
+ }
+ }
+ printf(" ... sector empty\n");
+ return ERR_OK;
+}
+
+int write_flash(long nOffset, unsigned short nValue)
+{
+ volatile unsigned short *memIndex;
+ unsigned long nTimeout;
+ unsigned short status;
+
+ memIndex = (unsigned short *)(CONFIG_SYS_FLASH_BASE + nOffset);
+
+ *memIndex = 0x0050; /* Reset statusregister */
+ SSYNC();
+
+ *memIndex = 0x0040;
+ SSYNC();
+
+ *memIndex = (unsigned short) nValue;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *memIndex;
+ nTimeout++;
+ SSYNC();
+ } while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ nTimeout = FLASH_TIMEOUT;
+ do {
+ *memIndex = 0xff; /* Back to "read array mode". */
+ SSYNC();
+ nTimeout--;
+ } while ((*memIndex != (unsigned short) nValue) && (nTimeout > 0));
+ if (!nTimeout)
+ status = 0xee00;
+
+ if (status == 0x0080)
+ return (ERR_OK);
+ else
+ return (ERR_TIMOUT);
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+ volatile unsigned short *memIndex;
+ unsigned short status;
+ unsigned long nTimeout;
+
+ if ((nBlock < 0) || (nBlock >= CONFIG_SYS_MAX_FLASH_SECT)) {
+ printf("Invalid sector number\n");
+ return -1;
+ }
+ memIndex = (unsigned short *)(address);
+
+ *memIndex = 0x0050;
+ SSYNC();
+
+ *memIndex = 0x0020;
+ SSYNC();
+
+ *memIndex = 0x00d0;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *memIndex;
+ SSYNC();
+ nTimeout++;
+ } while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *memIndex = 0xff; /* Zurueck zu "Read Array Mode" */
+ SSYNC();
+
+ if (status == 0xFF00)
+ return -1;
+ else
+ return ERR_OK;
+}
+
+int get_codes(void)
+{
+ int dev_id = 0;
+ long int manufacturer_id;
+ volatile unsigned short *nFlashAddr;
+
+ nFlashAddr = (unsigned short *)CONFIG_SYS_FLASH_BASE;
+
+ *nFlashAddr = 0x0090; /* Read identifier command. */
+ SSYNC();
+
+ manufacturer_id = *nFlashAddr;
+ SSYNC();
+ nFlashAddr++;
+ dev_id = *nFlashAddr;
+ SSYNC();
+
+ *nFlashAddr = 0x00ff; /* Return to read array mode. */
+ SSYNC();
+
+ dev_id = ((manufacturer_id << 16) | dev_id);
+ return dev_id;
+}
diff --git a/board/cm-bf533/u-boot.lds.S b/board/cm-bf533/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/cm-bf533/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
new file mode 100644
index 0000000..39dae37
--- /dev/null
+++ b/include/configs/cm-bf533.h
@@ -0,0 +1,100 @@
+/*
+ * U-boot - Configuration file for CM-BF533 board
+ */
+
+#ifndef __CONFIG_CM_BF533_H__
+#define __CONFIG_CM_BF533_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 22
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2))
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20200300
+#define CONFIG_HOSTNAME cm-bf533
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
+
+#define FLASH_TOT_SECT 16
+#define CONFIG_SYS_FLASH_SIZE 0x200000
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x10000
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 32/42] Blackfin: cm-bf533: new board port
2009-02-10 6:21 ` [U-Boot] [PATCH 32/42] Blackfin: cm-bf533: " Mike Frysinger
@ 2009-02-11 21:39 ` Wolfgang Denk
0 siblings, 0 replies; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-11 21:39 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <1234246880-32438-33-git-send-email-vapier@gentoo.org> you wrote:
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> ---
> MAINTAINERS | 5 +
> MAKEALL | 1 +
> Makefile | 4 +
> board/cm-bf533/.gitignore | 1 +
> board/cm-bf533/Makefile | 57 ++++++++
> board/cm-bf533/cm-bf533.c | 25 ++++
> board/cm-bf533/config.mk | 33 +++++
> board/cm-bf533/flash-defines.h | 49 +++++++
> board/cm-bf533/flash.c | 283 ++++++++++++++++++++++++++++++++++++++++
> board/cm-bf533/u-boot.lds.S | 143 ++++++++++++++++++++
> include/configs/cm-bf533.h | 100 ++++++++++++++
> 11 files changed, 701 insertions(+), 0 deletions(-)
> create mode 100644 board/cm-bf533/.gitignore
> create mode 100644 board/cm-bf533/Makefile
> create mode 100644 board/cm-bf533/cm-bf533.c
> create mode 100644 board/cm-bf533/config.mk
> create mode 100644 board/cm-bf533/flash-defines.h
> create mode 100644 board/cm-bf533/flash.c
> create mode 100644 board/cm-bf533/u-boot.lds.S
> create mode 100644 include/configs/cm-bf533.h
General comment here and for the othe rpatches:
...
> --- a/Makefile
> +++ b/Makefile
> @@ -3292,6 +3292,9 @@ suzaku_config: unconfig
> BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
> bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
>
> +# Bluetechnix tinyboards
> +BFIN_BOARDS += cm-bf533
> +
> $(BFIN_BOARDS:%=%_config) : unconfig
> @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
> @$(MAKE) -s -B $(obj)include/autoconf.mk
> @@ -3453,6 +3456,7 @@ clean:
> $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
> $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
> $(obj)board/{integratorap,integratorcp}/u-boot.lds \
> + $(obj)board/cm-bf533/u-boot.lds \
> $(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
...
> diff --git a/board/cm-bf533/flash-defines.h b/board/cm-bf533/flash-defines.h
> new file mode 100644
> index 0000000..a5b590a
> --- /dev/null
> +++ b/board/cm-bf533/flash-defines.h
> @@ -0,0 +1,49 @@
...
> +#define MT_MANUFACT_CM_BF533 0x00890016 /* MT manuf. ID in D23..D16, D7..D0 */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
...
> diff --git a/board/cm-bf533/flash.c b/board/cm-bf533/flash.c
> new file mode 100644
> index 0000000..f850840
> --- /dev/null
> +++ b/board/cm-bf533/flash.c
> @@ -0,0 +1,283 @@
...
> + * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
...
> + flash_info[0].start[i] = (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> + flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
> + flash_info[0].sector_count = FLASH_TOT_SECT;
> + if (flash_info[0].flash_id == FLASH_UNKNOWN)
> + printf("## Unknown FLASH on Bank 0\n");
> + else {
> + printf("Memory Map for the Flash\n");
> + printf("0x%x - 0x%x Single Flash Chip\n", CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE);
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Many, many lines are *way* too long.
Please fix gobally.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Wenn Du ein' weise Antwort verlangst, Mu?t Du vern?nftig fragen.
-- Goethe, Invektiven
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (31 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 32/42] Blackfin: cm-bf533: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-11 21:43 ` Wolfgang Denk
2009-02-10 6:21 ` [U-Boot] [PATCH 34/42] Blackfin: cm-bf561: " Mike Frysinger
` (8 subsequent siblings)
41 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/cm-bf537e/.gitignore | 1 +
board/cm-bf537e/Makefile | 58 +++++
board/cm-bf537e/cm-bf537e.c | 44 ++++
board/cm-bf537e/config.mk | 33 +++
board/cm-bf537e/flash-defines.h | 50 +++++
board/cm-bf537e/flash.c | 449 +++++++++++++++++++++++++++++++++++++++
board/cm-bf537e/spi_flash.c | 2 +
board/cm-bf537e/u-boot.lds.S | 143 +++++++++++++
include/configs/cm-bf537e.h | 133 ++++++++++++
12 files changed, 917 insertions(+), 2 deletions(-)
create mode 100644 board/cm-bf537e/.gitignore
create mode 100644 board/cm-bf537e/Makefile
create mode 100644 board/cm-bf537e/cm-bf537e.c
create mode 100644 board/cm-bf537e/config.mk
create mode 100644 board/cm-bf537e/flash-defines.h
create mode 100644 board/cm-bf537e/flash.c
create mode 100644 board/cm-bf537e/spi_flash.c
create mode 100644 board/cm-bf537e/u-boot.lds.S
create mode 100644 include/configs/cm-bf537e.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d5fa707..41e9903 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -859,6 +859,7 @@ Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF533 BF533
+ CM-BF537E BF537
#########################################################################
# End of MAINTAINERS list #
diff --git a/MAKEALL b/MAKEALL
index 3074465..bc1514d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -790,6 +790,7 @@ LIST_blackfin=" \
bf548-ezkit \
bf561-ezkit \
cm-bf533 \
+ cm-bf537e \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 69e3d83..53c56a4 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,7 +3293,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533
+BFIN_BOARDS += cm-bf533 cm-bf537e
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3456,7 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/cm-bf533/u-boot.lds \
+ $(obj)board/cm-bf5{33,37e}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/cm-bf537e/.gitignore b/board/cm-bf537e/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/cm-bf537e/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
new file mode 100644
index 0000000..45dc698
--- /dev/null
+++ b/board/cm-bf537e/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o flash.o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
new file mode 100644
index 0000000..ea20326
--- /dev/null
+++ b/board/cm-bf537e/cm-bf537e.c
@@ -0,0 +1,44 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF537E board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(unsigned char *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
new file mode 100644
index 0000000..c8b9fb8
--- /dev/null
+++ b/board/cm-bf537e/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf537e/flash-defines.h b/board/cm-bf537e/flash-defines.h
new file mode 100644
index 0000000..c281d2c
--- /dev/null
+++ b/board/cm-bf537e/flash-defines.h
@@ -0,0 +1,50 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_SECTOR_SIZE 0x20000
+#define MT_MANUFACT_CM_BF533 0x00890016 /* MT manuf. ID in D23..D16, D7..D0 */
+
+int get_codes(void);
+static int erase_block_flash(int, unsigned long);
+/* static int write_data(long lStart, long lCount, long lStride, int *pnData); */
+static int write_flash(long nOffset, unsigned short nValue);
+static int check_sector(unsigned short usSector);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#endif
diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c
new file mode 100644
index 0000000..1806be6
--- /dev/null
+++ b/board/cm-bf537e/flash.c
@@ -0,0 +1,449 @@
+/*
+ * U-boot - flash.c Flash driver for MT28F320J3FS-11
+ *
+
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include "flash-defines.h"
+
+static int write_flash(long nOffset, unsigned short nValue);
+static int erase_block_flash(int nBlock, unsigned long address);
+
+#define GPIO_4 (1<<4)
+
+#define SWITCH_BANK do { if (memIndex >= 0x20200000) {\
+ *pPORTFIO_SET = GPIO_4; \
+ memIndex -= 0x200000; \
+ crossed = 1;\
+ } else { \
+ *pPORTFIO_CLEAR = GPIO_4; \
+ } \
+ asm("ssync;"); } while (0)
+
+#define SWITCH_BACK do {if (crossed) {\
+ *pPORTFIO_CLEAR = GPIO_4; \
+ memIndex += 0x200000; \
+ crossed = 0;\
+ asm("ssync;");\
+ } } while (0)
+
+unsigned long flash_init(void)
+{
+ int i = 0;
+
+ if (CONFIG_SYS_MAX_FLASH_BANKS > 1)
+ printf("Only FLASH bank 0 will be used!");
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ if (get_codes() == MT_MANUFACT_CM_BF533)
+ flash_info[0].flash_id = MT_MANUFACT_CM_BF533;
+ printf("Device ID of the Flash is %lx\n", flash_info[0].flash_id);
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++)
+ flash_info[0].start[i] =
+ (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
+ flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+ flash_info[0].sector_count = FLASH_TOT_SECT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN
+ && CONFIG_SYS_FLASH_SIZE == 0x200000) {
+ printf("## Unknown FLASH on Bank 0\n");
+ } else {
+ printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
+ printf("Memory Map for the Flash\n");
+ printf("0x20000000 - 0x203FFFFF Single Flash Chip (4MB)\n");
+ printf("Using PF4 as a 2M bank switch\n");
+ printf
+ ("Please type command flinfo for information on Sectors \n");
+ *pPORTF_FER &= ~GPIO_4;
+ *pPORTFIO_DIR |= GPIO_4;
+ *pPORTFIO_CLEAR = GPIO_4;
+ asm("ssync;");
+ }
+ return (CONFIG_SYS_FLASH_SIZE);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case MT_MANUFACT_CM_BF533:
+ printf("MT_MANUFACT_on_CM-BF537");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect, i;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing \n");
+ return ERR_INVAL;
+ } else {
+ printf("Sector %i erased.\n", i);
+ }
+ }
+ }
+ return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, unsigned char *src, ulong addr, ulong cnt)
+{
+ long i = 0;
+ unsigned long ulOffset = addr - CONFIG_SYS_FLASH_BASE;
+ int nLeftover = cnt % 4;
+ int iSectors = 0;
+ int iFirst_sector = 0;
+ int iProgress = cnt / (4 * 20);
+
+ iFirst_sector = (int)(ulOffset / FLASH_SECTOR_SIZE);
+ for (iSectors = 1; (iSectors * FLASH_SECTOR_SIZE) < cnt; iSectors++) ;
+
+ printf("Bytes for programming: %li\n", cnt);
+ printf("First sector: %d\n", iFirst_sector);
+ printf("Sectors needed:%d\n", iSectors);
+
+ if (iFirst_sector + iSectors > FLASH_TOT_SECT) {
+ printf("Not enough free flash-sectors!\n");
+ return ERR_INVAL;
+ }
+
+ for (i = iFirst_sector; i < (iFirst_sector + iSectors); i++) {
+ if (check_sector(i) == ERR_NOT_ERASED)
+ printf("Sector %ld not erased\n", i);
+ /* return ERR_NOT_ERASED; */
+ }
+
+ printf("[ ]\n[");
+
+ for (i = 0; (i < cnt / 4); i++) {
+ if ((i % iProgress) == 0)
+ printf(".");
+
+ if (write_flash(ulOffset, (((int *)src)[i])) < 0) {
+ printf("Error programming the flash \n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ if (write_flash(ulOffset, (((int *)src)[i] >> 16)) < 0) {
+ printf("Error programming the flash \n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ }
+ if (nLeftover > 0) {
+ if (write_flash(ulOffset, ((int *)src)[i]) < 0) {
+ printf("Error programming flash \n");
+ return ERR_TIMOUT;
+ }
+ }
+ printf("]\n");
+ return ERR_OK;
+}
+
+/* assumes all bytes to be within a single bank */
+static int read_flash_chunk(char *addr, int size, char *dest)
+{
+ unsigned long memIndex;
+ int crossed = 0;
+
+ memIndex = (unsigned long)addr;
+ SWITCH_BANK;
+ memcpy((void *)dest, (void *)memIndex, size);
+ SWITCH_BACK;
+ return size;
+}
+
+
+/* handles bank switching (we hope) */
+
+int read_flash(char *addr, int size, char *dest)
+{
+ int chunk;
+ int done;
+ chunk = size;
+ done = 0;
+ if (addr < (char *)0x20200000) {
+ if ((addr + size) > (char *)0x20200000) {
+ chunk = (int)((char *)0x20200000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ done += read_flash_chunk(addr, chunk, dest);
+ return done;
+}
+
+static int check_sector(unsigned short usSector)
+{
+ long i = 0;
+ int ret;
+ unsigned short iData;
+ unsigned long memIndex;
+ int crossed = 0;
+
+ printf("Checking sector %d", usSector);
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE +
+ (usSector * FLASH_SECTOR_SIZE));
+
+ SWITCH_BANK;
+
+ ret = ERR_OK;
+
+ for (i = 0; i < FLASH_SECTOR_SIZE; i += 2) {
+
+ iData = *(volatile unsigned short *)memIndex;
+ if (iData != 0xFFFF) {
+ ret = ERR_NOT_ERASED;
+ break;
+ }
+ memIndex += 2;
+ }
+
+ SWITCH_BACK;
+
+ if (ret == ERR_OK) {
+ printf(" ... sector empty\n");
+ } else {
+ printf(" ... not empty!\n");
+ }
+ return ret;
+}
+
+static int write_flash(long nOffset, unsigned short nValue)
+{
+
+ unsigned long memIndex;
+ unsigned long nTimeout;
+ unsigned short status;
+ int crossed = 0;
+
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE + nOffset);
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050; /* Reset status register */
+ asm("ssync;");
+
+ *(volatile unsigned short *)memIndex = 0x0040;
+ asm("ssync;");
+
+ *(volatile unsigned short *)memIndex = (unsigned short)nValue;
+ asm("ssync;");
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ nTimeout++;
+ asm("ssync;");
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ nTimeout = FLASH_TIMEOUT;
+ do {
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "read array mode". */
+ asm("ssync;");
+ nTimeout--;
+ } while ((*(volatile unsigned short *)memIndex
+ != (unsigned short)nValue) && (nTimeout > 0));
+ if (!nTimeout)
+ status = 0xee00;
+
+ SWITCH_BACK;
+
+ if (status == 0x0080)
+ return (ERR_OK);
+ else
+ return (ERR_TIMOUT);
+}
+
+static int erase_block_flash(int nBlock, unsigned long address)
+{
+ unsigned long memIndex;
+ unsigned short status;
+ unsigned long nTimeout;
+ int crossed = 0;
+
+ if ((nBlock < 0) || (nBlock >= CONFIG_SYS_MAX_FLASH_SECT)) {
+ printf("Invalid sector number\n");
+ return -1;
+ }
+
+ memIndex = (unsigned long)(address); /* + CONFIG_SYS_FLASH_BASE); */
+
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050;
+ asm("ssync;");
+
+ *(volatile unsigned short *)memIndex = 0x0020;
+ asm("ssync;");
+
+ *(volatile unsigned short *)memIndex = 0x00d0;
+ asm("ssync;");
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ asm("ssync;");
+ nTimeout++;
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "Read Array Mode" */
+ asm("ssync;");
+
+ SWITCH_BACK;
+
+ if (status == 0xFF00)
+ return -1;
+ else
+ return ERR_OK;
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+ long int manufacturer_id;
+ volatile unsigned short *nFlashAddr;
+
+ nFlashAddr = (unsigned short *)CONFIG_SYS_FLASH_BASE;
+
+ *nFlashAddr = 0x0090; /* Read identifier command. */
+ asm("ssync;");
+
+ manufacturer_id = *nFlashAddr;
+ asm("ssync;");
+ nFlashAddr++;
+ dev_id = *nFlashAddr;
+ asm("ssync;");
+
+ *nFlashAddr = 0x00ff; /* Return to read array mode. */
+ asm("ssync;");
+
+ dev_id = ((manufacturer_id << 16) | dev_id);
+ return dev_id;
+}
+
+int do_pf4(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ if (dflg > 0) {
+ *pPORTFIO_SET = GPIO_4;
+ } else {
+ *pPORTFIO_CLEAR = GPIO_4;
+ }
+ } else {
+ data = *pPORTFIO;
+ printf(" PF4 command argc = %d data %04x\n", argc, data);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(pf4, CONFIG_SYS_MAXARGS, 1, do_pf4,
+ "pf4\t- set/clear pf4 mem bank switch\n",
+ "\n - set (1) uses 2nd bank clear (0) uses 1st bank\n"
+ "pf4 1 ...\n" "pf4 0 ...\n");
+
+int do_readflash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long src;
+ unsigned long dest;
+ int size;
+
+ if (argc == 4) {
+ src = simple_strtoul(argv[1], NULL, 16);
+ dest = simple_strtoul(argv[2], NULL, 16);
+ size = simple_strtol(argv[3], NULL, 16);
+ if (src < CONFIG_SYS_FLASH_BASE ||
+ (src + size) > CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in flash.\n",
+ src, src + size);
+ return 1;
+ }
+ if (dest < CONFIG_SYS_SDRAM_BASE ||
+ (dest + size) > CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in RAM.\n",
+ dest, dest + size);
+ return 1;
+ }
+ read_flash((char *)src, size, (char *)dest);
+ printf("Done.\n");
+ } else
+ printf("Error: Arguments missing.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(flread, 4, 0, do_readflash,
+ "flread - read from flash\n",
+ "reads flash memory and handles pf4 bank switching\n\n"
+ "readflash addr dest length\n"
+ " (all arguments in hex)\n");
diff --git a/board/cm-bf537e/spi_flash.c b/board/cm-bf537e/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/cm-bf537e/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/cm-bf537e/u-boot.lds.S b/board/cm-bf537e/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/cm-bf537e/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
new file mode 100644
index 0000000..4df9357
--- /dev/null
+++ b/include/configs/cm-bf537e.h
@@ -0,0 +1,133 @@
+/*
+ * U-boot - Configuration file for CM-BF537E board
+ */
+
+#ifndef __CONFIG_CM_BF537E_H__
+#define __CONFIG_CM_BF537E_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+#define CONFIG_EBIU_SDRRC_VAL 0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME cm-bf537e
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SYS_HAS_FLASHSWITCH 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+#define FLASH_TOT_SECT 32
+#define CONFIG_SYS_FLASH_SIZE 0x400000
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: new board port
2009-02-10 6:21 ` [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: " Mike Frysinger
@ 2009-02-11 21:43 ` Wolfgang Denk
2009-02-11 21:48 ` Mike Frysinger
0 siblings, 1 reply; 58+ messages in thread
From: Wolfgang Denk @ 2009-02-11 21:43 UTC (permalink / raw)
To: u-boot
Dear Mike Frysinger,
In message <1234246880-32438-34-git-send-email-vapier@gentoo.org> you wrote:
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> ---
> MAINTAINERS | 1 +
> MAKEALL | 1 +
> Makefile | 4 +-
> board/cm-bf537e/.gitignore | 1 +
> board/cm-bf537e/Makefile | 58 +++++
> board/cm-bf537e/cm-bf537e.c | 44 ++++
> board/cm-bf537e/config.mk | 33 +++
> board/cm-bf537e/flash-defines.h | 50 +++++
> board/cm-bf537e/flash.c | 449 +++++++++++++++++++++++++++++++++++++++
> board/cm-bf537e/spi_flash.c | 2 +
> board/cm-bf537e/u-boot.lds.S | 143 +++++++++++++
> include/configs/cm-bf537e.h | 133 ++++++++++++
> 12 files changed, 917 insertions(+), 2 deletions(-)
> create mode 100644 board/cm-bf537e/.gitignore
> create mode 100644 board/cm-bf537e/Makefile
> create mode 100644 board/cm-bf537e/cm-bf537e.c
> create mode 100644 board/cm-bf537e/config.mk
> create mode 100644 board/cm-bf537e/flash-defines.h
> create mode 100644 board/cm-bf537e/flash.c
> create mode 100644 board/cm-bf537e/spi_flash.c
> create mode 100644 board/cm-bf537e/u-boot.lds.S
> create mode 100644 include/configs/cm-bf537e.h
Global comment for all patches in this series:
> diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c
> new file mode 100644
> index 0000000..1806be6
> --- /dev/null
> +++ b/board/cm-bf537e/flash.c
> @@ -0,0 +1,449 @@
> +/*
> + * U-boot - flash.c Flash driver for MT28F320J3FS-11
...
> +#define SWITCH_BANK do { if (memIndex >= 0x20200000) {\
> + *pPORTFIO_SET = GPIO_4; \
> + memIndex -= 0x200000; \
> + crossed = 1;\
> + } else { \
> + *pPORTFIO_CLEAR = GPIO_4; \
> + } \
> + asm("ssync;"); } while (0)
> +
> +#define SWITCH_BACK do {if (crossed) {\
> + *pPORTFIO_CLEAR = GPIO_4; \
> + memIndex += 0x200000; \
> + crossed = 0;\
> + asm("ssync;");\
> + } } while (0)
Better use inline functions instead of such macros.
Please use accessor functions instead of pointer accesses (which alslo
will allow you to get rid of the "ssync" stuff here).
> + for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++)
> + flash_info[0].start[i] =
> + (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
Please use curly braces for multiline statements.
...
> +int flash_erase(flash_info_t *info, int s_first, int s_last)
> +{
> + int prot, sect, i;
> +
> + prot = 0;
> + for (sect = s_first; sect <= s_last; ++sect) {
> + if (info->protect[sect])
> + prot++;
> + }
> + if (prot)
> + printf("- Warning: %d protected sectors will not be erased!\n",
> + prot);
> + else
Please use curly braces for multiline statements.
> +int write_buff(flash_info_t *info, unsigned char *src, ulong addr, ulong cnt)
> +{
> + long i = 0;
> + unsigned long ulOffset = addr - CONFIG_SYS_FLASH_BASE;
> + int nLeftover = cnt % 4;
> + int iSectors = 0;
> + int iFirst_sector = 0;
> + int iProgress = cnt / (4 * 20);
Please do not use camel-case variable names.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Q: Do you know what the death rate around here is?
A: One per person.
^ permalink raw reply [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: new board port
2009-02-11 21:43 ` Wolfgang Denk
@ 2009-02-11 21:48 ` Mike Frysinger
0 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-11 21:48 UTC (permalink / raw)
To: u-boot
On Wednesday 11 February 2009 16:43:51 Wolfgang Denk wrote:
> In message Mike Frysinger you wrote:
> > +#define SWITCH_BANK do { if (memIndex >= 0x20200000) {\
> > + *pPORTFIO_SET = GPIO_4; \
> > + memIndex -= 0x200000; \
> > + crossed = 1;\
> > + } else { \
> > + *pPORTFIO_CLEAR = GPIO_4; \
> > + } \
> > + asm("ssync;"); } while (0)
> > +
> > +#define SWITCH_BACK do {if (crossed) {\
> > + *pPORTFIO_CLEAR = GPIO_4; \
> > + memIndex += 0x200000; \
> > + crossed = 0;\
> > + asm("ssync;");\
> > + } } while (0)
>
> Please use accessor functions instead of pointer accesses (which alslo
> will allow you to get rid of the "ssync" stuff here).
the ssync would still be required. it's to force the GPIO pins to the proper
state, not to make sure some address request has gone out.
all the flash drivers in the tinyboard dirs (cm-*) are "throw away" ... they
all exist because a common driver does not yet exist to hook CFI compliant
flashes up partially with addressing lines and partially with GPIOs. once i
get around to implementing that, all of these can be summarily scuttled.
sorry, i should have noted this in the summary.
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 34/42] Blackfin: cm-bf561: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (32 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 33/42] Blackfin: cm-bf537e: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 35/42] Blackfin: tcm-bf537: " Mike Frysinger
` (7 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/cm-bf561/.gitignore | 1 +
board/cm-bf561/Makefile | 57 +++++++++++++++++
board/cm-bf561/cm-bf561.c | 25 ++++++++
board/cm-bf561/config.mk | 33 ++++++++++
board/cm-bf561/u-boot.lds.S | 143 +++++++++++++++++++++++++++++++++++++++++++
include/configs/cm-bf561.h | 100 ++++++++++++++++++++++++++++++
9 files changed, 363 insertions(+), 2 deletions(-)
create mode 100644 board/cm-bf561/.gitignore
create mode 100644 board/cm-bf561/Makefile
create mode 100644 board/cm-bf561/cm-bf561.c
create mode 100644 board/cm-bf561/config.mk
create mode 100644 board/cm-bf561/u-boot.lds.S
create mode 100644 include/configs/cm-bf561.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 41e9903..727de20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -860,6 +860,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF533 BF533
CM-BF537E BF537
+ CM-BF561 BF561
#########################################################################
# End of MAINTAINERS list #
diff --git a/MAKEALL b/MAKEALL
index bc1514d..5ce3ea1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -791,6 +791,7 @@ LIST_blackfin=" \
bf561-ezkit \
cm-bf533 \
cm-bf537e \
+ cm-bf561 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 53c56a4..5ea9435 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,7 +3293,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533 cm-bf537e
+BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf561
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3456,7 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/cm-bf5{33,37e}/u-boot.lds \
+ $(obj)board/cm-bf5{33,37e,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/cm-bf561/.gitignore b/board/cm-bf561/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/cm-bf561/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
new file mode 100644
index 0000000..1b21728
--- /dev/null
+++ b/board/cm-bf561/Makefile
@@ -0,0 +1,57 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
new file mode 100644
index 0000000..5bce9eb
--- /dev/null
+++ b/board/cm-bf561/cm-bf561.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF561 core module\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
new file mode 100644
index 0000000..710809a
--- /dev/null
+++ b/board/cm-bf561/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf561/u-boot.lds.S b/board/cm-bf561/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/cm-bf561/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
new file mode 100644
index 0000000..d0a7fbe
--- /dev/null
+++ b/include/configs/cm-bf561.h
@@ -0,0 +1,100 @@
+/*
+ * U-boot - Configuration file for CM-BF561 board
+ */
+
+#ifndef __CONFIG_CM_BF561_H__
+#define __CONFIG_CM_BF561_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 22
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
+#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x28000300
+#define CONFIG_HOSTNAME cm-bf561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip; CM-BF561v2 has 8MB Flash */
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x10000
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 35/42] Blackfin: tcm-bf537: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (33 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 34/42] Blackfin: cm-bf561: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: " Mike Frysinger
` (6 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/tcm-bf537/.gitignore | 1 +
board/tcm-bf537/Makefile | 58 ++++
board/tcm-bf537/config.mk | 33 +++
board/tcm-bf537/flash-defines.h | 52 ++++
board/tcm-bf537/flash.c | 583 +++++++++++++++++++++++++++++++++++++++
board/tcm-bf537/spi_flash.c | 2 +
board/tcm-bf537/tcm-bf537.c | 44 +++
board/tcm-bf537/u-boot.lds.S | 143 ++++++++++
include/configs/tcm-bf537.h | 135 +++++++++
12 files changed, 1055 insertions(+), 2 deletions(-)
create mode 100644 board/tcm-bf537/.gitignore
create mode 100644 board/tcm-bf537/Makefile
create mode 100644 board/tcm-bf537/config.mk
create mode 100644 board/tcm-bf537/flash-defines.h
create mode 100644 board/tcm-bf537/flash.c
create mode 100644 board/tcm-bf537/spi_flash.c
create mode 100644 board/tcm-bf537/tcm-bf537.c
create mode 100644 board/tcm-bf537/u-boot.lds.S
create mode 100644 include/configs/tcm-bf537.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 727de20..6d1bfee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -861,6 +861,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF533 BF533
CM-BF537E BF537
CM-BF561 BF561
+ TCM-BF537 BF537
#########################################################################
# End of MAINTAINERS list #
diff --git a/MAKEALL b/MAKEALL
index 5ce3ea1..806e7a9 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -792,6 +792,7 @@ LIST_blackfin=" \
cm-bf533 \
cm-bf537e \
cm-bf561 \
+ tcm-bf537 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 5ea9435..65a6c9f 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,7 +3293,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf561
+BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf561 tcm-bf537
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3456,7 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/cm-bf5{33,37e,61}/u-boot.lds \
+ $(obj)board/{,t}cm-bf5{33,37e,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/tcm-bf537/.gitignore b/board/tcm-bf537/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/tcm-bf537/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
new file mode 100644
index 0000000..45dc698
--- /dev/null
+++ b/board/tcm-bf537/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o flash.o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
new file mode 100644
index 0000000..c8b9fb8
--- /dev/null
+++ b/board/tcm-bf537/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/tcm-bf537/flash-defines.h b/board/tcm-bf537/flash-defines.h
new file mode 100644
index 0000000..3e796f6
--- /dev/null
+++ b/board/tcm-bf537/flash-defines.h
@@ -0,0 +1,52 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ * Edited by Jahshan Bhatti, jabhatti91 at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_SECTOR_SIZE 0x20000
+#define MT_MANUFACT_P30 0x0089881A
+#define MT_MANUFACT_P33 0x00898820
+
+int get_codes(void);
+static int erase_block_flash(int, unsigned long);
+/* static int write_data(long lStart, long lCount, long lStride, int *pnData); */
+static int write_flash(long nOffset, unsigned short nValue);
+static int check_sector(unsigned short usSector);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#endif
diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c
new file mode 100644
index 0000000..ef1a2d8
--- /dev/null
+++ b/board/tcm-bf537/flash.c
@@ -0,0 +1,583 @@
+/*
+ * U-boot - flash.c Flash driver for MT28F320J3FS-11
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ * Edited by Jahshan Bhatti, jabhatti91 at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include "flash-defines.h"
+
+static int write_flash(long nOffset, unsigned short nValue);
+static int erase_block_flash(int nBlock, unsigned long address);
+
+#define SWITCH_BANK \
+ do { \
+ if (memIndex >= 0x20600000) { \
+ *pPORTFIO_SET = (PF4|PF5); \
+ memIndex -= 0x600000; \
+ crossed4 = 1; \
+ crossed5 = 1; \
+ } else if (memIndex >= 0x20400000) { \
+ *pPORTFIO_CLEAR = PF4; \
+ *pPORTFIO_SET = PF5; \
+ memIndex -= 0x400000; \
+ crossed5 = 1; \
+ } else if (memIndex >= 0x20200000) { \
+ *pPORTFIO_SET = PF4; \
+ *pPORTFIO_CLEAR = PF5; \
+ memIndex -= 0x200000; \
+ crossed4 = 1; \
+ } else { \
+ *pPORTFIO_CLEAR = (PF4|PF5); \
+ } \
+ SSYNC(); \
+ } while (0)
+
+#define SWITCH_BACK \
+ do { \
+ if (crossed4) { \
+ *pPORTFIO_CLEAR = PF4; \
+ memIndex += 0x200000; \
+ crossed4 = 0; \
+ SSYNC(); \
+ } \
+ if (crossed5) { \
+ *pPORTFIO_CLEAR = PF5; \
+ memIndex += 0x400000; \
+ crossed5 = 0; \
+ SSYNC(); \
+ } \
+ } while (0)
+
+unsigned long flash_init(void)
+{
+ int i = 0;
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ if (CONFIG_SYS_MAX_FLASH_BANKS > 1)
+ printf("Only FLASH bank 0 will be used!");
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ if (get_codes() == MT_MANUFACT_P33)
+ flash_info[0].flash_id = MT_MANUFACT_P33;
+ else if (get_codes() == MT_MANUFACT_P30)
+ flash_info[0].flash_id = MT_MANUFACT_P30;
+ printf("Device ID of the Flash is %lx\n", flash_info[0].flash_id);
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++)
+ flash_info[0].start[i] =
+ (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
+ flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+ flash_info[0].sector_count = FLASH_TOT_SECT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN
+ && CONFIG_SYS_FLASH_SIZE == 0x200000) {
+ printf("## Unknown FLASH on Bank 0\n");
+ } else {
+ printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
+ printf("Memory Map for the Flash\n");
+ printf("0x20000000 - 0x207FFFFF Single Flash Chip (8MB)\n");
+ printf("Using PF4 and PF5 as a 2M bank switch\n");
+ printf
+ ("Please type command flinfo for information on Sectors\n");
+ *pPORTF_FER &= ~(PF4|PF5);
+ *pPORTFIO_DIR |= (PF4|PF5);
+ *pPORTFIO_CLEAR = (PF4|PF5);
+ SSYNC();
+ }
+
+ /* unlock all flash sectors (default: locked) */
+ memIndex = CONFIG_SYS_FLASH_BASE;
+
+ /* [0...2 MB] */
+ for (; memIndex < 0x20020000; memIndex += 0x4000) {
+ /* first 4 sectors a 32Kbyte */
+ *(volatile unsigned short *)memIndex = 0x0050; /* clear status reg */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x0060; /* lock setup */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00d0; /* lock confirm */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00ff; /* read array mode */
+ SSYNC();
+ }
+ for (; memIndex < 0x20800000; memIndex += 0x10000) {
+ SWITCH_BANK;
+ *(volatile unsigned short *)memIndex = 0x0050; /* clear status reg */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x0060; /* lock setup */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00d0; /* lock confirm */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00ff; /* read array mode */
+ SSYNC();
+ SWITCH_BACK;
+ }
+
+ return CONFIG_SYS_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case MT_MANUFACT_P33:
+ printf("MT_MANUFACT_P33");
+ break;
+ case MT_MANUFACT_P30:
+ printf("MT_MANUFACT_P30");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect, i;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing\n");
+ return ERR_INVAL;
+ } else {
+ printf("Sector %i erased.\n", i);
+ }
+ }
+ }
+ return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, unsigned char *src, ulong addr, ulong cnt)
+{
+ long i = 0;
+ unsigned long ulOffset = addr - CONFIG_SYS_FLASH_BASE;
+ int nLeftover = cnt % 4;
+ int iSectors = 0;
+ int iFirst_sector = 0;
+ int iProgress = cnt / (4 * 20);
+
+ iFirst_sector = (int)(ulOffset / FLASH_SECTOR_SIZE);
+ for (iSectors = 1; (iSectors * FLASH_SECTOR_SIZE) < cnt; iSectors++) ;
+
+ printf("Bytes for programming: %li\n", cnt);
+ printf("First sector: %d\n", iFirst_sector);
+ printf("Sectors needed:%d\n", iSectors);
+
+ if (iFirst_sector + iSectors > FLASH_TOT_SECT) {
+ printf("Not enough free flash-sectors!\n");
+ return ERR_INVAL;
+ }
+
+ for (i = iFirst_sector; i < (iFirst_sector + iSectors); i++) {
+ if (check_sector(i) == ERR_NOT_ERASED)
+ printf("Sector %ld not erased\n", i);
+ /* return ERR_NOT_ERASED; */
+ }
+
+ printf("[ ]\n[");
+
+ for (i = 0; (i < cnt / 4); i++) {
+ if ((i % iProgress) == 0)
+ printf(".");
+
+ if (write_flash(ulOffset, (((int *)src)[i])) < 0) {
+ printf("Error programming the flash\n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ if (write_flash(ulOffset, (((int *)src)[i] >> 16)) < 0) {
+ printf("Error programming the flash\n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ }
+ if (nLeftover > 0) {
+ if (write_flash(ulOffset, ((int *)src)[i]) < 0) {
+ printf("Error programming flash\n");
+ return ERR_TIMOUT;
+ }
+ }
+ printf("]\n");
+ return ERR_OK;
+}
+
+/* assumes all bytes to be within a single bank */
+static int read_flash_chunk(char *addr, int size, char *dest)
+{
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ memIndex = (unsigned long)addr;
+ SWITCH_BANK;
+ memcpy((void *)dest, (void *)memIndex, size);
+ SWITCH_BACK;
+ return size;
+}
+
+
+/* handles bank switching (we hope) */
+
+int read_flash(char *addr, int size, char *dest)
+{
+ int chunk;
+ int done;
+ chunk = size;
+ done = 0;
+ if (addr < (char *)0x20200000) {
+ if ((addr + size) > (char *)0x20200000) {
+ chunk = (int)((char *)0x20200000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ if (addr < (char *)0x20400000) {
+ if ((addr + size) > (char *)0x20400000) {
+ chunk = (int)((char *)0x20400000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ if (addr < (char *)0x20600000) {
+ if ((addr + size) > (char *)0x20600000) {
+ chunk = (int)((char *)0x20600000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ done += read_flash_chunk(addr, chunk, dest);
+ return done;
+}
+
+static int check_sector(unsigned short usSector)
+{
+ long i = 0;
+ int ret;
+ unsigned short iData;
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ printf("Checking sector %d", usSector);
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE +
+ (usSector * FLASH_SECTOR_SIZE));
+
+ SWITCH_BANK;
+
+ ret = ERR_OK;
+
+ for (i = 0; i < FLASH_SECTOR_SIZE; i += 2) {
+
+ iData = *(volatile unsigned short *)memIndex;
+ if (iData != 0xFFFF) {
+ ret = ERR_NOT_ERASED;
+ break;
+ }
+ memIndex += 2;
+ }
+
+ SWITCH_BACK;
+
+ if (ret == ERR_OK) {
+ printf(" ... sector empty\n");
+ } else {
+ printf(" ... not empty!\n");
+ }
+ return ret;
+}
+
+static int write_flash(long nOffset, unsigned short nValue)
+{
+
+ unsigned long memIndex;
+ unsigned long nTimeout;
+ unsigned short status;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE + nOffset);
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050; /* Reset status register */
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0040;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = (unsigned short)nValue;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ nTimeout++;
+ SSYNC();
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ nTimeout = FLASH_TIMEOUT;
+ do {
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "read array mode". */
+ SSYNC();
+ nTimeout--;
+ } while ((*(volatile unsigned short *)memIndex
+ != (unsigned short)nValue) && (nTimeout > 0));
+ if (!nTimeout)
+ status = 0xee00;
+
+ SWITCH_BACK;
+
+ if (status == 0x0080)
+ return (ERR_OK);
+ else
+ return (ERR_TIMOUT);
+}
+
+static int erase_block_flash(int nBlock, unsigned long address)
+{
+ unsigned long memIndex;
+ unsigned short status;
+ unsigned long nTimeout;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ if ((nBlock < 0) || (nBlock >= CONFIG_SYS_MAX_FLASH_SECT)) {
+ printf("Invalid sector number\n");
+ return -1;
+ }
+
+ memIndex = (unsigned long)(address); /* + CONFIG_SYS_FLASH_BASE); */
+
+ if ( memIndex == 0x20000000 ) {
+
+ SWITCH_BANK;
+
+ for (;(u_long)memIndex < 0x20020000;memIndex+=0x4000) {
+ *(volatile unsigned short *)memIndex = 0x0050;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0020;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x00d0;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ SSYNC();
+ nTimeout++;
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "Read Array Mode" */
+ SSYNC();
+ }
+
+ } else {
+
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0020;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x00d0;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ SSYNC();
+ nTimeout++;
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "Read Array Mode" */
+ SSYNC();
+
+ }
+
+ SWITCH_BACK;
+
+ if (status == 0xFF00)
+ return -1;
+ else
+ return ERR_OK;
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+ long int manufacturer_id;
+ volatile unsigned short *nFlashAddr;
+
+ nFlashAddr = (unsigned short *)CONFIG_SYS_FLASH_BASE;
+
+ *nFlashAddr = 0x0090; /* Read identifier command. */
+ SSYNC();
+
+ manufacturer_id = *nFlashAddr;
+ SSYNC();
+ nFlashAddr++;
+ dev_id = *nFlashAddr;
+ SSYNC();
+
+ *nFlashAddr = 0x00ff; /* Return to read array mode. */
+ SSYNC();
+
+ dev_id = ((manufacturer_id << 16) | dev_id);
+ return dev_id;
+}
+
+int do_pf4(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ if (dflg > 0) {
+ *pPORTFIO_SET = PF4;
+ } else {
+ *pPORTFIO_CLEAR = PF4;
+ }
+ } else {
+ data = *pPORTFIO;
+ printf(" PF4 command argc = %d data %04x\n", argc, data);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(pf4, CONFIG_SYS_MAXARGS, 1, do_pf4,
+ "pf4\t- set/clear pf4 mem bank switch\n",
+ "\npf4 1 ...\n" "pf4 0 ...\n");
+
+int do_pf5(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ if (dflg > 0)
+ *pPORTFIO_SET = PF5;
+ else
+ *pPORTFIO_CLEAR = PF5;
+ } else {
+ data = *pPORTFIO;
+ printf(" PF5 command argc = %d data %04x\n", argc, data);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(pf5, CONFIG_SYS_MAXARGS, 1, do_pf5,
+ "pf5\t- set/clear pf5 mem bank switch\n",
+ "\npf5 1 ...\n" "pf5 0 ...\n");
+
+int do_readflash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long src;
+ unsigned long dest;
+ int size;
+
+ if (argc == 4) {
+ src = simple_strtoul(argv[1], NULL, 16);
+ dest = simple_strtoul(argv[2], NULL, 16);
+ size = simple_strtol(argv[3], NULL, 16);
+ if (src < CONFIG_SYS_FLASH_BASE ||
+ (src + size) > CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in flash.\n",
+ src, src + size);
+ return 1;
+ }
+ if (dest < CONFIG_SYS_SDRAM_BASE ||
+ (dest + size) > CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in RAM.\n",
+ dest, dest + size);
+ return 1;
+ }
+ read_flash((char *)src, size, (char *)dest);
+ printf("Done.\n");
+ } else
+ printf("Error: Arguments missing.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(flread, 4, 0, do_readflash,
+ "flread - read from flash\n",
+ "reads flash memory and handles pf4/pf5 bank switching\n\n"
+ "readflash addr dest length\n"
+ " (all arguments in hex)\n");
diff --git a/board/tcm-bf537/spi_flash.c b/board/tcm-bf537/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/tcm-bf537/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
new file mode 100644
index 0000000..9208aa2
--- /dev/null
+++ b/board/tcm-bf537/tcm-bf537.c
@@ -0,0 +1,44 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix TCM-BF537 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(unsigned char *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/tcm-bf537/u-boot.lds.S b/board/tcm-bf537/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/tcm-bf537/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
new file mode 100644
index 0000000..4cf60cb
--- /dev/null
+++ b/include/configs/tcm-bf537.h
@@ -0,0 +1,135 @@
+/*
+ * U-boot - Configuration file for TCM-BF537 board
+ */
+
+#ifndef __CONFIG_TCM_BF537_H__
+#define __CONFIG_TCM_BF537_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+#define CONFIG_EBIU_SDRRC_VAL 0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+/* TCM-BF537E has no PHY on it
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME tcm-bf537
+*/
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SYS_HAS_FLASHSWITCH 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+#define FLASH_TOT_SECT 64
+#define CONFIG_SYS_FLASH_SIZE 0x800000
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (34 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 35/42] Blackfin: tcm-bf537: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 17:34 ` Scott Wood
2009-02-10 6:21 ` [U-Boot] [PATCH 37/42] Blackfin: cm-bf527: " Mike Frysinger
` (5 subsequent siblings)
41 siblings, 1 reply; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/cm-bf548/.gitignore | 1 +
board/cm-bf548/Makefile | 60 ++++++++
board/cm-bf548/cm-bf548.c | 79 ++++++++++
board/cm-bf548/config.mk | 36 +++++
board/cm-bf548/nand.c | 2 +
board/cm-bf548/spi_flash.c | 2 +
board/cm-bf548/u-boot.lds.S | 124 ++++++++++++++++
board/cm-bf548/video.c | 339 +++++++++++++++++++++++++++++++++++++++++++
include/configs/cm-bf548.h | 150 +++++++++++++++++++
12 files changed, 797 insertions(+), 2 deletions(-)
create mode 100644 board/cm-bf548/.gitignore
create mode 100644 board/cm-bf548/Makefile
create mode 100644 board/cm-bf548/cm-bf548.c
create mode 100644 board/cm-bf548/config.mk
create mode 100644 board/cm-bf548/nand.c
create mode 100644 board/cm-bf548/spi_flash.c
create mode 100644 board/cm-bf548/u-boot.lds.S
create mode 100644 board/cm-bf548/video.c
create mode 100644 include/configs/cm-bf548.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d1bfee..37f8118 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -860,6 +860,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF533 BF533
CM-BF537E BF537
+ CM-BF548 BF548
CM-BF561 BF561
TCM-BF537 BF537
diff --git a/MAKEALL b/MAKEALL
index 806e7a9..32f770e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -791,6 +791,7 @@ LIST_blackfin=" \
bf561-ezkit \
cm-bf533 \
cm-bf537e \
+ cm-bf548 \
cm-bf561 \
tcm-bf537 \
"
diff --git a/Makefile b/Makefile
index 65a6c9f..7a50144 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,7 +3293,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf561 tcm-bf537
+BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3456,7 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{,t}cm-bf5{33,37e,61}/u-boot.lds \
+ $(obj)board/{,t}cm-bf5{33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/cm-bf548/.gitignore b/board/cm-bf548/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/cm-bf548/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
new file mode 100644
index 0000000..c7c297e
--- /dev/null
+++ b/board/cm-bf548/Makefile
@@ -0,0 +1,60 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+COBJS-$(CONFIG_VIDEO) += video.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
new file mode 100644
index 0000000..1c26600
--- /dev/null
+++ b/board/cm-bf548/cm-bf548.c
@@ -0,0 +1,79 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF548 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+int board_early_init_f(void)
+{
+ /* Port H: PH8 - PH13 == A4 - A9
+ * address lines of the parallel asynchronous memory interface
+ */
+
+ /************************************************
+ * configure GPIO *
+ * set port H function enable register *
+ * configure PH8-PH13 as peripheral (not GPIO) *
+ *************************************************/
+ bfin_write_PORTH_FER(0x3F03);
+
+ /************************************************
+ * set port H MUX to configure PH8-PH13 *
+ * 1st Function (MUX = 00) (bits 16-27 == 0) *
+ * Set to address signals A4-A9 *
+ *************************************************/
+ bfin_write_PORTH_MUX(0);
+
+ /************************************************
+ * set port H direction register *
+ * enable PH8-PH13 as outputs *
+ *************************************************/
+ bfin_write_PORTH_DIR_SET(0x3F00);
+
+ /* Port I: PI0 - PH14 == A10 - A24
+ * address lines of the parallel asynchronous memory interface
+ */
+
+ /************************************************
+ * set port I function enable register *
+ * configure PI0-PI14 as peripheral (not GPIO) *
+ *************************************************/
+ bfin_write_PORTI_FER(0x7fff);
+
+ /**************************************************
+ * set PORT I MUX to configure PI14-PI0 as *
+ * 1st Function (MUX=00) - address signals A10-A24 *
+ ***************************************************/
+ bfin_write_PORTI_MUX(0);
+
+ /****************************************
+ * set PORT I direction register *
+ * enable PI0 - PI14 as outputs *
+ *****************************************/
+ bfin_write_PORTI_DIR_SET(0x7fff);
+
+ return 0;
+}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
new file mode 100644
index 0000000..0dbce93
--- /dev/null
+++ b/board/cm-bf548/config.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART := --dma 1
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf548/nand.c b/board/cm-bf548/nand.c
new file mode 100644
index 0000000..bce563e
--- /dev/null
+++ b/board/cm-bf548/nand.c
@@ -0,0 +1,2 @@
+/* Share the nand driver */
+#include "../bf548-ezkit/nand.c"
diff --git a/board/cm-bf548/spi_flash.c b/board/cm-bf548/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/cm-bf548/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/cm-bf548/u-boot.lds.S b/board/cm-bf548/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/cm-bf548/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
new file mode 100644
index 0000000..49dbe77
--- /dev/null
+++ b/board/cm-bf548/video.c
@@ -0,0 +1,339 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+#ifdef CONFIG_VIDEO
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES 480 /*Horizontal Resolution */
+#define LCD_Y_RES 272 /* Vertical Resolution */
+
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+#define DMA_BUS_SIZE 32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* -- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period TH - 525 - Clock
+ * Pulse width THp - 41 - Clock
+ * Horizontal period THd - 480 - Clock
+ * Back porch THb - 2 - Clock
+ * Front porch THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period TV - 286 - Line
+ * Pulse width TVp - 10 - Line
+ * Vertical period TVd - 272 - Line
+ * Back porch TVb - 2 - Line
+ * Front porch TVf - 2 - Line
+ */
+
+#define LCD_CLK (8*1000*1000) /* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE 525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME 286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL 41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY 43
+
+/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB (EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY 12
+
+#define EPPI_CLIP 0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL (0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+ u32 sclk = get_sclk();
+
+ /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+ return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+ u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+ bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+ bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+ bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+ bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+ bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+ bfin_write_EPPI0_FRAME(EPPI_FRAME);
+ bfin_write_EPPI0_LINE(EPPI_LINE);
+
+ bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+ bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+ bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+ bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+ bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+ bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+ RGB_FMT_EN);
+#else
+ bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+ ~RGB_FMT_EN);
+#endif
+
+}
+
+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+
+#if defined(CONFIG_DEB_DMA_URGENT)
+ *pEBIU_DDRQUE |= DEB2_URGENT;
+#endif
+
+ *pDMA12_START_ADDR = dst;
+
+ /* X count */
+ *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
+ *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* Y count */
+ *pDMA12_Y_COUNT = LCD_Y_RES;
+ *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
+
+ /* DMA Config */
+ *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO; /* autobuffer mode */
+}
+
+void Init_Ports(void)
+{
+ *pPORTF_MUX = 0x00000000;
+ *pPORTF_FER |= 0xFFFF; /* PPI0..15 */
+
+ *pPORTG_MUX &=
+ ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
+ PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
+ *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */
+
+#if !defined(CONFIG_VIDEO_RGB666)
+ *pPORTD_MUX &=
+ ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
+ PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
+ *pPORTD_MUX |=
+ (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 |
+ PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
+ *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */
+#endif
+
+ *pPORTE_FER &= ~PE3; /* DISP */
+ *pPORTE_DIR_SET = PE3;
+ *pPORTE_SET = PE3;
+
+}
+
+void EnableDMA(void)
+{
+ *pDMA12_CONFIG |= DMAEN;
+}
+
+void DisableDMA(void)
+{
+ *pDMA12_CONFIG &= ~DMAEN;
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ Init_PPI();
+ EnablePPI();
+
+ return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data,
+ logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
+ DMA_SIZE16);
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
+ | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
+ | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ device_t videodev;
+
+ u8 *dst;
+ u32 fbmem_size =
+ LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+ bfin_logo.data = data;
+#endif
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
+ fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+ videodev.putc = video_putc; /* 'putc' function */
+ videodev.puts = video_puts; /* 'puts' function */
+
+ error = device_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
+
+#endif
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
new file mode 100644
index 0000000..e7eabf0
--- /dev/null
+++ b/include/configs/cm-bf548.h
@@ -0,0 +1,150 @@
+/*
+ * U-boot - Configuration file for cm-bf548 board
+ */
+
+#ifndef __CONFIG_CM_BF548_H__
+#define __CONFIG_CM_BF548_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf548-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
+#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
+#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
+
+/* Default bank mapping:
+ * Async Bank 0 - 32MB Burst Flash
+ * Async Bank 1 - Ethernet
+ * Async Bank 2 - Nothing
+ * Async Bank 3 - Nothing
+ */
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
+#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
+#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_HOSTNAME cm-bf548
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* Total Size of Environment Sector */
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20008000
+#define CONFIG_ENV_OFFSET 0x8000
+#define CONFIG_ENV_SIZE 0x8000
+#endif
+#define ENV_IS_EMBEDDED_CUSTOM
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 1
+
+#ifndef __ADSPBF542__
+/* Don't waste time transferring a logo over the UART */
+# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+# define CONFIG_VIDEO
+# endif
+# define CONFIG_DEB_DMA_URGENT
+#endif
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
+#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: new board port
2009-02-10 6:21 ` [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: " Mike Frysinger
@ 2009-02-10 17:34 ` Scott Wood
2009-02-10 17:51 ` Mike Frysinger
0 siblings, 1 reply; 58+ messages in thread
From: Scott Wood @ 2009-02-10 17:34 UTC (permalink / raw)
To: u-boot
On Tue, Feb 10, 2009 at 01:21:14AM -0500, Mike Frysinger wrote:
> diff --git a/board/cm-bf548/nand.c b/board/cm-bf548/nand.c
> new file mode 100644
> index 0000000..bce563e
> --- /dev/null
> +++ b/board/cm-bf548/nand.c
> @@ -0,0 +1,2 @@
> +/* Share the nand driver */
> +#include "../bf548-ezkit/nand.c"
> diff --git a/board/cm-bf548/spi_flash.c b/board/cm-bf548/spi_flash.c
> new file mode 100644
> index 0000000..8784741
> --- /dev/null
> +++ b/board/cm-bf548/spi_flash.c
> @@ -0,0 +1,2 @@
> +/* Share the spi flash code */
> +#include "../bf537-stamp/spi_flash.c"
Why not move the driver to a more appropriate directory, if it's going to
be shared?
-Scott
^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: new board port
2009-02-10 17:34 ` Scott Wood
@ 2009-02-10 17:51 ` Mike Frysinger
0 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 17:51 UTC (permalink / raw)
To: u-boot
On Tuesday 10 February 2009 12:34:03 Scott Wood wrote:
> On Tue, Feb 10, 2009 at 01:21:14AM -0500, Mike Frysinger wrote:
> > diff --git a/board/cm-bf548/nand.c b/board/cm-bf548/nand.c
> > new file mode 100644
> > index 0000000..bce563e
> > --- /dev/null
> > +++ b/board/cm-bf548/nand.c
> > @@ -0,0 +1,2 @@
> > +/* Share the nand driver */
> > +#include "../bf548-ezkit/nand.c"
> > diff --git a/board/cm-bf548/spi_flash.c b/board/cm-bf548/spi_flash.c
> > new file mode 100644
> > index 0000000..8784741
> > --- /dev/null
> > +++ b/board/cm-bf548/spi_flash.c
> > @@ -0,0 +1,2 @@
> > +/* Share the spi flash code */
> > +#include "../bf537-stamp/spi_flash.c"
>
> Why not move the driver to a more appropriate directory, if it's going to
> be shared?
hmm, the nand driver has already been moved, so the bf54x boards need
updating. the spi_flash.c driver is deprecated and ive been working on
getting the common spiflash driver up to date instead.
thanks for pointing the nand onoe ut
-mike
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [U-Boot] [PATCH 37/42] Blackfin: cm-bf527: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (35 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 36/42] Blackfin: cm-bf548: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 38/42] Blackfin: bf537-pnav: " Mike Frysinger
` (4 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/cm-bf527/.gitignore | 1 +
board/cm-bf527/Makefile | 59 ++++
board/cm-bf527/cm-bf527.c | 59 ++++
board/cm-bf527/config.mk | 32 +++
board/cm-bf527/flash-defines.h | 51 ++++
board/cm-bf527/flash.c | 589 ++++++++++++++++++++++++++++++++++++++++
board/cm-bf527/gpio.c | 74 +++++
board/cm-bf527/nand.c | 2 +
board/cm-bf527/spi_flash.c | 2 +
board/cm-bf527/u-boot.lds.S | 124 +++++++++
include/configs/cm-bf527.h | 144 ++++++++++
14 files changed, 1141 insertions(+), 2 deletions(-)
create mode 100644 board/cm-bf527/.gitignore
create mode 100644 board/cm-bf527/Makefile
create mode 100644 board/cm-bf527/cm-bf527.c
create mode 100644 board/cm-bf527/config.mk
create mode 100644 board/cm-bf527/flash-defines.h
create mode 100644 board/cm-bf527/flash.c
create mode 100644 board/cm-bf527/gpio.c
create mode 100644 board/cm-bf527/nand.c
create mode 100644 board/cm-bf527/spi_flash.c
create mode 100644 board/cm-bf527/u-boot.lds.S
create mode 100644 include/configs/cm-bf527.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 37f8118..f56fccf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -858,6 +858,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+ CM-BF527 BF527
CM-BF533 BF533
CM-BF537E BF537
CM-BF548 BF548
diff --git a/MAKEALL b/MAKEALL
index 32f770e..362730a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -789,6 +789,7 @@ LIST_blackfin=" \
bf538f-ezkit \
bf548-ezkit \
bf561-ezkit \
+ cm-bf527 \
cm-bf533 \
cm-bf537e \
cm-bf548 \
diff --git a/Makefile b/Makefile
index 7a50144..8fbc58f 100644
--- a/Makefile
+++ b/Makefile
@@ -3293,7 +3293,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
+BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3456,7 +3456,7 @@ clean:
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
- $(obj)board/{,t}cm-bf5{33,37e,48,61}/u-boot.lds \
+ $(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
diff --git a/board/cm-bf527/.gitignore b/board/cm-bf527/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/cm-bf527/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
new file mode 100644
index 0000000..f3d5b0b
--- /dev/null
+++ b/board/cm-bf527/Makefile
@@ -0,0 +1,59 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o gpio.o flash.o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c
new file mode 100644
index 0000000..712f05d
--- /dev/null
+++ b/board/cm-bf527/cm-bf527.c
@@ -0,0 +1,59 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF527 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ return;
+ }
+
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/cm-bf527/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf527/flash-defines.h b/board/cm-bf527/flash-defines.h
new file mode 100644
index 0000000..07308e5
--- /dev/null
+++ b/board/cm-bf527/flash-defines.h
@@ -0,0 +1,51 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ * Edited by Jahshan Bhatti, jabhatti91@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_TIMEOUT 0xffffff
+#define FLASH_SECTOR_SIZE 0x20000
+#define MT_MANUFACT_P30 0x0089881A
+#define MT_MANUFACT_P33 0x00898820
+
+int get_codes(void);
+static int erase_block_flash(int, unsigned long);
+/* static int write_data(long lStart, long lCount, long lStride, int *pnData); */
+static int write_flash(long nOffset, unsigned short nValue);
+static int check_sector(unsigned short usSector);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#endif
diff --git a/board/cm-bf527/flash.c b/board/cm-bf527/flash.c
new file mode 100644
index 0000000..889bdf5
--- /dev/null
+++ b/board/cm-bf527/flash.c
@@ -0,0 +1,589 @@
+/*
+ * U-boot - flash.c Flash driver for MT28F320J3FS-11
+ *
+
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * based on EZ-KIT flash driver
+ * Edited by Thomas Tamandl, thomas.tamandl at bluetechnix.at
+ * Edited by Jahshan Bhatti, jabhatti91 at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include "flash-defines.h"
+
+static int write_flash(long nOffset, unsigned short nValue);
+static int erase_block_flash(int nBlock, unsigned long address);
+
+#define SWITCH_BANK \
+ do { \
+ if (memIndex >= 0x20600000) { \
+ *pPORTHIO_SET = PH9; \
+ *pPORTGIO_SET = PG11; \
+ memIndex -= 0x600000; \
+ crossed4 = 1; \
+ crossed5 = 1; \
+ } else if (memIndex >= 0x20400000) { \
+ *pPORTHIO_CLEAR = PH9; \
+ *pPORTGIO_SET = PG11; \
+ memIndex -= 0x400000; \
+ crossed5 = 1; \
+ } else if (memIndex >= 0x20200000) { \
+ *pPORTHIO_SET = PH9; \
+ *pPORTGIO_CLEAR = PG11; \
+ memIndex -= 0x200000; \
+ crossed4 = 1; \
+ } else { \
+ *pPORTHIO_CLEAR = PH9; \
+ *pPORTGIO_CLEAR = PG11; \
+ } \
+ SSYNC(); \
+ } while (0)
+
+#define SWITCH_BACK \
+ do { \
+ if (crossed4) { \
+ *pPORTHIO_CLEAR = PH9; \
+ memIndex += 0x200000; \
+ crossed4 = 0; \
+ SSYNC(); \
+ } \
+ if (crossed5) { \
+ *pPORTGIO_CLEAR = PG11; \
+ memIndex += 0x400000; \
+ crossed5 = 0; \
+ SSYNC(); \
+ } \
+ } while (0)
+
+unsigned long flash_init(void)
+{
+ int i = 0;
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ if (CONFIG_SYS_MAX_FLASH_BANKS > 1)
+ printf("Only FLASH bank 0 will be used!");
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ if (get_codes() == MT_MANUFACT_P33)
+ flash_info[0].flash_id = MT_MANUFACT_P33;
+ else if (get_codes() == MT_MANUFACT_P30)
+ flash_info[0].flash_id = MT_MANUFACT_P30;
+ printf("Device ID of the Flash is %lx\n", flash_info[0].flash_id);
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++)
+ flash_info[0].start[i] =
+ (CONFIG_SYS_FLASH_BASE + (i * FLASH_SECTOR_SIZE));
+ flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+ flash_info[0].sector_count = FLASH_TOT_SECT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN
+ && CONFIG_SYS_FLASH_SIZE == 0x200000) {
+ printf("## Unknown FLASH on Bank 0\n");
+ } else {
+ printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
+ printf("Memory Map for the Flash\n");
+ printf("0x20000000 - 0x207FFFFF Single Flash Chip (8MB)\n");
+ printf("Using PH9 and PG11 as a 2M bank switch\n");
+ printf
+ ("Please type command flinfo for information on Sectors\n");
+ *pPORTH_FER &= ~PH9;
+ *pPORTG_FER &= ~PG11;
+ *pPORTHIO_DIR |= PH9;
+ *pPORTGIO_DIR |= PG11;
+ *pPORTHIO_CLEAR = PH9;
+ *pPORTGIO_CLEAR = PG11;
+ SSYNC();
+ }
+
+ /* unlock all flash sectors (default: locked) */
+ memIndex = CONFIG_SYS_FLASH_BASE;
+
+ /* [0...2 MB] */
+ for (; memIndex < 0x20020000; memIndex += 0x4000) {
+ /* first 4 sectors a 32Kbyte */
+ *(volatile unsigned short *)memIndex = 0x0050; /* clear status reg */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x0060; /* lock setup */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00d0; /* lock confirm */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00ff; /* read array mode */
+ SSYNC();
+ }
+ for (; memIndex < 0x20800000; memIndex += 0x10000) {
+ SWITCH_BANK;
+ *(volatile unsigned short *)memIndex = 0x0050; /* clear status reg */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x0060; /* lock setup */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00d0; /* lock confirm */
+ SSYNC();
+ *(volatile unsigned short *)memIndex = 0x00ff; /* read array mode */
+ SSYNC();
+ SWITCH_BACK;
+ }
+
+ return CONFIG_SYS_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case MT_MANUFACT_P33:
+ printf("MT_MANUFACT_P33");
+ break;
+ case MT_MANUFACT_P30:
+ printf("MT_MANUFACT_P30");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect, i;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing\n");
+ return ERR_INVAL;
+ } else {
+ printf("Sector %i erased.\n", i);
+ }
+ }
+ }
+ return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, unsigned char *src, ulong addr, ulong cnt)
+{
+ long i = 0;
+ unsigned long ulOffset = addr - CONFIG_SYS_FLASH_BASE;
+ int nLeftover = cnt % 4;
+ int iSectors = 0;
+ int iFirst_sector = 0;
+ int iProgress = cnt / (4 * 20);
+
+ iFirst_sector = (int)(ulOffset / FLASH_SECTOR_SIZE);
+ for (iSectors = 1; (iSectors * FLASH_SECTOR_SIZE) < cnt; iSectors++) ;
+
+ printf("Bytes for programming: %li\n", cnt);
+ printf("First sector: %d\n", iFirst_sector);
+ printf("Sectors needed:%d\n", iSectors);
+
+ if (iFirst_sector + iSectors > FLASH_TOT_SECT) {
+ printf("Not enough free flash-sectors!\n");
+ return ERR_INVAL;
+ }
+
+ for (i = iFirst_sector; i < (iFirst_sector + iSectors); i++) {
+ if (check_sector(i) == ERR_NOT_ERASED)
+ printf("Sector %ld not erased\n", i);
+ /* return ERR_NOT_ERASED; */
+ }
+
+ printf("[ ]\n[");
+
+ for (i = 0; (i < cnt / 4); i++) {
+ if ((i % iProgress) == 0)
+ printf(".");
+
+ if (write_flash(ulOffset, (((int *)src)[i])) < 0) {
+ printf("Error programming the flash\n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ if (write_flash(ulOffset, (((int *)src)[i] >> 16)) < 0) {
+ printf("Error programming the flash\n");
+ return ERR_TIMOUT;
+ }
+ ulOffset += 2;
+ }
+ if (nLeftover > 0) {
+ if (write_flash(ulOffset, ((int *)src)[i]) < 0) {
+ printf("Error programming flash\n");
+ return ERR_TIMOUT;
+ }
+ }
+ printf("]\n");
+ return ERR_OK;
+}
+
+/* assumes all bytes to be within a single bank */
+static int read_flash_chunk(char *addr, int size, char *dest)
+{
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ memIndex = (unsigned long)addr;
+ SWITCH_BANK;
+ memcpy((void *)dest, (void *)memIndex, size);
+ SWITCH_BACK;
+ return size;
+}
+
+
+/* handles bank switching (we hope) */
+
+int read_flash(char *addr, int size, char *dest)
+{
+ int chunk;
+ int done;
+ chunk = size;
+ done = 0;
+ if (addr < (char *)0x20200000) {
+ if ((addr + size) > (char *)0x20200000) {
+ chunk = (int)((char *)0x20200000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ if (addr < (char *)0x20400000) {
+ if ((addr + size) > (char *)0x20400000) {
+ chunk = (int)((char *)0x20400000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ if (addr < (char *)0x20600000) {
+ if ((addr + size) > (char *)0x20600000) {
+ chunk = (int)((char *)0x20600000 - addr);
+ done = read_flash_chunk(addr, chunk, dest);
+ addr += chunk;
+ dest += chunk;
+ chunk = size - chunk;
+ }
+ }
+ done += read_flash_chunk(addr, chunk, dest);
+ return done;
+}
+
+static int check_sector(unsigned short usSector)
+{
+ long i = 0;
+ int ret;
+ unsigned short iData;
+ unsigned long memIndex;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ printf("Checking sector %d", usSector);
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE +
+ (usSector * FLASH_SECTOR_SIZE));
+
+ SWITCH_BANK;
+
+ ret = ERR_OK;
+
+ for (i = 0; i < FLASH_SECTOR_SIZE; i += 2) {
+
+ iData = *(volatile unsigned short *)memIndex;
+ if (iData != 0xFFFF) {
+ ret = ERR_NOT_ERASED;
+ break;
+ }
+ memIndex += 2;
+ }
+
+ SWITCH_BACK;
+
+ if (ret == ERR_OK) {
+ printf(" ... sector empty\n");
+ } else {
+ printf(" ... not empty!\n");
+ }
+ return ret;
+}
+
+static int write_flash(long nOffset, unsigned short nValue)
+{
+
+ unsigned long memIndex;
+ unsigned long nTimeout;
+ unsigned short status;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ memIndex = (unsigned long)(CONFIG_SYS_FLASH_BASE + nOffset);
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050; /* Reset status register */
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0040;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = (unsigned short)nValue;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ nTimeout++;
+ SSYNC();
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ nTimeout = FLASH_TIMEOUT;
+ do {
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "read array mode". */
+ SSYNC();
+ nTimeout--;
+ } while ((*(volatile unsigned short *)memIndex
+ != (unsigned short)nValue) && (nTimeout > 0));
+ if (!nTimeout)
+ status = 0xee00;
+
+ SWITCH_BACK;
+
+ if (status == 0x0080)
+ return (ERR_OK);
+ else
+ return (ERR_TIMOUT);
+}
+
+static int erase_block_flash(int nBlock, unsigned long address)
+{
+ unsigned long memIndex;
+ unsigned short status;
+ unsigned long nTimeout;
+ int crossed4 = 0;
+ int crossed5 = 0;
+
+ if ((nBlock < 0) || (nBlock >= CONFIG_SYS_MAX_FLASH_SECT)) {
+ printf("Invalid sector number\n");
+ return -1;
+ }
+
+ memIndex = (unsigned long)(address); /* + CONFIG_SYS_FLASH_BASE); */
+
+ if ( memIndex == 0x20000000 ) {
+
+ SWITCH_BANK;
+
+ for (;(u_long)memIndex < 0x20020000;memIndex+=0x4000) {
+ *(volatile unsigned short *)memIndex = 0x0050;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0020;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x00d0;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ SSYNC();
+ nTimeout++;
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "Read Array Mode" */
+ SSYNC();
+ }
+
+ } else {
+
+ SWITCH_BANK;
+
+ *(volatile unsigned short *)memIndex = 0x0050;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x0020;
+ SSYNC();
+
+ *(volatile unsigned short *)memIndex = 0x00d0;
+ SSYNC();
+
+ nTimeout = 0;
+ do {
+ status = *(volatile unsigned short *)memIndex;
+ SSYNC();
+ nTimeout++;
+ }
+ while (((status & 0x0080) == 0x00) && (nTimeout < FLASH_TIMEOUT));
+ if (nTimeout >= FLASH_TIMEOUT)
+ status = 0xff00;
+
+ *(volatile unsigned short *)memIndex = 0xff; /* Back to "Read Array Mode" */
+ SSYNC();
+
+ }
+
+ SWITCH_BACK;
+
+ if (status == 0xFF00)
+ return -1;
+ else
+ return ERR_OK;
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+ long int manufacturer_id;
+ volatile unsigned short *nFlashAddr;
+
+ nFlashAddr = (unsigned short *)CONFIG_SYS_FLASH_BASE;
+
+ *nFlashAddr = 0x0090; /* Read identifier command. */
+ SSYNC();
+
+ manufacturer_id = *nFlashAddr;
+ SSYNC();
+ nFlashAddr++;
+ dev_id = *nFlashAddr;
+ SSYNC();
+
+ *nFlashAddr = 0x00ff; /* Return to read array mode. */
+ SSYNC();
+
+ dev_id = ((manufacturer_id << 16) | dev_id);
+ return dev_id;
+}
+
+int do_ph9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ if (dflg > 0) {
+ *pPORTHIO_SET = PH9;
+ } else {
+ *pPORTHIO_CLEAR = PH9;
+ }
+ } else {
+ data = *pPORTHIO;
+ printf(" PH9 command argc = %d data %04x\n", argc, data);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(ph9, CONFIG_SYS_MAXARGS, 1, do_ph9,
+ "ph9\t- set/clear ph9 mem bank switch\n",
+ "\nph9 1 ...\n" "ph9 0 ...\n");
+
+int do_pg11(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ if (dflg > 0) {
+ *pPORTGIO_SET = PG11;
+ } else {
+ *pPORTGIO_CLEAR = PG11;
+ }
+ } else {
+ data = *pPORTGIO;
+ printf(" PG11 command argc = %d data %04x\n", argc, data);
+ }
+ return 0;
+}
+
+U_BOOT_CMD(pg11, CONFIG_SYS_MAXARGS, 1, do_pg11,
+ "pg11\t- set/clear pg11 mem bank switch\n",
+ "\npg11 1 ...\n" "pg11 0 ...\n");
+
+int do_readflash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long src;
+ unsigned long dest;
+ int size;
+
+ if (argc == 4) {
+ src = simple_strtoul(argv[1], NULL, 16);
+ dest = simple_strtoul(argv[2], NULL, 16);
+ size = simple_strtol(argv[3], NULL, 16);
+ if (src < CONFIG_SYS_FLASH_BASE ||
+ (src + size) > CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in flash.\n",
+ src, src + size);
+ return 1;
+ }
+ if (dest < CONFIG_SYS_SDRAM_BASE ||
+ (dest + size) > CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE) {
+ printf("Error: Memory area %#08lx to %#08lx is not in RAM.\n",
+ dest, dest + size);
+ return 1;
+ }
+ read_flash((char *)src, size, (char *)dest);
+ printf("Done.\n");
+ } else
+ printf("Error: Arguments missing.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(flread, 4, 0, do_readflash,
+ "flread - read from flash\n",
+ "reads flash memory and handles ph9/pg11 bank switching\n\n"
+ "readflash addr dest length\n"
+ " (all arguments in hex)\n");
diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c
new file mode 100644
index 0000000..dcf641b
--- /dev/null
+++ b/board/cm-bf527/gpio.c
@@ -0,0 +1,74 @@
+/*
+ * Control GPIO pins on the fly
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+
+int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc != 3) {
+ show_usage:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* parse the behavior */
+ ulong port_cmd = 0;
+ switch (argv[1][0]) {
+ case 'i': break;
+ case 's': port_cmd = (PORTFIO_SET - PORTFIO); break;
+ case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break;
+ case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break;
+ default: goto show_usage;
+ }
+
+ /* parse the pin with format: [p]<fgh><#> */
+ const char *str_pin = argv[2];
+
+ /* grab the [p]<fgh> portion */
+ ulong port_base;
+ if (*str_pin == 'p') ++str_pin;
+ switch (*str_pin) {
+ case 'f': port_base = PORTFIO; break;
+ case 'g': port_base = PORTGIO; break;
+ case 'h': port_base = PORTHIO; break;
+ default: goto show_usage;
+ }
+
+ /* grab the <#> portion */
+ ulong pin = simple_strtoul(str_pin+1, NULL, 10);
+ ulong pin_mask = (1 << pin);
+ if (pin > 15)
+ goto show_usage;
+
+ /* finally, let's do it: set direction and exec command */
+ switch (*str_pin) {
+ case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break;
+ case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break;
+ case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break;
+ }
+
+ ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO);
+ if (argv[1][0] == 'i')
+ bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask);
+ else {
+ bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask);
+ bfin_write16(port_base + port_cmd, pin_mask);
+ }
+
+ printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]);
+
+ return 0;
+}
+
+U_BOOT_CMD(gpio, 3, 0, do_gpio,
+ "gpio - set/clear/toggle gpio output pins\n",
+ "<s|c|t> <port><pin>\n"
+ " - set/clear/toggle the specified pin\n");
diff --git a/board/cm-bf527/nand.c b/board/cm-bf527/nand.c
new file mode 100644
index 0000000..bce563e
--- /dev/null
+++ b/board/cm-bf527/nand.c
@@ -0,0 +1,2 @@
+/* Share the nand driver */
+#include "../bf548-ezkit/nand.c"
diff --git a/board/cm-bf527/spi_flash.c b/board/cm-bf527/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/cm-bf527/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/cm-bf527/u-boot.lds.S b/board/cm-bf527/u-boot.lds.S
new file mode 100644
index 0000000..3e8be35
--- /dev/null
+++ b/board/cm-bf527/u-boot.lds.S
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
new file mode 100644
index 0000000..65c976c
--- /dev/null
+++ b/include/configs/cm-bf527.h
@@ -0,0 +1,144 @@
+/*
+ * U-boot - Configuration file for CM-BF527 board
+ */
+
+#ifndef __CONFIG_CM_BF527_H__
+#define __CONFIG_CM_BF527_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf527-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 21
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+#define CONFIG_EBIU_SDRRC_VAL 0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used sametime as ethernet)
+ */
+/* #define CONFIG_BFIN_NFC */
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_CMD_NAND
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+ !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+#define CONFIG_HOSTNAME cm-bf527
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define FLASH_TOT_SECT 64
+#define CONFIG_SYS_FLASH_SIZE 0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+#else
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20008000
+#define CONFIG_ENV_OFFSET 0x8000
+#define CONFIG_ENV_SIZE 0x8000
+#endif
+#define ENV_IS_EMBEDDED_CUSTOM
+
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD 2
+#define CONFIG_SYS_I2C_FRAM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 38/42] Blackfin: bf537-pnav: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (36 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 37/42] Blackfin: cm-bf527: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 39/42] Blackfin: bf537-minotaur: " Mike Frysinger
` (3 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +-
board/bf537-pnav/.gitignore | 1 +
board/bf537-pnav/Makefile | 59 +++++++++
board/bf537-pnav/bf537-pnav.c | 43 +++++++
board/bf537-pnav/config.mk | 32 +++++
board/bf537-pnav/nand.c | 100 +++++++++++++++
board/bf537-pnav/spi_flash.c | 2 +
board/bf537-pnav/u-boot.lds.S | 143 ++++++++++++++++++++++
include/configs/bf537-pnav.h | 271 +++++++++++++++++++++++++++++++++++++++++
11 files changed, 655 insertions(+), 1 deletions(-)
create mode 100644 board/bf537-pnav/.gitignore
create mode 100644 board/bf537-pnav/Makefile
create mode 100644 board/bf537-pnav/bf537-pnav.c
create mode 100644 board/bf537-pnav/config.mk
create mode 100644 board/bf537-pnav/nand.c
create mode 100644 board/bf537-pnav/spi_flash.c
create mode 100644 board/bf537-pnav/u-boot.lds.S
create mode 100644 include/configs/bf537-pnav.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f56fccf..5a790e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF527-EZKIT BF527
BF533-EZKIT BF533
BF533-STAMP BF533
+ BF537-PNAV BF537
BF537-STAMP BF537
BF538F-EZKIT BF538
BF548-EZKIT BF548
diff --git a/MAKEALL b/MAKEALL
index 362730a..6fe71aa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -785,6 +785,7 @@ LIST_blackfin=" \
bf527-ezkit \
bf533-ezkit \
bf533-stamp \
+ bf537-pnav \
bf537-stamp \
bf538f-ezkit \
bf548-ezkit \
diff --git a/Makefile b/Makefile
index 8fbc58f..8c1e1f7 100644
--- a/Makefile
+++ b/Makefile
@@ -3290,7 +3290,7 @@ suzaku_config: unconfig
# Analog Devices boards
BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
- bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
+ bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
@@ -3458,6 +3458,7 @@ clean:
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
$(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
+ $(obj)board/bf537-pnav/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf537-pnav/.gitignore b/board/bf537-pnav/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf537-pnav/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
new file mode 100644
index 0000000..e6077b4
--- /dev/null
+++ b/board/bf537-pnav/Makefile
@@ -0,0 +1,59 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
new file mode 100644
index 0000000..3d6ef47
--- /dev/null
+++ b/board/bf537-pnav/bf537-pnav.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF537 PNAV board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/bf537-pnav/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf537-pnav/nand.c b/board/bf537-pnav/nand.c
new file mode 100644
index 0000000..181e83d
--- /dev/null
+++ b/board/bf537-pnav/nand.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <nand.h>
+
+#define CONCAT(a,b,c,d) a ## b ## c ## d
+#define PORT(a,b) CONCAT(pPORT,a,b,)
+
+#ifndef CONFIG_NAND_GPIO_PORT
+#define CONFIG_NAND_GPIO_PORT F
+#endif
+
+/*
+ * hardware specific access to control-lines
+ */
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ register struct nand_chip *this = mtd->priv;
+ u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
+ else
+ IO_ADDR_W = CONFIG_SYS_NAND_BASE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
+ else
+ IO_ADDR_W = CONFIG_SYS_NAND_BASE;
+ this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
+ }
+ this->IO_ADDR_R = this->IO_ADDR_W;
+
+ /* Drain the writebuffer */
+ SSYNC();
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int bfin_device_ready(struct mtd_info *mtd)
+{
+ int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
+ SSYNC();
+ return ret;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
+ *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
+ *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
+
+ nand->cmd_ctrl = bfin_hwcontrol;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->dev_ready = bfin_device_ready;
+ nand->chip_delay = 30;
+
+ return 0;
+}
diff --git a/board/bf537-pnav/spi_flash.c b/board/bf537-pnav/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf537-pnav/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf537-pnav/u-boot.lds.S b/board/bf537-pnav/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/bf537-pnav/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
new file mode 100644
index 0000000..6ecf15f
--- /dev/null
+++ b/include/configs/bf537-pnav.h
@@ -0,0 +1,271 @@
+/*
+ * U-boot - Configuration file for BF537 PNAV board
+ */
+
+#ifndef __CONFIG_BF537_PNAV_H__
+#define __CONFIG_BF537_PNAV_H__
+
+#include <asm/blackfin-config-pre.h>
+
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_BAUDRATE 115200
+
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_DCACHE_OFF
+#define CONFIG_ICACHE_OFF
+
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE 0
+
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 24576000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 20
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 4
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+
+#define CONFIG_LOADS_ECHO 1
+
+#define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
+ /* configuration lookup from the BOOTP/DHCP server, */
+ /* but not try to load any image using TFTP */
+
+/*
+ * Network Settings
+ */
+/* network support */
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME bf537-pnav
+#endif
+
+#define CONFIG_ROOTPATH /romfs
+/* Uncomment next line to use fixed MAC address */
+#define CONFIG_ETHADDR 02:80:ad:24:21:18
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+#else
+# define CONFIG_BOOTDELAY 5
+#endif
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+#define CONFIG_BF537_NAND /* Add nand flash support */
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMI
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#ifndef CONFIG_BFIN_MAC
+#undef CONFIG_CMD_NET
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=yaffs"
+#define CONFIG_LOADADDR 0x1000000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+# define BOOT_ENV_SETTINGS \
+ "update=tftpboot $(loadaddr) u-boot.bin;" \
+ "protect off 0x20000000 0x2003FFFF;" \
+ "erase 0x20000000 0x2003FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+# define BOOT_ENV_SETTINGS \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0"
+#else
+# define BOOT_ENV_SETTINGS
+#endif
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux;" \
+ "run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
+ "flashboot=bootm 0x20100000\0" \
+ "nandboot=nand read $(loadaddr) 0x20000 0x100000;bootm $(loadaddr)" \
+ BOOT_ENV_SETTINGS
+
+#define CONFIG_SYS_PROMPT "bfin> "
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x03F00000 /* 1 ... 63 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
+#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000
+
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) || (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET 0x4000
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define ENV_IS_EMBEDDED_CUSTOM
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
+
+
+#define FLASH_TOT_SECT 71
+
+
+/*
+ * Serial Flash Infomation
+ */
+ /* NAME Sector Size Sectors
+ * m25p05 32 * 1024 2
+ * m25p10 32 * 1024 4
+ * m25p20 64 * 1024 4
+ * m25p40 64 * 1024 8
+ * m25p80 64 * 1024 16
+ * m25p16 64 * 1024 32
+ * m25p32 64 * 1024 64
+ * m25p64 64 * 1024 128
+ * m25p128 256 * 1024 64
+ */
+
+#define CONFIG_SPI
+#define CONFIG_SYS_I2C_FRAM
+
+/*
+ * Board NAND Infomation
+ */
+
+#define CONFIG_SYS_NAND_ADDR 0x20100000
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define SECTORSIZE 512
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+#define BFIN_NAND_READY PF12
+
+#define CONFIG_NAND_GPIO_PORT H
+
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int timeout = 0; \
+ while(!(*pPORTHIO & BFIN_NAND_READY)) \
+ if (timeout++ > 100000) \
+ break; \
+ } while (0)
+
+#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
+#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+
+#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+#define CONFIG_EBIU_SDRRC_VAL 0x3b7
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+#define CONFIG_EBIU_SDBCTL_VAL 0x25
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 39/42] Blackfin: bf537-minotaur: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (37 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 38/42] Blackfin: bf537-pnav: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 40/42] Blackfin: bf537-srv1: " Mike Frysinger
` (2 subsequent siblings)
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 5 +
MAKEALL | 1 +
Makefile | 5 +-
board/bf537-minotaur/.gitignore | 1 +
board/bf537-minotaur/Makefile | 58 +++++++++
board/bf537-minotaur/bf537-minotaur.c | 43 +++++++
board/bf537-minotaur/config.mk | 33 +++++
board/bf537-minotaur/spi_flash.c | 2 +
board/bf537-minotaur/u-boot.lds.S | 143 ++++++++++++++++++++++
include/configs/bf537-minotaur.h | 214 +++++++++++++++++++++++++++++++++
10 files changed, 504 insertions(+), 1 deletions(-)
create mode 100644 board/bf537-minotaur/.gitignore
create mode 100644 board/bf537-minotaur/Makefile
create mode 100644 board/bf537-minotaur/bf537-minotaur.c
create mode 100644 board/bf537-minotaur/config.mk
create mode 100644 board/bf537-minotaur/spi_flash.c
create mode 100644 board/bf537-minotaur/u-boot.lds.S
create mode 100644 include/configs/bf537-minotaur.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 5a790e0..5bf9dd3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -866,6 +866,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF561 BF561
TCM-BF537 BF537
+Martin Strubel <strubel@section5.ch>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+ BF537-minotaur BF537
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index 6fe71aa..bb5a305 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -785,6 +785,7 @@ LIST_blackfin=" \
bf527-ezkit \
bf533-ezkit \
bf533-stamp \
+ bf537-minotaur \
bf537-pnav \
bf537-stamp \
bf538f-ezkit \
diff --git a/Makefile b/Makefile
index 8c1e1f7..a2e7c89 100644
--- a/Makefile
+++ b/Makefile
@@ -3295,6 +3295,9 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
# Bluetechnix tinyboards
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
+# Misc third party boards
+BFIN_BOARDS += bf537-minotaur
+
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@$(MAKE) -s -B $(obj)include/autoconf.mk
@@ -3458,7 +3461,7 @@ clean:
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
$(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
- $(obj)board/bf537-pnav/u-boot.lds \
+ $(obj)board/bf537-{minotaur,pnav}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf537-minotaur/.gitignore b/board/bf537-minotaur/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf537-minotaur/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
new file mode 100644
index 0000000..9e667db
--- /dev/null
+++ b/board/bf537-minotaur/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c
new file mode 100644
index 0000000..e273c50
--- /dev/null
+++ b/board/bf537-minotaur/bf537-minotaur.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: CSP BF537 Minotaur board\n");
+ printf(" Support: http://www.camsig.co.uk/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk
new file mode 100644
index 0000000..feafcef
--- /dev/null
+++ b/board/bf537-minotaur/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf537-minotaur/spi_flash.c b/board/bf537-minotaur/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf537-minotaur/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf537-minotaur/u-boot.lds.S b/board/bf537-minotaur/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/bf537-minotaur/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
new file mode 100644
index 0000000..c2df972
--- /dev/null
+++ b/include/configs/bf537-minotaur.h
@@ -0,0 +1,214 @@
+/*
+ * U-boot - Configuration file for CSP Minotaur board
+ *
+ * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
+ * Minotaur config, brushed up for official uClinux dist.
+ * Parallel flash support disabled, SPI flash boot command
+ * added ('run flashboot').
+ *
+ * Flash image map:
+ *
+ * 0x00000000 u-boot bootstrap
+ * 0x00010000 environment
+ * 0x00020000 u-boot code
+ * 0x00030000 uImage.initramfs
+ *
+ */
+
+#ifndef __CONFIG_BF537_MINOTAUR_H__
+#define __CONFIG_BF537_MINOTAUR_H__
+
+#include <asm/blackfin-config-pre.h>
+
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_BAUDRATE 57600
+
+/* We don't have a parallel flash chip there */
+#define CONFIG_SYS_NO_FLASH
+
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE 0
+/* define CONFIG_BF537_MINOTAUR_LEDCMD to enable LED command*/
+/*#define CONFIG_BF537_MINOTAUR_LEDCMD 1*/
+
+#define CONFIG_PANIC_HANG 1
+
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL*/
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 20
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * rarpb, bootp or dhcp commands will perform only a
+ * configuration lookup from the BOOTP/DHCP server
+ * but not try to load any image using TFTP
+ */
+#define CONFIG_SYS_AUTOLOAD "no"
+
+/*
+ * Network Settings
+ */
+/* network support */
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME bf537-minotaur
+#endif
+
+#define CONFIG_ROOTPATH /romfs
+/* Use a fixed MAC address for booting up. Firstboot linux
+ * must fetch a valid MAC from the production server. */
+#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+#else
+# define CONFIG_BOOTDELAY 5
+#endif
+
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
+#define CONFIG_LOADADDR 0x1000000
+
+#define BOOT_ENV_SETTINGS \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
+ "flashboot= eeprom read 0x1000000 0x30000 0x280000;" \
+ "bootm 0x1000000\0"
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux;" \
+ "run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
+ BOOT_ENV_SETTINGS
+
+#define CONFIG_SYS_PROMPT "minotaur> "
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
+#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+
+
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED_CUSTOM
+
+/*
+ * Serial Flash Infomation
+ */
+#define CONFIG_SPI
+#define CONFIG_SYS_I2C_FRAM
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+#define CONFIG_EBIU_SDRRC_VAL 0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x13
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 40/42] Blackfin: bf537-srv1: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (38 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 39/42] Blackfin: bf537-minotaur: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 41/42] Blackfin: blackstamp: " Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 42/42] Blackfin: ibf-dsp561: " Mike Frysinger
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 4 +-
board/bf537-srv1/.gitignore | 1 +
board/bf537-srv1/Makefile | 58 +++++++++++
board/bf537-srv1/bf537-srv1.c | 43 ++++++++
board/bf537-srv1/config.mk | 33 +++++++
board/bf537-srv1/spi_flash.c | 2 +
board/bf537-srv1/u-boot.lds.S | 143 +++++++++++++++++++++++++++
include/configs/bf537-srv1.h | 214 +++++++++++++++++++++++++++++++++++++++++
10 files changed, 498 insertions(+), 2 deletions(-)
create mode 100644 board/bf537-srv1/.gitignore
create mode 100644 board/bf537-srv1/Makefile
create mode 100644 board/bf537-srv1/bf537-srv1.c
create mode 100644 board/bf537-srv1/config.mk
create mode 100644 board/bf537-srv1/spi_flash.c
create mode 100644 board/bf537-srv1/u-boot.lds.S
create mode 100644 include/configs/bf537-srv1.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 5bf9dd3..74f38d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -870,6 +870,7 @@ Martin Strubel <strubel@section5.ch>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF537-minotaur BF537
+ BF537-srv1 BF537
#########################################################################
# End of MAINTAINERS list #
diff --git a/MAKEALL b/MAKEALL
index bb5a305..c8cb1f4 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -787,6 +787,7 @@ LIST_blackfin=" \
bf533-stamp \
bf537-minotaur \
bf537-pnav \
+ bf537-srv1 \
bf537-stamp \
bf538f-ezkit \
bf548-ezkit \
diff --git a/Makefile b/Makefile
index a2e7c89..73d778c 100644
--- a/Makefile
+++ b/Makefile
@@ -3296,7 +3296,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
# Misc third party boards
-BFIN_BOARDS += bf537-minotaur
+BFIN_BOARDS += bf537-minotaur bf537-srv1
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3461,7 +3461,7 @@ clean:
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
$(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
- $(obj)board/bf537-{minotaur,pnav}/u-boot.lds \
+ $(obj)board/bf537-{minotaur,pnav,srv1}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/bf537-srv1/.gitignore b/board/bf537-srv1/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/bf537-srv1/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
new file mode 100644
index 0000000..9e667db
--- /dev/null
+++ b/board/bf537-srv1/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c
new file mode 100644
index 0000000..77de5f1
--- /dev/null
+++ b/board/bf537-srv1/bf537-srv1.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Surveyor SRV1 board\n");
+ printf(" Support: http://www.surveyor.com/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+void board_get_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk
new file mode 100644
index 0000000..feafcef
--- /dev/null
+++ b/board/bf537-srv1/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf537-srv1/spi_flash.c b/board/bf537-srv1/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/bf537-srv1/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/bf537-srv1/u-boot.lds.S b/board/bf537-srv1/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/bf537-srv1/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
new file mode 100644
index 0000000..a28c83f
--- /dev/null
+++ b/include/configs/bf537-srv1.h
@@ -0,0 +1,214 @@
+/*
+ * U-boot - Configuration file for CSP Minotaur board
+ *
+ * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
+ * Minotaur config, brushed up for official uClinux dist.
+ * Parallel flash support disabled, SPI flash boot command
+ * added ('run flashboot').
+ *
+ * Flash image map:
+ *
+ * 0x00000000 u-boot bootstrap
+ * 0x00010000 environment
+ * 0x00020000 u-boot code
+ * 0x00030000 uImage.initramfs
+ *
+ */
+
+#ifndef __CONFIG_BF537_SRV1_H__
+#define __CONFIG_BF537_SRV1_H__
+
+#include <asm/blackfin-config-pre.h>
+
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_BAUDRATE 57600
+
+/* We don't have a parallel flash chip there */
+#define CONFIG_SYS_NO_FLASH
+
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#endif
+
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE 0
+/* define CONFIG_BF537_SRV1_LEDCMD to enable LED command*/
+/*#define CONFIG_BF537_SRV1_LEDCMD 1*/
+
+#define CONFIG_PANIC_HANG 1
+
+#define CONFIG_RTC_BFIN 1
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 22118400
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
+/* 1=CLKIN/2 */
+#define CONFIG_CLKIN_HALF 0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/* 1=bypass PLL*/
+#define CONFIG_PLL_BYPASS 0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
+/* Values can range from 1-64 */
+#define CONFIG_VCO_MULT 20
+/* CONFIG_CCLK_DIV controls what the core clock divider is */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 2
+
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * rarpb, bootp or dhcp commands will perform only a
+ * configuration lookup from the BOOTP/DHCP server
+ * but not try to load any image using TFTP
+ */
+#define CONFIG_SYS_AUTOLOAD "no"
+
+/*
+ * Network Settings
+ */
+/* network support */
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME bf537-srv1
+#endif
+
+#define CONFIG_ROOTPATH /romfs
+/* Use a fixed MAC address for booting up. Firstboot linux
+ * must fetch a valid MAC from the production server. */
+#define CONFIG_ETHADDR 02:80:ad:20:31:42
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY -1
+#else
+# define CONFIG_BOOTDELAY 5
+#endif
+
+#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
+#define CONFIG_LOADADDR 0x1000000
+
+#define BOOT_ENV_SETTINGS \
+ "update=tftpboot $(loadaddr) u-boot.ldr;" \
+ "eeprom write $(loadaddr) 0x0 $(filesize);\0" \
+ "flashboot= eeprom read 0x1000000 0x30000 0x320000;" \
+ "bootm 0x1000000\0"
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off\0" \
+ "ramboot=tftpboot $(loadaddr) linux;" \
+ "run ramargs;run addip;bootelf\0" \
+ "nfsboot=tftpboot $(loadaddr) linux;" \
+ "run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ NETWORK_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
+ BOOT_ENV_SETTINGS
+
+#define CONFIG_SYS_PROMPT "srv1> "
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
+#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+
+
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+#define ENV_IS_EMBEDDED_CUSTOM
+
+/*
+ * Serial Flash Infomation
+ */
+#define CONFIG_SPI
+#define CONFIG_SYS_I2C_FRAM
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+
+#define CONFIG_EBIU_SDRRC_VAL 0x2ac
+#define CONFIG_EBIU_SDGCTL_VAL 0x91110d
+#define CONFIG_EBIU_SDBCTL_VAL 0x13
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 41/42] Blackfin: blackstamp: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (39 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 40/42] Blackfin: bf537-srv1: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
2009-02-10 6:21 ` [U-Boot] [PATCH 42/42] Blackfin: ibf-dsp561: " Mike Frysinger
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 5 +
MAKEALL | 1 +
Makefile | 4 +-
board/blackstamp/.gitignore | 1 +
board/blackstamp/Makefile | 58 +++++++++
board/blackstamp/blackstamp.c | 53 ++++++++
board/blackstamp/config.mk | 32 +++++
board/blackstamp/spi_flash.c | 2 +
board/blackstamp/u-boot.lds.S | 143 ++++++++++++++++++++++
include/configs/blackstamp.h | 266 +++++++++++++++++++++++++++++++++++++++++
10 files changed, 563 insertions(+), 2 deletions(-)
create mode 100644 board/blackstamp/.gitignore
create mode 100644 board/blackstamp/Makefile
create mode 100644 board/blackstamp/blackstamp.c
create mode 100644 board/blackstamp/config.mk
create mode 100644 board/blackstamp/spi_flash.c
create mode 100644 board/blackstamp/u-boot.lds.S
create mode 100644 include/configs/blackstamp.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 74f38d8..8d95bde 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -872,6 +872,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF537-minotaur BF537
BF537-srv1 BF537
+Wojtek Skulski <skulski@pas.rochester.edu>
+Benjamin Matthews <mben12@gmail.com>
+
+ BLACKSTAMP BF532
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index c8cb1f4..69a8a5f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -792,6 +792,7 @@ LIST_blackfin=" \
bf538f-ezkit \
bf548-ezkit \
bf561-ezkit \
+ blackstamp \
cm-bf527 \
cm-bf533 \
cm-bf537e \
diff --git a/Makefile b/Makefile
index 73d778c..cc2abf8 100644
--- a/Makefile
+++ b/Makefile
@@ -3296,7 +3296,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
# Misc third party boards
-BFIN_BOARDS += bf537-minotaur bf537-srv1
+BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3461,7 +3461,7 @@ clean:
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
$(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \
$(obj)board/bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}/u-boot.lds \
- $(obj)board/bf537-{minotaur,pnav,srv1}/u-boot.lds \
+ $(obj)board/{bf537-{minotaur,pnav,srv1},blackstamp}/u-boot.lds \
$(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/blackstamp/.gitignore b/board/blackstamp/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/blackstamp/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
new file mode 100644
index 0000000..9e667db
--- /dev/null
+++ b/board/blackstamp/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
new file mode 100644
index 0000000..0b25e8b
--- /dev/null
+++ b/board/blackstamp/blackstamp.c
@@ -0,0 +1,53 @@
+/*
+ * U-boot - blackstamp.c BlackStamp board specific routines
+ * Most code stolen from boards/bf533-stamp/bf533-stamp.c
+ * Edited to the BlackStamp by Ben Matthews for UR LLE
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: BlackStamp\n");
+ printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#ifdef SHARED_RESOURCES
+void swap_to(int device_id)
+{
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
+ SSYNC();
+ if (device_id == ETHERNET)
+ bfin_write_FIO_FLAG_S(PF0);
+ else if (device_id == FLASH)
+ bfin_write_FIO_FLAG_C(PF0);
+ else
+ printf("Unknown device to switch\n");
+ SSYNC();
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+}
+#endif
diff --git a/board/blackstamp/config.mk b/board/blackstamp/config.mk
new file mode 100644
index 0000000..f4a5a80
--- /dev/null
+++ b/board/blackstamp/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/blackstamp/spi_flash.c b/board/blackstamp/spi_flash.c
new file mode 100644
index 0000000..8784741
--- /dev/null
+++ b/board/blackstamp/spi_flash.c
@@ -0,0 +1,2 @@
+/* Share the spi flash code */
+#include "../bf537-stamp/spi_flash.c"
diff --git a/board/blackstamp/u-boot.lds.S b/board/blackstamp/u-boot.lds.S
new file mode 100644
index 0000000..8ddfa81
--- /dev/null
+++ b/board/blackstamp/u-boot.lds.S
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
new file mode 100644
index 0000000..8f8f69b
--- /dev/null
+++ b/include/configs/blackstamp.h
@@ -0,0 +1,266 @@
+/*
+ * U-boot - Configuration file for BlackStamp board
+ * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
+ * as a template
+ * See http://blackfin.uclinux.org/gf/project/blackstamp/
+ */
+
+#ifndef __CONFIG_BLACKSTAMP_H__
+#define __CONFIG_BLACKSTAMP_H__
+
+#include <asm/blackfin-config-pre.h>
+
+/*
+ * Debugging: Set these options if you're having problems
+ */
+/*
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+*/
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options
+ * Be sure to set the Silicon Revision Correctly
+ */
+#define CONFIG_BFIN_CPU bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
+
+/*
+ * Board settings
+ */
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE 0x20300300
+
+/* FLASH/ETHERNET uses the same address range
+ * Depending on what you have the CPLD doing
+ * this probably isn't needed
+ */
+#define SHARED_RESOURCES 1
+
+/* Is I2C bit-banged? */
+#undef CONFIG_SOFT_I2
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 16
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 3
+
+/*
+ * Network settings
+ */
+
+#ifdef CONFIG_DRIVER_SMC91111
+#define CONFIG_IPADDR 192.168.0.15
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_HOSTNAME blackstamp
+#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
+#define CONFIG_SYS_AUTOLOAD "no"
+
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
+#endif
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_OFFSET 0x4000
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (384 << 10)
+
+/*
+ * Command settings
+ */
+
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_ENV_OVERWRITE 1
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_DRIVER_SMC91111
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+# define CONFIG_CMD_I2C
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#define CONFIG_BOOTARGS \
+ "root=/dev/mtdblock0 rw " \
+ "earlyprintk=serial,uart" \
+ MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+
+#ifdef CONFIG_CMD_KGDB
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+# define UBOOT_ENV_FILE "u-boot.bin"
+# else
+# define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+# define UBOOT_ENV_UPDATE \
+ "eeprom write $(loadaddr) 0x0 $(filesize)"
+# else
+# define UBOOT_ENV_UPDATE \
+ "protect off 0x20000000 0x2003FFFF;" \
+ "erase 0x20000000 0x2003FFFF;" \
+ "cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
+# define NETWORK_ENV_SETTINGS \
+ "ubootfile=" UBOOT_ENV_FILE "\0" \
+ "update=" \
+ "tftp $(loadaddr) $(ubootfile);" \
+ UBOOT_ENV_UPDATE \
+ "\0" \
+ "addip=set bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+ "ramboot=" \
+ "tftp $(loadaddr) uImage;" \
+ "run ramargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0" \
+ "nfsargs=set bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3\0" \
+ "nfsboot=" \
+ "tftp $(loadaddr) vmImage;" \
+ "run nfsargs;" \
+ "run addip;" \
+ "bootm" \
+ "\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_UART_CONSOLE 0
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ * Located on the expansion connector on pins 86/85
+ * Note these pins are arbitrarily chosen because we aren't using
+ * them yet. You can (and probably should) change these values!
+ */
+#ifdef CONFIG_SOFT_I2C
+
+#define PF_SCL PF9
+#define PF_SDA PF8
+
+#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
+#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
+#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
+#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SDA; \
+ else \
+ *pFIO_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO_FLAG_S = PF_SCL; \
+ else \
+ *pFIO_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0xFE
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_RTC_BFIN 1
+
+/*
+ * Serial Flash Infomation
+ */
+#define CONFIG_SPI
+#define CONFIG_SYS_I2C_FRAM
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
+/* Values can range from 2-65535 */
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
+#define CONFIG_SPI_BAUD 5
+/* For the M25P64 SCK Should be Kept < 20Mhz */
+
+/*
+ * FLASH organization and environment definitions
+ */
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
+#define CONFIG_EBIU_SDRRC_VAL 0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
+
+/* Even though Rev C boards have Parallel Flash
+ * We aren't supporting it. Newer versions of the
+ * hardware don't support Parallel Flash@all.
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#include <asm/blackfin-config-post.h>
+
+#endif
--
1.6.1.2
^ permalink raw reply related [flat|nested] 58+ messages in thread* [U-Boot] [PATCH 42/42] Blackfin: ibf-dsp561: new board port
2009-02-10 6:20 [U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03 Mike Frysinger
` (40 preceding siblings ...)
2009-02-10 6:21 ` [U-Boot] [PATCH 41/42] Blackfin: blackstamp: " Mike Frysinger
@ 2009-02-10 6:21 ` Mike Frysinger
41 siblings, 0 replies; 58+ messages in thread
From: Mike Frysinger @ 2009-02-10 6:21 UTC (permalink / raw)
To: u-boot
From: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
MAINTAINERS | 5 ++
MAKEALL | 1 +
Makefile | 3 +
board/ibf-dsp561/.gitignore | 1 +
board/ibf-dsp561/Makefile | 57 ++++++++++++++++
board/ibf-dsp561/config.mk | 33 +++++++++
board/ibf-dsp561/ibf-dsp561.c | 25 +++++++
board/ibf-dsp561/u-boot.lds.S | 145 +++++++++++++++++++++++++++++++++++++++++
include/configs/ibf-dsp561.h | 130 ++++++++++++++++++++++++++++++++++++
9 files changed, 400 insertions(+), 0 deletions(-)
create mode 100644 board/ibf-dsp561/.gitignore
create mode 100644 board/ibf-dsp561/Makefile
create mode 100644 board/ibf-dsp561/config.mk
create mode 100644 board/ibf-dsp561/ibf-dsp561.c
create mode 100644 board/ibf-dsp561/u-boot.lds.S
create mode 100644 include/configs/ibf-dsp561.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d95bde..5ad7eab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -877,6 +877,11 @@ Benjamin Matthews <mben12@gmail.com>
BLACKSTAMP BF532
+I-SYST Micromodule <support@i-syst.com>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+
+ IBF-DSP561 BF561
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index 69a8a5f..206a0d6 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -798,6 +798,7 @@ LIST_blackfin=" \
cm-bf537e \
cm-bf548 \
cm-bf561 \
+ ibf-dsp561 \
tcm-bf537 \
"
diff --git a/Makefile b/Makefile
index cc2abf8..36c6517 100644
--- a/Makefile
+++ b/Makefile
@@ -3298,6 +3298,9 @@ BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
# Misc third party boards
BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp
+# I-SYST Micromodule
+BFIN_BOARDS += ibf-dsp561
+
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@$(MAKE) -s -B $(obj)include/autoconf.mk
diff --git a/board/ibf-dsp561/.gitignore b/board/ibf-dsp561/.gitignore
new file mode 100644
index 0000000..945f324
--- /dev/null
+++ b/board/ibf-dsp561/.gitignore
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile
new file mode 100644
index 0000000..daebb74
--- /dev/null
+++ b/board/ibf-dsp561/Makefile
@@ -0,0 +1,57 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk
new file mode 100644
index 0000000..710809a
--- /dev/null
+++ b/board/ibf-dsp561/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c
new file mode 100644
index 0000000..551fc29
--- /dev/null
+++ b/board/ibf-dsp561/ibf-dsp561.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 I-SYST.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: I-SYST IBF-DSP561 Micromodule\n");
+ printf(" Support: http://www.i-syst.com/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
diff --git a/board/ibf-dsp561/u-boot.lds.S b/board/ibf-dsp561/u-boot.lds.S
new file mode 100644
index 0000000..bce99f0
--- /dev/null
+++ b/board/ibf-dsp561/u-boot.lds.S
@@ -0,0 +1,145 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error. If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+ l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
+ l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+ /* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+ lib_generic/zlib.o (.text .text.*)
+ board/ibf-dsp561/ibf-dsp561.o (.text .text.*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text .text.*)
+#endif
+
+ __initcode_start = .;
+ cpu/blackfin/initcode.o (.text .text.*)
+ __initcode_end = .;
+
+ *(.text .text.*)
+ } >ram
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.eh_frame)
+ . = ALIGN(4);
+ } >ram
+
+ .data :
+ {
+ . = ALIGN(256);
+ *(.data .data.*)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ } >ram
+
+ .u_boot_cmd :
+ {
+ ___u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ ___u_boot_cmd_end = .;
+ } >ram
+
+ .text_l1 :
+ {
+ . = ALIGN(4);
+ __stext_l1 = .;
+ *(.l1.text)
+ . = ALIGN(4);
+ __etext_l1 = .;
+ } >l1_code AT>ram
+ __stext_l1_lma = LOADADDR(.text_l1);
+
+ .data_l1 :
+ {
+ . = ALIGN(4);
+ __sdata_l1 = .;
+ *(.l1.data)
+ *(.l1.bss)
+ . = ALIGN(4);
+ __edata_l1 = .;
+ } >l1_data AT>ram
+ __sdata_l1_lma = LOADADDR(.data_l1);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(COMMON)
+ __bss_end = .;
+ } >ram
+}
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
new file mode 100644
index 0000000..6d03c4c
--- /dev/null
+++ b/include/configs/ibf-dsp561.h
@@ -0,0 +1,130 @@
+/*
+ * U-boot - Configuration file for IBF-DSP561 board
+ */
+
+#ifndef __CONFIG_IBF_DSP561__H__
+#define __CONFIG_IBF_DSP561__H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf561-0.5
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 24
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x377
+#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
+#define CONFIG_EBIU_SDBCTL_VAL 0x15
+
+#define CONFIG_EBIU_AMGCTL_VAL 0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
+/* The BF561-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x20004000
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_SOFT_I2C 1
+#define PF_SCL 0x1/*PF0*/
+#define PF_SDA 0x2/*PF1*/
+
+#ifdef CONFIG_SOFT_I2C
+#define I2C_INIT do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0)
+#define I2C_ACTIVE do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0)
+#define I2C_TRISTATE do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0)
+#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SDA; \
+ else \
+ *pFIO0_FLAG_C = PF_SDA; \
+ SSYNC(); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ *pFIO0_FLAG_S = PF_SCL; \
+ else \
+ *pFIO0_FLAG_C = PF_SCL; \
+ SSYNC(); \
+ } while (0)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_UART_CONSOLE 0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif /* __CONFIG_IBF_DSP561__H__ */
--
1.6.1.2
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