From: Jan Kiszka <jan.kiszka@web.de>
To: Nitin A Kamble <nitin.a.kamble@intel.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Avi Kivity <avi@redhat.com>
Subject: Re: [PATCH] QEMU KVM: i386: Fix the cpu reset state
Date: Sat, 06 Jun 2009 09:46:04 +0200 [thread overview]
Message-ID: <4A2A1EBC.1070702@web.de> (raw)
In-Reply-To: <1244150990-8234-1-git-send-email-nitin.a.kamble@intel.com>
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Nitin A Kamble wrote:
> As per the IA32 processor manual, the accessed bit is set to 1 in the
> processor state after reset. qemu pc cpu_reset code was missing this
> accessed bit setting.
>
> Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
> ---
> target-i386/helper.c | 18 ++++++++++++------
> 1 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 7fc5366..573fb5b 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -493,17 +493,23 @@ void cpu_reset(CPUX86State *env)
> env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
>
> cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
> + DESC_R_MASK | DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
>
> env->eip = 0xfff0;
> env->regs[R_EDX] = env->cpuid_version;
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Thanks,
Jan
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WARNING: multiple messages have this Message-ID (diff)
From: Jan Kiszka <jan.kiszka@web.de>
To: Nitin A Kamble <nitin.a.kamble@intel.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Avi Kivity <avi@redhat.com>
Subject: [Qemu-devel] Re: [PATCH] QEMU KVM: i386: Fix the cpu reset state
Date: Sat, 06 Jun 2009 09:46:04 +0200 [thread overview]
Message-ID: <4A2A1EBC.1070702@web.de> (raw)
In-Reply-To: <1244150990-8234-1-git-send-email-nitin.a.kamble@intel.com>
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Nitin A Kamble wrote:
> As per the IA32 processor manual, the accessed bit is set to 1 in the
> processor state after reset. qemu pc cpu_reset code was missing this
> accessed bit setting.
>
> Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
> ---
> target-i386/helper.c | 18 ++++++++++++------
> 1 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 7fc5366..573fb5b 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -493,17 +493,23 @@ void cpu_reset(CPUX86State *env)
> env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
>
> cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
> + DESC_R_MASK | DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
> cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
> - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
> + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
> + DESC_A_MASK);
>
> env->eip = 0xfff0;
> env->regs[R_EDX] = env->cpuid_version;
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Thanks,
Jan
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next prev parent reply other threads:[~2009-06-06 7:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <i386_cpu_reset>
2009-06-04 21:29 ` [PATCH] QEMU KVM: i386: Fix the cpu reset state Nitin A Kamble
2009-06-04 21:29 ` [Qemu-devel] " Nitin A Kamble
2009-06-06 7:46 ` Jan Kiszka [this message]
2009-06-06 7:46 ` [Qemu-devel] " Jan Kiszka
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