[Qemu-devel] [PATCH 0/6] tcg-sparc improvements

[Qemu-devel] [PATCH 0/6] tcg-sparc improvements

[Richard Henderson]

All of these patches are toward reducing the number of TCG opcodes
generated.  Three of the patches reduce the number of real insns
generated as well.  The ANDC and ORC opcodes are already generated
by the ARM, PPC, and Alpha translators.

I now have remote access to a real debian sparc64 machine, so this
has actually been tested on real hardware for a change.  ;-)


r~


Richard Henderson (6):
  tcg-sparc: Implement neg.
  tcg-sparc: Implement not.
  tcg: Optional target implementation of ANDC.
  tcg: Optional target implementation of ORC.
  tcg-sparc: Implement ANDC.
  tcg-sparc: Implement ORC.

 tcg/sparc/tcg-target.c |   30 ++++++++++++++++++++++++++++++
 tcg/sparc/tcg-target.h |   11 +++++++++--
 tcg/tcg-op.h           |   22 ++++++++++++++++++++++
 tcg/tcg-opc.h          |   12 ++++++++++++
 4 files changed, 73 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH 1/6] tcg-sparc: Implement neg.

[Richard Henderson]

The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |   13 +++++++++++++
 tcg/sparc/tcg-target.h |    5 +++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index dd7a598..9f0fd0b 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1126,6 +1126,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         c = ARITH_UMUL;
         goto gen_arith;
 
+    OP_32_64(neg):
+	c = ARITH_SUB;
+	goto gen_arith1;
+
     case INDEX_op_div_i32:
         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
         break;
@@ -1269,6 +1273,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
         break;
 
+    gen_arith1:
+	tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
+	break;
+
     default:
         fprintf(stderr, "unknown opcode 0x%x\n", opc);
         tcg_abort();
@@ -1308,6 +1316,8 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 
+    { INDEX_op_neg_i32, { "r", "rJ" } },
+
     { INDEX_op_brcond_i32, { "r", "rJ" } },
 #if TCG_TARGET_REG_BITS == 32
     { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
@@ -1358,6 +1368,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
+
+    { INDEX_op_neg_i64, { "r", "rJ" } },
+
     { INDEX_op_ext32s_i64, { "r", "ri" } },
     { INDEX_op_ext32u_i64, { "r", "ri" } },
 
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index d27ed5a..66031ba 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -91,15 +91,16 @@ enum {
 #define TCG_TARGET_HAS_div_i32
 #define TCG_TARGET_HAS_div_i64
 
+#define TCG_TARGET_HAS_neg_i32
+
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
+#define TCG_TARGET_HAS_neg_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
 //#define TCG_TARGET_HAS_bswap64_i64
-//#define TCG_TARGET_HAS_neg_i32
-//#define TCG_TARGET_HAS_neg_i64
 
 
 /* Note: must be synced with dyngen-exec.h and Makefile.target */
-- 
1.6.2.5

[Qemu-devel] [PATCH 2/6] tcg-sparc: Implement not.

[Richard Henderson]

The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    6 ++++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 9f0fd0b..b876b3a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -222,6 +222,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
+#define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
@@ -1129,6 +1130,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(neg):
 	c = ARITH_SUB;
 	goto gen_arith1;
+    OP_32_64(not):
+	c = ARITH_ORN;
+	goto gen_arith1;
 
     case INDEX_op_div_i32:
         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
@@ -1317,6 +1321,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_neg_i32, { "r", "rJ" } },
+    { INDEX_op_not_i32, { "r", "rJ" } },
 
     { INDEX_op_brcond_i32, { "r", "rJ" } },
 #if TCG_TARGET_REG_BITS == 32
@@ -1370,6 +1375,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_neg_i64, { "r", "rJ" } },
+    { INDEX_op_not_i64, { "r", "rJ" } },
 
     { INDEX_op_ext32s_i64, { "r", "ri" } },
     { INDEX_op_ext32u_i64, { "r", "ri" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 66031ba..f5ee205 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -92,11 +92,13 @@ enum {
 #define TCG_TARGET_HAS_div_i64
 
 #define TCG_TARGET_HAS_neg_i32
+#define TCG_TARGET_HAS_not_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
 #define TCG_TARGET_HAS_neg_i64
+#define TCG_TARGET_HAS_not_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.2.5

[Qemu-devel] [PATCH 3/6] tcg: Optional target implementation of ANDC.

[Richard Henderson]

Previously ANDC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h  |   11 +++++++++++
 tcg/tcg-opc.h |    6 ++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 13eaa5a..447878d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi
 
 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i32
+    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_and_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i64
+    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_and_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 89db3b4..6d855a7 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -109,6 +109,9 @@ DEF2(not_i32, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_neg_i32
 DEF2(neg_i32, 1, 1, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_andc_i32
+DEF2(andc_i32, 1, 2, 0, 0)
+#endif
 
 #if TCG_TARGET_REG_BITS == 64
 DEF2(mov_i64, 1, 1, 0, 0)
@@ -185,6 +188,9 @@ DEF2(not_i64, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_neg_i64
 DEF2(neg_i64, 1, 1, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_andc_i64
+DEF2(andc_i64, 1, 2, 0, 0)
+#endif
 #endif
 
 /* QEMU specific */
-- 
1.6.2.5

[Qemu-devel] Re: [PATCH 3/6] tcg: Optional target implementation of ANDC.

[Blue Swirl]

On Wed, Feb 17, 2010 at 12:10 AM, Richard Henderson <rth@twiddle.net> wrote:
> Previously ANDC was always implemented by tcg-op.h with
> an explicit NOT opcode.  Allow a target implementation.

I think the convention is to add commented out #defines or #undefs for
all targets, like sparc in bswap case:
//#define TCG_TARGET_HAS_bswap32_i32
//#define TCG_TARGET_HAS_bswap64_i64
or mips:
#undef TCG_TARGET_HAS_bswap32_i32
#undef TCG_TARGET_HAS_bswap16_i32

Then as each target maintainer decides whether it's a good idea to
implement the optional feature, the #undef can be changed to #define
as needed.

The same also applies to ORC patch (#4).

>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h  |   11 +++++++++++
>  tcg/tcg-opc.h |    6 ++++++
>  2 files changed, 17 insertions(+), 0 deletions(-)
>
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 13eaa5a..447878d 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi
>
>  static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  {
> +#ifdef TCG_TARGET_HAS_andc_i32
> +    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
> +#else
>     TCGv_i32 t0;
>     t0 = tcg_temp_new_i32();
>     tcg_gen_not_i32(t0, arg2);
>     tcg_gen_and_i32(ret, arg1, t0);
>     tcg_temp_free_i32(t0);
> +#endif
>  }
>
>  static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  {
> +#ifdef TCG_TARGET_HAS_andc_i64
> +    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
> +#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
> +    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
> +    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
> +#else
>     TCGv_i64 t0;
>     t0 = tcg_temp_new_i64();
>     tcg_gen_not_i64(t0, arg2);
>     tcg_gen_and_i64(ret, arg1, t0);
>     tcg_temp_free_i64(t0);
> +#endif
>  }
>
>  static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 89db3b4..6d855a7 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -109,6 +109,9 @@ DEF2(not_i32, 1, 1, 0, 0)
>  #ifdef TCG_TARGET_HAS_neg_i32
>  DEF2(neg_i32, 1, 1, 0, 0)
>  #endif
> +#ifdef TCG_TARGET_HAS_andc_i32
> +DEF2(andc_i32, 1, 2, 0, 0)
> +#endif
>
>  #if TCG_TARGET_REG_BITS == 64
>  DEF2(mov_i64, 1, 1, 0, 0)
> @@ -185,6 +188,9 @@ DEF2(not_i64, 1, 1, 0, 0)
>  #ifdef TCG_TARGET_HAS_neg_i64
>  DEF2(neg_i64, 1, 1, 0, 0)
>  #endif
> +#ifdef TCG_TARGET_HAS_andc_i64
> +DEF2(andc_i64, 1, 2, 0, 0)
> +#endif
>  #endif
>
>  /* QEMU specific */
> --
> 1.6.2.5
>
>

[Qemu-devel] Re: [PATCH 3/6] tcg: Optional target implementation of ANDC.

[Richard Henderson]

On 02/17/2010 10:34 AM, Blue Swirl wrote:
> On Wed, Feb 17, 2010 at 12:10 AM, Richard Henderson <rth@twiddle.net> wrote:
>> Previously ANDC was always implemented by tcg-op.h with
>> an explicit NOT opcode.  Allow a target implementation.
> 
> I think the convention is to add commented out #defines or #undefs for
> all targets, like sparc in bswap case:
> //#define TCG_TARGET_HAS_bswap32_i32
> //#define TCG_TARGET_HAS_bswap64_i64
> or mips:
> #undef TCG_TARGET_HAS_bswap32_i32
> #undef TCG_TARGET_HAS_bswap16_i32

Apparently that was only done for bswap, because there's a lot of 
optional opcodes that are missing everywhere.  I suppose I could
add those as a separate patch.


r~

[Qemu-devel] [PATCH 4/6] tcg: Optional target implementation of ORC.

[Richard Henderson]

Previously ORC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h  |   11 +++++++++++
 tcg/tcg-opc.h |    6 ++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 447878d..6ae1760 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1715,20 +1715,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i32
+    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_or_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i64
+    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_or_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d855a7..34cdba5 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -112,6 +112,9 @@ DEF2(neg_i32, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_andc_i32
 DEF2(andc_i32, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_orc_i32
+DEF2(orc_i32, 1, 2, 0, 0)
+#endif
 
 #if TCG_TARGET_REG_BITS == 64
 DEF2(mov_i64, 1, 1, 0, 0)
@@ -191,6 +194,9 @@ DEF2(neg_i64, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_andc_i64
 DEF2(andc_i64, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_orc_i64
+DEF2(orc_i64, 1, 2, 0, 0)
+#endif
 #endif
 
 /* QEMU specific */
-- 
1.6.2.5

[Qemu-devel] [PATCH 5/6] tcg-sparc: Implement ANDC.

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    6 ++++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index b876b3a..c1761cc 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -220,6 +220,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
+#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 #define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
@@ -1108,6 +1109,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(and):
         c = ARITH_AND;
         goto gen_arith;
+    OP_32_64(andc):
+        c = ARITH_ANDN;
+        goto gen_arith;
     OP_32_64(or):
         c = ARITH_OR;
         goto gen_arith;
@@ -1313,6 +1317,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_remu_i32, { "r", "r", "rJ" } },
     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
     { INDEX_op_and_i32, { "r", "r", "rJ" } },
+    { INDEX_op_andc_i32, { "r", "r", "rJ" } },
     { INDEX_op_or_i32, { "r", "r", "rJ" } },
     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
@@ -1367,6 +1372,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_remu_i64, { "r", "r", "rJ" } },
     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
     { INDEX_op_and_i64, { "r", "r", "rJ" } },
+    { INDEX_op_andc_i64, { "r", "r", "rJ" } },
     { INDEX_op_or_i64, { "r", "r", "rJ" } },
     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f5ee205..4ea0c19 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -93,12 +93,14 @@ enum {
 
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_andc_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
+#define TCG_TARGET_HAS_andc_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.2.5

[Qemu-devel] [PATCH 6/6] tcg-sparc: Implement ORC.

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    5 +++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index c1761cc..e8bbcdc 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1115,6 +1115,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(or):
         c = ARITH_OR;
         goto gen_arith;
+    OP_32_64(orc):
+        c = ARITH_ORN;
+        goto gen_arith;
     OP_32_64(xor):
         c = ARITH_XOR;
         goto gen_arith;
@@ -1319,6 +1322,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "rJ" } },
     { INDEX_op_andc_i32, { "r", "r", "rJ" } },
     { INDEX_op_or_i32, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i32, { "r", "r", "rJ" } },
     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
@@ -1374,6 +1378,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rJ" } },
     { INDEX_op_andc_i64, { "r", "r", "rJ" } },
     { INDEX_op_or_i64, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i64, { "r", "r", "rJ" } },
     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 4ea0c19..dc68787 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -94,6 +94,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_orc_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
@@ -101,6 +102,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_orc_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.2.5

[Qemu-devel] Re: [PATCH 0/6] tcg-sparc improvements

[Blue Swirl]

On Wed, Feb 17, 2010 at 1:15 AM, Richard Henderson <rth@twiddle.net> wrote:
> All of these patches are toward reducing the number of TCG opcodes
> generated.  Three of the patches reduce the number of real insns
> generated as well.  The ANDC and ORC opcodes are already generated
> by the ARM, PPC, and Alpha translators.
>
> I now have remote access to a real debian sparc64 machine, so this
> has actually been tested on real hardware for a change.  ;-)

Nice work, but the patches don't apply anymore since I applied the
setcond patches.