From: Felix Fietkau <nbd@openwrt.org>
To: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Cc: linville@tuxdriver.com, linux-wireless@vger.kernel.org
Subject: Re: [PATCH 10/26] ath9k: Configure pll control for AR9485
Date: Wed, 01 Dec 2010 17:39:24 +0100 [thread overview]
Message-ID: <4CF67A3C.4060105@openwrt.org> (raw)
In-Reply-To: <1291188775-13707-11-git-send-email-vasanth@atheros.com>
On 2010-12-01 8:32 AM, Vasanthakumar Thiagarajan wrote:
> Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
> ---
> drivers/net/wireless/ath/ath9k/ar9003_phy.c | 16 ++++++++++------
> drivers/net/wireless/ath/ath9k/hw.c | 7 ++++++-
> drivers/net/wireless/ath/ath9k/reg.h | 2 ++
> 3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> index b34a9e9..4e35bda 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> @@ -390,14 +390,18 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
> {
> u32 pll;
>
> - pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
> + if (AR_SREV_9485(ah))
> + pll = 0x142c;
> + else {
> + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
>
> - if (chan && IS_CHAN_HALF_RATE(chan))
> - pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
> - else if (chan && IS_CHAN_QUARTER_RATE(chan))
> - pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
> + if (chan && IS_CHAN_HALF_RATE(chan))
> + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
> + else if (chan && IS_CHAN_QUARTER_RATE(chan))
> + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
>
> - pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
> + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
> + }
>
> return pll;
> }
NACK for this part. Take a look at what gets set for the older chips:
0x5 << AR_RTC_9300_PLL_REFDIV_S == 0x1400
0x2c << AR_RTC_9300_PLL_DIV_S == 0x002c
Hint: it's exactly the same ;)
- Felix
next prev parent reply other threads:[~2010-12-01 16:39 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-01 7:32 [PATCH 00/26] Add support for AR9485 Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 01/26] ath9k_hw: Define hw version macros " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 02/26] ath9k_hw: Add initvals.h " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 03/26] ath9k_hw: Enable hw initialization " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 04/26] ath9k_hw: Initialize mode registers " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 05/26] ath9k_hw: Initialize tx/rx gain table from initvals.h " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 06/26] ath9k_hw: Eeeprom changes " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 07/26] ath9k_hw: Disable LDPC " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 08/26] ath9k: Disable TX STBC " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 09/26] ath9k: Enable extended synch for AR9485 to fix L0s recovery issue Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 10/26] ath9k: Configure pll control for AR9485 Vasanthakumar Thiagarajan
2010-12-01 16:39 ` Felix Fietkau [this message]
2010-12-02 5:05 ` Vasanthakumar Thiagarajan
2010-12-02 5:09 ` Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 11/26] ath9k_hw: Find chansel of AR_PHY_65NM_CH0_SYNTH7 from an array " Vasanthakumar Thiagarajan
2010-12-01 16:45 ` Felix Fietkau
2010-12-02 5:43 ` Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 12/26] ath9k_hw: Add a helper function to get spur channel pointer from cal data for AR9003 family Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 13/26] ath9k: Read spur channel information from eeprom for AR9485 Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 14/26] ath9k_hw: Configure xpa bias level " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 15/26] ath9k_hw: Read and configure antenna diversity control " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 16/26] ath9k_hw: Configure attenuation control only for chain 0 on AR9485 Vasanthakumar Thiagarajan
2010-12-01 16:50 ` Felix Fietkau
2010-12-02 5:13 ` Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 17/26] ath9k_hw: Configure internal regulator for AR9485 Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 18/26] ath9k_hw: Read and configure turnning caps to regulate freq accuracy Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 19/26] ath9k_hw: Configure power control only for chain 0 on AR9485 Vasanthakumar Thiagarajan
2010-12-01 16:51 ` Felix Fietkau
2010-12-01 7:32 ` [PATCH 20/26] ath9k_hw: Program appropriate chianmask for AR9485 before starting AGC/IQ cal Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 21/26] ath9k_hw: Define IQcal correction coefficient registers using index Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 22/26] ath9k_hw: Add IQ cal changes for AR9485 Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 23/26] ath9k_hw: Program appropriate register for temperature compensation cal " Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 24/26] ath9k_hw: Setup paprd only for chain 0 on AR9485 Vasanthakumar Thiagarajan
2010-12-01 16:52 ` Felix Fietkau
2010-12-01 7:32 ` [PATCH 25/26] ath9k_hw: Disable MRC CCK for AR9485 Vasanthakumar Thiagarajan
2010-12-01 7:32 ` [PATCH 26/26] ath9k: Add device id of AR9485 to pci table Vasanthakumar Thiagarajan
2010-12-01 7:52 ` [PATCH 00/26] Add support for AR9485 Luis R. Rodriguez
2010-12-01 8:36 ` Vasanthakumar Thiagarajan
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