[PATCH 1/2] xen/pv: blacklist inappropriate new CPUID bits

[PATCH 1/2] xen/pv: blacklist inappropriate new CPUID bits

[Andre Przywara]

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Hi,

there are some new CPUID bits (and leaves) which Dom0 and PV domains
should not see to avoid trouble, since we don't emulate the features.
This affects 2.6.37+ kernels on upcoming CPUs.
The most prominent one is a topology leaf, which contains information
specific to the physical CPU, not the virtual one. To avoid confusion
(and possibly crashes) due to a confused Dom0 scheduler simply disable
these bits.
Version 2 including DomU support.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>

-- 
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany


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commit 2501d1aee52947f26efbb18ecae79f8b4d9da181
Author: Andre Przywara <andre.przywara@amd.com>
Date:   Wed Jan 26 11:48:05 2011 +0100

    disable CPUID feature bits not emulated to guests

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 724ed0f..407a535 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -427,12 +427,17 @@ static void xc_cpuid_pv_policy(
         clear_bit(X86_FEATURE_IBS, regs[2]);
         clear_bit(X86_FEATURE_SKINIT, regs[2]);
         clear_bit(X86_FEATURE_WDT, regs[2]);
+        clear_bit(X86_FEATURE_LWP, regs[2]);
+        clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
+        clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0xd: /* XSAVE */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         regs[0] = regs[1] = regs[2] = regs[3] = 0;
         break;
     }
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 75d305f..97e3dc4 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -802,11 +802,16 @@ static void pv_cpuid(struct cpu_user_regs *regs)
         __clear_bit(X86_FEATURE_IBS % 32, &c);
         __clear_bit(X86_FEATURE_SKINIT % 32, &c);
         __clear_bit(X86_FEATURE_WDT % 32, &c);
+        __clear_bit(X86_FEATURE_LWP % 32, &c);
+        __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
+        __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         a = b = c = d = 0;
         break;
     default:

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