From: John Crispin <blogic@openwrt.org>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Ralph Hempel <ralph.hempel@lantiq.com>,
David Woodhouse <dwmw2@infradead.org>,
Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>,
linux-mips@linux-mips.org, linux-mtd@lists.infradead.org
Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support
Date: Fri, 04 Mar 2011 21:13:00 +0100 [thread overview]
Message-ID: <4D7147CC.1020009@openwrt.org> (raw)
In-Reply-To: <4D70DDEA.2050308@mvista.com>
Hi,
>> + if (ltq_mtd_probing)
>> + adr ^= 2;
>> + spin_lock_irqsave(&ebu_lock, flags);
>> + temp.x[0] = *((__u16 *)(map->virt + adr));
>> + spin_unlock_irqrestore(&ebu_lock, flags);
>
> Hm, what does this lock gain, if the read is atomic anyway?
the SoC has a hardware arbitor for the EBU. I have so far not been able
to activate it properly and the lock is needed to protect from PCI and
NOR i/o clashing with eachother. i know that the arbitor works when
using lantiqs 2.6.28. i will provide a follow up patch once i figured
how to bring up the arbitor properly. until that time we need to use the
lock.
thanks,
John
WARNING: multiple messages have this Message-ID (diff)
From: John Crispin <blogic@openwrt.org>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
Ralph Hempel <ralph.hempel@lantiq.com>,
linux-mtd@lists.infradead.org,
Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>,
David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH V3 06/10] MIPS: lantiq: add NOR flash support
Date: Fri, 04 Mar 2011 21:13:00 +0100 [thread overview]
Message-ID: <4D7147CC.1020009@openwrt.org> (raw)
In-Reply-To: <4D70DDEA.2050308@mvista.com>
Hi,
>> + if (ltq_mtd_probing)
>> + adr ^= 2;
>> + spin_lock_irqsave(&ebu_lock, flags);
>> + temp.x[0] = *((__u16 *)(map->virt + adr));
>> + spin_unlock_irqrestore(&ebu_lock, flags);
>
> Hm, what does this lock gain, if the read is atomic anyway?
the SoC has a hardware arbitor for the EBU. I have so far not been able
to activate it properly and the lock is needed to protect from PCI and
NOR i/o clashing with eachother. i know that the arbitor works when
using lantiqs 2.6.28. i will provide a follow up patch once i figured
how to bring up the arbitor properly. until that time we need to use the
lock.
thanks,
John
next prev parent reply other threads:[~2011-03-04 20:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-03 10:03 [PATCH V3 00/10] MIPS: add initial support for the Lantiq SoCs John Crispin
2011-03-03 10:03 ` [PATCH V3 01/10] MIPS: lantiq: add initial support for " John Crispin
2011-03-03 10:03 ` [PATCH V3 02/10] MIPS: lantiq: add SoC specific code for XWAY family John Crispin
2011-03-03 10:03 ` [PATCH V3 03/10] MIPS: lantiq: add PCI controller support John Crispin
2011-03-03 10:03 ` [PATCH V3 04/10] MIPS: lantiq: add serial port support John Crispin
2011-03-03 10:03 ` [PATCH V3 05/10] MIPS: lantiq: add watchdog support John Crispin
2011-03-03 11:44 ` Sergei Shtylyov
2011-03-03 11:58 ` John Crispin
2011-03-03 10:03 ` [PATCH V3 06/10] MIPS: lantiq: add NOR flash support John Crispin
2011-03-03 10:03 ` John Crispin
2011-03-04 12:41 ` Sergei Shtylyov
2011-03-04 12:41 ` Sergei Shtylyov
2011-03-04 15:10 ` Sergei Shtylyov
2011-03-04 15:10 ` Sergei Shtylyov
2011-03-04 20:13 ` John Crispin [this message]
2011-03-04 20:13 ` John Crispin
2011-03-03 10:03 ` [PATCH V3 07/10] MIPS: lantiq: add platform device support John Crispin
2011-03-03 10:03 ` [PATCH V3 08/10] MIPS: lantiq: add mips_machine support John Crispin
2011-03-03 10:03 ` [PATCH V3 09/10] MIPS: lantiq: add machtypes for lantiq eval kits John Crispin
2011-03-03 10:03 ` [PATCH V3 10/10] MIPS: lantiq: add more gpio drivers John Crispin
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