From: viresh kumar <viresh.kumar@st.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Vinod Koul <vinod.koul@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
amitgoel <amit.goel@st.com>,
Armando VISCONTI <armando.visconti@st.com>,
Shiraz HASHIM <shiraz.hashim@st.com>,
"linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>,
"viresh.linux@gmail.com" <viresh.linux@gmail.com>
Subject: Re: [PATCH] dmaengine: implement pause and resume for dw_dmac
Date: Tue, 19 Apr 2011 10:59:09 +0530 [thread overview]
Message-ID: <4DAD1DA5.7010801@st.com> (raw)
In-Reply-To: <1303173092-21785-1-git-send-email-linus.walleij@linaro.org>
On 04/19/2011 06:01 AM, Linus Walleij wrote:
> It seems that the SPEAr needs this.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thanks for sending this.
Actually i wasn't sure that disabling channel will simply pause it, and not
finish the transfer. So, didn't went for this change.
> ---
> drivers/dma/dw_dmac.c | 22 ++++++++++++++++++++--
> drivers/dma/dw_dmac_regs.h | 1 +
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
> index 9c25c7d..60ac779 100644
> --- a/drivers/dma/dw_dmac.c
> +++ b/drivers/dma/dw_dmac.c
> @@ -801,8 +801,7 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> struct dw_desc *desc, *_desc;
> LIST_HEAD(list);
>
> - /* Only supports DMA_TERMINATE_ALL */
> - if (cmd != DMA_TERMINATE_ALL)
> + if (cmd != DMA_TERMINATE_ALL && cmd != DMA_PAUSE && cmd != DMA_RESUME)
> return -ENXIO;
>
> /*
> @@ -813,11 +812,30 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> */
> spin_lock_bh(&dwc->lock);
>
> + if (cmd == DMA_RESUME) {
> + if (dwc->paused) {
> + channel_set_bit(dw, CH_EN, dwc->mask);
> + while (!dma_readl(dw, CH_EN) & dwc->mask)
Probably should be written as
while (!(dma_readl(dw, CH_EN) & dwc->mask))
> + cpu_relax();
> + }
Should return error in else part??
> + spin_unlock_bh(&dwc->lock);
> + return 0;
> + }
> +
> channel_clear_bit(dw, CH_EN, dwc->mask);
>
> while (dma_readl(dw, CH_EN) & dwc->mask)
> cpu_relax();
>
> + if (cmd == DMA_PAUSE) {
> + dwc->paused = true;
> + spin_unlock_bh(&dwc->lock);
I have sent another patchset in which _bh variants are replaced with irqsave
variants. To remove any conflicts, i would add your patch in my patchset, with
above mentioned changes keeping your authorship intact.
Will that be fine??
--
viresh
WARNING: multiple messages have this Message-ID (diff)
From: viresh.kumar@st.com (viresh kumar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] dmaengine: implement pause and resume for dw_dmac
Date: Tue, 19 Apr 2011 10:59:09 +0530 [thread overview]
Message-ID: <4DAD1DA5.7010801@st.com> (raw)
In-Reply-To: <1303173092-21785-1-git-send-email-linus.walleij@linaro.org>
On 04/19/2011 06:01 AM, Linus Walleij wrote:
> It seems that the SPEAr needs this.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thanks for sending this.
Actually i wasn't sure that disabling channel will simply pause it, and not
finish the transfer. So, didn't went for this change.
> ---
> drivers/dma/dw_dmac.c | 22 ++++++++++++++++++++--
> drivers/dma/dw_dmac_regs.h | 1 +
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
> index 9c25c7d..60ac779 100644
> --- a/drivers/dma/dw_dmac.c
> +++ b/drivers/dma/dw_dmac.c
> @@ -801,8 +801,7 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> struct dw_desc *desc, *_desc;
> LIST_HEAD(list);
>
> - /* Only supports DMA_TERMINATE_ALL */
> - if (cmd != DMA_TERMINATE_ALL)
> + if (cmd != DMA_TERMINATE_ALL && cmd != DMA_PAUSE && cmd != DMA_RESUME)
> return -ENXIO;
>
> /*
> @@ -813,11 +812,30 @@ static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> */
> spin_lock_bh(&dwc->lock);
>
> + if (cmd == DMA_RESUME) {
> + if (dwc->paused) {
> + channel_set_bit(dw, CH_EN, dwc->mask);
> + while (!dma_readl(dw, CH_EN) & dwc->mask)
Probably should be written as
while (!(dma_readl(dw, CH_EN) & dwc->mask))
> + cpu_relax();
> + }
Should return error in else part??
> + spin_unlock_bh(&dwc->lock);
> + return 0;
> + }
> +
> channel_clear_bit(dw, CH_EN, dwc->mask);
>
> while (dma_readl(dw, CH_EN) & dwc->mask)
> cpu_relax();
>
> + if (cmd == DMA_PAUSE) {
> + dwc->paused = true;
> + spin_unlock_bh(&dwc->lock);
I have sent another patchset in which _bh variants are replaced with irqsave
variants. To remove any conflicts, i would add your patch in my patchset, with
above mentioned changes keeping your authorship intact.
Will that be fine??
--
viresh
next prev parent reply other threads:[~2011-04-19 5:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-19 0:31 [PATCH] dmaengine: implement pause and resume for dw_dmac Linus Walleij
2011-04-19 0:31 ` Linus Walleij
2011-04-19 0:31 ` Linus Walleij
2011-04-19 5:29 ` viresh kumar [this message]
2011-04-19 5:29 ` viresh kumar
2011-04-19 6:04 ` viresh kumar
2011-04-19 6:04 ` viresh kumar
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