* [PATCH v2 1/7] ARM: SAMSUNG: Add clkdev infrastructure
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 2/7] ARM: S3C24XX: Add clkdev support Thomas Abraham
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
The struct clk definition for Samsung platforms is extended to include
a instance of struct clk_lookup and a device name. When clocks are
registered using s3c24xx_register_clock function, the dev_id, con_id
and clk members are initialized with information from the struct clk
instance and struct clk_lookup member is registered.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/plat-samsung/clock.c | 98 ++--------------------------
arch/arm/plat-samsung/include/plat/clock.h | 3 +
2 files changed, 9 insertions(+), 92 deletions(-)
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 7728928..86633e8 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0;
}
-static int dev_is_s3c_uart(struct device *dev)
-{
- struct platform_device **pdev = s3c24xx_uart_devs;
- int i;
- for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
- if (*pdev && dev == &(*pdev)->dev)
- return 1;
- return 0;
-}
-
-/*
- * Serial drivers call get_clock() very early, before platform bus
- * has been set up, this requires a special check to let them get
- * a proper clock
- */
-
-static int dev_is_platform_device(struct device *dev)
-{
- return dev->bus == &platform_bus_type ||
- (dev->bus == NULL && dev_is_s3c_uart(dev));
-}
-
-/* Clock API calls */
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *p;
- struct clk *clk = ERR_PTR(-ENOENT);
- int idno;
-
- if (dev == NULL || !dev_is_platform_device(dev))
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
-
- spin_lock(&clocks_lock);
-
- list_for_each_entry(p, &clocks, list) {
- if (p->id == idno &&
- strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
-
- /* check for the case where a device was supplied, but the
- * clock that was being searched for is not device specific */
-
- if (IS_ERR(clk)) {
- list_for_each_entry(p, &clocks, list) {
- if (p->id == -1 && strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- }
-
- spin_unlock(&clocks_lock);
- return clk;
-}
-
-void clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return ret;
}
-EXPORT_SYMBOL(clk_get);
-EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
@@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
struct clk clk_xtal = {
.name = "xtal",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -273,30 +202,25 @@ struct clk clk_xtal = {
struct clk clk_ext = {
.name = "ext",
- .id = -1,
};
struct clk clk_epll = {
.name = "epll",
- .id = -1,
};
struct clk clk_mpll = {
.name = "mpll",
- .id = -1,
.ops = &clk_ops_def_setrate,
};
struct clk clk_upll = {
.name = "upll",
- .id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
- .id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
@@ -304,7 +228,6 @@ struct clk clk_f = {
struct clk clk_h = {
.name = "hclk",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -313,7 +236,6 @@ struct clk clk_h = {
struct clk clk_p = {
.name = "pclk",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -322,7 +244,6 @@ struct clk clk_p = {
struct clk clk_usb_bus = {
.name = "usb-bus",
- .id = -1,
.rate = 0,
.parent = &clk_upll,
};
@@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
struct clk s3c24xx_uclk = {
.name = "uclk",
- .id = -1,
};
/* initialise the clock system */
@@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
if (clk->enable == NULL)
clk->enable = clk_null_enable;
- /* add to the list of available clocks */
-
- /* Quick check to see if this clock has already been registered. */
- BUG_ON(clk->list.prev != clk->list.next);
-
- spin_lock(&clocks_lock);
- list_add(&clk->list, &clocks);
- spin_unlock(&clocks_lock);
+ /* fill up the clk_lookup structure and register it*/
+ clk->lookup.dev_id = clk->devname;
+ clk->lookup.con_id = clk->name;
+ clk->lookup.clk = clk;
+ clkdev_add(&clk->lookup);
return 0;
}
@@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
char s[255];
char *p = s;
- p += sprintf(p, "%s", c->name);
-
- if (c->id >= 0)
- sprintf(p, ":%d", c->id);
+ p += sprintf(p, "%s", c->dev_name);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
if (!d)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578..87d5b38 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -10,6 +10,7 @@
*/
#include <linux/spinlock.h>
+#include <linux/clkdev.h>
struct clk;
@@ -40,6 +41,7 @@ struct clk {
struct module *owner;
struct clk *parent;
const char *name;
+ const char *devname;
int id;
int usage;
unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {
struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
+ struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/7] ARM: S3C24XX: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 3/7] ARM: S3C64XX: " Thomas Abraham
` (5 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's s3c24xx platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s3c2412/clock.c | 36 ++----------------------
arch/arm/mach-s3c2416/clock.c | 10 +++---
arch/arm/mach-s3c2440/clock.c | 3 --
arch/arm/mach-s3c2443/clock.c | 16 +++--------
arch/arm/plat-s3c24xx/clock-dclk.c | 4 ---
arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 +++++
arch/arm/plat-s3c24xx/s3c2410-clock.c | 21 ++------------
arch/arm/plat-s3c24xx/s3c2443-clock.c | 39 +++------------------------
arch/arm/plat-samsung/pwm-clock.c | 10 +++++++
arch/arm/plat-samsung/time.c | 2 +
11 files changed, 39 insertions(+), 110 deletions(-)
create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a5..225f63a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -686,6 +686,7 @@ config ARCH_S3C2410
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C
help
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b..140711d 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
static struct clk clk_erefclk = {
.name = "erefclk",
- .id = -1,
};
static struct clk clk_urefclk = {
.name = "urefclk",
- .id = -1,
};
static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
static struct clk clk_usysclk = {
.name = "usysclk",
- .id = -1,
.parent = &clk_xtal,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
static struct clk clk_mrefclk = {
.name = "mrefclk",
.parent = &clk_xtal,
- .id = -1,
};
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_xtal,
- .id = -1,
};
static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = {
.name = "usbsrc",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_usbsrc,
.set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = {
.name = "msysclk",
- .id = -1,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_msysclk,
},
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_armclk = {
.name = "armclk",
- .id = -1,
.parent = &clk_msysclk,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = {
.name = "uartclk",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_uart,
.set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = {
.name = "i2sclk",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_i2s,
.set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_cam,
.set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {
static struct clk init_clocks_disable[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_NAND,
}, {
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SDI,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIC,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIS,
}, {
.name = "spi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
- .id = 0,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0,
}, {
.name = "dma",
- .id = 1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1,
}, {
.name = "dma",
- .id = 2,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2,
}, {
.name = "dma",
- .id = 3,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3,
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_LCDC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBD,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_PWMT,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2412-uart.0",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2412-uart.1",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2412-uart.2",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART2,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-gadget",
- .id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_DEV48,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_HOST48,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d85..21a5e81 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
.name = "hsmmc-div",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = {
.clk = {
.name = "hsmmc-div",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
static struct clksrc_clk hsmmc_mux[] = {
[0] = {
.clk = {
- .id = 0,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s,
},
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
},
[1] = {
.clk = {
- .id = 1,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s,
},
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2416_HCLKCON_HSMMC0,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 3dc2426..554e0d3 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
static struct clk s3c2440_clk_cam = {
.name = "camif",
- .id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll",
- .id = -1,
.ops = &(struct clk_ops) {
.set_rate = s3c2440_camif_upll_setrate,
.round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
static struct clk s3c2440_clk_ac97 = {
.name = "ac97",
- .id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5..a1a7176 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -59,7 +59,6 @@
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
- .id = -1,
};
/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
static struct clk clk_armdiv = {
.name = "armdiv",
- .id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
static struct clksrc_clk clk_arm = {
.clk = {
.name = "armclk",
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = {
.clk = {
.name = "hsspi",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = {
.clk = {
.name = "hsmmc-div",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = {
.name = "hsmmc-if",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc,
.ops = &(struct clk_ops) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
static struct clksrc_clk clk_i2s_eplldiv = {
.clk = {
.name = "i2s-eplldiv",
- .id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
static struct clksrc_clk clk_i2s = {
.clk = {
.name = "i2s-if",
- .id = -1,
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
static struct clk init_clocks_off[] = {
{
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c2410-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0,
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c2410-spi.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI1,
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index cf97caa..f95d326 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
- .id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
- .id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
- .id = -1,
.ops = &clkout_ops,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
- .id = -1,
.ops = &clkout_ops,
};
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
new file mode 100644
index 0000000..089757c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_S3C24XX_CLKDEV_H__
+#define __MACH_S3C24XX_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d9..def76aa 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_NAND,
}, {
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SDI,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIC,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIS,
}, {
.name = "spi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SPI,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2410-uart.0",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2410-uart.1",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2410-uart.2",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus,
}, {
.name = "usb-bus-gadget",
- .id = -1,
.parent = &clk_usb_bus,
},
};
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a..59552c0 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
- .id = -1,
};
static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
struct clksrc_clk clk_epllref = {
.clk = {
.name = "epllref",
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
.clk = {
.name = "esysclk",
.parent = &clk_epll,
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk,
},
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
static struct clk clk_prediv = {
.name = "prediv",
- .id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {
static struct clksrc_clk clk_usb_bus_host = {
.clk = {
.name = "usb-bus-host-parent",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* ART baud-rate clock sourced from esysclk via a divisor */
.clk = {
.name = "uartclk",
- .id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* camera interface bus-clock, divided down from esysclk */
.clk = {
.name = "camif-upll", /* same as 2440 name */
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
}, {
.clk = {
.name = "display-if",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
static struct clk init_clocks_off[] = {
{
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
- .id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
- .id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
- .id = 2,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
- .id = 3,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
- .id = 4,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
- .id = 5,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "hsmmc",
- .id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT,
}, {
.name = "cfc",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
}, {
.name = "ssmc",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2440-uart.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2440-uart.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2440-uart.2",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c2440-uart.3",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT,
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97,
}, {
.name = "nand",
- .id = -1,
.parent = &clk_h,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus_host.clk,
}
};
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381..f1bba88 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.0",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
},
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[1] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.1",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
}
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[2] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.2",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[3] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.3",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[4] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.4",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
static struct clk clk_tin[] = {
[0] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.0",
.id = 0,
.ops = &clk_tin_ops,
},
[1] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.1",
.id = 1,
.ops = &clk_tin_ops,
},
[2] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.2",
.id = 2,
.ops = &clk_tin_ops,
},
[3] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.3",
.id = 3,
.ops = &clk_tin_ops,
},
[4] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.4",
.id = 4,
.ops = &clk_tin_ops,
},
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80..e3bb806 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
clk_enable(timerclk);
if (!use_tclk1_12()) {
+ tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/7] ARM: S3C64XX: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 1/7] ARM: SAMSUNG: Add clkdev infrastructure Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 2/7] ARM: S3C24XX: Add clkdev support Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 4/7] ARM: S5P64X0: " Thomas Abraham
` (4 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's s3c64xx platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s3c64xx/clock.c | 86 ++++++++-------------------
arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 ++
3 files changed, 33 insertions(+), 61 deletions(-)
create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 225f63a..e0a62fe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -704,6 +704,7 @@ config ARCH_S3C64XX
select CPU_V6
select ARM_VIC
select HAVE_CLK
+ select CLKDEV_LOOKUP
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5..8cf39e3 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
- .id = -1,
};
#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
struct clk clk_h2 = {
.name = "hclk2",
- .id = -1,
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
- .id = -1,
.rate = 27000000,
};
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
struct clk clk_48m = {
.name = "clk_48m",
- .id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
- .id = -1,
.rate = 48000000,
};
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
#ifdef CONFIG_CPU_S3C6410
.name = "iis",
- .id = -1, /* There's only one IISv4 port */
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, {
#endif
.name = "keypad",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "dma0",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "otg",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}, {
.name = "cfcon",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
static struct clk clk_fout_apll = {
.name = "fout_apll",
- .id = -1,
};
static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
static struct clk clk_arm = {
.name = "armclk",
- .id = -1,
.parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
- .id = -1,
.parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops,
};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
- .id = -1,
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
- .id = -1,
};
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
- .id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
- .id = -1,
};
static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "usb-bus-host",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */
.clk = {
.name = "spi-bus",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "spi-bus",
- .id = 1,
- .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .devname = "s3c64xx-spi.1",
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 0,
+ .devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 1,
+ .devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 2,
+ .devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "irda-bus",
- .id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "camera",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
},
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 0000000..15dbe1f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_S3C64XX_CLKDEV_H__
+#define __MACH_S3C64XX_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 4/7] ARM: S5P64X0: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
` (2 preceding siblings ...)
2011-05-27 15:26 ` [PATCH v2 3/7] ARM: S3C64XX: " Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 5/7] ARM: S5PC100: " Thomas Abraham
` (3 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's s5p64x0 platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5p64x0/clock-s5p6440.c | 74 +++++++-------------------
arch/arm/mach-s5p64x0/clock-s5p6450.c | 68 +++++++------------------
arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 +++
arch/arm/plat-s5p/s5p-time.c | 9 +++
5 files changed, 56 insertions(+), 103 deletions(-)
create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e0a62fe..33ad464 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -729,6 +729,7 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2e..11fd481 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
- .id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
- .id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
- .id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_mem_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "post",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 5)
}, {
.name = "2d",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "pdma",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "otg",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20)
}, {
.name = "irom",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hclk_fimgvg",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "pcm",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "gps",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "dsim",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "etm",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dmc0",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "pclk_fimgvg",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "mmc_48m",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mmc_48m",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "mmc_48m",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40",
- .id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
- .id = -1,
};
static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_post",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimgvg",
- .id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_audio2",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 4eec457..80bfcd9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -36,7 +36,6 @@
static struct clksrc_clk clk_mout_dpll = {
.clk = {
.name = "mout_dpll",
- .id = -1,
},
.sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
static struct clksrc_clk clk_dout_epll = {
.clk = {
.name = "dout_epll",
- .id = -1,
.parent = &clk_mout_epll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
static struct clksrc_clk clk_mout_hclk_sel = {
.clk = {
.name = "mout_hclk_sel",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
- .id = -1,
},
.sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
- .id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = {
.name = "clk_dout_pwm_ratio0",
- .id = -1,
.parent = &clk_mout_hclk_sel.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = {
.name = "clk_pclk_to_wdt_pwm",
- .id = -1,
.parent = &clk_dout_pwm_ratio0.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
- .id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "usbhost",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "usbotg",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "dmc0",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
@@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
- .id = -1,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
@@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "aclk_mali",
- .id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_2d",
- .id = -1,
.ctrlbit = (1 << 12),
.enable = s5p64x0_sclk_ctrl,
},
@@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_usi",
- .id = -1,
.ctrlbit = (1 << 7),
.enable = s5p64x0_sclk_ctrl,
},
@@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_camif",
- .id = -1,
.ctrlbit = (1 << 6),
.enable = s5p64x0_sclk_ctrl,
},
@@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_hsmmc44",
- .id = -1,
.ctrlbit = (1 << 30),
.enable = s5p64x0_sclk_ctrl,
},
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
new file mode 100644
index 0000000..17bc68e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_S5P64X0_CLKDEV_H__
+#define __MACH_S5P64X0_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 8090403..d9efd29 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -408,6 +408,7 @@ static void __init s5p_timer_resources(void)
unsigned long event_id = timer_source.event_id;
unsigned long source_id = timer_source.source_id;
+ char devname[15];
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
@@ -415,6 +416,10 @@ static void __init s5p_timer_resources(void)
clk_enable(timerclk);
+ sprintf(devname, "s3c24xx-pwm.%lu", event_id);
+ s3c_device_timer[event_id].id = event_id;
+ s3c_device_timer[event_id].dev.init_name = devname;
+
tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
if (IS_ERR(tin_event))
panic("failed to get pwm-tin clock for event timer");
@@ -425,6 +430,10 @@ static void __init s5p_timer_resources(void)
clk_enable(tin_event);
+ sprintf(devname, "s3c24xx-pwm.%lu", source_id);
+ s3c_device_timer[source_id].id = source_id;
+ s3c_device_timer[source_id].dev.init_name = devname;
+
tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
if (IS_ERR(tin_source))
panic("failed to get pwm-tin clock for source timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 5/7] ARM: S5PC100: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
` (3 preceding siblings ...)
2011-05-27 15:26 ` [PATCH v2 4/7] ARM: S5P64X0: " Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 6/7] ARM: S5PV210: " Thomas Abraham
` (2 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's s5pc100 platforms.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5pc100/clock.c | 163 +++++++--------------------
arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 +
3 files changed, 48 insertions(+), 123 deletions(-)
create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 33ad464..b329ee4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -753,6 +753,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b..de0e880 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -31,7 +31,6 @@
static struct clk s5p_clk_otgphy = {
.name = "otg_phy",
- .id = -1,
};
static struct clk *clk_src_mout_href_list[] = {
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
static struct clksrc_clk clk_mout_href = {
.clk = {
.name = "mout_href",
- .id = -1,
},
.sources = &clk_src_mout_href,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
static struct clksrc_clk clk_mout_48m = {
.clk = {
.name = "mout_48m",
- .id = -1,
},
.sources = &clk_src_mout_48m,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
static struct clksrc_clk clk_mout_hpll = {
.clk = {
.name = "mout_hpll",
- .id = -1,
},
.sources = &clk_src_mout_hpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
static struct clksrc_clk clk_div_apll = {
.clk = {
.name = "div_apll",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
static struct clksrc_clk clk_div_arm = {
.clk = {
.name = "div_arm",
- .id = -1,
.parent = &clk_div_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
static struct clksrc_clk clk_div_d0_bus = {
.clk = {
.name = "div_d0_bus",
- .id = -1,
.parent = &clk_div_arm.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
static struct clksrc_clk clk_div_pclkd0 = {
.clk = {
.name = "div_pclkd0",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
static struct clksrc_clk clk_div_secss = {
.clk = {
.name = "div_secss",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
static struct clksrc_clk clk_div_apll2 = {
.clk = {
.name = "div_apll2",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
static struct clksrc_clk clk_mout_am = {
.clk = {
.name = "mout_am",
- .id = -1,
},
.sources = &clk_src_mout_am,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
static struct clksrc_clk clk_div_d1_bus = {
.clk = {
.name = "div_d1_bus",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
static struct clksrc_clk clk_div_mpll2 = {
.clk = {
.name = "div_mpll2",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
static struct clksrc_clk clk_div_mpll = {
.clk = {
.name = "div_mpll",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
static struct clksrc_clk clk_mout_onenand = {
.clk = {
.name = "mout_onenand",
- .id = -1,
},
.sources = &clk_src_mout_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
static struct clksrc_clk clk_div_onenand = {
.clk = {
.name = "div_onenand",
- .id = -1,
.parent = &clk_mout_onenand.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
static struct clksrc_clk clk_div_pclkd1 = {
.clk = {
.name = "div_pclkd1",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
static struct clksrc_clk clk_div_cam = {
.clk = {
.name = "div_cam",
- .id = -1,
.parent = &clk_div_mpll2.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
static struct clksrc_clk clk_div_hdmi = {
.clk = {
.name = "div_hdmi",
- .id = -1,
.parent = &clk_mout_hpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "cssys",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "secss",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "g2d",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "mdma",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "cfcon",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "nfcon",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "onenandc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "sdm",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "seckey",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "modemif",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "otg",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "usbhost",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "rotator",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "s5p-fimc.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "s5p-fimc.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimc",
- .id = 2,
- .parent = &clk_div_d1_bus.clk,
+ .devname = "s5p-fimc.2",
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "jpeg",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "mipi-dsim",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "mipi-csis",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "g3d",
- .id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "tv",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "vp",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mixer",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "hdmi",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "mfc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "apc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "iec",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "systimer",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irda",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "ccan",
- .id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "ccan",
- .id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "hsitx",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsirx",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pcm",
- .id = 0,
+ .devname = "samsung-pcm.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "pcm",
- .id = 1,
+ .devname = "samsung-pcm.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spdif",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "keypad",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi_48m",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "mmc_48m",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "mmc_48m",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "mmc_48m",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 17),
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
static struct clk clk_vclk54m = {
.name = "vclk_54m",
- .id = -1,
.rate = 54000000,
};
static struct clk clk_i2scdclk0 = {
.name = "i2s_cdclk0",
- .id = -1,
};
static struct clk clk_i2scdclk1 = {
.name = "i2s_cdclk1",
- .id = -1,
};
static struct clk clk_i2scdclk2 = {
.name = "i2s_cdclk2",
- .id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcm_cdclk0",
- .id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcm_cdclk1",
- .id = -1,
};
static struct clk *clk_src_group1_list[] = {
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
- .id = 0,
+ .devname = "samsung-pcm.0",
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
},
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
- .id = 1,
+ .devname = "samsung-pcm.1",
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
},
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
- .id = 2,
+ .devname = "samsung-pcm.2",
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
},
@@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk1_ctrl,
.ops = &s5pc100_sclk_spdif_ops,
@@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
@@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
@@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl,
@@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
- .id = -1,
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_lcd",
- .id = -1,
.ctrlbit = (1 << 0),
.enable = s5pc100_sclk1_ctrl,
@@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "s5p-fimc.0",
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk1_ctrl,
@@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "s5p-fimc.1",
.ctrlbit = (1 << 2),
.enable = s5pc100_sclk1_ctrl,
@@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "s5p-fimc.2",
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk1_ctrl,
@@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.ctrlbit = (1 << 12),
.enable = s5pc100_sclk1_ctrl,
@@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.ctrlbit = (1 << 13),
.enable = s5pc100_sclk1_ctrl,
@@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.ctrlbit = (1 << 14),
.enable = s5pc100_sclk1_ctrl,
@@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
- .id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk0_ctrl,
@@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_uhost",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk0_ctrl,
@@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
static struct clk init_clocks[] = {
{
.name = "tzic",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "intc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "ebi",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "intmem",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sromc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "dmc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "chipid",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 6),
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
new file mode 100644
index 0000000..b8ff60b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_S5PC100_CLKDEV_H__
+#define __MACH_S5PC100_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 6/7] ARM: S5PV210: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
` (4 preceding siblings ...)
2011-05-27 15:26 ` [PATCH v2 5/7] ARM: S5PC100: " Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-27 15:26 ` [PATCH v2 7/7] ARM: Exynos4: " Thomas Abraham
2011-05-27 15:26 ` [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's s5pv210 platform.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5pv210/clock.c | 130 ++++++++------------------
arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 ++
3 files changed, 48 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b329ee4..8d010f2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -769,6 +769,7 @@ config ARCH_S5PV210
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d59949..cf74205 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
- .id = -1,
},
.sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_hclk_msys = {
.clk = {
.name = "hclk_msys",
- .id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
static struct clksrc_clk clk_pclk_msys = {
.clk = {
.name = "pclk_msys",
- .id = -1,
.parent = &clk_hclk_msys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
static struct clksrc_clk clk_sclk_a2m = {
.clk = {
.name = "sclk_a2m",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
static struct clksrc_clk clk_hclk_dsys = {
.clk = {
.name = "hclk_dsys",
- .id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
static struct clksrc_clk clk_pclk_dsys = {
.clk = {
.name = "pclk_dsys",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
static struct clksrc_clk clk_hclk_psys = {
.clk = {
.name = "hclk_psys",
- .id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
static struct clksrc_clk clk_pclk_psys = {
.clk = {
.name = "pclk_psys",
- .id = -1,
.parent = &clk_hclk_psys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
- .id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
- .id = -1,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
- .id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7),
},
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
- .id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
static struct clksrc_clk clk_mout_dmc0 = {
.clk = {
.name = "mout_dmc0",
- .id = -1,
},
.sources = &clkset_moutdmc0src,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
static struct clksrc_clk clk_sclk_dmc0 = {
.clk = {
.name = "sclk_dmc0",
- .id = -1,
.parent = &clk_mout_dmc0.clk,
},
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = {
{
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "rot",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "fimc",
- .id = 2,
+ .devname = "s5pv210-fimc.2",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "otg",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0),
}, {
.name = "cfcon",
- .id = 0,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "hsmmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "systimer",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
- .id = 2,
+ .devname = "s3c2440-i2c.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "keypad",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spdif",
- .id = -1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 0),
@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "hclk_imem",
- .id = -1,
.parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "sromc",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 26),
@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
static struct clksrc_clk clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 2),
},
@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
static struct clksrc_clk clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
- .id = -1,
.parent = &clk_sclk_vpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
static struct clksrc_clk clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
- .id = 0,
+ .devname = "soc-audio.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24),
},
@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
- .id = 1,
+ .devname = "soc-audio.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25),
},
@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
- .id = 2,
+ .devname = "soc-audio.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26),
},
@@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27),
.ops = &s5pv210_sclk_spdif_ops,
@@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_dmc",
- .id = -1,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_onenand",
- .id = -1,
},
.sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13),
},
@@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14),
},
@@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15),
},
@@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1),
},
@@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2),
},
@@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3),
},
@@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "s5pv210-fimc.2",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4),
},
@@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3),
},
@@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4),
},
@@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 5),
},
@@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "sdhci-s3c.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "sdhci-s3c.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9),
},
@@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "sdhci-s3c.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10),
},
@@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 3,
+ .devname = "sdhci-s3c.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11),
},
@@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mfc",
- .id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g2d",
- .id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g3d",
- .id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 6),
},
@@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
@@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29),
},
@@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 19),
},
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 0000000..4c281c9
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_S5PV210_CLKDEV_H__
+#define __MACH_S5PV210_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
` (5 preceding siblings ...)
2011-05-27 15:26 ` [PATCH v2 6/7] ARM: S5PV210: " Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
2011-05-28 1:53 ` Kyungmin Park
2011-05-27 15:26 ` [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
7 siblings, 1 reply; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
Add clkdev support for Samsung's Exynos4 platform and fixes the
incorrect clock name for the dw_mmc controller.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-exynos4/clock.c | 178 +++++++++------------------
arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
arch/arm/mach-exynos4/time.c | 2 +
4 files changed, 67 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d010f2..452e1c1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -786,6 +786,7 @@ config ARCH_EXYNOS4
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d5..4fecbe9 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
- .id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
- .id = -1,
};
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
static struct clksrc_clk clk_moutcore = {
.clk = {
.name = "moutcore",
- .id = -1,
},
.sources = &clkset_moutcore,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
static struct clksrc_clk clk_coreclk = {
.clk = {
.name = "core_clk",
- .id = -1,
.parent = &clk_moutcore.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
- .id = -1,
.parent = &clk_coreclk.clk,
},
};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_aclk_corem0 = {
.clk = {
.name = "aclk_corem0",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
static struct clksrc_clk clk_aclk_cores = {
.clk = {
.name = "aclk_cores",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
static struct clksrc_clk clk_aclk_corem1 = {
.clk = {
.name = "aclk_corem1",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
static struct clksrc_clk clk_periphclk = {
.clk = {
.name = "periphclk",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
static struct clksrc_clk clk_mout_corebus = {
.clk = {
.name = "mout_corebus",
- .id = -1,
},
.sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
static struct clksrc_clk clk_sclk_dmc = {
.clk = {
.name = "sclk_dmc",
- .id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clksrc_clk clk_aclk_cored = {
.clk = {
.name = "aclk_cored",
- .id = -1,
.parent = &clk_sclk_dmc.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
static struct clksrc_clk clk_aclk_corep = {
.clk = {
.name = "aclk_corep",
- .id = -1,
.parent = &clk_aclk_cored.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
static struct clksrc_clk clk_aclk_acp = {
.clk = {
.name = "aclk_acp",
- .id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
static struct clksrc_clk clk_pclk_acp = {
.clk = {
.name = "pclk_acp",
- .id = -1,
.parent = &clk_aclk_acp.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
static struct clksrc_clk clk_aclk_200 = {
.clk = {
.name = "aclk_200",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
static struct clksrc_clk clk_aclk_100 = {
.clk = {
.name = "aclk_100",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
static struct clksrc_clk clk_aclk_160 = {
.clk = {
.name = "aclk_160",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
static struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
- .id = -1,
.enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
- .id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,289 +371,263 @@ static struct clksrc_clk clk_sclk_vpll = {
static struct clk init_clocks_off[] = {
{
.name = "timers",
- .id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "csis",
- .id = 0,
+ .devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
- .id = 1,
+ .devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
- .id = 2,
+ .devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
- .id = 3,
+ .devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
- .id = 0,
+ .devname = "s5pv310-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
- .id = 1,
+ .devname = "s5pv310-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "sataphy",
- .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "hsmmc",
- .id = 4,
+ .name = "dwmmc",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sata",
- .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "adc",
- .id = -1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "keypad",
- .id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "rtc",
- .id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "usbhost",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12),
}, {
.name = "otg",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "ac97",
- .id = -1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "fimg2d",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
- .id = 2,
+ .devname = "s3c2440-i2c.2",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
- .id = 3,
+ .devname = "s3c2440-i2c.3",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
- .id = 4,
+ .devname = "s3c2440-i2c.4",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
- .id = 5,
+ .devname = "s3c2440-i2c.5",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
- .id = 6,
+ .devname = "s3c2440-i2c.6",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = 7,
+ .devname = "s3c2440-i2c.7",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "SYSMMU_MDMA",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "SYSMMU_FIMC0",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "SYSMMU_FIMC1",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "SYSMMU_FIMC2",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "SYSMMU_FIMC3",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "SYSMMU_JPEG",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "SYSMMU_FIMD0",
- .id = -1,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_FIMD1",
- .id = -1,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_PCIe",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "SYSMMU_G2D",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "SYSMMU_ROTATOR",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_TV",
- .id = -1,
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_MFC_L",
- .id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "SYSMMU_MFC_R",
- .id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}
@@ -689,32 +636,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "uart",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 4,
+ .devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
- .id = 5,
+ .devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
@@ -750,7 +697,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
static struct clksrc_clk clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
- .id = -1,
},
.sources = &clkset_mout_g2d0,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +715,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
static struct clksrc_clk clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
- .id = -1,
},
.sources = &clkset_mout_g2d1,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -788,7 +733,6 @@ static struct clksrc_sources clkset_mout_g2d = {
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +742,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
static struct clksrc_clk clk_dout_mmc1 = {
.clk = {
.name = "dout_mmc1",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +751,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
static struct clksrc_clk clk_dout_mmc2 = {
.clk = {
.name = "dout_mmc2",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +760,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
static struct clksrc_clk clk_dout_mmc3 = {
.clk = {
.name = "dout_mmc3",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +769,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
static struct clksrc_clk clk_dout_mmc4 = {
.clk = {
.name = "dout_mmc4",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +779,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -849,7 +789,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
@@ -859,7 +799,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -869,7 +809,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -879,7 +819,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
- .id = -1,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
@@ -889,7 +828,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = 0,
+ .devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
},
@@ -899,7 +838,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = 1,
+ .devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
},
@@ -909,7 +848,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
@@ -919,7 +858,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
@@ -929,7 +868,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
},
@@ -939,7 +878,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
},
@@ -949,7 +888,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
},
@@ -959,7 +898,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 3,
+ .devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
},
@@ -969,7 +908,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = 0,
+ .devname = "s5pv310-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -979,7 +918,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = 1,
+ .devname = "s5pv310-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
@@ -989,7 +928,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_sata",
- .id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
@@ -999,7 +937,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1009,7 +947,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
@@ -1019,7 +957,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
@@ -1029,7 +967,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimg2d",
- .id = -1,
},
.sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@@ -1037,7 +974,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@@ -1046,7 +983,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@@ -1055,7 +992,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@@ -1064,7 +1001,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@@ -1072,8 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, {
.clk = {
- .name = "sclk_mmc",
- .id = 4,
+ .name = "sclk_dwmmc",
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
index 86b9fa0..cb63f97 100644
--- a/arch/arm/mach-exynos4/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -262,6 +262,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(timerclk);
tmpdev.id = 2;
+ tmpdev.dev.init_name = "s3c24xx-pwm.2";
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
@@ -272,6 +273,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(tin2);
tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-27 15:26 ` [PATCH v2 7/7] ARM: Exynos4: " Thomas Abraham
@ 2011-05-28 1:53 ` Kyungmin Park
2011-05-28 2:14 ` Kukjin Kim
0 siblings, 1 reply; 16+ messages in thread
From: Kyungmin Park @ 2011-05-28 1:53 UTC (permalink / raw)
To: Thomas Abraham; +Cc: linux-samsung-soc, kgene.kim, ben-linux
On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham <thomas.ab@samsung.com> wrote:
> Add clkdev support for Samsung's Exynos4 platform and fixes the
> incorrect clock name for the dw_mmc controller.
>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-exynos4/clock.c | 178 +++++++++------------------
> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
> arch/arm/mach-exynos4/time.c | 2 +
> 4 files changed, 67 insertions(+), 121 deletions(-)
> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8d010f2..452e1c1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -786,6 +786,7 @@ config ARCH_EXYNOS4
> select ARCH_SPARSEMEM_ENABLE
> select GENERIC_GPIO
> select HAVE_CLK
> + select CLKDEV_LOOKUP
> select ARCH_HAS_CPUFREQ
> select GENERIC_CLOCKEVENTS
> select HAVE_S3C_RTC if RTC_CLASS
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 871f9d5..4fecbe9 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -27,24 +27,20 @@
>
> static struct clk clk_sclk_hdmi27m = {
> .name = "sclk_hdmi27m",
> - .id = -1,
> .rate = 27000000,
> };
>
> static struct clk clk_sclk_hdmiphy = {
> .name = "sclk_hdmiphy",
> - .id = -1,
> };
>
> static struct clk clk_sclk_usbphy0 = {
> .name = "sclk_usbphy0",
> - .id = -1,
> .rate = 27000000,
> };
>
> static struct clk clk_sclk_usbphy1 = {
> .name = "sclk_usbphy1",
> - .id = -1,
> };
>
> static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
> @@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
> static struct clksrc_clk clk_mout_apll = {
> .clk = {
> .name = "mout_apll",
> - .id = -1,
> },
> .sources = &clk_src_apll,
> .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
> @@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
> static struct clksrc_clk clk_sclk_apll = {
> .clk = {
> .name = "sclk_apll",
> - .id = -1,
> .parent = &clk_mout_apll.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
> @@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
> static struct clksrc_clk clk_mout_epll = {
> .clk = {
> .name = "mout_epll",
> - .id = -1,
> },
> .sources = &clk_src_epll,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
> @@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
> static struct clksrc_clk clk_mout_mpll = {
> .clk = {
> .name = "mout_mpll",
> - .id = -1,
> },
> .sources = &clk_src_mpll,
> .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
> @@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
> static struct clksrc_clk clk_moutcore = {
> .clk = {
> .name = "moutcore",
> - .id = -1,
> },
> .sources = &clkset_moutcore,
> .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
> @@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
> static struct clksrc_clk clk_coreclk = {
> .clk = {
> .name = "core_clk",
> - .id = -1,
> .parent = &clk_moutcore.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
> @@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
> static struct clksrc_clk clk_armclk = {
> .clk = {
> .name = "armclk",
> - .id = -1,
> .parent = &clk_coreclk.clk,
> },
> };
> @@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
> static struct clksrc_clk clk_aclk_corem0 = {
> .clk = {
> .name = "aclk_corem0",
> - .id = -1,
> .parent = &clk_coreclk.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
> @@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
> static struct clksrc_clk clk_aclk_cores = {
> .clk = {
> .name = "aclk_cores",
> - .id = -1,
> .parent = &clk_coreclk.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
> @@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
> static struct clksrc_clk clk_aclk_corem1 = {
> .clk = {
> .name = "aclk_corem1",
> - .id = -1,
> .parent = &clk_coreclk.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
> @@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
> static struct clksrc_clk clk_periphclk = {
> .clk = {
> .name = "periphclk",
> - .id = -1,
> .parent = &clk_coreclk.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
> @@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
> static struct clksrc_clk clk_mout_corebus = {
> .clk = {
> .name = "mout_corebus",
> - .id = -1,
> },
> .sources = &clkset_mout_corebus,
> .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
> @@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
> static struct clksrc_clk clk_sclk_dmc = {
> .clk = {
> .name = "sclk_dmc",
> - .id = -1,
> .parent = &clk_mout_corebus.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
> @@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
> static struct clksrc_clk clk_aclk_cored = {
> .clk = {
> .name = "aclk_cored",
> - .id = -1,
> .parent = &clk_sclk_dmc.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
> @@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
> static struct clksrc_clk clk_aclk_corep = {
> .clk = {
> .name = "aclk_corep",
> - .id = -1,
> .parent = &clk_aclk_cored.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
> @@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
> static struct clksrc_clk clk_aclk_acp = {
> .clk = {
> .name = "aclk_acp",
> - .id = -1,
> .parent = &clk_mout_corebus.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
> @@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
> static struct clksrc_clk clk_pclk_acp = {
> .clk = {
> .name = "pclk_acp",
> - .id = -1,
> .parent = &clk_aclk_acp.clk,
> },
> .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
> @@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
> static struct clksrc_clk clk_aclk_200 = {
> .clk = {
> .name = "aclk_200",
> - .id = -1,
> },
> .sources = &clkset_aclk,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
> @@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
> static struct clksrc_clk clk_aclk_100 = {
> .clk = {
> .name = "aclk_100",
> - .id = -1,
> },
> .sources = &clkset_aclk,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
> @@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
> static struct clksrc_clk clk_aclk_160 = {
> .clk = {
> .name = "aclk_160",
> - .id = -1,
> },
> .sources = &clkset_aclk,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
> @@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
> static struct clksrc_clk clk_aclk_133 = {
> .clk = {
> .name = "aclk_133",
> - .id = -1,
> },
> .sources = &clkset_aclk,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
> @@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
> static struct clksrc_clk clk_vpllsrc = {
> .clk = {
> .name = "vpll_src",
> - .id = -1,
> .enable = exynos4_clksrc_mask_top_ctrl,
> .ctrlbit = (1 << 0),
> },
> @@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
> static struct clksrc_clk clk_sclk_vpll = {
> .clk = {
> .name = "sclk_vpll",
> - .id = -1,
> },
> .sources = &clkset_sclk_vpll,
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
> @@ -398,289 +371,263 @@ static struct clksrc_clk clk_sclk_vpll = {
> static struct clk init_clocks_off[] = {
> {
> .name = "timers",
> - .id = -1,
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1<<24),
> }, {
> .name = "csis",
> - .id = 0,
> + .devname = "s5p-mipi-csis.0",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "csis",
> - .id = 1,
> + .devname = "s5p-mipi-csis.1",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 5),
> }, {
> .name = "fimc",
> - .id = 0,
> + .devname = "exynos4-fimc.0",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "fimc",
> - .id = 1,
> + .devname = "exynos4-fimc.1",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 1),
> }, {
> .name = "fimc",
> - .id = 2,
> + .devname = "exynos4-fimc.2",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 2),
> }, {
> .name = "fimc",
> - .id = 3,
> + .devname = "exynos4-fimc.3",
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> .name = "fimd",
> - .id = 0,
> + .devname = "s5pv310-fb.0",
> .enable = exynos4_clk_ip_lcd0_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "fimd",
> - .id = 1,
> + .devname = "s5pv310-fb.1",
> .enable = exynos4_clk_ip_lcd1_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "sataphy",
> - .id = -1,
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> .name = "hsmmc",
> - .id = 0,
> + .devname = "s3c-sdhci.0",
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 5),
> }, {
> .name = "hsmmc",
> - .id = 1,
> + .devname = "s3c-sdhci.1",
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 6),
> }, {
> .name = "hsmmc",
> - .id = 2,
> + .devname = "s3c-sdhci.2",
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 7),
> }, {
> .name = "hsmmc",
> - .id = 3,
> + .devname = "s3c-sdhci.3",
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 8),
> }, {
> - .name = "hsmmc",
> - .id = 4,
> + .name = "dwmmc",
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 9),
> }, {
> .name = "sata",
> - .id = -1,
> .parent = &clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 10),
> }, {
> .name = "pdma",
> - .id = 0,
> + .devname = "s3c-pl330.0",
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "pdma",
> - .id = 1,
> + .devname = "s3c-pl330.1",
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 1),
> }, {
> .name = "adc",
> - .id = -1,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 15),
> }, {
> .name = "keypad",
> - .id = -1,
> .enable = exynos4_clk_ip_perir_ctrl,
> .ctrlbit = (1 << 16),
> }, {
> .name = "rtc",
> - .id = -1,
> .enable = exynos4_clk_ip_perir_ctrl,
> .ctrlbit = (1 << 15),
> }, {
> .name = "watchdog",
> - .id = -1,
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_perir_ctrl,
> .ctrlbit = (1 << 14),
> }, {
> .name = "usbhost",
> - .id = -1,
> .enable = exynos4_clk_ip_fsys_ctrl ,
> .ctrlbit = (1 << 12),
> }, {
> .name = "otg",
> - .id = -1,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 13),
> }, {
> .name = "spi",
> - .id = 0,
> + .devname = "s3c64xx-spi.0",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 16),
> }, {
> .name = "spi",
> - .id = 1,
> + .devname = "s3c64xx-spi.1",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 17),
> }, {
> .name = "spi",
> - .id = 2,
> + .devname = "s3c64xx-spi.2",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 18),
> }, {
> .name = "iis",
> - .id = 0,
> + .devname = "samsung-i2s.0",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 19),
> }, {
> .name = "iis",
> - .id = 1,
> + .devname = "samsung-i2s.1",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 20),
> }, {
> .name = "iis",
> - .id = 2,
> + .devname = "samsung-i2s.2",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 21),
> }, {
> .name = "ac97",
> - .id = -1,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 27),
> }, {
> .name = "fimg2d",
> - .id = -1,
> .enable = exynos4_clk_ip_image_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "i2c",
> - .id = 0,
> + .devname = "s3c2440-i2c.0",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 6),
> }, {
> .name = "i2c",
> - .id = 1,
> + .devname = "s3c2440-i2c.1",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 7),
> }, {
> .name = "i2c",
> - .id = 2,
> + .devname = "s3c2440-i2c.2",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 8),
> }, {
> .name = "i2c",
> - .id = 3,
> + .devname = "s3c2440-i2c.3",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 9),
> }, {
> .name = "i2c",
> - .id = 4,
> + .devname = "s3c2440-i2c.4",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 10),
> }, {
> .name = "i2c",
> - .id = 5,
> + .devname = "s3c2440-i2c.5",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 11),
> }, {
> .name = "i2c",
> - .id = 6,
> + .devname = "s3c2440-i2c.6",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 12),
> }, {
> .name = "i2c",
> - .id = 7,
> + .devname = "s3c2440-i2c.7",
> .parent = &clk_aclk_100.clk,
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 13),
> }, {
> .name = "SYSMMU_MDMA",
> - .id = -1,
> .enable = exynos4_clk_ip_image_ctrl,
> .ctrlbit = (1 << 5),
> }, {
> .name = "SYSMMU_FIMC0",
> - .id = -1,
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 7),
> }, {
> .name = "SYSMMU_FIMC1",
> - .id = -1,
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 8),
> }, {
> .name = "SYSMMU_FIMC2",
> - .id = -1,
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 9),
> }, {
> .name = "SYSMMU_FIMC3",
> - .id = -1,
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 10),
> }, {
> .name = "SYSMMU_JPEG",
> - .id = -1,
> .enable = exynos4_clk_ip_cam_ctrl,
> .ctrlbit = (1 << 11),
> }, {
> .name = "SYSMMU_FIMD0",
> - .id = -1,
> .enable = exynos4_clk_ip_lcd0_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "SYSMMU_FIMD1",
> - .id = -1,
> .enable = exynos4_clk_ip_lcd1_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "SYSMMU_PCIe",
> - .id = -1,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 18),
> }, {
> .name = "SYSMMU_G2D",
> - .id = -1,
> .enable = exynos4_clk_ip_image_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> .name = "SYSMMU_ROTATOR",
> - .id = -1,
> .enable = exynos4_clk_ip_image_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "SYSMMU_TV",
> - .id = -1,
> .enable = exynos4_clk_ip_tv_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "SYSMMU_MFC_L",
> - .id = -1,
> .enable = exynos4_clk_ip_mfc_ctrl,
> .ctrlbit = (1 << 1),
> }, {
> .name = "SYSMMU_MFC_R",
> - .id = -1,
> .enable = exynos4_clk_ip_mfc_ctrl,
> .ctrlbit = (1 << 2),
> }
> @@ -689,32 +636,32 @@ static struct clk init_clocks_off[] = {
> static struct clk init_clocks[] = {
> {
> .name = "uart",
> - .id = 0,
> + .devname = "s5pv210-uart.0",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 0),
> }, {
> .name = "uart",
> - .id = 1,
> + .devname = "s5pv210-uart.1",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 1),
> }, {
> .name = "uart",
> - .id = 2,
> + .devname = "s5pv210-uart.2",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 2),
> }, {
> .name = "uart",
> - .id = 3,
> + .devname = "s5pv210-uart.3",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 3),
> }, {
> .name = "uart",
> - .id = 4,
> + .devname = "s5pv210-uart.4",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 4),
> }, {
> .name = "uart",
> - .id = 5,
> + .devname = "s5pv210-uart.5",
> .enable = exynos4_clk_ip_peril_ctrl,
> .ctrlbit = (1 << 5),
> }
> @@ -750,7 +697,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
> static struct clksrc_clk clk_mout_g2d0 = {
> .clk = {
> .name = "mout_g2d0",
> - .id = -1,
> },
> .sources = &clkset_mout_g2d0,
> .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
> @@ -769,7 +715,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
> static struct clksrc_clk clk_mout_g2d1 = {
> .clk = {
> .name = "mout_g2d1",
> - .id = -1,
> },
> .sources = &clkset_mout_g2d1,
> .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
> @@ -788,7 +733,6 @@ static struct clksrc_sources clkset_mout_g2d = {
> static struct clksrc_clk clk_dout_mmc0 = {
> .clk = {
> .name = "dout_mmc0",
> - .id = -1,
> },
> .sources = &clkset_group,
> .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
> @@ -798,7 +742,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
> static struct clksrc_clk clk_dout_mmc1 = {
> .clk = {
> .name = "dout_mmc1",
> - .id = -1,
> },
> .sources = &clkset_group,
> .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
> @@ -808,7 +751,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
> static struct clksrc_clk clk_dout_mmc2 = {
> .clk = {
> .name = "dout_mmc2",
> - .id = -1,
> },
> .sources = &clkset_group,
> .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
> @@ -818,7 +760,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
> static struct clksrc_clk clk_dout_mmc3 = {
> .clk = {
> .name = "dout_mmc3",
> - .id = -1,
> },
> .sources = &clkset_group,
> .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
> @@ -828,7 +769,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
> static struct clksrc_clk clk_dout_mmc4 = {
> .clk = {
> .name = "dout_mmc4",
> - .id = -1,
> },
> .sources = &clkset_group,
> .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
> @@ -839,7 +779,7 @@ static struct clksrc_clk clksrcs[] = {
> {
> .clk = {
> .name = "uclk1",
> - .id = 0,
> + .devname = "s5pv210-uart.0",
> .enable = exynos4_clksrc_mask_peril0_ctrl,
> .ctrlbit = (1 << 0),
> },
> @@ -849,7 +789,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "uclk1",
> - .id = 1,
> + .devname = "s5pv210-uart.1",
> .enable = exynos4_clksrc_mask_peril0_ctrl,
> .ctrlbit = (1 << 4),
> },
> @@ -859,7 +799,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "uclk1",
> - .id = 2,
> + .devname = "s5pv210-uart.2",
> .enable = exynos4_clksrc_mask_peril0_ctrl,
> .ctrlbit = (1 << 8),
> },
> @@ -869,7 +809,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "uclk1",
> - .id = 3,
> + .devname = "s5pv210-uart.3",
> .enable = exynos4_clksrc_mask_peril0_ctrl,
> .ctrlbit = (1 << 12),
> },
> @@ -879,7 +819,6 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_pwm",
> - .id = -1,
> .enable = exynos4_clksrc_mask_peril0_ctrl,
> .ctrlbit = (1 << 24),
> },
> @@ -889,7 +828,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_csis",
> - .id = 0,
> + .devname = "s5p-mipi-csis.0",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 24),
> },
> @@ -899,7 +838,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_csis",
> - .id = 1,
> + .devname = "s5p-mipi-csis.1",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 28),
> },
> @@ -909,7 +848,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_cam",
> - .id = 0,
> + .devname = "exynos4-fimc.0",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 16),
> },
> @@ -919,7 +858,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_cam",
> - .id = 1,
> + .devname = "exynos4-fimc.1",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 20),
> },
> @@ -929,7 +868,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimc",
> - .id = 0,
> + .devname = "exynos4-fimc.0",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 0),
> },
> @@ -939,7 +878,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimc",
> - .id = 1,
> + .devname = "exynos4-fimc.1",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 4),
> },
> @@ -949,7 +888,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimc",
> - .id = 2,
> + .devname = "exynos4-fimc.2",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 8),
> },
> @@ -959,7 +898,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimc",
> - .id = 3,
> + .devname = "exynos4-fimc.3",
> .enable = exynos4_clksrc_mask_cam_ctrl,
> .ctrlbit = (1 << 12),
> },
> @@ -969,7 +908,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimd",
> - .id = 0,
> + .devname = "s5pv310-fb.0",
> .enable = exynos4_clksrc_mask_lcd0_ctrl,
> .ctrlbit = (1 << 0),
> },
> @@ -979,7 +918,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimd",
> - .id = 1,
> + .devname = "s5pv310-fb.1",
> .enable = exynos4_clksrc_mask_lcd1_ctrl,
> .ctrlbit = (1 << 0),
> },
> @@ -989,7 +928,6 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_sata",
> - .id = -1,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 24),
> },
> @@ -999,7 +937,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_spi",
> - .id = 0,
> + .devname = "s3c64xx-spi.0",
> .enable = exynos4_clksrc_mask_peril1_ctrl,
> .ctrlbit = (1 << 16),
> },
> @@ -1009,7 +947,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_spi",
> - .id = 1,
> + .devname = "s3c64xx-spi.1",
> .enable = exynos4_clksrc_mask_peril1_ctrl,
> .ctrlbit = (1 << 20),
> },
> @@ -1019,7 +957,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_spi",
> - .id = 2,
> + .devname = "s3c64xx-spi.2",
> .enable = exynos4_clksrc_mask_peril1_ctrl,
> .ctrlbit = (1 << 24),
> },
> @@ -1029,7 +967,6 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_fimg2d",
> - .id = -1,
> },
> .sources = &clkset_mout_g2d,
> .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
> @@ -1037,7 +974,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_mmc",
> - .id = 0,
> + .devname = "s3c-sdhci.0",
> .parent = &clk_dout_mmc0.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 0),
> @@ -1046,7 +983,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_mmc",
> - .id = 1,
> + .devname = "s3c-sdhci.1",
> .parent = &clk_dout_mmc1.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 4),
> @@ -1055,7 +992,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_mmc",
> - .id = 2,
> + .devname = "s3c-sdhci.2",
> .parent = &clk_dout_mmc2.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 8),
> @@ -1064,7 +1001,7 @@ static struct clksrc_clk clksrcs[] = {
> }, {
> .clk = {
> .name = "sclk_mmc",
> - .id = 3,
> + .devname = "s3c-sdhci.3",
> .parent = &clk_dout_mmc3.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 12),
> @@ -1072,8 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
> .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> }, {
> .clk = {
> - .name = "sclk_mmc",
> - .id = 4,
> + .name = "sclk_dwmmc",
> .parent = &clk_dout_mmc4.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit = (1 << 16),
> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
> new file mode 100644
> index 0000000..1247f5e
> --- /dev/null
> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
> @@ -0,0 +1,7 @@
> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
> +#define __MACH_EXYNOS4_CLKDEV_H__
> +
> +#define __clk_get(clk) ({ 1; })
> +#define __clk_put(clk) do { } while (0)
> +
> +#endif
Looks good to me.
One nitpick
How about to just create the one clkdev.h at plat-samsung with proper
ifdef endif config.
I think don't need to create clkdev.h for each SoCs.
Thank you,
Kyungmin Park
> diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
> index 86b9fa0..cb63f97 100644
> --- a/arch/arm/mach-exynos4/time.c
> +++ b/arch/arm/mach-exynos4/time.c
> @@ -262,6 +262,7 @@ static void __init exynos4_timer_resources(void)
> clk_enable(timerclk);
>
> tmpdev.id = 2;
> + tmpdev.dev.init_name = "s3c24xx-pwm.2";
> tin2 = clk_get(&tmpdev.dev, "pwm-tin");
> if (IS_ERR(tin2))
> panic("failed to get pwm-tin2 clock for system timer");
> @@ -272,6 +273,7 @@ static void __init exynos4_timer_resources(void)
> clk_enable(tin2);
>
> tmpdev.id = 4;
> + tmpdev.dev.init_name = "s3c24xx-pwm.4";
> tin4 = clk_get(&tmpdev.dev, "pwm-tin");
> if (IS_ERR(tin4))
> panic("failed to get pwm-tin4 clock for system timer");
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-28 1:53 ` Kyungmin Park
@ 2011-05-28 2:14 ` Kukjin Kim
2011-05-28 2:33 ` Kyungmin Park
0 siblings, 1 reply; 16+ messages in thread
From: Kukjin Kim @ 2011-05-28 2:14 UTC (permalink / raw)
To: Kyungmin Park; +Cc: Thomas Abraham, linux-samsung-soc, kgene.kim, ben-linux
On 05/27/11 18:53, Kyungmin Park wrote:
> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com> wrote:
>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>> incorrect clock name for the dw_mmc controller.
>>
>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>> ---
>> arch/arm/Kconfig | 1 +
>> arch/arm/mach-exynos4/clock.c | 178 +++++++++------------------
>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
>> arch/arm/mach-exynos4/time.c | 2 +
>> 4 files changed, 67 insertions(+), 121 deletions(-)
>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
(snip)
>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
>> new file mode 100644
>> index 0000000..1247f5e
>> --- /dev/null
>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>> @@ -0,0 +1,7 @@
>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>> +#define __MACH_EXYNOS4_CLKDEV_H__
>> +
>> +#define __clk_get(clk) ({ 1; })
>> +#define __clk_put(clk) do { } while (0)
>> +
>> +#endif
>
> Looks good to me.
>
> One nitpick
> How about to just create the one clkdev.h at plat-samsung with proper
> ifdef endif config.
> I think don't need to create clkdev.h for each SoCs.
No, basically the "mach/clkdev.h" should be added, please see
arch/arm/include/asm/clkdev.h.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-28 2:14 ` Kukjin Kim
@ 2011-05-28 2:33 ` Kyungmin Park
2011-05-28 2:36 ` Kyungmin Park
0 siblings, 1 reply; 16+ messages in thread
From: Kyungmin Park @ 2011-05-28 2:33 UTC (permalink / raw)
To: Kukjin Kim; +Cc: Thomas Abraham, linux-samsung-soc, ben-linux, Arnd Bergmann
On Sat, May 28, 2011 at 11:14 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>
>
> On 05/27/11 18:53, Kyungmin Park wrote:
>>
>> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com>
>> wrote:
>>>
>>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>>> incorrect clock name for the dw_mmc controller.
>>>
>>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>>> ---
>>> arch/arm/Kconfig | 1 +
>>> arch/arm/mach-exynos4/clock.c | 178
>>> +++++++++------------------
>>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
>>> arch/arm/mach-exynos4/time.c | 2 +
>>> 4 files changed, 67 insertions(+), 121 deletions(-)
>>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>
> (snip)
>
>>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
>>> b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>> new file mode 100644
>>> index 0000000..1247f5e
>>> --- /dev/null
>>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>> @@ -0,0 +1,7 @@
>>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>>> +#define __MACH_EXYNOS4_CLKDEV_H__
>>> +
>>> +#define __clk_get(clk) ({ 1; })
>>> +#define __clk_put(clk) do { } while (0)
>>> +
>>> +#endif
>>
>> Looks good to me.
>>
>> One nitpick
>> How about to just create the one clkdev.h at plat-samsung with proper
>> ifdef endif config.
>> I think don't need to create clkdev.h for each SoCs.
>
> No, basically the "mach/clkdev.h" should be added, please see
> arch/arm/include/asm/clkdev.h.
Okay it's required,
but also see the others.
http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/mach-omap2/include/mach/clkdev.h
1 /*
2 * arch/arm/mach-omap2/include/mach/clkdev.h
3 */
4
5 #include <plat/clkdev.h>
Thank you,
Kyungmin Park
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-28 2:33 ` Kyungmin Park
@ 2011-05-28 2:36 ` Kyungmin Park
0 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2011-05-28 2:36 UTC (permalink / raw)
To: Kukjin Kim, arm-linux
Cc: Thomas Abraham, linux-samsung-soc, ben-linux, Arnd Bergmann
On Sat, May 28, 2011 at 11:33 AM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Sat, May 28, 2011 at 11:14 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>
>>
>> On 05/27/11 18:53, Kyungmin Park wrote:
>>>
>>> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com>
>>> wrote:
>>>>
>>>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>>>> incorrect clock name for the dw_mmc controller.
>>>>
>>>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>>>> ---
>>>> arch/arm/Kconfig | 1 +
>>>> arch/arm/mach-exynos4/clock.c | 178
>>>> +++++++++------------------
>>>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
>>>> arch/arm/mach-exynos4/time.c | 2 +
>>>> 4 files changed, 67 insertions(+), 121 deletions(-)
>>>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>>
>> (snip)
>>
>>>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> new file mode 100644
>>>> index 0000000..1247f5e
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> @@ -0,0 +1,7 @@
>>>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>>>> +#define __MACH_EXYNOS4_CLKDEV_H__
>>>> +
>>>> +#define __clk_get(clk) ({ 1; })
>>>> +#define __clk_put(clk) do { } while (0)
>>>> +
>>>> +#endif
>>>
>>> Looks good to me.
>>>
>>> One nitpick
>>> How about to just create the one clkdev.h at plat-samsung with proper
>>> ifdef endif config.
>>> I think don't need to create clkdev.h for each SoCs.
>>
>> No, basically the "mach/clkdev.h" should be added, please see
>> arch/arm/include/asm/clkdev.h.
>
> Okay it's required,
> but also see the others.
> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/mach-omap2/include/mach/clkdev.h
>
> 1 /*
> 2 * arch/arm/mach-omap2/include/mach/clkdev.h
> 3 */
> 4
> 5 #include <plat/clkdev.h>
and
http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/plat-omap/include/plat/clkdev.h
1 #ifndef __MACH_CLKDEV_H
2 #define __MACH_CLKDEV_H
3
4 static inline int __clk_get(struct clk *clk)
5 {
6 return 1;
7 }
8
9 static inline void __clk_put(struct clk *clk)
10 {
11 }
12
13 #endif
To Arnd,
in case of ARM, it has almost same form. then how about to move the
arm generic one?
>
> Thank you,
> Kyungmin Park
>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
@ 2011-05-28 2:36 ` Kyungmin Park
0 siblings, 0 replies; 16+ messages in thread
From: Kyungmin Park @ 2011-05-28 2:36 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, May 28, 2011 at 11:33 AM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Sat, May 28, 2011 at 11:14 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>
>>
>> On 05/27/11 18:53, Kyungmin Park wrote:
>>>
>>> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com>
>>> ?wrote:
>>>>
>>>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>>>> incorrect clock name for the dw_mmc controller.
>>>>
>>>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>>>> ---
>>>> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
>>>> ?arch/arm/mach-exynos4/clock.c ? ? ? ? ? ? ? | ?178
>>>> +++++++++------------------
>>>> ?arch/arm/mach-exynos4/include/mach/clkdev.h | ? ?7 +
>>>> ?arch/arm/mach-exynos4/time.c ? ? ? ? ? ? ? ?| ? ?2 +
>>>> ?4 files changed, 67 insertions(+), 121 deletions(-)
>>>> ?create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>>
>> (snip)
>>
>>>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> new file mode 100644
>>>> index 0000000..1247f5e
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>> @@ -0,0 +1,7 @@
>>>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>>>> +#define __MACH_EXYNOS4_CLKDEV_H__
>>>> +
>>>> +#define __clk_get(clk) ({ 1; })
>>>> +#define __clk_put(clk) do { } while (0)
>>>> +
>>>> +#endif
>>>
>>> Looks good to me.
>>>
>>> One nitpick
>>> How about to just create the one clkdev.h at plat-samsung with proper
>>> ifdef endif config.
>>> I think don't need to create clkdev.h for each SoCs.
>>
>> No, basically the "mach/clkdev.h" should be added, please see
>> arch/arm/include/asm/clkdev.h.
>
> Okay it's required,
> but also see the others.
> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/mach-omap2/include/mach/clkdev.h
>
> ? 1 /*
> ? 2 ?* arch/arm/mach-omap2/include/mach/clkdev.h
> ? 3 ?*/
> ? 4
> ? 5 #include <plat/clkdev.h>
and
http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/plat-omap/include/plat/clkdev.h
1 #ifndef __MACH_CLKDEV_H
2 #define __MACH_CLKDEV_H
3
4 static inline int __clk_get(struct clk *clk)
5 {
6 return 1;
7 }
8
9 static inline void __clk_put(struct clk *clk)
10 {
11 }
12
13 #endif
To Arnd,
in case of ARM, it has almost same form. then how about to move the
arm generic one?
>
> Thank you,
> Kyungmin Park
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
2011-05-28 2:36 ` Kyungmin Park
@ 2011-05-28 3:39 ` Thomas Abraham
-1 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-28 3:39 UTC (permalink / raw)
To: Kyungmin Park
Cc: Kukjin Kim, arm-linux, linux-samsung-soc, ben-linux,
Arnd Bergmann
On Sat, May 28, 2011 at 8:06 AM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Sat, May 28, 2011 at 11:33 AM, Kyungmin Park <kmpark@infradead.org> wrote:
>> On Sat, May 28, 2011 at 11:14 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>>
>>>
>>> On 05/27/11 18:53, Kyungmin Park wrote:
>>>>
>>>> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com>
>>>> wrote:
>>>>>
>>>>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>>>>> incorrect clock name for the dw_mmc controller.
>>>>>
>>>>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>>>>> ---
>>>>> arch/arm/Kconfig | 1 +
>>>>> arch/arm/mach-exynos4/clock.c | 178
>>>>> +++++++++------------------
>>>>> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
>>>>> arch/arm/mach-exynos4/time.c | 2 +
>>>>> 4 files changed, 67 insertions(+), 121 deletions(-)
>>>>> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>>>
>>> (snip)
>>>
>>>>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> new file mode 100644
>>>>> index 0000000..1247f5e
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> @@ -0,0 +1,7 @@
>>>>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>>>>> +#define __MACH_EXYNOS4_CLKDEV_H__
>>>>> +
>>>>> +#define __clk_get(clk) ({ 1; })
>>>>> +#define __clk_put(clk) do { } while (0)
>>>>> +
>>>>> +#endif
>>>>
>>>> Looks good to me.
>>>>
>>>> One nitpick
>>>> How about to just create the one clkdev.h at plat-samsung with proper
>>>> ifdef endif config.
>>>> I think don't need to create clkdev.h for each SoCs.
>>>
>>> No, basically the "mach/clkdev.h" should be added, please see
>>> arch/arm/include/asm/clkdev.h.
>>
>> Okay it's required,
>> but also see the others.
>> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/mach-omap2/include/mach/clkdev.h
>>
>> 1 /*
>> 2 * arch/arm/mach-omap2/include/mach/clkdev.h
>> 3 */
>> 4
>> 5 #include <plat/clkdev.h>
>
> and
> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/plat-omap/include/plat/clkdev.h
>
> 1 #ifndef __MACH_CLKDEV_H
> 2 #define __MACH_CLKDEV_H
> 3
> 4 static inline int __clk_get(struct clk *clk)
> 5 {
> 6 return 1;
> 7 }
> 8
> 9 static inline void __clk_put(struct clk *clk)
> 10 {
> 11 }
> 12
> 13 #endif
>
> To Arnd,
>
> in case of ARM, it has almost same form. then how about to move the
> arm generic one?
>>
We also need to consider the case in which a platform requires a
custom implementation of __clk_get and __clk_put. In that case, will a
single clkdev.h suffice?
Thanks,
Thomas.
>> Thank you,
>> Kyungmin Park
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v2 7/7] ARM: Exynos4: Add clkdev support
@ 2011-05-28 3:39 ` Thomas Abraham
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-28 3:39 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, May 28, 2011 at 8:06 AM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Sat, May 28, 2011 at 11:33 AM, Kyungmin Park <kmpark@infradead.org> wrote:
>> On Sat, May 28, 2011 at 11:14 AM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>>>
>>>
>>> On 05/27/11 18:53, Kyungmin Park wrote:
>>>>
>>>> On Sat, May 28, 2011 at 12:26 AM, Thomas Abraham<thomas.ab@samsung.com>
>>>> ?wrote:
>>>>>
>>>>> Add clkdev support for Samsung's Exynos4 platform and fixes the
>>>>> incorrect clock name for the dw_mmc controller.
>>>>>
>>>>> Signed-off-by: Thomas Abraham<thomas.ab@samsung.com>
>>>>> ---
>>>>> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
>>>>> ?arch/arm/mach-exynos4/clock.c ? ? ? ? ? ? ? | ?178
>>>>> +++++++++------------------
>>>>> ?arch/arm/mach-exynos4/include/mach/clkdev.h | ? ?7 +
>>>>> ?arch/arm/mach-exynos4/time.c ? ? ? ? ? ? ? ?| ? ?2 +
>>>>> ?4 files changed, 67 insertions(+), 121 deletions(-)
>>>>> ?create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
>>>
>>> (snip)
>>>
>>>>> diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> new file mode 100644
>>>>> index 0000000..1247f5e
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
>>>>> @@ -0,0 +1,7 @@
>>>>> +#ifndef __MACH_EXYNOS4_CLKDEV_H__
>>>>> +#define __MACH_EXYNOS4_CLKDEV_H__
>>>>> +
>>>>> +#define __clk_get(clk) ({ 1; })
>>>>> +#define __clk_put(clk) do { } while (0)
>>>>> +
>>>>> +#endif
>>>>
>>>> Looks good to me.
>>>>
>>>> One nitpick
>>>> How about to just create the one clkdev.h at plat-samsung with proper
>>>> ifdef endif config.
>>>> I think don't need to create clkdev.h for each SoCs.
>>>
>>> No, basically the "mach/clkdev.h" should be added, please see
>>> arch/arm/include/asm/clkdev.h.
>>
>> Okay it's required,
>> but also see the others.
>> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/mach-omap2/include/mach/clkdev.h
>>
>> ? 1 /*
>> ? 2 ?* arch/arm/mach-omap2/include/mach/clkdev.h
>> ? 3 ?*/
>> ? 4
>> ? 5 #include <plat/clkdev.h>
>
> and
> http://git.infradead.org/linux-2.6.git/blob/HEAD:/arch/arm/plat-omap/include/plat/clkdev.h
>
> ? 1 #ifndef __MACH_CLKDEV_H
> ? 2 #define __MACH_CLKDEV_H
> ? 3
> ? 4 static inline int __clk_get(struct clk *clk)
> ? 5 {
> ? 6 ? ? ? ? return 1;
> ? 7 }
> ? 8
> ? 9 static inline void __clk_put(struct clk *clk)
> ?10 {
> ?11 }
> ?12
> ?13 #endif
>
> To Arnd,
>
> in case of ARM, it has almost same form. then how about to move the
> arm generic one?
>>
We also need to consider the case in which a platform requires a
custom implementation of __clk_get and __clk_put. In that case, will a
single clkdev.h suffice?
Thanks,
Thomas.
>> Thank you,
>> Kyungmin Park
>>
> --
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> the body of a message to majordomo at vger.kernel.org
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* Re: [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms
2011-05-27 15:26 [RFC][PATCH v2 0/7] Add clkdev support for Samsung platforms Thomas Abraham
` (6 preceding siblings ...)
2011-05-27 15:26 ` [PATCH v2 7/7] ARM: Exynos4: " Thomas Abraham
@ 2011-05-27 15:26 ` Thomas Abraham
7 siblings, 0 replies; 16+ messages in thread
From: Thomas Abraham @ 2011-05-27 15:26 UTC (permalink / raw)
To: linux-samsung-soc; +Cc: kgene.kim, ben-linux
On Fri, May 27, 2011 at 8:56 PM, Thomas Abraham <thomas.ab@samsung.com> wrote:
> This patch series adds clkdev support for all Samsung platforms. clkdev
> support is a prerequisite for adding device tree and common clock
> features on Samsung platforms.
This patch series is based on the latest
git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git master
and has been tested on the following boards.
SMDK2416, SMDK2440, SMDK2450, SMDK6410, SMDK6440, SMDK6450,
SMDKC100, SMDKV210 and SMDKV310.
>
> Changes since v1:
>
> 1. Removed the clock id field from clock instances.
> 2. Fixed incorrect naming of guards in mach/clkdev.h files.
>
> Thomas Abraham (7):
> ARM: SAMSUNG: Add clkdev infrastructure
> ARM: S3C24XX: Add clkdev support
> ARM: S3C64XX: Add clkdev support
> ARM: S5P64X0: Add clkdev support
> ARM: S5PC100: Add clkdev support
> ARM: S5PV210: Add clkdev support
> ARM: Exynos4: Add clkdev support
>
> arch/arm/Kconfig | 6 +
> arch/arm/mach-exynos4/clock.c | 178 +++++++++------------------
> arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +
> arch/arm/mach-exynos4/time.c | 2 +
> arch/arm/mach-s3c2412/clock.c | 36 +-----
> arch/arm/mach-s3c2416/clock.c | 10 +-
> arch/arm/mach-s3c2440/clock.c | 3 -
> arch/arm/mach-s3c2443/clock.c | 16 +--
> arch/arm/mach-s3c64xx/clock.c | 86 ++++---------
> arch/arm/mach-s3c64xx/include/mach/clkdev.h | 7 +
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 74 +++--------
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 68 +++--------
> arch/arm/mach-s5p64x0/include/mach/clkdev.h | 7 +
> arch/arm/mach-s5pc100/clock.c | 163 ++++++------------------
> arch/arm/mach-s5pc100/include/mach/clkdev.h | 7 +
> arch/arm/mach-s5pv210/clock.c | 130 ++++++--------------
> arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 +
> arch/arm/plat-s3c24xx/clock-dclk.c | 4 -
> arch/arm/plat-s3c24xx/include/mach/clkdev.h | 7 +
> arch/arm/plat-s3c24xx/s3c2410-clock.c | 21 +---
> arch/arm/plat-s3c24xx/s3c2443-clock.c | 39 +-----
> arch/arm/plat-s5p/s5p-time.c | 9 ++
> arch/arm/plat-samsung/clock.c | 98 +--------------
> arch/arm/plat-samsung/include/plat/clock.h | 3 +
> arch/arm/plat-samsung/pwm-clock.c | 10 ++
> arch/arm/plat-samsung/time.c | 2 +
> 26 files changed, 300 insertions(+), 700 deletions(-)
> create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s3c64xx/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5p64x0/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5pc100/include/mach/clkdev.h
> create mode 100644 arch/arm/mach-s5pv210/include/mach/clkdev.h
> create mode 100644 arch/arm/plat-s3c24xx/include/mach/clkdev.h
>
> --
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>
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