From: Larry Finger <Larry.Finger@lwfinger.net>
To: Andreas Schwab <schwab@linux-m68k.org>
Cc: "Rafał Miłecki"
<public-zajec5-Re5JQEeQqe8AvxtiuMwx3w@plane.gmane.org>,
"Michael Büsch"
<public-mb-fseUSCV1ubazQB+pC5nmwQ@plane.gmane.org>,
public-linux-wireless-u79uwXL29TY76Z2rM5mHXA@plane.gmane.org,
"John W. Linville"
<public-linville-2XuSBdqkA4R54TAoqtyWWQ@plane.gmane.org>,
public-b43-dev-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@plane.gmane.org,
linuxppc-dev@ozlabs.org
Subject: Re: [PATCH] ssb: pci: implement serdes workaround
Date: Tue, 31 May 2011 11:17:11 -0500 [thread overview]
Message-ID: <4DE51487.1000808@lwfinger.net> (raw)
In-Reply-To: <m3wrh6hnmn.fsf@linux-m68k.org>
On 05/31/2011 10:54 AM, Andreas Schwab wrote:
> Larry Finger<Larry.Finger@lwfinger.net> writes:
>
>> From the traceback, it must be the serdes_pll_device read that failed.
>
> Why not ssb_pcicore_polarity_workaround (note r4 == 0x134)?
Mainly because the last two steps in the traceback are
[c2ca5c40] [f2146244] ssb_pcie_read+0x4c/0x54 [ssb]
[c2ca5c50] [f2146440] ssb_pcicore_serdes_workaround+0x1c/0x170 [ssb]
Larry
WARNING: multiple messages have this Message-ID (diff)
From: Larry Finger <Larry.Finger@lwfinger.net>
To: Andreas Schwab <schwab@linux-m68k.org>
Cc: "Rafał Miłecki"
<public-zajec5-Re5JQEeQqe8AvxtiuMwx3w@plane.gmane.org>,
"Michael Büsch"
<public-mb-fseUSCV1ubazQB+pC5nmwQ@plane.gmane.org>,
public-b43-dev-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@plane.gmane.org,
linuxppc-dev@ozlabs.org,
"John W. Linville"
<public-linville-2XuSBdqkA4R54TAoqtyWWQ@plane.gmane.org>,
public-linux-wireless-u79uwXL29TY76Z2rM5mHXA@plane.gmane.org
Subject: Re: [PATCH] ssb: pci: implement serdes workaround
Date: Tue, 31 May 2011 11:17:11 -0500 [thread overview]
Message-ID: <4DE51487.1000808@lwfinger.net> (raw)
In-Reply-To: <m3wrh6hnmn.fsf@linux-m68k.org>
On 05/31/2011 10:54 AM, Andreas Schwab wrote:
> Larry Finger<Larry.Finger@lwfinger.net> writes:
>
>> From the traceback, it must be the serdes_pll_device read that failed.
>
> Why not ssb_pcicore_polarity_workaround (note r4 == 0x134)?
Mainly because the last two steps in the traceback are
[c2ca5c40] [f2146244] ssb_pcie_read+0x4c/0x54 [ssb]
[c2ca5c50] [f2146440] ssb_pcicore_serdes_workaround+0x1c/0x170 [ssb]
Larry
next prev parent reply other threads:[~2011-05-31 16:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-01 11:26 [PATCH] ssb: pci: implement serdes workaround Rafał Miłecki
2011-04-01 11:26 ` Rafał Miłecki
2011-05-31 9:37 ` Andreas Schwab
2011-05-31 9:37 ` Andreas Schwab
2011-05-31 15:14 ` Larry Finger
2011-05-31 15:14 ` Larry Finger
2011-05-31 15:54 ` Andreas Schwab
2011-05-31 15:54 ` Andreas Schwab
2011-05-31 16:17 ` Larry Finger [this message]
2011-05-31 16:17 ` Larry Finger
2011-05-31 17:07 ` Andreas Schwab
2011-05-31 17:07 ` Andreas Schwab
2011-05-31 17:32 ` Andreas Schwab
2011-05-31 17:32 ` Andreas Schwab
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