* [PATCH V3 0/3] ARM: SAMSUNG: Add support for sdhci clock lookup using generic names @ 2011-10-12 9:43 ` Rajeshwari Shinde 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-mmc, linux-samsung-soc; +Cc: cjb, kgene.kim, linux-arm-kernel This patchset adds support for sdhci controller clock lookup using generic names. With this patchset, there will be no need to pass clock names in sdhci platform data. This patchset depends on the patchset: Add a common macro for creating struct clk_lookup entries. mmc: sdhci-s3c: add default controller configuration. V2 Changes: - Added HCLK instance for HSMMC instance 1 as suggested by Heiko. - Rebased on UART clkdev patches. So these patches should be applied after UART clkdev patches are applied. V3 Changes: - Removed double registration of hsmmc1 hclk from s3c2416 as suggested by Heiko Rajeshwari Shinde (3): SDHCI: S3C: Use generic clock names for sdhci bus clock options ARM: SAMSUNG: Remove SDHCI bus clocks from platform data ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names arch/arm/mach-exynos4/Makefile | 1 - arch/arm/mach-exynos4/clock.c | 88 +++++++++------ arch/arm/mach-exynos4/setup-sdhci.c | 22 ---- arch/arm/mach-s3c2416/Makefile | 1 - arch/arm/mach-s3c2416/clock.c | 68 ++++++----- arch/arm/mach-s3c2416/setup-sdhci.c | 24 ---- arch/arm/mach-s3c64xx/Makefile | 1 - arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++-------- arch/arm/mach-s3c64xx/setup-sdhci.c | 24 ---- arch/arm/mach-s5pc100/Makefile | 1 - arch/arm/mach-s5pc100/clock.c | 130 +++++++++++++--------- arch/arm/mach-s5pc100/setup-sdhci.c | 23 ---- arch/arm/mach-s5pv210/Makefile | 1 - arch/arm/mach-s5pv210/clock.c | 167 +++++++++++++++++----------- arch/arm/mach-s5pv210/setup-sdhci.c | 22 ---- arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- arch/arm/plat-samsung/include/plat/sdhci.h | 31 ----- drivers/mmc/host/sdhci-s3c.c | 6 +- 18 files changed, 361 insertions(+), 390 deletions(-) delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c -- 1.7.4.4 ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V3 0/3] ARM: SAMSUNG: Add support for sdhci clock lookup using generic names @ 2011-10-12 9:43 ` Rajeshwari Shinde 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-arm-kernel This patchset adds support for sdhci controller clock lookup using generic names. With this patchset, there will be no need to pass clock names in sdhci platform data. This patchset depends on the patchset: Add a common macro for creating struct clk_lookup entries. mmc: sdhci-s3c: add default controller configuration. V2 Changes: - Added HCLK instance for HSMMC instance 1 as suggested by Heiko. - Rebased on UART clkdev patches. So these patches should be applied after UART clkdev patches are applied. V3 Changes: - Removed double registration of hsmmc1 hclk from s3c2416 as suggested by Heiko Rajeshwari Shinde (3): SDHCI: S3C: Use generic clock names for sdhci bus clock options ARM: SAMSUNG: Remove SDHCI bus clocks from platform data ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names arch/arm/mach-exynos4/Makefile | 1 - arch/arm/mach-exynos4/clock.c | 88 +++++++++------ arch/arm/mach-exynos4/setup-sdhci.c | 22 ---- arch/arm/mach-s3c2416/Makefile | 1 - arch/arm/mach-s3c2416/clock.c | 68 ++++++----- arch/arm/mach-s3c2416/setup-sdhci.c | 24 ---- arch/arm/mach-s3c64xx/Makefile | 1 - arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++-------- arch/arm/mach-s3c64xx/setup-sdhci.c | 24 ---- arch/arm/mach-s5pc100/Makefile | 1 - arch/arm/mach-s5pc100/clock.c | 130 +++++++++++++--------- arch/arm/mach-s5pc100/setup-sdhci.c | 23 ---- arch/arm/mach-s5pv210/Makefile | 1 - arch/arm/mach-s5pv210/clock.c | 167 +++++++++++++++++----------- arch/arm/mach-s5pv210/setup-sdhci.c | 22 ---- arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- arch/arm/plat-samsung/include/plat/sdhci.h | 31 ----- drivers/mmc/host/sdhci-s3c.c | 6 +- 18 files changed, 361 insertions(+), 390 deletions(-) delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c -- 1.7.4.4 ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V3 1/3] SDHCI: S3C: Use generic clock names for sdhci bus clock options 2011-10-12 9:43 ` Rajeshwari Shinde @ 2011-10-12 9:43 ` Rajeshwari Shinde -1 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-mmc, linux-samsung-soc; +Cc: cjb, kgene.kim, linux-arm-kernel This patch modifies the driver to stop depending on the clock names being passed from the platform and switch over to bus clock lookup using generic clock names. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- drivers/mmc/host/sdhci-s3c.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 82709b6..a5fde87 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -435,14 +435,12 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev) for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { struct clk *clk; - char *name = pdata->clocks[ptr]; + char name[14]; - if (name == NULL) - continue; + sprintf(name, "mmc_busclk.%d", ptr); clk = clk_get(dev, name); if (IS_ERR(clk)) { - dev_err(dev, "failed to get clock %s\n", name); continue; } -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V3 1/3] SDHCI: S3C: Use generic clock names for sdhci bus clock options @ 2011-10-12 9:43 ` Rajeshwari Shinde 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-arm-kernel This patch modifies the driver to stop depending on the clock names being passed from the platform and switch over to bus clock lookup using generic clock names. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- drivers/mmc/host/sdhci-s3c.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 82709b6..a5fde87 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -435,14 +435,12 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev) for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { struct clk *clk; - char *name = pdata->clocks[ptr]; + char name[14]; - if (name == NULL) - continue; + sprintf(name, "mmc_busclk.%d", ptr); clk = clk_get(dev, name); if (IS_ERR(clk)) { - dev_err(dev, "failed to get clock %s\n", name); continue; } -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V3 2/3] ARM: SAMSUNG: Remove SDHCI bus clocks from platform data 2011-10-12 9:43 ` Rajeshwari Shinde @ 2011-10-12 9:43 ` Rajeshwari Shinde -1 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-mmc, linux-samsung-soc; +Cc: cjb, kgene.kim, linux-arm-kernel The bus clocks previously sent through platform data to SDHCI controller are removed. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- arch/arm/mach-exynos4/Makefile | 1 - arch/arm/mach-exynos4/setup-sdhci.c | 22 ------------------- arch/arm/mach-s3c2416/Makefile | 1 - arch/arm/mach-s3c2416/setup-sdhci.c | 24 --------------------- arch/arm/mach-s3c64xx/Makefile | 1 - arch/arm/mach-s3c64xx/setup-sdhci.c | 24 --------------------- arch/arm/mach-s5pc100/Makefile | 1 - arch/arm/mach-s5pc100/setup-sdhci.c | 23 -------------------- arch/arm/mach-s5pv210/Makefile | 1 - arch/arm/mach-s5pv210/setup-sdhci.c | 22 ------------------- arch/arm/plat-samsung/include/plat/sdhci.h | 31 ---------------------------- 11 files changed, 0 insertions(+), 151 deletions(-) delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 2bb18f4..c47aae3 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -55,7 +55,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c deleted file mode 100644 index 92937b4..0000000 --- a/arch/arm/mach-exynos4/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-sdhci.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *exynos4_hsmmc_clksrcs[4] = { - [0] = NULL, - [1] = NULL, - [2] = "sclk_mmc", /* mmc_bus */ - [3] = NULL, -}; diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile index 7b805b2..ca0cd22 100644 --- a/arch/arm/mach-s3c2416/Makefile +++ b/arch/arm/mach-s3c2416/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o #obj-$(CONFIG_S3C2416_DMA) += dma.o # Device setup -obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # Machine support diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c deleted file mode 100644 index cee5395..0000000 --- a/arch/arm/mach-s3c2416/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/setup-sdhci.c - * - * Copyright 2010 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c64xx/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c2416_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "hsmmc-if", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 902ab9a..94de24b 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c deleted file mode 100644 index c75a71b..0000000 --- a/arch/arm/mach-s3c64xx/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c64xx_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index a5e6e60..2320e54 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # device support diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c deleted file mode 100644 index 6418c6e..0000000 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ /dev/null @@ -1,23 +0,0 @@ -/* linux/arch/arm/mach-s5pc100/setup-sdhci.c - * - * Copyright 2008 Samsung Electronics - * - * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c6410/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pc100_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 009fbe5..53c346a 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -35,5 +35,4 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c deleted file mode 100644 index 6b8ccc4..0000000 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/setup-sdhci.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pv210_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = NULL, - reserved */ -}; diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index e7b3c75..dcff7dd 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -66,8 +66,6 @@ struct s3c_sdhci_platdata { enum cd_types cd_type; enum clk_types clk_type; - char **clocks; /* set of clock sources */ - int ext_cd_gpio; bool ext_cd_gpio_invert; int (*ext_cd_init)(void (*notify_func)(struct platform_device *, @@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ #ifdef CONFIG_S3C2416_SETUP_SDHCI -extern char *s3c2416_hsmmc_clksrcs[4]; - static inline void s3c2416_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC */ } @@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void) static inline void s3c2416_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC1 */ } @@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { } /* S3C64XX SDHCI setup */ #ifdef CONFIG_S3C64XX_SETUP_SDHCI -extern char *s3c64xx_hsmmc_clksrcs[4]; - static inline void s3c6400_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void) static inline void s3c6400_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void) static inline void s3c6400_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void) static inline void s3c6410_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void) static inline void s3c6410_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void) static inline void s3c6410_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { } /* S5PC100 SDHCI setup */ #ifdef CONFIG_S5PC100_SETUP_SDHCI -extern char *s5pc100_hsmmc_clksrcs[4]; - static inline void s5pc100_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; #endif } @@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void) static inline void s5pc100_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; #endif } @@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void) static inline void s5pc100_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; #endif } @@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { } /* S5PV210 SDHCI setup */ #ifdef CONFIG_S5PV210_SETUP_SDHCI -extern char *s5pv210_hsmmc_clksrcs[4]; - static inline void s5pv210_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; #endif } @@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void) static inline void s5pv210_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; #endif } @@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void) static inline void s5pv210_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; #endif } @@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void) static inline void s5pv210_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; #endif } @@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { } /* EXYNOS4 SDHCI setup */ #ifdef CONFIG_EXYNOS4_SETUP_SDHCI -extern char *exynos4_hsmmc_clksrcs[4]; - static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; #endif } @@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void) static inline void exynos4_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; #endif } @@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void) static inline void exynos4_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; #endif } @@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void) static inline void exynos4_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; #endif } -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V3 2/3] ARM: SAMSUNG: Remove SDHCI bus clocks from platform data @ 2011-10-12 9:43 ` Rajeshwari Shinde 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-arm-kernel The bus clocks previously sent through platform data to SDHCI controller are removed. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- arch/arm/mach-exynos4/Makefile | 1 - arch/arm/mach-exynos4/setup-sdhci.c | 22 ------------------- arch/arm/mach-s3c2416/Makefile | 1 - arch/arm/mach-s3c2416/setup-sdhci.c | 24 --------------------- arch/arm/mach-s3c64xx/Makefile | 1 - arch/arm/mach-s3c64xx/setup-sdhci.c | 24 --------------------- arch/arm/mach-s5pc100/Makefile | 1 - arch/arm/mach-s5pc100/setup-sdhci.c | 23 -------------------- arch/arm/mach-s5pv210/Makefile | 1 - arch/arm/mach-s5pv210/setup-sdhci.c | 22 ------------------- arch/arm/plat-samsung/include/plat/sdhci.h | 31 ---------------------------- 11 files changed, 0 insertions(+), 151 deletions(-) delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 2bb18f4..c47aae3 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -55,7 +55,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c deleted file mode 100644 index 92937b4..0000000 --- a/arch/arm/mach-exynos4/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-sdhci.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *exynos4_hsmmc_clksrcs[4] = { - [0] = NULL, - [1] = NULL, - [2] = "sclk_mmc", /* mmc_bus */ - [3] = NULL, -}; diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile index 7b805b2..ca0cd22 100644 --- a/arch/arm/mach-s3c2416/Makefile +++ b/arch/arm/mach-s3c2416/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o #obj-$(CONFIG_S3C2416_DMA) += dma.o # Device setup -obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # Machine support diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c deleted file mode 100644 index cee5395..0000000 --- a/arch/arm/mach-s3c2416/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/setup-sdhci.c - * - * Copyright 2010 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c64xx/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c2416_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "hsmmc-if", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 902ab9a..94de24b 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c deleted file mode 100644 index c75a71b..0000000 --- a/arch/arm/mach-s3c64xx/setup-sdhci.c +++ /dev/null @@ -1,24 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c - * - * Copyright 2008 Simtec Electronics - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s3c64xx_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - [2] = "mmc_bus", - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index a5e6e60..2320e54 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o # device support diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c deleted file mode 100644 index 6418c6e..0000000 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ /dev/null @@ -1,23 +0,0 @@ -/* linux/arch/arm/mach-s5pc100/setup-sdhci.c - * - * Copyright 2008 Samsung Electronics - * - * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * Based on mach-s3c6410/setup-sdhci.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pc100_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = "48m", - note not successfully used yet */ -}; diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 009fbe5..53c346a 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -35,5 +35,4 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c deleted file mode 100644 index 6b8ccc4..0000000 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ /dev/null @@ -1,22 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/setup-sdhci.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pv210_hsmmc_clksrcs[4] = { - [0] = "hsmmc", /* HCLK */ - /* [1] = "hsmmc", - duplicate HCLK entry */ - [2] = "sclk_mmc", /* mmc_bus */ - /* [3] = NULL, - reserved */ -}; diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index e7b3c75..dcff7dd 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -66,8 +66,6 @@ struct s3c_sdhci_platdata { enum cd_types cd_type; enum clk_types clk_type; - char **clocks; /* set of clock sources */ - int ext_cd_gpio; bool ext_cd_gpio_invert; int (*ext_cd_init)(void (*notify_func)(struct platform_device *, @@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ #ifdef CONFIG_S3C2416_SETUP_SDHCI -extern char *s3c2416_hsmmc_clksrcs[4]; - static inline void s3c2416_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC */ } @@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void) static inline void s3c2416_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; #endif /* CONFIG_S3C_DEV_HSMMC1 */ } @@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { } /* S3C64XX SDHCI setup */ #ifdef CONFIG_S3C64XX_SETUP_SDHCI -extern char *s3c64xx_hsmmc_clksrcs[4]; - static inline void s3c6400_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void) static inline void s3c6400_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void) static inline void s3c6400_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void) static inline void s3c6410_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; #endif } @@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void) static inline void s3c6410_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; #endif } @@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void) static inline void s3c6410_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; #endif } @@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { } /* S5PC100 SDHCI setup */ #ifdef CONFIG_S5PC100_SETUP_SDHCI -extern char *s5pc100_hsmmc_clksrcs[4]; - static inline void s5pc100_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; #endif } @@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void) static inline void s5pc100_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; #endif } @@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void) static inline void s5pc100_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; #endif } @@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { } /* S5PV210 SDHCI setup */ #ifdef CONFIG_S5PV210_SETUP_SDHCI -extern char *s5pv210_hsmmc_clksrcs[4]; - static inline void s5pv210_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; #endif } @@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void) static inline void s5pv210_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; #endif } @@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void) static inline void s5pv210_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; #endif } @@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void) static inline void s5pv210_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; #endif } @@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { } /* EXYNOS4 SDHCI setup */ #ifdef CONFIG_EXYNOS4_SETUP_SDHCI -extern char *exynos4_hsmmc_clksrcs[4]; - static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; #endif } @@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void) static inline void exynos4_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; #endif } @@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void) static inline void exynos4_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; #endif } @@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void) static inline void exynos4_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; #endif } -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-12 9:43 ` Rajeshwari Shinde @ 2011-10-12 9:43 ` Rajeshwari Shinde -1 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-mmc, linux-samsung-soc; +Cc: cjb, kgene.kim, linux-arm-kernel Add support for lookup of sdhci-s3c controller clocks using generic names for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- arch/arm/mach-s3c2416/clock.c | 68 +++++++------ arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- 6 files changed, 359 insertions(+), 235 deletions(-) diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 9f50e33..c6383b9 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .parent = &clk_dout_mmc0.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 0), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .parent = &clk_dout_mmc1.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 4), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .parent = &clk_dout_mmc2.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 8), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .parent = &clk_dout_mmc3.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 12), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, - }, { - .clk = { .name = "sclk_dwmmc", .parent = &clk_dout_mmc4.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .parent = &clk_dout_mmc0.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .parent = &clk_dout_mmc1.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .parent = &clk_dout_mmc2.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .parent = &clk_dout_mmc3.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart1, &clk_sclk_uart2, &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, }; static struct clk_lookup exynos4_clk_lookup[] = { @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 72b7c62..6ece510 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -82,39 +82,38 @@ static struct clksrc_clk hsmmc_div[] = { }, }; -static struct clksrc_clk hsmmc_mux[] = { - [0] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 6), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[0].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +static struct clksrc_clk hsmmc_mux0 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 6), + .enable = s3c2443_clkcon_enable_s, }, - [1] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 12), - .enable = s3c2443_clkcon_enable_s, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[0].clk, + [1] = NULL, /* to fix */ }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[1].clk, - [1] = NULL, /* to fix */ - }, + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +}; + +static struct clksrc_clk hsmmc_mux1 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 12), + .enable = s3c2443_clkcon_enable_s, + }, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[1].clk, + [1] = NULL, /* to fix */ }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }; static struct clk hsmmc0_clk = { @@ -143,8 +142,14 @@ static struct clksrc_clk *clksrcs[] __initdata = { &hsspi_mux, &hsmmc_div[0], &hsmmc_div[1], - &hsmmc_mux[0], - &hsmmc_mux[1], + &hsmmc_mux0, + &hsmmc_mux1, +}; + +static struct clk_lookup s3c2416_clk_lookup[] = { + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), }; void __init s3c2416_init_clocks(int xtal) @@ -164,6 +169,7 @@ void __init s3c2416_init_clocks(int xtal) s3c_register_clksrc(clksrcs[ptr], 1); s3c24xx_register_clock(&hsmmc0_clk); + clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 2addd98..415c540 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -243,24 +243,6 @@ static struct clk init_clocks[] = { .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, - }, { .name = "otg", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, @@ -310,6 +292,29 @@ static struct clk init_clocks[] = { } }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, +}; static struct clk clk_fout_apll = { .name = "fout_apll", @@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.0", - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.1", - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.2", - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { .name = "usb-bus-host", .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, @@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = { .sources = &clkset_uart, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.0", + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.1", + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.2", + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + /* Clock initialisation code */ static struct clksrc_clk *init_parents[] = { @@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = { static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uclk, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, }; static struct clk_lookup s3c64xx_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), }; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) @@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal, s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) + s3c_disable_clocks(clk_cdev[cnt], 1); + s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 9d644ec..69829ba 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = { .enable = s5pc100_d0_2_ctrl, .ctrlbit = (1 << 1), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 5), - }, { .name = "modemif", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, @@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = { }, }; +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 7), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 6), +}; + +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 5), +}; + static struct clk clk_vclk54m = { .name = "vclk_54m", .rate = 54000000, @@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 12), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc0, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 13), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .ctrlbit = (1 << 14), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, - }, { - .clk = { .name = "sclk_irda", .ctrlbit = (1 << 10), .enable = s5pc100_sclk0_ctrl, @@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 12), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc0, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 13), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .ctrlbit = (1 << 14), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, +}; + /* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_spdif, }; +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, +}; + static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, }; void __init_or_cpufreq s5pc100_setup_clocks(void) @@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = { static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), }; void __init s5pc100_register_clocks(void) @@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void) s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c24xx_register_clock(&dummy_apb_pclk); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 43a045d..dc4586b 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<16), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<17), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<18), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.3", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<19), - }, { .name = "systimer", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, @@ -559,6 +535,38 @@ static struct clk init_clocks[] = { }, }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<16), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<17), +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<18), +}; + +static struct clk clk_hsmmc3 = { + .name = "hsmmc", + .devname = "s3c-sdhci.3", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<19), +}; + static struct clk *clkset_uart_list[] = { [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, @@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 9), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 10), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 11), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, - }, { - .clk = { .name = "sclk_mfc", .devname = "s5p-mfc", .enable = s5pv210_clk_ip0_ctrl, @@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3 = { .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 10), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 11), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, +}; + static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart0, &clk_sclk_uart1, &clk_sclk_uart2, &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_hsmmc3, }; /* Clock initialisation code */ @@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = { CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), }; void __init s5pv210_register_clocks(void) @@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void) s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c24xx_register_clock(&dummy_apb_pclk); s3c_pwmclk_init(); } diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 4a24e15..2a2a255 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -309,11 +309,6 @@ static struct clk init_clocks[] = { .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA5, }, { - .name = "hsmmc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, - }, { .name = "gpio", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, @@ -395,6 +390,14 @@ static struct clk init_clocks[] = { } }; +static struct clk hsmmc1_clk = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, +}; + static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) { clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; @@ -460,6 +463,7 @@ static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, &clk_usb_bus, + &hsmmc1_clk, }; static struct clksrc_clk *clksrcs[] __initdata = { @@ -475,6 +479,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-12 9:43 ` Rajeshwari Shinde 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw) To: linux-arm-kernel Add support for lookup of sdhci-s3c controller clocks using generic names for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- arch/arm/mach-s3c2416/clock.c | 68 +++++++------ arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- 6 files changed, 359 insertions(+), 235 deletions(-) diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 9f50e33..c6383b9 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .parent = &clk_dout_mmc0.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 0), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .parent = &clk_dout_mmc1.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 4), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .parent = &clk_dout_mmc2.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 8), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .parent = &clk_dout_mmc3.clk, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 12), - }, - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, - }, { - .clk = { .name = "sclk_dwmmc", .parent = &clk_dout_mmc4.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .parent = &clk_dout_mmc0.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .parent = &clk_dout_mmc1.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .parent = &clk_dout_mmc2.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .parent = &clk_dout_mmc3.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart1, &clk_sclk_uart2, &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, }; static struct clk_lookup exynos4_clk_lookup[] = { @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 72b7c62..6ece510 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -82,39 +82,38 @@ static struct clksrc_clk hsmmc_div[] = { }, }; -static struct clksrc_clk hsmmc_mux[] = { - [0] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 6), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[0].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +static struct clksrc_clk hsmmc_mux0 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 6), + .enable = s3c2443_clkcon_enable_s, }, - [1] = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 12), - .enable = s3c2443_clkcon_enable_s, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[0].clk, + [1] = NULL, /* to fix */ }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk *[]) { - [0] = &hsmmc_div[1].clk, - [1] = NULL, /* to fix */ - }, + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, +}; + +static struct clksrc_clk hsmmc_mux1 = { + .clk = { + .name = "hsmmc-if", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 12), + .enable = s3c2443_clkcon_enable_s, + }, + .sources = &(struct clksrc_sources) { + .nr_sources = 2, + .sources = (struct clk * []) { + [0] = &hsmmc_div[1].clk, + [1] = NULL, /* to fix */ }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, }; static struct clk hsmmc0_clk = { @@ -143,8 +142,14 @@ static struct clksrc_clk *clksrcs[] __initdata = { &hsspi_mux, &hsmmc_div[0], &hsmmc_div[1], - &hsmmc_mux[0], - &hsmmc_mux[1], + &hsmmc_mux0, + &hsmmc_mux1, +}; + +static struct clk_lookup s3c2416_clk_lookup[] = { + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), }; void __init s3c2416_init_clocks(int xtal) @@ -164,6 +169,7 @@ void __init s3c2416_init_clocks(int xtal) s3c_register_clksrc(clksrcs[ptr], 1); s3c24xx_register_clock(&hsmmc0_clk); + clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 2addd98..415c540 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -243,24 +243,6 @@ static struct clk init_clocks[] = { .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_h, - .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, - }, { .name = "otg", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, @@ -310,6 +292,29 @@ static struct clk init_clocks[] = { } }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, +}; static struct clk clk_fout_apll = { .name = "fout_apll", @@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = { static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.0", - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.1", - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { - .name = "mmc_bus", - .devname = "s3c-sdhci.2", - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, - .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, - .sources = &clkset_spi_mmc, - }, { - .clk = { .name = "usb-bus-host", .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, @@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = { .sources = &clkset_uart, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.0", + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.1", + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.2", + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + /* Clock initialisation code */ static struct clksrc_clk *init_parents[] = { @@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = { static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uclk, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, }; static struct clk_lookup s3c64xx_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), }; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) @@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal, s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) + s3c_disable_clocks(clk_cdev[cnt], 1); + s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 9d644ec..69829ba 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = { .enable = s5pc100_d0_2_ctrl, .ctrlbit = (1 << 1), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_div_d1_bus.clk, - .enable = s5pc100_d1_0_ctrl, - .ctrlbit = (1 << 5), - }, { .name = "modemif", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, @@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = { }, }; +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 7), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 6), +}; + +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_div_d1_bus.clk, + .enable = s5pc100_d1_0_ctrl, + .ctrlbit = (1 << 5), +}; + static struct clk clk_vclk54m = { .name = "vclk_54m", .rate = 54000000, @@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 12), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc0, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 13), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .ctrlbit = (1 << 14), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_mmc12, - .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, - .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, - }, { - .clk = { .name = "sclk_irda", .ctrlbit = (1 << 10), .enable = s5pc100_sclk0_ctrl, @@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .ctrlbit = (1 << 12), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc0, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .ctrlbit = (1 << 13), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .ctrlbit = (1 << 14), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_mmc12, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, +}; + /* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_spdif, }; +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, +}; + static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, }; void __init_or_cpufreq s5pc100_setup_clocks(void) @@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = { static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), }; void __init s5pc100_register_clocks(void) @@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void) s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c24xx_register_clock(&dummy_apb_pclk); s3c_pwmclk_init(); diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 43a045d..dc4586b 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<16), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<17), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<18), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.3", - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip2_ctrl, - .ctrlbit = (1<<19), - }, { .name = "systimer", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, @@ -559,6 +535,38 @@ static struct clk init_clocks[] = { }, }; +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<16), +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<17), +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<18), +}; + +static struct clk clk_hsmmc3 = { + .name = "hsmmc", + .devname = "s3c-sdhci.3", + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1<<19), +}; + static struct clk *clkset_uart_list[] = { [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, @@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, }, { .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 9), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 10), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 11), - }, - .sources = &clkset_group2, - .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, - }, { - .clk = { .name = "sclk_mfc", .devname = "s5p-mfc", .enable = s5pv210_clk_ip0_ctrl, @@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3 = { .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, }; +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.0", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.1", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.2", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 10), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "s3c-sdhci.3", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 11), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, +}; + static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart0, &clk_sclk_uart1, &clk_sclk_uart2, &clk_sclk_uart3, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_mmc3, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_hsmmc3, }; /* Clock initialisation code */ @@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = { CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), }; void __init s5pv210_register_clocks(void) @@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void) s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c24xx_register_clock(&dummy_apb_pclk); s3c_pwmclk_init(); } diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 4a24e15..2a2a255 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -309,11 +309,6 @@ static struct clk init_clocks[] = { .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA5, }, { - .name = "hsmmc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, - }, { .name = "gpio", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, @@ -395,6 +390,14 @@ static struct clk init_clocks[] = { } }; +static struct clk hsmmc1_clk = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_HSMMC, +}; + static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) { clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; @@ -460,6 +463,7 @@ static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, &clk_usb_bus, + &hsmmc1_clk, }; static struct clksrc_clk *clksrcs[] __initdata = { @@ -475,6 +479,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, -- 1.7.4.4 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-12 9:43 ` Rajeshwari Shinde @ 2011-10-12 10:24 ` Sylwester Nawrocki -1 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-12 10:24 UTC (permalink / raw) To: Rajeshwari Shinde Cc: linux-mmc, linux-samsung-soc, cjb, kgene.kim, linux-arm-kernel Hi Rajeshwari, On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: > Add support for lookup of sdhci-s3c controller clocks using generic names > for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. > > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > --- > arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- > arch/arm/mach-s3c2416/clock.c | 68 +++++++------ > arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- > arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- > arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- > arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- > 6 files changed, 359 insertions(+), 235 deletions(-) > > diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c > index 9f50e33..c6383b9 100644 > --- a/arch/arm/mach-exynos4/clock.c > +++ b/arch/arm/mach-exynos4/clock.c > @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { > .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, > }, { > .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.0", > - .parent = &clk_dout_mmc0.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 0), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.1", > - .parent = &clk_dout_mmc1.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 4), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.2", > - .parent = &clk_dout_mmc2.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 8), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.3", > - .parent = &clk_dout_mmc3.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 12), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, > - }, { > - .clk = { > .name = "sclk_dwmmc", > .parent = &clk_dout_mmc4.clk, > .enable = exynos4_clksrc_mask_fsys_ctrl, > @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { > .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, > }; > > +static struct clksrc_clk clk_sclk_mmc0 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.0", Would it make sense to drop this 'devname' field here and others until sclk_mmc3 .... > + .parent = &clk_dout_mmc0.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 0), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc1 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.1", > + .parent = &clk_dout_mmc1.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 4), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc2 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.2", > + .parent = &clk_dout_mmc2.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 8), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc3 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.3", > + .parent = &clk_dout_mmc3.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 12), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, > +}; > + > /* Clock initialization code */ > static struct clksrc_clk *sysclks[] = { > &clk_mout_apll, > @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { > &clk_sclk_uart1, > &clk_sclk_uart2, > &clk_sclk_uart3, > + &clk_sclk_mmc0, > + &clk_sclk_mmc1, > + &clk_sclk_mmc2, > + &clk_sclk_mmc3, ..then drop the above 4 lines... > }; > > static struct clk_lookup exynos4_clk_lookup[] = { > @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { > CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), > CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), > CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), > + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), > + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), > + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), > + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), ..and add something like: + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), ? Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? Does it all work on exynos ? I would expect the device name to be same across all the clock definitions, otherwise clk_get(dev, ..) will fail. > }; > Regards -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-12 10:24 ` Sylwester Nawrocki 0 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-12 10:24 UTC (permalink / raw) To: linux-arm-kernel Hi Rajeshwari, On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: > Add support for lookup of sdhci-s3c controller clocks using generic names > for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. > > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > --- > arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- > arch/arm/mach-s3c2416/clock.c | 68 +++++++------ > arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- > arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- > arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- > arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- > 6 files changed, 359 insertions(+), 235 deletions(-) > > diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c > index 9f50e33..c6383b9 100644 > --- a/arch/arm/mach-exynos4/clock.c > +++ b/arch/arm/mach-exynos4/clock.c > @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { > .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, > }, { > .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.0", > - .parent = &clk_dout_mmc0.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 0), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.1", > - .parent = &clk_dout_mmc1.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 4), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.2", > - .parent = &clk_dout_mmc2.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 8), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, > - }, { > - .clk = { > - .name = "sclk_mmc", > - .devname = "s3c-sdhci.3", > - .parent = &clk_dout_mmc3.clk, > - .enable = exynos4_clksrc_mask_fsys_ctrl, > - .ctrlbit = (1 << 12), > - }, > - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, > - }, { > - .clk = { > .name = "sclk_dwmmc", > .parent = &clk_dout_mmc4.clk, > .enable = exynos4_clksrc_mask_fsys_ctrl, > @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { > .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, > }; > > +static struct clksrc_clk clk_sclk_mmc0 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.0", Would it make sense to drop this 'devname' field here and others until sclk_mmc3 .... > + .parent = &clk_dout_mmc0.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 0), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc1 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.1", > + .parent = &clk_dout_mmc1.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 4), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc2 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.2", > + .parent = &clk_dout_mmc2.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 8), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, > +}; > + > +static struct clksrc_clk clk_sclk_mmc3 = { > + .clk = { > + .name = "sclk_mmc", > + .devname = "s3c-sdhci.3", > + .parent = &clk_dout_mmc3.clk, > + .enable = exynos4_clksrc_mask_fsys_ctrl, > + .ctrlbit = (1 << 12), > + }, > + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, > +}; > + > /* Clock initialization code */ > static struct clksrc_clk *sysclks[] = { > &clk_mout_apll, > @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { > &clk_sclk_uart1, > &clk_sclk_uart2, > &clk_sclk_uart3, > + &clk_sclk_mmc0, > + &clk_sclk_mmc1, > + &clk_sclk_mmc2, > + &clk_sclk_mmc3, ..then drop the above 4 lines... > }; > > static struct clk_lookup exynos4_clk_lookup[] = { > @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { > CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), > CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), > CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), > + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), > + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), > + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), > + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), ..and add something like: + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), ? Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? Does it all work on exynos ? I would expect the device name to be same across all the clock definitions, otherwise clk_get(dev, ..) will fail. > }; > Regards -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-12 10:24 ` Sylwester Nawrocki @ 2011-10-12 12:36 ` Rajeshwari Birje -1 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Birje @ 2011-10-12 12:36 UTC (permalink / raw) To: Sylwester Nawrocki Cc: Rajeshwari Shinde, linux-mmc, linux-samsung-soc, cjb, kgene.kim, linux-arm-kernel Hi Sylwester, On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > Hi Rajeshwari, > > On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >> Add support for lookup of sdhci-s3c controller clocks using generic names >> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >> >> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >> --- >> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >> 6 files changed, 359 insertions(+), 235 deletions(-) >> >> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >> index 9f50e33..c6383b9 100644 >> --- a/arch/arm/mach-exynos4/clock.c >> +++ b/arch/arm/mach-exynos4/clock.c >> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, >> }, { >> .clk = { >> - .name = "sclk_mmc", >> - .devname = "s3c-sdhci.0", >> - .parent = &clk_dout_mmc0.clk, >> - .enable = exynos4_clksrc_mask_fsys_ctrl, >> - .ctrlbit = (1 << 0), >> - }, >> - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >> - }, { >> - .clk = { >> - .name = "sclk_mmc", >> - .devname = "s3c-sdhci.1", >> - .parent = &clk_dout_mmc1.clk, >> - .enable = exynos4_clksrc_mask_fsys_ctrl, >> - .ctrlbit = (1 << 4), >> - }, >> - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >> - }, { >> - .clk = { >> - .name = "sclk_mmc", >> - .devname = "s3c-sdhci.2", >> - .parent = &clk_dout_mmc2.clk, >> - .enable = exynos4_clksrc_mask_fsys_ctrl, >> - .ctrlbit = (1 << 8), >> - }, >> - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >> - }, { >> - .clk = { >> - .name = "sclk_mmc", >> - .devname = "s3c-sdhci.3", >> - .parent = &clk_dout_mmc3.clk, >> - .enable = exynos4_clksrc_mask_fsys_ctrl, >> - .ctrlbit = (1 << 12), >> - }, >> - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >> - }, { >> - .clk = { >> .name = "sclk_dwmmc", >> .parent = &clk_dout_mmc4.clk, >> .enable = exynos4_clksrc_mask_fsys_ctrl, >> @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { >> .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, >> }; >> >> +static struct clksrc_clk clk_sclk_mmc0 = { >> + .clk = { >> + .name = "sclk_mmc", >> + .devname = "s3c-sdhci.0", > > Would it make sense to drop this 'devname' field here and others > until sclk_mmc3 .... *** The devname here distinguishes these clocks. So it should be okay to have a devname for these clocks. > >> + .parent = &clk_dout_mmc0.clk, >> + .enable = exynos4_clksrc_mask_fsys_ctrl, >> + .ctrlbit = (1 << 0), >> + }, >> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc1 = { >> + .clk = { >> + .name = "sclk_mmc", >> + .devname = "s3c-sdhci.1", > >> + .parent = &clk_dout_mmc1.clk, >> + .enable = exynos4_clksrc_mask_fsys_ctrl, >> + .ctrlbit = (1 << 4), >> + }, >> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc2 = { >> + .clk = { >> + .name = "sclk_mmc", >> + .devname = "s3c-sdhci.2", > >> + .parent = &clk_dout_mmc2.clk, >> + .enable = exynos4_clksrc_mask_fsys_ctrl, >> + .ctrlbit = (1 << 8), >> + }, >> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc3 = { >> + .clk = { >> + .name = "sclk_mmc", >> + .devname = "s3c-sdhci.3", > >> + .parent = &clk_dout_mmc3.clk, >> + .enable = exynos4_clksrc_mask_fsys_ctrl, >> + .ctrlbit = (1 << 12), >> + }, >> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >> +}; >> + >> /* Clock initialization code */ >> static struct clksrc_clk *sysclks[] = { >> &clk_mout_apll, >> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >> &clk_sclk_uart1, >> &clk_sclk_uart2, >> &clk_sclk_uart3, >> + &clk_sclk_mmc0, >> + &clk_sclk_mmc1, >> + &clk_sclk_mmc2, >> + &clk_sclk_mmc3, > > ..then drop the above 4 lines... **** The registration for these clocks are important. The s3c_register_clksrc() function sets the .ops of this clock and also its parent. So the registration cannot be dropped. > >> }; >> >> static struct clk_lookup exynos4_clk_lookup[] = { >> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >> CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >> CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >> CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >> + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >> + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >> + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >> + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), > > ..and add something like: > > + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), > + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), > + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), > + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), > > ? **** The driver uses a common name for the possible bus clock sources, that is “mmc_busclk”. This keeps the clock lookup code in the driver simple. Also, there could be SoC’s which do no use sclk_mmc as the bus clock name as per the user manual > > Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 > clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? > > Does it all work on exynos ? I would expect the device name to be same > across all the clock definitions, otherwise clk_get(dev, ..) will fail. **** There was a patch submitted to rename the device name of sdhci for Exynos to exynos4-sdhci. I will remove this change from this patch and let that patch handle this change. > >> }; >> > > Regards > -- > Sylwester Nawrocki > Samsung Poland R&D Center > -- > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Regards, Rajeshwari Shinde. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-12 12:36 ` Rajeshwari Birje 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Birje @ 2011-10-12 12:36 UTC (permalink / raw) To: linux-arm-kernel Hi Sylwester, On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > Hi Rajeshwari, > > On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >> Add support for lookup of sdhci-s3c controller clocks using generic names >> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >> >> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >> --- >> ?arch/arm/mach-exynos4/clock.c ? ? ? ? | ? 88 ++++++++++------- >> ?arch/arm/mach-s3c2416/clock.c ? ? ? ? | ? 68 +++++++------ >> ?arch/arm/mach-s3c64xx/clock.c ? ? ? ? | ?126 +++++++++++++++---------- >> ?arch/arm/mach-s5pc100/clock.c ? ? ? ? | ?130 ++++++++++++++++---------- >> ?arch/arm/mach-s5pv210/clock.c ? ? ? ? | ?167 ++++++++++++++++++++------------- >> ?arch/arm/plat-s3c24xx/s3c2443-clock.c | ? 15 ++- >> ?6 files changed, 359 insertions(+), 235 deletions(-) >> >> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >> index 9f50e33..c6383b9 100644 >> --- a/arch/arm/mach-exynos4/clock.c >> +++ b/arch/arm/mach-exynos4/clock.c >> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >> ? ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, >> ? ? ? }, { >> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= { >> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.0", >> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc0.clk, >> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0), >> - ? ? ? ? ? ? }, >> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >> - ? ? }, { >> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= { >> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.1", >> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc1.clk, >> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4), >> - ? ? ? ? ? ? }, >> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >> - ? ? }, { >> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= { >> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.2", >> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc2.clk, >> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8), >> - ? ? ? ? ? ? }, >> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >> - ? ? }, { >> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= { >> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.3", >> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc3.clk, >> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12), >> - ? ? ? ? ? ? }, >> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >> - ? ? }, { >> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= { >> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_dwmmc", >> ? ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc4.clk, >> ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = { >> ? ? ? .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, >> ?}; >> >> +static struct clksrc_clk clk_sclk_mmc0 = { >> + ? ? .clk ? ? ? ? ? ?= { >> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.0", > > Would it make sense to drop this 'devname' field here and others > until sclk_mmc3 .... *** The devname here distinguishes these clocks. So it should be okay to have a devname for these clocks. > >> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc0.clk, >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0), >> + ? ? }, >> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc1 = { >> + ? ? .clk ? ? ? ? ? ?= { >> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.1", > >> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc1.clk, >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4), >> + ? ? }, >> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc2 = { >> + ? ? .clk ? ? ? ? ? ?= { >> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.2", > >> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc2.clk, >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8), >> + ? ? }, >> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >> +}; >> + >> +static struct clksrc_clk clk_sclk_mmc3 = { >> + ? ? .clk ? ? ? ? ? ?= { >> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.3", > >> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc3.clk, >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12), >> + ? ? }, >> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >> +}; >> + >> ?/* Clock initialization code */ >> ?static struct clksrc_clk *sysclks[] = { >> ? ? ? &clk_mout_apll, >> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >> ? ? ? &clk_sclk_uart1, >> ? ? ? &clk_sclk_uart2, >> ? ? ? &clk_sclk_uart3, >> + ? ? &clk_sclk_mmc0, >> + ? ? &clk_sclk_mmc1, >> + ? ? &clk_sclk_mmc2, >> + ? ? &clk_sclk_mmc3, > > ..then drop the above 4 lines... **** The registration for these clocks are important. The s3c_register_clksrc() function sets the .ops of this clock and also its parent. So the registration cannot be dropped. > >> ?}; >> >> ?static struct clk_lookup exynos4_clk_lookup[] = { >> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >> ? ? ? CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >> ? ? ? CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >> ? ? ? CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >> + ? ? CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >> + ? ? CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >> + ? ? CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >> + ? ? CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), > > ..and add something like: > > ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), > ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), > ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), > ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), > > ? **** The driver uses a common name for the possible bus clock sources, that is ?mmc_busclk?. This keeps the clock lookup code in the driver simple. Also, there could be SoC?s which do no use sclk_mmc as the bus clock name as per the user manual > > Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 > clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? > > Does it all work on exynos ? I would expect the device name to be same > across all the clock definitions, otherwise clk_get(dev, ..) will fail. **** There was a patch submitted to rename the device name of sdhci for Exynos to exynos4-sdhci. I will remove this change from this patch and let that patch handle this change. > >> ?}; >> > > Regards > -- > Sylwester Nawrocki > Samsung Poland R&D Center > -- > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at ?http://vger.kernel.org/majordomo-info.html > Regards, Rajeshwari Shinde. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-12 12:36 ` Rajeshwari Birje @ 2011-10-12 16:19 ` Sylwester Nawrocki -1 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-12 16:19 UTC (permalink / raw) To: Rajeshwari Birje Cc: Rajeshwari Shinde, linux-mmc, linux-samsung-soc, cjb, kgene.kim, linux-arm-kernel On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: > On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> Hi Rajeshwari, >> >> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>> Add support for lookup of sdhci-s3c controller clocks using generic names >>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>> >>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>> --- >>> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >>> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >>> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >>> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >>> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >>> 6 files changed, 359 insertions(+), 235 deletions(-) >>> >>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>> index 9f50e33..c6383b9 100644 >>> --- a/arch/arm/mach-exynos4/clock.c >>> +++ b/arch/arm/mach-exynos4/clock.c >>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, ... >>> +static struct clksrc_clk clk_sclk_mmc0 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.0", >> >> Would it make sense to drop this 'devname' field here and others >> until sclk_mmc3 .... > > *** The devname here distinguishes these clocks. So it should be okay > to have a devname for these clocks. I'm not sure what's Mr Kukjin's opinion on that, but I personally would really like to see all the devname fields disappear from samsung clk data structures. Possibly if all involved people would keep that in mind we could achieve this over time. > >> >>> + .parent = &clk_dout_mmc0.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 0), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc1 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.1", >> >>> + .parent = &clk_dout_mmc1.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 4), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc2 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.2", >> >>> + .parent = &clk_dout_mmc2.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 8), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc3 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.3", >> >>> + .parent = &clk_dout_mmc3.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 12), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >>> +}; >>> + >>> /* Clock initialization code */ >>> static struct clksrc_clk *sysclks[] = { >>> &clk_mout_apll, >>> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >>> &clk_sclk_uart1, >>> &clk_sclk_uart2, >>> &clk_sclk_uart3, >>> + &clk_sclk_mmc0, >>> + &clk_sclk_mmc1, >>> + &clk_sclk_mmc2, >>> + &clk_sclk_mmc3, >> >> ..then drop the above 4 lines... > > **** The registration for these clocks are important. The > s3c_register_clksrc() function sets the .ops of this clock and also > its parent. So the registration cannot be dropped. OK. > >> >>> }; >>> >>> static struct clk_lookup exynos4_clk_lookup[] = { >>> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >>> CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >>> CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >>> CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >>> + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >>> + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >>> + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >>> + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), >> >> ..and add something like: >> >> + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), >> + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), >> + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), >> + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), >> >> ? > > **** The driver uses a common name for the possible bus clock sources, > that is “mmc_busclk”. This keeps the clock lookup code in the driver > simple. Also, there could be SoC’s which do no use sclk_mmc as the bus > clock name as per the user manual OK, I was aware of that. I didn't mean removing the "mmc_busclk.2" entries, just adding another 4, which are created anyway by s3c_register_clksrc() function. But for now I think the patch is OK. > > >> >> Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 >> clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? >> >> Does it all work on exynos ? I would expect the device name to be same >> across all the clock definitions, otherwise clk_get(dev, ..) will fail. > > **** There was a patch submitted to rename the device name of sdhci > for Exynos to exynos4-sdhci. I will remove this change from this patch > and let that patch handle this change. I wouldn't do that. IMHO it's better to keep this patch as is, to make the final diff size lower. Perhaps it's even worth to consider doing the clock rename altogether in this patch. But it's of course up to you. Regards, -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-12 16:19 ` Sylwester Nawrocki 0 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-12 16:19 UTC (permalink / raw) To: linux-arm-kernel On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: > On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> Hi Rajeshwari, >> >> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>> Add support for lookup of sdhci-s3c controller clocks using generic names >>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>> >>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>> --- >>> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >>> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >>> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >>> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >>> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >>> 6 files changed, 359 insertions(+), 235 deletions(-) >>> >>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>> index 9f50e33..c6383b9 100644 >>> --- a/arch/arm/mach-exynos4/clock.c >>> +++ b/arch/arm/mach-exynos4/clock.c >>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, ... >>> +static struct clksrc_clk clk_sclk_mmc0 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.0", >> >> Would it make sense to drop this 'devname' field here and others >> until sclk_mmc3 .... > > *** The devname here distinguishes these clocks. So it should be okay > to have a devname for these clocks. I'm not sure what's Mr Kukjin's opinion on that, but I personally would really like to see all the devname fields disappear from samsung clk data structures. Possibly if all involved people would keep that in mind we could achieve this over time. > >> >>> + .parent = &clk_dout_mmc0.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 0), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc1 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.1", >> >>> + .parent = &clk_dout_mmc1.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 4), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc2 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.2", >> >>> + .parent = &clk_dout_mmc2.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 8), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >>> +}; >>> + >>> +static struct clksrc_clk clk_sclk_mmc3 = { >>> + .clk = { >>> + .name = "sclk_mmc", >>> + .devname = "s3c-sdhci.3", >> >>> + .parent = &clk_dout_mmc3.clk, >>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>> + .ctrlbit = (1 << 12), >>> + }, >>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >>> +}; >>> + >>> /* Clock initialization code */ >>> static struct clksrc_clk *sysclks[] = { >>> &clk_mout_apll, >>> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >>> &clk_sclk_uart1, >>> &clk_sclk_uart2, >>> &clk_sclk_uart3, >>> + &clk_sclk_mmc0, >>> + &clk_sclk_mmc1, >>> + &clk_sclk_mmc2, >>> + &clk_sclk_mmc3, >> >> ..then drop the above 4 lines... > > **** The registration for these clocks are important. The > s3c_register_clksrc() function sets the .ops of this clock and also > its parent. So the registration cannot be dropped. OK. > >> >>> }; >>> >>> static struct clk_lookup exynos4_clk_lookup[] = { >>> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >>> CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >>> CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >>> CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >>> + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >>> + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >>> + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >>> + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), >> >> ..and add something like: >> >> + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), >> + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), >> + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), >> + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), >> >> ? > > **** The driver uses a common name for the possible bus clock sources, > that is ?mmc_busclk?. This keeps the clock lookup code in the driver > simple. Also, there could be SoC?s which do no use sclk_mmc as the bus > clock name as per the user manual OK, I was aware of that. I didn't mean removing the "mmc_busclk.2" entries, just adding another 4, which are created anyway by s3c_register_clksrc() function. But for now I think the patch is OK. > > >> >> Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 >> clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? >> >> Does it all work on exynos ? I would expect the device name to be same >> across all the clock definitions, otherwise clk_get(dev, ..) will fail. > > **** There was a patch submitted to rename the device name of sdhci > for Exynos to exynos4-sdhci. I will remove this change from this patch > and let that patch handle this change. I wouldn't do that. IMHO it's better to keep this patch as is, to make the final diff size lower. Perhaps it's even worth to consider doing the clock rename altogether in this patch. But it's of course up to you. Regards, -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-12 16:19 ` Sylwester Nawrocki @ 2011-10-13 7:16 ` Rajeshwari Birje -1 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Birje @ 2011-10-13 7:16 UTC (permalink / raw) To: Sylwester Nawrocki Cc: Rajeshwari Shinde, linux-mmc, linux-samsung-soc, cjb, kgene.kim, linux-arm-kernel Hi Sylwester, On Wed, Oct 12, 2011 at 9:49 PM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: >> On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki >> <s.nawrocki@samsung.com> wrote: >>> Hi Rajeshwari, >>> >>> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>>> Add support for lookup of sdhci-s3c controller clocks using generic names >>>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>>> >>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>>> --- >>>> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >>>> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >>>> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >>>> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >>>> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >>>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >>>> 6 files changed, 359 insertions(+), 235 deletions(-) >>>> >>>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>>> index 9f50e33..c6383b9 100644 >>>> --- a/arch/arm/mach-exynos4/clock.c >>>> +++ b/arch/arm/mach-exynos4/clock.c >>>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>>> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, > ... >>>> +static struct clksrc_clk clk_sclk_mmc0 = { >>>> + .clk = { >>>> + .name = "sclk_mmc", >>>> + .devname = "s3c-sdhci.0", >>> >>> Would it make sense to drop this 'devname' field here and others >>> until sclk_mmc3 .... >> >> *** The devname here distinguishes these clocks. So it should be okay >> to have a devname for these clocks. > > I'm not sure what's Mr Kukjin's opinion on that, but I personally would really > like to see all the devname fields disappear from samsung clk data structures. > Possibly if all involved people would keep that in mind we could achieve this > over time. **** Devname field is still required for clocks like hsmmc for driver to work fine. Hence it would be tough to remove the devname completely. > >> >>> >>>> + .parent = &clk_dout_mmc0.clk, >>>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>>> + .ctrlbit = (1 << 0), >>>> + }, >>>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc1 = { >>>> + .clk = { >>>> + .name = "sclk_mmc", >>>> + .devname = "s3c-sdhci.1", >>> >>>> + .parent = &clk_dout_mmc1.clk, >>>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>>> + .ctrlbit = (1 << 4), >>>> + }, >>>> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc2 = { >>>> + .clk = { >>>> + .name = "sclk_mmc", >>>> + .devname = "s3c-sdhci.2", >>> >>>> + .parent = &clk_dout_mmc2.clk, >>>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>>> + .ctrlbit = (1 << 8), >>>> + }, >>>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc3 = { >>>> + .clk = { >>>> + .name = "sclk_mmc", >>>> + .devname = "s3c-sdhci.3", >>> >>>> + .parent = &clk_dout_mmc3.clk, >>>> + .enable = exynos4_clksrc_mask_fsys_ctrl, >>>> + .ctrlbit = (1 << 12), >>>> + }, >>>> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >>>> +}; >>>> + >>>> /* Clock initialization code */ >>>> static struct clksrc_clk *sysclks[] = { >>>> &clk_mout_apll, >>>> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >>>> &clk_sclk_uart1, >>>> &clk_sclk_uart2, >>>> &clk_sclk_uart3, >>>> + &clk_sclk_mmc0, >>>> + &clk_sclk_mmc1, >>>> + &clk_sclk_mmc2, >>>> + &clk_sclk_mmc3, >>> >>> ..then drop the above 4 lines... >> >> **** The registration for these clocks are important. The >> s3c_register_clksrc() function sets the .ops of this clock and also >> its parent. So the registration cannot be dropped. > > OK. > >> >>> >>>> }; >>>> >>>> static struct clk_lookup exynos4_clk_lookup[] = { >>>> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >>>> CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >>>> CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >>>> CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >>>> + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >>>> + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >>>> + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >>>> + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), >>> >>> ..and add something like: >>> >>> + CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), >>> + CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), >>> + CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), >>> + CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), >>> >>> ? >> >> **** The driver uses a common name for the possible bus clock sources, >> that is “mmc_busclk”. This keeps the clock lookup code in the driver >> simple. Also, there could be SoC’s which do no use sclk_mmc as the bus >> clock name as per the user manual > > OK, I was aware of that. I didn't mean removing the "mmc_busclk.2" entries, > just adding another 4, which are created anyway by s3c_register_clksrc() > function. But for now I think the patch is OK. > >> >> >>> >>> Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 >>> clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? >>> >>> Does it all work on exynos ? I would expect the device name to be same >>> across all the clock definitions, otherwise clk_get(dev, ..) will fail. >> >> **** There was a patch submitted to rename the device name of sdhci >> for Exynos to exynos4-sdhci. I will remove this change from this patch >> and let that patch handle this change. > > I wouldn't do that. IMHO it's better to keep this patch as is, to make the final > diff size lower. **** Will modify the exynos4-sdhci. to s3c-sdhci. and send the updated patch for review. > Perhaps it's even worth to consider doing the clock rename altogether in this patch. > But it's of course up to you. > > > Regards, > -- > Sylwester Nawrocki > Samsung Poland R&D Center > Regards, Rajeshwari Shinde. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-13 7:16 ` Rajeshwari Birje 0 siblings, 0 replies; 22+ messages in thread From: Rajeshwari Birje @ 2011-10-13 7:16 UTC (permalink / raw) To: linux-arm-kernel Hi Sylwester, On Wed, Oct 12, 2011 at 9:49 PM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: >> On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki >> <s.nawrocki@samsung.com> wrote: >>> Hi Rajeshwari, >>> >>> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>>> Add support for lookup of sdhci-s3c controller clocks using generic names >>>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>>> >>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>>> --- >>>> ?arch/arm/mach-exynos4/clock.c ? ? ? ? | ? 88 ++++++++++------- >>>> ?arch/arm/mach-s3c2416/clock.c ? ? ? ? | ? 68 +++++++------ >>>> ?arch/arm/mach-s3c64xx/clock.c ? ? ? ? | ?126 +++++++++++++++---------- >>>> ?arch/arm/mach-s5pc100/clock.c ? ? ? ? | ?130 ++++++++++++++++---------- >>>> ?arch/arm/mach-s5pv210/clock.c ? ? ? ? | ?167 ++++++++++++++++++++------------- >>>> ?arch/arm/plat-s3c24xx/s3c2443-clock.c | ? 15 ++- >>>> ?6 files changed, 359 insertions(+), 235 deletions(-) >>>> >>>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>>> index 9f50e33..c6383b9 100644 >>>> --- a/arch/arm/mach-exynos4/clock.c >>>> +++ b/arch/arm/mach-exynos4/clock.c >>>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>>> ? ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, > ... >>>> +static struct clksrc_clk clk_sclk_mmc0 = { >>>> + ? ? .clk ? ? ? ? ? ?= { >>>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >>>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.0", >>> >>> Would it make sense to drop this 'devname' field here and others >>> until sclk_mmc3 .... >> >> *** The devname here distinguishes these clocks. So it should be okay >> to have a devname for these clocks. > > I'm not sure what's Mr Kukjin's opinion on that, but I personally would really > like to see all the devname fields disappear from samsung clk data structures. > Possibly if all involved people would keep that in mind we could achieve this > over time. **** Devname field is still required for clocks like hsmmc for driver to work fine. Hence it would be tough to remove the devname completely. > >> >>> >>>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc0.clk, >>>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >>>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0), >>>> + ? ? }, >>>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc1 = { >>>> + ? ? .clk ? ? ? ? ? ?= { >>>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >>>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.1", >>> >>>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc1.clk, >>>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >>>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4), >>>> + ? ? }, >>>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc2 = { >>>> + ? ? .clk ? ? ? ? ? ?= { >>>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >>>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.2", >>> >>>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc2.clk, >>>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >>>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8), >>>> + ? ? }, >>>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, >>>> +}; >>>> + >>>> +static struct clksrc_clk clk_sclk_mmc3 = { >>>> + ? ? .clk ? ? ? ? ? ?= { >>>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc", >>>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.3", >>> >>>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc3.clk, >>>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl, >>>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12), >>>> + ? ? }, >>>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, >>>> +}; >>>> + >>>> ?/* Clock initialization code */ >>>> ?static struct clksrc_clk *sysclks[] = { >>>> ? ? ? &clk_mout_apll, >>>> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = { >>>> ? ? ? &clk_sclk_uart1, >>>> ? ? ? &clk_sclk_uart2, >>>> ? ? ? &clk_sclk_uart3, >>>> + ? ? &clk_sclk_mmc0, >>>> + ? ? &clk_sclk_mmc1, >>>> + ? ? &clk_sclk_mmc2, >>>> + ? ? &clk_sclk_mmc3, >>> >>> ..then drop the above 4 lines... >> >> **** The registration for these clocks are important. The >> s3c_register_clksrc() function sets the .ops of this clock and also >> its parent. So the registration cannot be dropped. > > OK. > >> >>> >>>> ?}; >>>> >>>> ?static struct clk_lookup exynos4_clk_lookup[] = { >>>> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { >>>> ? ? ? CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), >>>> ? ? ? CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), >>>> ? ? ? CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), >>>> + ? ? CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), >>>> + ? ? CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), >>>> + ? ? CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), >>>> + ? ? CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), >>> >>> ..and add something like: >>> >>> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk), >>> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk), >>> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk), >>> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk), >>> >>> ? >> >> **** The driver uses a common name for the possible bus clock sources, >> that is ?mmc_busclk?. This keeps the clock lookup code in the driver >> simple. Also, there could be SoC?s which do no use sclk_mmc as the bus >> clock name as per the user manual > > OK, I was aware of that. I didn't mean removing the "mmc_busclk.2" entries, > just adding another 4, which are created anyway by s3c_register_clksrc() > function. But for now I think the patch is OK. > >> >> >>> >>> Also I'm wondering why we're using different device names for clk_sclk_mmc0..3 >>> clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ? >>> >>> Does it all work on exynos ? I would expect the device name to be same >>> across all the clock definitions, otherwise clk_get(dev, ..) will fail. >> >> **** There was a patch submitted to rename the device name of sdhci >> for Exynos to exynos4-sdhci. I will remove this change from this patch >> and let that patch handle this change. > > I wouldn't do that. IMHO it's better to keep this patch as is, to make the final > diff size lower. **** Will modify the exynos4-sdhci. to s3c-sdhci. and send the updated patch for review. > Perhaps it's even worth to consider doing the clock rename altogether in this patch. > But it's of course up to you. > > > Regards, > -- > Sylwester Nawrocki > Samsung Poland R&D Center > Regards, Rajeshwari Shinde. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-13 7:16 ` Rajeshwari Birje @ 2011-10-13 7:55 ` Sylwester Nawrocki -1 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-13 7:55 UTC (permalink / raw) To: Rajeshwari Shinde Cc: linux-mmc, linux-samsung-soc, cjb, kgene.kim, linux-arm-kernel On 10/13/2011 09:16 AM, Rajeshwari Birje wrote: > On Wed, Oct 12, 2011 at 9:49 PM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: >>> On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki >>> <s.nawrocki@samsung.com> wrote: >>>> Hi Rajeshwari, >>>> >>>> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>>>> Add support for lookup of sdhci-s3c controller clocks using generic names >>>>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>>>> >>>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>>>> --- >>>>> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >>>>> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >>>>> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >>>>> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >>>>> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >>>>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >>>>> 6 files changed, 359 insertions(+), 235 deletions(-) >>>>> >>>>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>>>> index 9f50e33..c6383b9 100644 >>>>> --- a/arch/arm/mach-exynos4/clock.c >>>>> +++ b/arch/arm/mach-exynos4/clock.c >>>>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>>>> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, >> ... >>>>> +static struct clksrc_clk clk_sclk_mmc0 = { >>>>> + .clk = { >>>>> + .name = "sclk_mmc", >>>>> + .devname = "s3c-sdhci.0", >>>> >>>> Would it make sense to drop this 'devname' field here and others >>>> until sclk_mmc3 .... >>> >>> *** The devname here distinguishes these clocks. So it should be okay >>> to have a devname for these clocks. >> >> I'm not sure what's Mr Kukjin's opinion on that, but I personally would really >> like to see all the devname fields disappear from samsung clk data structures. >> Possibly if all involved people would keep that in mind we could achieve this >> over time. > > > **** Devname field is still required for clocks like hsmmc for driver > to work fine. Hence it would be tough to remove the devname > completely. Yes, it allowed to add clkdev support with minimal changes required. But let's see what happens when the works on common struct clk for all architectures are more or less completed and we convert Samsung platforms to use it;) Regards, -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-13 7:55 ` Sylwester Nawrocki 0 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-13 7:55 UTC (permalink / raw) To: linux-arm-kernel On 10/13/2011 09:16 AM, Rajeshwari Birje wrote: > On Wed, Oct 12, 2011 at 9:49 PM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> On 10/12/2011 02:36 PM, Rajeshwari Birje wrote: >>> On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki >>> <s.nawrocki@samsung.com> wrote: >>>> Hi Rajeshwari, >>>> >>>> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote: >>>>> Add support for lookup of sdhci-s3c controller clocks using generic names >>>>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. >>>>> >>>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> >>>>> --- >>>>> arch/arm/mach-exynos4/clock.c | 88 ++++++++++------- >>>>> arch/arm/mach-s3c2416/clock.c | 68 +++++++------ >>>>> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++---------- >>>>> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++---------- >>>>> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++------------- >>>>> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++- >>>>> 6 files changed, 359 insertions(+), 235 deletions(-) >>>>> >>>>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c >>>>> index 9f50e33..c6383b9 100644 >>>>> --- a/arch/arm/mach-exynos4/clock.c >>>>> +++ b/arch/arm/mach-exynos4/clock.c >>>>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = { >>>>> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, >> ... >>>>> +static struct clksrc_clk clk_sclk_mmc0 = { >>>>> + .clk = { >>>>> + .name = "sclk_mmc", >>>>> + .devname = "s3c-sdhci.0", >>>> >>>> Would it make sense to drop this 'devname' field here and others >>>> until sclk_mmc3 .... >>> >>> *** The devname here distinguishes these clocks. So it should be okay >>> to have a devname for these clocks. >> >> I'm not sure what's Mr Kukjin's opinion on that, but I personally would really >> like to see all the devname fields disappear from samsung clk data structures. >> Possibly if all involved people would keep that in mind we could achieve this >> over time. > > > **** Devname field is still required for clocks like hsmmc for driver > to work fine. Hence it would be tough to remove the devname > completely. Yes, it allowed to add clkdev support with minimal changes required. But let's see what happens when the works on common struct clk for all architectures are more or less completed and we convert Samsung platforms to use it;) Regards, -- Sylwester Nawrocki Samsung Poland R&D Center ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-13 7:55 ` Sylwester Nawrocki @ 2011-10-13 8:55 ` Russell King - ARM Linux -1 siblings, 0 replies; 22+ messages in thread From: Russell King - ARM Linux @ 2011-10-13 8:55 UTC (permalink / raw) To: Sylwester Nawrocki Cc: linux-samsung-soc, linux-mmc, kgene.kim, Rajeshwari Shinde, cjb, linux-arm-kernel On Thu, Oct 13, 2011 at 09:55:04AM +0200, Sylwester Nawrocki wrote: > Yes, it allowed to add clkdev support with minimal changes required. > > But let's see what happens when the works on common struct clk for all > architectures are more or less completed and we convert Samsung platforms > to use it;) The common struct clk shouldn't have much to do with the clkdev part of it - clkdev just provides a method to associate a struct clk with the drivers request. The common struct clk doesn't change that. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-13 8:55 ` Russell King - ARM Linux 0 siblings, 0 replies; 22+ messages in thread From: Russell King - ARM Linux @ 2011-10-13 8:55 UTC (permalink / raw) To: linux-arm-kernel On Thu, Oct 13, 2011 at 09:55:04AM +0200, Sylwester Nawrocki wrote: > Yes, it allowed to add clkdev support with minimal changes required. > > But let's see what happens when the works on common struct clk for all > architectures are more or less completed and we convert Samsung platforms > to use it;) The common struct clk shouldn't have much to do with the clkdev part of it - clkdev just provides a method to associate a struct clk with the drivers request. The common struct clk doesn't change that. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names 2011-10-13 8:55 ` Russell King - ARM Linux @ 2011-10-13 9:40 ` Sylwester Nawrocki -1 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-13 9:40 UTC (permalink / raw) To: Russell King - ARM Linux Cc: Rajeshwari Shinde, kgene.kim, linux-samsung-soc, linux-mmc, cjb, linux-arm-kernel On 10/13/2011 10:55 AM, Russell King - ARM Linux wrote: > On Thu, Oct 13, 2011 at 09:55:04AM +0200, Sylwester Nawrocki wrote: >> Yes, it allowed to add clkdev support with minimal changes required. >> >> But let's see what happens when the works on common struct clk for all >> architectures are more or less completed and we convert Samsung platforms >> to use it;) > > The common struct clk shouldn't have much to do with the clkdev part of > it - clkdev just provides a method to associate a struct clk with the > drivers request. The common struct clk doesn't change that. Indeed. I was just wondering where we end up with the arch struct clk attribute which is specific to clkdev processes. It could just go into the hardware-specific data, although it doesn't sound like a perfectly right approach. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names @ 2011-10-13 9:40 ` Sylwester Nawrocki 0 siblings, 0 replies; 22+ messages in thread From: Sylwester Nawrocki @ 2011-10-13 9:40 UTC (permalink / raw) To: linux-arm-kernel On 10/13/2011 10:55 AM, Russell King - ARM Linux wrote: > On Thu, Oct 13, 2011 at 09:55:04AM +0200, Sylwester Nawrocki wrote: >> Yes, it allowed to add clkdev support with minimal changes required. >> >> But let's see what happens when the works on common struct clk for all >> architectures are more or less completed and we convert Samsung platforms >> to use it;) > > The common struct clk shouldn't have much to do with the clkdev part of > it - clkdev just provides a method to associate a struct clk with the > drivers request. The common struct clk doesn't change that. Indeed. I was just wondering where we end up with the arch struct clk attribute which is specific to clkdev processes. It could just go into the hardware-specific data, although it doesn't sound like a perfectly right approach. ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2011-10-13 9:40 UTC | newest] Thread overview: 22+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-10-12 9:43 [PATCH V3 0/3] ARM: SAMSUNG: Add support for sdhci clock lookup using generic names Rajeshwari Shinde 2011-10-12 9:43 ` Rajeshwari Shinde 2011-10-12 9:43 ` [PATCH V3 1/3] SDHCI: S3C: Use generic clock names for sdhci bus clock options Rajeshwari Shinde 2011-10-12 9:43 ` Rajeshwari Shinde 2011-10-12 9:43 ` [PATCH V3 2/3] ARM: SAMSUNG: Remove SDHCI bus clocks from platform data Rajeshwari Shinde 2011-10-12 9:43 ` Rajeshwari Shinde 2011-10-12 9:43 ` [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names Rajeshwari Shinde 2011-10-12 9:43 ` Rajeshwari Shinde 2011-10-12 10:24 ` Sylwester Nawrocki 2011-10-12 10:24 ` Sylwester Nawrocki 2011-10-12 12:36 ` Rajeshwari Birje 2011-10-12 12:36 ` Rajeshwari Birje 2011-10-12 16:19 ` Sylwester Nawrocki 2011-10-12 16:19 ` Sylwester Nawrocki 2011-10-13 7:16 ` Rajeshwari Birje 2011-10-13 7:16 ` Rajeshwari Birje 2011-10-13 7:55 ` Sylwester Nawrocki 2011-10-13 7:55 ` Sylwester Nawrocki 2011-10-13 8:55 ` Russell King - ARM Linux 2011-10-13 8:55 ` Russell King - ARM Linux 2011-10-13 9:40 ` Sylwester Nawrocki 2011-10-13 9:40 ` Sylwester Nawrocki
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