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From: Mark Langsdorf <mark.langsdorf@calxeda.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Rob Herring <rob.herring@calxeda.com>,
	"afaerber@suse.de" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register
Date: Wed, 04 Jan 2012 10:32:33 -0600	[thread overview]
Message-ID: <4F047F21.4070304@calxeda.com> (raw)
In-Reply-To: <CAFEAcA9XZtvnwTHfzAdNiKMNyHN1oYewGZNRhqZbFZFifP5PiQ@mail.gmail.com>

On 01/04/2012 08:32 AM, Peter Maydell wrote:
> On 29 December 2011 16:19, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> Add a cp15 config_base_register that currently defaults to 0.
>> After the QOM CPU support is added, the value will be properly
>> set to the periphal base value.
>>
>> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> I need to revoke this Reviewed-by: because...
> 
>> @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>>              * 0x200 << ($rn & 0xfff), when MMU is off.  */
>>             goto bad_reg;
>>         }
>> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
>> +            switch (crm) {
>> +            case 0:
>> +                /* The config_base_address should hold the value of
>> +                 * the peripheral base. ARM should get this from a CPU
>> +                 * object property, but that support isn't available in
>> +                 * December 2011. Default to 0 for now and board models
>> +                 * that care can set it by a private hook */
>> +                if ((op1 == 4) && (op2 == 0)) {
>> +                    return env->cp15.c15_config_base_address;
>> +                }
>> +            }
>> +            goto bad_reg;
>> +        }
>>         return 0;
> 
> this breaks booting on vexpress, which complains
> qemu: fatal: Unimplemented cp15 register read (c15, c0, {0, 1})
> because we're now barfing on all the other c15 registers which we
> used to read as zero.

Fair enough. Can I just resubmit this one patch or do you want
the entire series?

--Mark Langsdorf
Calxeda, Inc.

  reply	other threads:[~2012-01-04 16:32 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-12-29 16:19 [Qemu-devel] [PATCH v5 0/7] various ARM fixes for Calxeda Highbank Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 1/7] arm: add missing scu registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register Mark Langsdorf
2012-01-04 14:32   ` Peter Maydell
2012-01-04 16:32     ` Mark Langsdorf [this message]
2012-01-04 16:47       ` Peter Maydell
2012-01-04 16:53         ` [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers Mark Langsdorf
2012-01-04 17:50           ` Peter Maydell
2012-01-04 18:23             ` Mark Langsdorf
2012-01-04 19:07             ` [Qemu-devel] [PATCH v7] " Mark Langsdorf
2012-01-04 23:50               ` Peter Maydell
2012-01-05  0:14                 ` [Qemu-devel] [PATCH v8] " Mark Langsdorf
2012-01-05  0:22                   ` Peter Maydell
2012-01-05  0:54                     ` Mark Langsdorf
2012-01-05  8:36                       ` Peter Maydell
2012-01-05 13:16                         ` [Qemu-devel] [PATCH v9] " Mark Langsdorf
2012-01-05 15:33                           ` Peter Maydell
2012-01-05 15:34                             ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device Mark Langsdorf
2012-01-04 13:29   ` Peter Maydell
2012-06-07 13:45   ` Andreas Färber
2012-06-07 14:21     ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 6/7] Add xgmac ethernet model Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 7/7] arm: make the number of GIC interrupts configurable Mark Langsdorf

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