From: Mark Langsdorf <mark.langsdorf@calxeda.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"afaerber@suse.de" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH v8] arm: add dummy v7 cp15 registers
Date: Wed, 04 Jan 2012 18:54:21 -0600 [thread overview]
Message-ID: <4F04F4BD.2080809@calxeda.com> (raw)
In-Reply-To: <CAFEAcA_A8wWcbg5HvsQt=9hJhvwq5x6pHbMMOHesK=9Lu7r3Jw@mail.gmail.com>
On 01/04/2012 06:22 PM, Peter Maydell wrote:
> On 5 January 2012 00:14, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> Add dummy register support for the cp15, CRn=c15 registers and
>> for c1 SCR.
>
> Can you drop the SCR code, please? This needs to be done properly
> as part of trustzone support, which is a different and rather larger
> kettle of fish.
I found out that the Highbank SoC model depends on the scr code
through four days of tedious debugging. Would it possible to keep
it in as a stub?
I'm still waiting on Kevin Wolf's review of the AHCI changes and
review of the last two patches from this series. I suppose I can
resubmit without scr and delay the SoC model for another while.
--Mark Langsdorf
Calxeda, Inc.
next prev parent reply other threads:[~2012-01-05 0:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-29 16:19 [Qemu-devel] [PATCH v5 0/7] various ARM fixes for Calxeda Highbank Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 1/7] arm: add missing scu registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register Mark Langsdorf
2012-01-04 14:32 ` Peter Maydell
2012-01-04 16:32 ` Mark Langsdorf
2012-01-04 16:47 ` Peter Maydell
2012-01-04 16:53 ` [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers Mark Langsdorf
2012-01-04 17:50 ` Peter Maydell
2012-01-04 18:23 ` Mark Langsdorf
2012-01-04 19:07 ` [Qemu-devel] [PATCH v7] " Mark Langsdorf
2012-01-04 23:50 ` Peter Maydell
2012-01-05 0:14 ` [Qemu-devel] [PATCH v8] " Mark Langsdorf
2012-01-05 0:22 ` Peter Maydell
2012-01-05 0:54 ` Mark Langsdorf [this message]
2012-01-05 8:36 ` Peter Maydell
2012-01-05 13:16 ` [Qemu-devel] [PATCH v9] " Mark Langsdorf
2012-01-05 15:33 ` Peter Maydell
2012-01-05 15:34 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device Mark Langsdorf
2012-01-04 13:29 ` Peter Maydell
2012-06-07 13:45 ` Andreas Färber
2012-06-07 14:21 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 6/7] Add xgmac ethernet model Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 7/7] arm: make the number of GIC interrupts configurable Mark Langsdorf
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