From: "Andreas Färber" <afaerber@suse.de>
To: Mark Langsdorf <mark.langsdorf@calxeda.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org,
rob.herring@calxeda.com, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device
Date: Thu, 07 Jun 2012 15:45:59 +0200 [thread overview]
Message-ID: <4FD0B097.7030106@suse.de> (raw)
In-Reply-To: <1325175596-5807-6-git-send-email-mark.langsdorf@calxeda.com>
Am 29.12.2011 17:19, schrieb Mark Langsdorf:
> From: Rob Herring <rob.herring@calxeda.com>
>
> This is just a dummy device for ARM L2 cache controllers, based on the
> pl310. The cache type parameter can be defined by a property value
> and has a meaningful default.
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
> diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
> new file mode 100644
> index 0000000..ba106f1
> --- /dev/null
> +++ b/hw/arm_l2x0.c
[...]
> +static SysBusDeviceInfo l2x0_info = {
> + .init = l2x0_priv_init,
> + .qdev.name = "l2x0",
> + .qdev.size = sizeof(l2x0_state),
> + .qdev.vmsd = &vmstate_l2x0,
> + .qdev.no_user = 1,
> + .qdev.props = (Property[]) {
> + DEFINE_PROP_UINT32("type", l2x0_state, cache_type, 0x1c100100),
Mark, this "type" property conflicts with a QOM refactoring by Paolo.
Mind if we rename it to "cache-type"? It always has its default value in
upstream.
Thanks,
Andreas
> + DEFINE_PROP_END_OF_LIST(),
> + },
> + .qdev.reset = l2x0_priv_reset,
> +};
> +
> +static void l2x0_register_device(void)
> +{
> + sysbus_register_withprop(&l2x0_info);
> +}
> +
> +device_init(l2x0_register_device)
> +
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2012-06-07 13:46 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-29 16:19 [Qemu-devel] [PATCH v5 0/7] various ARM fixes for Calxeda Highbank Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 1/7] arm: add missing scu registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 2/7] arm: Set frequencies for arm_timer Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register Mark Langsdorf
2012-01-04 14:32 ` Peter Maydell
2012-01-04 16:32 ` Mark Langsdorf
2012-01-04 16:47 ` Peter Maydell
2012-01-04 16:53 ` [Qemu-devel] [PATCH v6 1/1] arm: add dummy v7 cp15 registers Mark Langsdorf
2012-01-04 17:50 ` Peter Maydell
2012-01-04 18:23 ` Mark Langsdorf
2012-01-04 19:07 ` [Qemu-devel] [PATCH v7] " Mark Langsdorf
2012-01-04 23:50 ` Peter Maydell
2012-01-05 0:14 ` [Qemu-devel] [PATCH v8] " Mark Langsdorf
2012-01-05 0:22 ` Peter Maydell
2012-01-05 0:54 ` Mark Langsdorf
2012-01-05 8:36 ` Peter Maydell
2012-01-05 13:16 ` [Qemu-devel] [PATCH v9] " Mark Langsdorf
2012-01-05 15:33 ` Peter Maydell
2012-01-05 15:34 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 5/5] add L2x0/PL310 cache controller device Mark Langsdorf
2012-01-04 13:29 ` Peter Maydell
2012-06-07 13:45 ` Andreas Färber [this message]
2012-06-07 14:21 ` Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 6/7] Add xgmac ethernet model Mark Langsdorf
2011-12-29 16:19 ` [Qemu-devel] [PATCH v5 7/7] arm: make the number of GIC interrupts configurable Mark Langsdorf
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