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From: Aneesh V <aneesh@ti.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Joe Woodward <jw@terrafix.co.uk>,
	"Shilimkar, Santosh" <santosh.shilimkar@ti.com>,
	Russell King - ARM Linux <linux@arm.linux.org.uk>,
	"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
	linux-arm <linux-arm-kernel@lists.infradead.org>
Subject: Re: OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)?
Date: Tue, 17 Jan 2012 19:24:56 +0530	[thread overview]
Message-ID: <4F157DB0.4020202@ti.com> (raw)
In-Reply-To: <20120117134143.GF11475@arm.com>

On Tuesday 17 January 2012 07:11 PM, Catalin Marinas wrote:
> On Tue, Jan 17, 2012 at 12:27:25PM +0000, Aneesh V wrote:
>> Hi Catalin,
>>
>> On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
>>> On Tue, Jan 17, 2012 at 08:54:44AM +0000, Joe Woodward wrote:
>>>> So, is the upshot of this that the kernel isn't going to be in a
>>>> position to enable the L2/outer cache on OMAP3 (due to the need for
>>>> hacky/unmaintainable code)?
>>>>
>>>> Hence the bootloader/uBoot had better leave it enabled...
>>>
>>> It could but the Linux decompressor needs to be aware and either flush
>>> the L2 (more difficult as it doesn't have all the device information) or
>>
>> Cortex-A8 is aware of L2$ and can flush it, isn't it?
>
> As I said to Santosh, I only had the outer cache in mind (e.g. PL310).
> There is no extra configuration needed in the kernel decompressor in
> this case.
>
>>> set the page table attributes to outer non-cacheable (TEX[2:0] = 0b100).
>>
>> If the above is right, this is not needed right?
>
> Correct, since L2 is inner cache.
>
>>> The latter may still not work if there are stale L2 cache lines left by
>>> U-Boot (and that's always possible unless U-Boot also uses outer
>>> non-cacheable memory attributes).
>>
>> U-Boot flushes the caches before disabling it. On top of it, it does an
>> invalidate after the disabling the caches to cover some corner case.
>> So, it's guaranteed that there won't be any stale entries in L2 after
>> U-Boot.
>>
>> So, we could as well leave L2$ enabled (and invalidated) and caches
>> disabled globally after U-Boot.
>
> Yes.
>
>> But I thought enabling L2$ again in kernel is the cleaner solution.
>
> Why? It gets enabled via SCTLR.M together with L1.

Well, technically I don't see any issue. But after all, it's a
bootloader dependency that could be avoided. We could not blame U-Boot
or any other bootloader for disabling L2$ given [1]

[1] http://www.arm.linux.org.uk/developer/booting.php#5

WARNING: multiple messages have this Message-ID (diff)
From: aneesh@ti.com (Aneesh V)
To: linux-arm-kernel@lists.infradead.org
Subject: OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)?
Date: Tue, 17 Jan 2012 19:24:56 +0530	[thread overview]
Message-ID: <4F157DB0.4020202@ti.com> (raw)
In-Reply-To: <20120117134143.GF11475@arm.com>

On Tuesday 17 January 2012 07:11 PM, Catalin Marinas wrote:
> On Tue, Jan 17, 2012 at 12:27:25PM +0000, Aneesh V wrote:
>> Hi Catalin,
>>
>> On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
>>> On Tue, Jan 17, 2012 at 08:54:44AM +0000, Joe Woodward wrote:
>>>> So, is the upshot of this that the kernel isn't going to be in a
>>>> position to enable the L2/outer cache on OMAP3 (due to the need for
>>>> hacky/unmaintainable code)?
>>>>
>>>> Hence the bootloader/uBoot had better leave it enabled...
>>>
>>> It could but the Linux decompressor needs to be aware and either flush
>>> the L2 (more difficult as it doesn't have all the device information) or
>>
>> Cortex-A8 is aware of L2$ and can flush it, isn't it?
>
> As I said to Santosh, I only had the outer cache in mind (e.g. PL310).
> There is no extra configuration needed in the kernel decompressor in
> this case.
>
>>> set the page table attributes to outer non-cacheable (TEX[2:0] = 0b100).
>>
>> If the above is right, this is not needed right?
>
> Correct, since L2 is inner cache.
>
>>> The latter may still not work if there are stale L2 cache lines left by
>>> U-Boot (and that's always possible unless U-Boot also uses outer
>>> non-cacheable memory attributes).
>>
>> U-Boot flushes the caches before disabling it. On top of it, it does an
>> invalidate after the disabling the caches to cover some corner case.
>> So, it's guaranteed that there won't be any stale entries in L2 after
>> U-Boot.
>>
>> So, we could as well leave L2$ enabled (and invalidated) and caches
>> disabled globally after U-Boot.
>
> Yes.
>
>> But I thought enabling L2$ again in kernel is the cleaner solution.
>
> Why? It gets enabled via SCTLR.M together with L1.

Well, technically I don't see any issue. But after all, it's a
bootloader dependency that could be avoided. We could not blame U-Boot
or any other bootloader for disabling L2$ given [1]

[1] http://www.arm.linux.org.uk/developer/booting.php#5

  reply	other threads:[~2012-01-17 13:55 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-01-16 10:03 OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)? Joe Woodward
2012-01-16 10:18 ` Shilimkar, Santosh
2012-01-16 10:18   ` Shilimkar, Santosh
2012-01-16 10:59   ` Russell King - ARM Linux
2012-01-16 10:59     ` Russell King - ARM Linux
2012-01-16 12:43     ` Shilimkar, Santosh
2012-01-16 12:43       ` Shilimkar, Santosh
2012-01-16 13:13       ` Russell King - ARM Linux
2012-01-16 13:13         ` Russell King - ARM Linux
2012-01-16 13:22         ` Shilimkar, Santosh
2012-01-16 13:22           ` Shilimkar, Santosh
2012-01-17  8:54           ` Joe Woodward
2012-01-17 12:11             ` Catalin Marinas
2012-01-17 12:11               ` Catalin Marinas
2012-01-17 12:27               ` Aneesh V
2012-01-17 12:27                 ` Aneesh V
2012-01-17 12:40                 ` Shilimkar, Santosh
2012-01-17 13:39                   ` Catalin Marinas
2012-01-17 13:39                     ` Catalin Marinas
2012-01-17 13:58                     ` Shilimkar, Santosh
2012-01-17 13:58                       ` Shilimkar, Santosh
2012-01-17 16:27                       ` Catalin Marinas
2012-01-17 16:27                         ` Catalin Marinas
2012-01-17 17:27                         ` Shilimkar, Santosh
2012-01-17 17:27                           ` Shilimkar, Santosh
2012-01-17 19:39                           ` Nicolas Pitre
2012-01-17 19:39                             ` Nicolas Pitre
2012-01-17 20:27                             ` Shilimkar, Santosh
2012-01-17 20:27                               ` Shilimkar, Santosh
2012-01-17 20:45                               ` Nicolas Pitre
2012-01-17 20:45                                 ` Nicolas Pitre
2012-01-17 20:57                                 ` Nicolas Pitre
2012-01-17 20:57                                   ` Nicolas Pitre
2012-01-17 20:58                                 ` Shilimkar, Santosh
2012-01-17 20:58                                   ` Shilimkar, Santosh
2012-01-17 21:02                                   ` Nicolas Pitre
2012-01-17 21:02                                     ` Nicolas Pitre
2012-01-18  8:43                                     ` Shilimkar, Santosh
2012-01-18  8:43                                       ` Shilimkar, Santosh
2012-01-17 21:15                               ` Russell King - ARM Linux
2012-01-17 21:15                                 ` Russell King - ARM Linux
2012-01-17 19:47                         ` Russell King - ARM Linux
2012-01-17 19:47                           ` Russell King - ARM Linux
2012-01-17 20:11                           ` Shilimkar, Santosh
2012-01-17 20:11                             ` Shilimkar, Santosh
2012-01-17 20:48                             ` Russell King - ARM Linux
2012-01-17 20:48                               ` Russell King - ARM Linux
2012-01-17 19:43                       ` Russell King - ARM Linux
2012-01-17 19:43                         ` Russell King - ARM Linux
2012-01-20  8:57                       ` Joe Woodward
2012-01-27 11:45                         ` Joe Woodward
2012-01-27 17:30                         ` Catalin Marinas
2012-01-27 17:30                           ` Catalin Marinas
2012-01-31  5:21                           ` Aneesh V
2012-01-31  5:21                             ` Aneesh V
2012-01-31  7:31                             ` Catalin Marinas
2012-01-31  7:31                               ` Catalin Marinas
2012-01-31  7:38                               ` Shilimkar, Santosh
2012-01-31  7:38                                 ` Shilimkar, Santosh
2012-01-31  8:54                                 ` Catalin Marinas
2012-01-31  8:54                                   ` Catalin Marinas
2012-01-31  9:05                                   ` Shilimkar, Santosh
2012-01-31  9:05                                     ` Shilimkar, Santosh
2012-01-31  9:53                                     ` Catalin Marinas
2012-01-31  9:53                                       ` Catalin Marinas
2012-01-31 10:10                                       ` Russell King - ARM Linux
2012-01-31 10:10                                         ` Russell King - ARM Linux
2012-01-31 12:10                                         ` Catalin Marinas
2012-01-31 12:10                                           ` Catalin Marinas
2012-01-31 18:09                                       ` Nicolas Pitre
2012-01-31 18:09                                         ` Nicolas Pitre
2012-02-02 14:32                                         ` Catalin Marinas
2012-02-02 14:32                                           ` Catalin Marinas
2012-02-02 14:49                                           ` Russell King - ARM Linux
2012-02-02 14:49                                             ` Russell King - ARM Linux
2012-02-02 15:10                                             ` Catalin Marinas
2012-02-02 15:10                                               ` Catalin Marinas
2012-01-31  9:56                                     ` Russell King - ARM Linux
2012-01-31  9:56                                       ` Russell King - ARM Linux
2012-01-31 10:51                                       ` Shilimkar, Santosh
2012-01-31 10:51                                         ` Shilimkar, Santosh
2012-01-31 18:27                                         ` Nicolas Pitre
2012-01-31 18:27                                           ` Nicolas Pitre
2012-02-01  7:12                                           ` Shilimkar, Santosh
2012-02-01  7:12                                             ` Shilimkar, Santosh
2012-01-17 14:18                     ` Grazvydas Ignotas
2012-01-17 14:18                       ` Grazvydas Ignotas
2012-01-17 13:41                 ` Catalin Marinas
2012-01-17 13:41                   ` Catalin Marinas
2012-01-17 13:54                   ` Aneesh V [this message]
2012-01-17 13:54                     ` Aneesh V
2012-01-17 14:23                   ` Måns Rullgård
2012-01-17 14:23                     ` Måns Rullgård
2012-01-17 12:01           ` Aneesh V
2012-01-17 12:01             ` Aneesh V

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