From: Leonid Yegoshin <yegoshin@mips.com>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: "Steven J. Hill" <sjhill@mips.com>, <linux-mips@linux-mips.org>,
<ralf@linux-mips.org>
Subject: Re: [PATCH] Add MIPS64R2 core support.
Date: Tue, 10 Apr 2012 12:09:42 -0700 [thread overview]
Message-ID: <4F848576.6040204@mips.com> (raw)
In-Reply-To: <4F841E48.7000104@mvista.com>
On 04/10/2012 04:49 AM, Sergei Shtylyov wrote:
> From: "Steven J. Hill"<sjhill@mips.com>
>
>>
>> +config 64BIT_PHYS_ADDR
>> + bool "Kernel supports 64 bit physical addresses" if EXPERIMENTAL
>> + depends on 64BIT
>
> This option is selected on 32-bit CPUs like Alchemy, which has
> 36-bit physical address. It will cause a warning about unmet
Just verified - selected Alchemy and DB1000 board and got
# CONFIG_64BIT is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_PHYS_ADDR_T_64BIT=y
???
I also want to say that NetLogic Microsystems web site indicates that
some of Alchemy CPU has only 14 bit DDR/SDRAM address, for exam - Au1550
(http://www.netlogicmicro.com/Products/Alchemy/Au1550.asp) but
arch/mips/configs/db1550_defconfig (and pb1550) choses 64BIT_PHYS_ADDR
too. Seems like something wrong here.
- Leonid.
WARNING: multiple messages have this Message-ID (diff)
From: Leonid Yegoshin <yegoshin@mips.com>
To: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: "Steven J. Hill" <sjhill@mips.com>,
linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH] Add MIPS64R2 core support.
Date: Tue, 10 Apr 2012 12:09:42 -0700 [thread overview]
Message-ID: <4F848576.6040204@mips.com> (raw)
Message-ID: <20120410190942.-sHrn8lISUv5H9WFdk5em382FIrOaGdoIcfXqyMrTmY@z> (raw)
In-Reply-To: <4F841E48.7000104@mvista.com>
On 04/10/2012 04:49 AM, Sergei Shtylyov wrote:
> From: "Steven J. Hill"<sjhill@mips.com>
>
>>
>> +config 64BIT_PHYS_ADDR
>> + bool "Kernel supports 64 bit physical addresses" if EXPERIMENTAL
>> + depends on 64BIT
>
> This option is selected on 32-bit CPUs like Alchemy, which has
> 36-bit physical address. It will cause a warning about unmet
Just verified - selected Alchemy and DB1000 board and got
# CONFIG_64BIT is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_PHYS_ADDR_T_64BIT=y
???
I also want to say that NetLogic Microsystems web site indicates that
some of Alchemy CPU has only 14 bit DDR/SDRAM address, for exam - Au1550
(http://www.netlogicmicro.com/Products/Alchemy/Au1550.asp) but
arch/mips/configs/db1550_defconfig (and pb1550) choses 64BIT_PHYS_ADDR
too. Seems like something wrong here.
- Leonid.
next prev parent reply other threads:[~2012-04-10 19:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-09 16:04 [PATCH] Add MIPS64R2 core support Steven J. Hill
2012-04-10 11:49 ` Sergei Shtylyov
2012-04-10 19:09 ` Leonid Yegoshin [this message]
2012-04-10 19:09 ` Leonid Yegoshin
2012-04-10 19:26 ` Sergei Shtylyov
2012-04-10 19:55 ` Leonid Yegoshin
2012-04-10 19:55 ` Leonid Yegoshin
2012-04-11 11:53 ` Sergei Shtylyov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4F848576.6040204@mips.com \
--to=yegoshin@mips.com \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=sjhill@mips.com \
--cc=sshtylyov@mvista.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.