[PATCH 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set

[PATCH 01/14] MIPS: make oprofile use cp0_perfcount_irq if it is set

[John Crispin]

Make the oprofile code use the performance counters irq.

The patch was written by Felix.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/oprofile/op_model_mipsxx.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..86cf234 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -298,6 +298,11 @@ static void reset_counters(void *arg)
 	}
 }
 
+static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
+{
+	return mipsxx_perfcount_handler();
+}
+
 static int __init mipsxx_init(void)
 {
 	int counters;
@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
 	save_perf_irq = perf_irq;
 	perf_irq = mipsxx_perfcount_handler;
 
+	if (cp0_perfcount_irq >= 0)
+		return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
+			IRQF_SHARED, "Perfcounter", save_perf_irq);
+
 	return 0;
 }
 
@@ -381,6 +390,9 @@ static void mipsxx_exit(void)
 {
 	int counters = op_model_mipsxx_ops.num_counters;
 
+	if (cp0_perfcount_irq >= 0)
+		free_irq(cp0_perfcount_irq, save_perf_irq);
+
 	counters = counters_per_cpu_to_total(counters);
 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
 
-- 
1.7.9.1

[PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[John Crispin]

Implement pci_load_OF_ranges on MIPS. Due to lack of test hardware only 32bit bus
width is supported. This function is based on the implementation found on powerpc.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/pci.h |   12 +++++++++
 arch/mips/pci/pci.c         |   57 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fcd4060..fdc47c5 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -17,6 +17,9 @@
  */
 
 #include <linux/ioport.h>
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#endif
 
 /*
  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
@@ -26,6 +29,9 @@
 struct pci_controller {
 	struct pci_controller *next;
 	struct pci_bus *bus;
+#ifdef CONFIG_OF
+	struct device_node *of_node;
+#endif
 
 	struct pci_ops *pci_ops;
 	struct resource *mem_resource;
@@ -142,4 +148,10 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 
 extern char * (*pcibios_plat_setup)(char *str);
 
+#ifdef CONFIG_OF
+/* this function parses memory ranges from a device node */
+extern void __devinit pci_load_OF_ranges(struct pci_controller *hose,
+					 struct device_node *node);
+#endif
+
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0514866..e211819 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/of_address.h>
 
 #include <asm/cpu-info.h>
 
@@ -114,8 +115,64 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
 			pci_bus_assign_resources(bus);
 			pci_enable_bridges(bus);
 		}
+#ifdef CONFIG_OF
+		bus->dev.of_node = hose->of_node;
+#endif
+	}
+}
+
+#ifdef CONFIG_OF
+void __devinit pci_load_OF_ranges(struct pci_controller *hose,
+				struct device_node *node)
+{
+	const __be32 *ranges;
+	int rlen;
+	int pna = of_n_addr_cells(node);
+	int np = pna + 5;
+
+	pr_info("PCI host bridge %s ranges:\n", node->full_name);
+	ranges = of_get_property(node, "ranges", &rlen);
+	if (ranges == NULL)
+		return;
+	hose->of_node = node;
+
+	while ((rlen -= np * 4) >= 0) {
+		u32 pci_space;
+		struct resource *res = 0;
+		unsigned long long addr, size;
+
+		pci_space = ranges[0];
+		addr = of_translate_address(node, ranges + 3);
+		size = of_read_number(ranges + pna + 3, 2);
+		ranges += np;
+		switch ((pci_space >> 24) & 0x3) {
+		case 1:		/* PCI IO space */
+			pr_info("  IO 0x%016llx..0x%016llx\n",
+					addr, addr + size - 1);
+			hose->io_map_base =
+				(unsigned long)ioremap(addr, size);
+			res = hose->io_resource;
+			res->flags = IORESOURCE_IO;
+			break;
+		case 2:		/* PCI Memory space */
+		case 3:		/* PCI 64 bits Memory space */
+			pr_info(" MEM 0x%016llx..0x%016llx\n",
+					addr, addr + size - 1);
+			res = hose->mem_resource;
+			res->flags = IORESOURCE_MEM;
+			break;
+		}
+		if (res != NULL) {
+			res->start = addr;
+			res->name = node->full_name;
+			res->end = res->start + size - 1;
+			res->parent = NULL;
+			res->sibling = NULL;
+			res->child = NULL;
+		}
 	}
 }
+#endif
 
 static DEFINE_MUTEX(pci_scan_mutex);
 
-- 
1.7.9.1

[PATCH 03/14] MIPS: Provide pci_address_to_pio.

[John Crispin]

From: Ralf Baechle <ralf@linux-mips.org>

Without I/O ports won't work.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/include/asm/prom.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 7a6e82e..40ed259 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -12,6 +12,9 @@
 #define __ASM_PROM_H
 
 #ifdef CONFIG_OF
+#include <linux/bug.h>
+#include <linux/io.h>
+#include <linux/types.h>
 #include <asm/bootinfo.h>
 
 extern int early_init_dt_scan_memory_arch(unsigned long node,
@@ -21,6 +24,18 @@ extern int reserve_mem_mach(unsigned long addr, unsigned long size);
 extern void free_mem_mach(unsigned long addr, unsigned long size);
 
 extern void device_tree_init(void);
+
+static inline unsigned long pci_address_to_pio(phys_addr_t address)
+{
+	/*
+	 * The ioport address can be directly used by inX() / outX()
+	 */
+	BUG_ON(address > IO_SPACE_LIMIT);
+
+	return (unsigned long) address;
+}
+#define pci_address_to_pio pci_address_to_pio
+
 #else /* CONFIG_OF */
 static inline void device_tree_init(void) { }
 #endif /* CONFIG_OF */
-- 
1.7.9.1

[PATCH 04/14] MIPS: Add helper function to allow platforms to point at a DTB.

[John Crispin]

Add __dt_setup_arch() that can be called to load a builtin DT.
Additionally we add a macro to allow loading a specific symbol
from the __dtb_* section.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/prom.h |   11 +++++++++++
 arch/mips/kernel/prom.c      |   14 ++++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 40ed259..7206d44 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -36,6 +36,17 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address)
 }
 #define pci_address_to_pio pci_address_to_pio
 
+struct boot_param_header;
+
+extern void __dt_setup_arch(struct boot_param_header *bph);
+
+#define dt_setup_arch(sym)						\
+({									\
+	extern struct boot_param_header __dtb_##sym##_begin;		\
+									\
+	__dt_setup_arch(&__dtb_##sym##_begin);				\
+})
+
 #else /* CONFIG_OF */
 static inline void device_tree_init(void) { }
 #endif /* CONFIG_OF */
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 558b539..271ad98 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -95,3 +95,17 @@ void __init device_tree_init(void)
 	/* free the space reserved for the dt blob */
 	free_mem_mach(base, size);
 }
+
+void __init __dt_setup_arch(struct boot_param_header *bph)
+{
+	unsigned long size;
+
+	if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
+		pr_err("DTB has bad magic, ignoring builtin OF DTB\n");
+
+		return;
+	}
+
+	initial_boot_params = bph;
+	size = be32_to_cpu(bph->totalsize);
+}
-- 
1.7.9.1

[PATCH 05/14] MIPS: parse chosen node on boot

[John Crispin]

Call early_init_devtree from inside __dt_setup_arch to allow parsing of the
chosen node.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/kernel/prom.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 271ad98..dc6dedf 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -108,4 +108,6 @@ void __init __dt_setup_arch(struct boot_param_header *bph)
 
 	initial_boot_params = bph;
 	size = be32_to_cpu(bph->totalsize);
+
+	early_init_devtree(initial_boot_params);
 }
-- 
1.7.9.1

[PATCH 06/14] MIPS: add clkdev.h

[John Crispin]

For clock device lookup tables to work on MIPS, we need to provide this
architecture specific header file.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/clkdev.h |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/clkdev.h

diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
new file mode 100644
index 0000000..2624754
--- /dev/null
+++ b/arch/mips/include/asm/clkdev.h
@@ -0,0 +1,25 @@
+/*
+ *  based on arch/arm/include/asm/clkdev.h
+ *
+ *  Copyright (C) 2008 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Helper for the clk API to assist looking up a struct clk.
+ */
+#ifndef __ASM_CLKDEV_H
+#define __ASM_CLKDEV_H
+
+#include <linux/slab.h>
+
+#define __clk_get(clk)	({ 1; })
+#define __clk_put(clk)	do { } while (0)
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+	return kzalloc(size, GFP_KERNEL);
+}
+
+#endif
-- 
1.7.9.1

[PATCH 07/14] MIPS: remove unused prototype kgdb_config

[John Crispin]

Trivial fix that removes an orphaned prototype.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mips-boards/generic.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 46c0856..6e23ceb 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -93,8 +93,4 @@ extern void mips_pcibios_init(void);
 #define mips_pcibios_init() do { } while (0)
 #endif
 
-#ifdef CONFIG_KGDB
-extern void kgdb_config(void);
-#endif
-
 #endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
-- 
1.7.9.1

[PATCH 08/14] MIPS: lantiq: clear all irqs properly on boot

[John Crispin]

Due to a wrongly placed bracket, the irq modules were not properly reset on
boot.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/irq.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index d673731..b6b1c72 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -271,12 +271,13 @@ void __init arch_init_irq(void)
 	if (!ltq_eiu_membase)
 		panic("Failed to remap eiu memory");
 
-	/* make sure all irqs are turned off by default */
-	for (i = 0; i < 5; i++)
+	/* turn off all irqs by default */
+	for (i = 0; i < 5; i++) {
+		/* make sure all irqs are turned off by default */
 		ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
-
-	/* clear all possibly pending interrupts */
-	ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
+		/* clear all possibly pending interrupts */
+		ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
+	}
 
 	mips_cpu_irq_init();
 
-- 
1.7.9.1

[PATCH 09/14] MIPS: lantiq: enable oprofile support on lantiq targets

[John Crispin]

This patch sets the performance counters irq and HAVE_OPROFILE flag for Lantiq
SoCs.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/Kconfig      |    1 +
 arch/mips/lantiq/irq.c |    6 ++++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ce30e2f..948f2a0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -229,6 +229,7 @@ config LANTIQ
 	select SWAP_IO_SPACE
 	select BOOT_RAW
 	select HAVE_CLK
+	select HAVE_OPROFILE
 	select MIPS_MACHINE
 
 config LASAT
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index b6b1c72..bfd4ad1 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -40,6 +40,9 @@
 
 #define MAX_EIU			6
 
+/* the performance counter */
+#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)
+
 /* irqs generated by device attached to the EBU need to be acked in
  * a special manner
  */
@@ -316,6 +319,9 @@ void __init arch_init_irq(void)
 	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 #endif
+
+	/* tell oprofile which irq to use */
+	cp0_perfcount_irq = LTQ_PERF_IRQ;
 }
 
 unsigned int __cpuinit get_c0_compare_int(void)
-- 
1.7.9.1

[PATCH 10/14] MIPS: lantiq: add ipi handlers to make vsmp work

[John Crispin]

Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
on lantiq socs. The code is based on the malta implementation.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/irq.c  |   60 +++++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/lantiq/prom.c |    5 ++++
 2 files changed, 65 insertions(+), 0 deletions(-)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index bfd4ad1..d227be1 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -54,6 +54,14 @@
 #define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
 #define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))
 
+/* our 2 ipi interrupts for VSMP */
+#define MIPS_CPU_IPI_RESCHED_IRQ	0
+#define MIPS_CPU_IPI_CALL_IRQ		1
+
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+int gic_present;
+#endif
+
 static unsigned short ltq_eiu_irq[MAX_EIU] = {
 	LTQ_EIU_IR0,
 	LTQ_EIU_IR1,
@@ -219,6 +227,47 @@ static void ltq_hw5_irqdispatch(void)
 	do_IRQ(MIPS_CPU_TIMER_IRQ);
 }
 
+#ifdef CONFIG_MIPS_MT_SMP
+void __init arch_init_ipiirq(int irq, struct irqaction *action)
+{
+	setup_irq(irq, action);
+	irq_set_handler(irq, handle_percpu_irq);
+}
+
+static void ltq_sw0_irqdispatch(void)
+{
+	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
+}
+
+static void ltq_sw1_irqdispatch(void)
+{
+	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
+}
+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
+{
+	scheduler_ipi();
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
+{
+	smp_call_function_interrupt();
+	return IRQ_HANDLED;
+}
+
+static struct irqaction irq_resched = {
+	.handler	= ipi_resched_interrupt,
+	.flags		= IRQF_PERCPU,
+	.name		= "IPI_resched"
+};
+
+static struct irqaction irq_call = {
+	.handler	= ipi_call_interrupt,
+	.flags		= IRQF_PERCPU,
+	.name		= "IPI_call"
+};
+#endif
+
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -312,6 +361,17 @@ void __init arch_init_irq(void)
 			irq_set_chip_and_handler(i, &ltq_irq_type,
 				handle_level_irq);
 
+#if defined(CONFIG_MIPS_MT_SMP)
+	if (cpu_has_vint) {
+		pr_info("Setting up IPI vectored interrupts\n");
+		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
+		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
+	}
+	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
+		&irq_resched);
+	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
+#endif
+
 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index e34fcfd..664b7b7 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -68,4 +68,9 @@ void __init prom_init(void)
 	soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
 	pr_info("SoC: %s\n", soc_info.sys_type);
 	prom_init_cmdline();
+
+#if defined(CONFIG_MIPS_MT_SMP)
+	if (register_vsmp_smp_ops())
+		panic("failed to register_vsmp_smp_ops()");
+#endif
 }
-- 
1.7.9.1

[PATCH 11/14] MIPS: lantiq: fix early printk

[John Crispin]

The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    6 ++++++
 arch/mips/lantiq/early_printk.c                    |   17 ++++++++---------
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 8a3c6be..8bc9030 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -34,6 +34,12 @@
 #define LTQ_ASC1_BASE_ADDR	0x1E100C00
 #define LTQ_ASC_SIZE		0x400
 
+/*
+ * during early_printk no ioremap is possible
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+
 /* RCU - reset control unit */
 #define LTQ_RCU_BASE_ADDR	0x1F203000
 #define LTQ_RCU_SIZE		0x1000
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
index 972e05f..9b28d09 100644
--- a/arch/mips/lantiq/early_printk.c
+++ b/arch/mips/lantiq/early_printk.c
@@ -6,17 +6,16 @@
  *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  */
 
-#include <linux/init.h>
 #include <linux/cpu.h>
-
-#include <lantiq.h>
 #include <lantiq_soc.h>
 
-/* no ioremap possible at this early stage, lets use KSEG1 instead  */
-#define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
 #define ASC_BUF		1024
-#define LTQ_ASC_FSTAT	((u32 *)(LTQ_ASC_BASE + 0x0048))
-#define LTQ_ASC_TBUF	((u32 *)(LTQ_ASC_BASE + 0x0020))
+#define LTQ_ASC_FSTAT	((u32 *)(LTQ_EARLY_ASC + 0x0048))
+#ifdef __BIG_ENDIAN
+#define LTQ_ASC_TBUF	((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
+#else
+#define LTQ_ASC_TBUF	((u32 *)(LTQ_EARLY_ASC + 0x0020))
+#endif
 #define TXMASK		0x3F00
 #define TXOFFSET	8
 
@@ -27,7 +26,7 @@ void prom_putchar(char c)
 	local_irq_save(flags);
 	do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
 	if (c == '\n')
-		ltq_w32('\r', LTQ_ASC_TBUF);
-	ltq_w32(c, LTQ_ASC_TBUF);
+		ltq_w8('\r', LTQ_ASC_TBUF);
+	ltq_w8(c, LTQ_ASC_TBUF);
 	local_irq_restore(flags);
 }
-- 
1.7.9.1

[PATCH 12/14] MIPS: lantiq: fix cmdline parsing

[John Crispin]

The code tested if the KSEG1 mapped address of argv was != 0. We need to use
CPHYSADDR instead to make the conditional actually work.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/lantiq/prom.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 664b7b7..cd56892 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(void)
 	char **argv = (char **) KSEG1ADDR(fw_arg1);
 	int i;
 
+	arcs_cmdline[0] = '\0';
+
 	for (i = 0; i < argc; i++) {
-		char *p = (char *)  KSEG1ADDR(argv[i]);
+		char *p = (char *) KSEG1ADDR(argv[i]);
 
-		if (p && *p) {
+		if (CPHYSADDR(p) && *p) {
 			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
 			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
 		}
-- 
1.7.9.1

[PATCH 13/14] MIPS: lantiq: add xway soc ids

[John Crispin]

Add the soc ids for additional xway socs. The patch also merges the amazon_se
code with the other socs.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   27 ++++-
 arch/mips/lantiq/prom.h                            |    5 +
 arch/mips/lantiq/xway/Makefile                     |    6 +-
 arch/mips/lantiq/xway/prom-ase.c                   |   39 -------
 arch/mips/lantiq/xway/prom-xway.c                  |   54 ---------
 arch/mips/lantiq/xway/prom.c                       |  115 ++++++++++++++++++++
 6 files changed, 144 insertions(+), 102 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/prom-ase.c
 delete mode 100644 arch/mips/lantiq/xway/prom-xway.c
 create mode 100644 arch/mips/lantiq/xway/prom.c

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 8bc9030..af6c0f0 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -17,17 +17,32 @@
 #define SOC_ID_DANUBE1		0x129
 #define SOC_ID_DANUBE2		0x12B
 #define SOC_ID_TWINPASS		0x12D
-#define SOC_ID_AMAZON_SE	0x152
+#define SOC_ID_AMAZON_SE_1	0x152 /* 50601 */
+#define SOC_ID_AMAZON_SE_2	0x153 /* 50600 */
 #define SOC_ID_ARX188		0x16C
-#define SOC_ID_ARX168		0x16D
+#define SOC_ID_ARX168_1		0x16D
+#define SOC_ID_ARX168_2		0x16E
 #define SOC_ID_ARX182		0x16F
-
-/* SoC Types */
+#define SOC_ID_GRX188		0x170
+#define SOC_ID_GRX168		0x171
+
+#define SOC_ID_VRX288		0x1C0 /* v1.1 */
+#define SOC_ID_VRX282		0x1C1 /* v1.1 */
+#define SOC_ID_VRX268		0x1C2 /* v1.1 */
+#define SOC_ID_GRX268		0x1C8 /* v1.1 */
+#define SOC_ID_GRX288		0x1C9 /* v1.1 */
+#define SOC_ID_VRX288_2		0x00B /* v1.2 */
+#define SOC_ID_VRX268_2		0x00C /* v1.2 */
+#define SOC_ID_GRX288_2		0x00D /* v1.2 */
+#define SOC_ID_GRX282_2		0x00E /* v1.2 */
+
+ /* SoC Types */
 #define SOC_TYPE_DANUBE		0x01
 #define SOC_TYPE_TWINPASS	0x02
 #define SOC_TYPE_AR9		0x03
-#define SOC_TYPE_VR9		0x04
-#define SOC_TYPE_AMAZON_SE	0x05
+#define SOC_TYPE_VR9		0x04 /* v1.1 */
+#define SOC_TYPE_VR9_2		0x05 /* v1.2 */
+#define SOC_TYPE_AMAZON_SE	0x06
 
 /* ASC0/1 - serial port */
 #define LTQ_ASC0_BASE_ADDR	0x1E100400
diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
index b4229d9..90070a5 100644
--- a/arch/mips/lantiq/prom.h
+++ b/arch/mips/lantiq/prom.h
@@ -10,16 +10,21 @@
 #define _LTQ_PROM_H__
 
 #define LTQ_SYS_TYPE_LEN	0x100
+#define LTQ_SYS_REV_LEN         0x10
 
 struct ltq_soc_info {
 	unsigned char *name;
 	unsigned int rev;
+	unsigned char rev_type[LTQ_SYS_REV_LEN];
+	unsigned int srev;
 	unsigned int partnum;
 	unsigned int type;
 	unsigned char sys_type[LTQ_SYS_TYPE_LEN];
+	unsigned char *compatible;
 };
 
 extern void ltq_soc_detect(struct ltq_soc_info *i);
 extern void ltq_soc_setup(void);
+extern void ltq_soc_init(void);
 
 #endif
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index c517f2e..42d5fda 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,7 @@
-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
+obj-y := prom.o pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
 
-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
+obj-$(CONFIG_SOC_XWAY) += clk-xway.o setup-xway.o
+obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o setup-ase.o
 
 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
deleted file mode 100644
index ae4959a..0000000
--- a/arch/mips/lantiq/xway/prom-ase.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-#define SOC_AMAZON_SE	"Amazon_SE"
-
-#define PART_SHIFT	12
-#define PART_MASK	0x0FFFFFFF
-#define REV_SHIFT	28
-#define REV_MASK	0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
-	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
-	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
-	switch (i->partnum) {
-	case SOC_ID_AMAZON_SE:
-		i->name = SOC_AMAZON_SE;
-		i->type = SOC_TYPE_AMAZON_SE;
-		break;
-
-	default:
-		unreachable();
-		break;
-	}
-}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
deleted file mode 100644
index 2228133..0000000
--- a/arch/mips/lantiq/xway/prom-xway.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-#define SOC_DANUBE	"Danube"
-#define SOC_TWINPASS	"Twinpass"
-#define SOC_AR9		"AR9"
-
-#define PART_SHIFT	12
-#define PART_MASK	0x0FFFFFFF
-#define REV_SHIFT	28
-#define REV_MASK	0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
-	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
-	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
-	switch (i->partnum) {
-	case SOC_ID_DANUBE1:
-	case SOC_ID_DANUBE2:
-		i->name = SOC_DANUBE;
-		i->type = SOC_TYPE_DANUBE;
-		break;
-
-	case SOC_ID_TWINPASS:
-		i->name = SOC_TWINPASS;
-		i->type = SOC_TYPE_DANUBE;
-		break;
-
-	case SOC_ID_ARX188:
-	case SOC_ID_ARX168:
-	case SOC_ID_ARX182:
-		i->name = SOC_AR9;
-		i->type = SOC_TYPE_AR9;
-		break;
-
-	default:
-		unreachable();
-		break;
-	}
-}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
new file mode 100644
index 0000000..248429a
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom.c
@@ -0,0 +1,115 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/export.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+
+#define SOC_DANUBE	"Danube"
+#define SOC_TWINPASS	"Twinpass"
+#define SOC_AMAZON_SE	"Amazon_SE"
+#define SOC_AR9		"AR9"
+#define SOC_GR9		"GR9"
+#define SOC_VR9		"VR9"
+
+#define COMP_DANUBE	"lantiq,danube"
+#define COMP_TWINPASS	"lantiq,twinpass"
+#define COMP_AMAZON_SE	"lantiq,ase"
+#define COMP_AR9	"lantiq,ar9"
+#define COMP_GR9	"lantiq,gr9"
+#define COMP_VR9	"lantiq,vr9"
+
+#define PART_SHIFT	12
+#define PART_MASK	0x0FFFFFFF
+#define REV_SHIFT	28
+#define REV_MASK	0xF0000000
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+	sprintf(i->rev_type, "1.%d", i->rev);
+	switch (i->partnum) {
+	case SOC_ID_DANUBE1:
+	case SOC_ID_DANUBE2:
+		i->name = SOC_DANUBE;
+		i->type = SOC_TYPE_DANUBE;
+		i->compatible = COMP_DANUBE;
+		break;
+
+	case SOC_ID_TWINPASS:
+		i->name = SOC_TWINPASS;
+		i->type = SOC_TYPE_DANUBE;
+		i->compatible = COMP_TWINPASS;
+		break;
+
+	case SOC_ID_ARX188:
+	case SOC_ID_ARX168_1:
+	case SOC_ID_ARX168_2:
+	case SOC_ID_ARX182:
+		i->name = SOC_AR9;
+		i->type = SOC_TYPE_AR9;
+		i->compatible = COMP_AR9;
+		break;
+
+	case SOC_ID_GRX188:
+	case SOC_ID_GRX168:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_AR9;
+		i->compatible = COMP_GR9;
+		break;
+
+	case SOC_ID_AMAZON_SE_1:
+	case SOC_ID_AMAZON_SE_2:
+#ifdef CONFIG_PCI
+		panic("ase is only supported for non pci kernels");
+#endif
+		i->name = SOC_AMAZON_SE;
+		i->type = SOC_TYPE_AMAZON_SE;
+		i->compatible = COMP_AMAZON_SE;
+		break;
+
+	case SOC_ID_VRX282:
+	case SOC_ID_VRX268:
+	case SOC_ID_VRX288:
+		i->name = SOC_VR9;
+		i->type = SOC_TYPE_VR9;
+		i->compatible = COMP_VR9;
+		break;
+
+	case SOC_ID_GRX268:
+	case SOC_ID_GRX288:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_VR9;
+		i->compatible = COMP_GR9;
+		break;
+
+	case SOC_ID_VRX268_2:
+	case SOC_ID_VRX288_2:
+		i->name = SOC_VR9;
+		i->type = SOC_TYPE_VR9_2;
+		i->compatible = COMP_VR9;
+		break;
+
+	case SOC_ID_GRX282_2:
+	case SOC_ID_GRX288_2:
+		i->name = SOC_GR9;
+		i->type = SOC_TYPE_VR9_2;
+		i->compatible = COMP_GR9;
+		break;
+
+	default:
+		unreachable();
+		break;
+	}
+}
-- 
1.7.9.1

[PATCH 14/14] MIPS: lantiq: cleanup reset code

[John Crispin]

Add 2 new soc specifc handlers and remove superflous pr_notice calls.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-lantiq/lantiq.h         |    3 +-
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   10 ++++
 arch/mips/lantiq/xway/reset.c                      |   48 +++++++++++++++-----
 3 files changed, 48 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index ce2f029..7a90190 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -48,7 +48,8 @@ extern spinlock_t ebu_lock;
 extern void ltq_disable_irq(struct irq_data *data);
 extern void ltq_mask_and_ack_irq(struct irq_data *data);
 extern void ltq_enable_irq(struct irq_data *data);
-
+/* find out what bootsource we have */
+extern unsigned char ltq_boot_select(void);
 /* find out what caused the last cpu reset */
 extern int ltq_reset_cause(void);
 #define LTQ_RST_CAUSE_WDTRST	0x20
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index af6c0f0..15eb4dc 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -49,6 +49,16 @@
 #define LTQ_ASC1_BASE_ADDR	0x1E100C00
 #define LTQ_ASC_SIZE		0x400
 
+/* BOOT_SEL - find what boot media we have */
+#define BS_EXT_ROM		0x0
+#define BS_FLASH		0x1
+#define BS_MII0			0x2
+#define BS_PCI			0x3
+#define BS_UART1		0x4
+#define BS_SPI			0x5
+#define BS_NAND			0x6
+#define BS_RMII0		0x7
+
 /*
  * during early_printk no ioremap is possible
  * lets use KSEG1 instead
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 8b66bd8..3327211 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -11,19 +11,31 @@
 #include <linux/ioport.h>
 #include <linux/pm.h>
 #include <linux/export.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
 #include <asm/reboot.h>
 
 #include <lantiq_soc.h>
 
+#include "../prom.h"
+
 #define ltq_rcu_w32(x, y)	ltq_w32((x), ltq_rcu_membase + (y))
 #define ltq_rcu_r32(x)		ltq_r32(ltq_rcu_membase + (x))
 
-/* register definitions */
-#define LTQ_RCU_RST		0x0010
-#define LTQ_RCU_RST_ALL		0x40000000
+/* reset request register */
+#define RCU_RST_REQ		0x0010
+/* reset status register */
+#define RCU_RST_STAT		0x0014
 
-#define LTQ_RCU_RST_STAT	0x0014
-#define LTQ_RCU_STAT_SHIFT	26
+/* reboot bit */
+#define RCU_RD_SRST		BIT(30)
+/* reset cause */
+#define RCU_STAT_SHIFT		26
+/* boot selection */
+#define RCU_BOOT_SEL_SHIFT	26
+#define RCU_BOOT_SEL_MASK	0x7
 
 static struct resource ltq_rcu_resource = {
 	.name   = "rcu",
@@ -38,29 +50,41 @@ static void __iomem *ltq_rcu_membase;
 /* This function is used by the watchdog driver */
 int ltq_reset_cause(void)
 {
-	u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
-	return val >> LTQ_RCU_STAT_SHIFT;
+	u32 val = ltq_rcu_r32(RCU_RST_STAT);
+	return val >> RCU_STAT_SHIFT;
 }
 EXPORT_SYMBOL_GPL(ltq_reset_cause);
 
+/* allow platform code to find out what source we booted from */
+unsigned char ltq_boot_select(void)
+{
+	u32 val = ltq_rcu_r32(RCU_RST_STAT);
+	return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
+}
+
+/* reset a io domain for u micro seconds */
+void ltq_reset_once(unsigned int module, ulong u)
+{
+	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
+	udelay(u);
+	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
+}
+
 static void ltq_machine_restart(char *command)
 {
-	pr_notice("System restart\n");
 	local_irq_disable();
-	ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
+	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
 	unreachable();
 }
 
 static void ltq_machine_halt(void)
 {
-	pr_notice("System halted.\n");
 	local_irq_disable();
 	unreachable();
 }
 
 static void ltq_machine_power_off(void)
 {
-	pr_notice("Please turn off the power now.\n");
 	local_irq_disable();
 	unreachable();
 }
@@ -79,7 +103,7 @@ static int __init mips_reboot_setup(void)
 	ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
 				resource_size(&ltq_rcu_resource));
 	if (!ltq_rcu_membase)
-		panic("Failed to remap rcu memory");
+		panic("Failed to remap core memory");
 
 	_machine_restart = ltq_machine_restart;
 	_machine_halt = ltq_machine_halt;
-- 
1.7.9.1

Re: [PATCH 04/14] MIPS: Add helper function to allow platforms to point at a DTB.

[David Daney]

On 04/30/2012 04:32 AM, John Crispin wrote:
> Add __dt_setup_arch() that can be called to load a builtin DT.
> Additionally we add a macro to allow loading a specific symbol
> from the __dtb_* section.
>
> Signed-off-by: Ralf Baechle<ralf@linux-mips.org>
> Signed-off-by: John Crispin<blogic@openwrt.org>
> ---
>   arch/mips/include/asm/prom.h |   11 +++++++++++
>   arch/mips/kernel/prom.c      |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
>
[...]
> +
> +void __init __dt_setup_arch(struct boot_param_header *bph)
> +{
> +	unsigned long size;
> +
> +	if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
> +		pr_err("DTB has bad magic, ignoring builtin OF DTB\n");
> +
> +		return;
> +	}
> +
> +	initial_boot_params = bph;
> +	size = be32_to_cpu(bph->totalsize);

size is unused, you can remove it.

> +}

Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[David Daney]

On 04/30/2012 04:32 AM, John Crispin wrote:
> Implement pci_load_OF_ranges on MIPS. Due to lack of test hardware only 32bit bus
> width is supported. This function is based on the implementation found on powerpc.
>
> Signed-off-by: John Crispin<blogic@openwrt.org>
> ---
>   arch/mips/include/asm/pci.h |   12 +++++++++
>   arch/mips/pci/pci.c         |   57 +++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 69 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
> index fcd4060..fdc47c5 100644
> --- a/arch/mips/include/asm/pci.h
> +++ b/arch/mips/include/asm/pci.h
> @@ -17,6 +17,9 @@
>    */
>
>   #include<linux/ioport.h>
> +#ifdef CONFIG_OF
> +#include<linux/of.h>
> +#endif
>

No need for the #ifdef here.



>   /*
>    * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
> @@ -26,6 +29,9 @@
>   struct pci_controller {
>   	struct pci_controller *next;
>   	struct pci_bus *bus;
> +#ifdef CONFIG_OF
> +	struct device_node *of_node;
> +#endif
>

Probably no #ifdef here either.

>   	struct pci_ops *pci_ops;
>   	struct resource *mem_resource;
> @@ -142,4 +148,10 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
>
>   extern char * (*pcibios_plat_setup)(char *str);
>
> +#ifdef CONFIG_OF
> +/* this function parses memory ranges from a device node */
> +extern void __devinit pci_load_OF_ranges(struct pci_controller *hose,
> +					 struct device_node *node);
> +#endif

Again, no #ifdef.

> +
>   #endif /* _ASM_PCI_H */
> diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
> index 0514866..e211819 100644
> --- a/arch/mips/pci/pci.c
> +++ b/arch/mips/pci/pci.c
> @@ -16,6 +16,7 @@
>   #include<linux/init.h>
>   #include<linux/types.h>
>   #include<linux/pci.h>
> +#include<linux/of_address.h>
>
>   #include<asm/cpu-info.h>
>
> @@ -114,8 +115,64 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
>   			pci_bus_assign_resources(bus);
>   			pci_enable_bridges(bus);
>   		}
> +#ifdef CONFIG_OF
> +		bus->dev.of_node = hose->of_node;
> +#endif

Same here.

> +	}
> +}
> +
> +#ifdef CONFIG_OF
> +void __devinit pci_load_OF_ranges(struct pci_controller *hose,
> +				struct device_node *node)
> +{

s/load_OF/load_of/


> +	const __be32 *ranges;
> +	int rlen;
> +	int pna = of_n_addr_cells(node);
> +	int np = pna + 5;
> +
> +	pr_info("PCI host bridge %s ranges:\n", node->full_name);
> +	ranges = of_get_property(node, "ranges",&rlen);
> +	if (ranges == NULL)
> +		return;
> +	hose->of_node = node;
> +
> +	while ((rlen -= np * 4)>= 0) {
> +		u32 pci_space;
> +		struct resource *res = 0;
> +		unsigned long long addr, size;
> +
> +		pci_space = ranges[0];
> +		addr = of_translate_address(node, ranges + 3);
> +		size = of_read_number(ranges + pna + 3, 2);

All of this should be able to be replaced with of_get_address();

There is a bunch of of/pci related infrastructure.  Can any of it be 
leveraged?


> +		ranges += np;
> +		switch ((pci_space>>  24)&  0x3) {
> +		case 1:		/* PCI IO space */
> +			pr_info("  IO 0x%016llx..0x%016llx\n",
> +					addr, addr + size - 1);
> +			hose->io_map_base =
> +				(unsigned long)ioremap(addr, size);
> +			res = hose->io_resource;
> +			res->flags = IORESOURCE_IO;
> +			break;
> +		case 2:		/* PCI Memory space */
> +		case 3:		/* PCI 64 bits Memory space */
> +			pr_info(" MEM 0x%016llx..0x%016llx\n",
> +					addr, addr + size - 1);
> +			res = hose->mem_resource;
> +			res->flags = IORESOURCE_MEM;
> +			break;
> +		}
> +		if (res != NULL) {
> +			res->start = addr;
> +			res->name = node->full_name;
> +			res->end = res->start + size - 1;
> +			res->parent = NULL;
> +			res->sibling = NULL;
> +			res->child = NULL;
> +		}
>   	}
>   }
> +#endif
>
>   static DEFINE_MUTEX(pci_scan_mutex);
>

Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[John Crispin]

Hi,
>
> No need for the #ifdef here.
>

i will fix this globally in the patch


>> +void __devinit pci_load_OF_ranges(struct pci_controller *hose,
>> +                struct device_node *node)
>> +{
>
> s/load_OF/load_of/

ok, some other arch did _OF_ so i blindly copied it.


>> +    const __be32 *ranges;
>> +    int rlen;
>> +    int pna = of_n_addr_cells(node);
>> +    int np = pna + 5;
>> +
>> +    pr_info("PCI host bridge %s ranges:\n", node->full_name);
>> +    ranges = of_get_property(node, "ranges",&rlen);
>> +    if (ranges == NULL)
>> +        return;
>> +    hose->of_node = node;
>> +
>> +    while ((rlen -= np * 4)>= 0) {
>> +        u32 pci_space;
>> +        struct resource *res = 0;
>> +        unsigned long long addr, size;
>> +
>> +        pci_space = ranges[0];
>> +        addr = of_translate_address(node, ranges + 3);
>> +        size = of_read_number(ranges + pna + 3, 2);
>
> All of this should be able to be replaced with of_get_address();
>
> There is a bunch of of/pci related infrastructure.  Can any of it be
> leveraged?

i look at it when i made the patch 3 months ago. the pci ranges are
mapped very differently to normal reg= <addr len>;  properties. You can
find some info about this at the bottom of this link
http://devicetree.org/Device_Tree_Usage 

Re: [PATCH 04/14] MIPS: Add helper function to allow platforms to point at a DTB.

[Sergei Shtylyov]

Hello.

On 30-04-2012 15:32, John Crispin wrote:

> Add __dt_setup_arch() that can be called to load a builtin DT.
> Additionally we add a macro to allow loading a specific symbol
> from the __dtb_* section.

> Signed-off-by: Ralf Baechle<ralf@linux-mips.org>
> Signed-off-by: John Crispin<blogic@openwrt.org>
> ---
>   arch/mips/include/asm/prom.h |   11 +++++++++++
>   arch/mips/kernel/prom.c      |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)

> diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
> index 558b539..271ad98 100644
> --- a/arch/mips/kernel/prom.c
> +++ b/arch/mips/kernel/prom.c
> @@ -95,3 +95,17 @@ void __init device_tree_init(void)
>   	/* free the space reserved for the dt blob */
>   	free_mem_mach(base, size);
>   }
> +
> +void __init __dt_setup_arch(struct boot_param_header *bph)
> +{
> +	unsigned long size;
> +
> +	if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
> +		pr_err("DTB has bad magic, ignoring builtin OF DTB\n");
> +
> +		return;
> +	}
> +
> +	initial_boot_params = bph;
> +	size = be32_to_cpu(bph->totalsize);

    'size' only assigned, not used.

> +}

WBR, Sergei

Re: [PATCH 08/14] MIPS: lantiq: clear all irqs properly on boot

[Sergei Shtylyov]

Hello.

On 30-04-2012 15:33, John Crispin wrote:

> Due to a wrongly placed bracket,

    I don't see a bracket in old code at all.

> the irq modules were not properly reset on
> boot.

> Signed-off-by: John Crispin<blogic@openwrt.org>
> ---
>   arch/mips/lantiq/irq.c |   11 ++++++-----
>   1 files changed, 6 insertions(+), 5 deletions(-)

> diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
> index d673731..b6b1c72 100644
> --- a/arch/mips/lantiq/irq.c
> +++ b/arch/mips/lantiq/irq.c
> @@ -271,12 +271,13 @@ void __init arch_init_irq(void)
>   	if (!ltq_eiu_membase)
>   		panic("Failed to remap eiu memory");
>
> -	/* make sure all irqs are turned off by default */
> -	for (i = 0; i<  5; i++)
> +	/* turn off all irqs by default */
> +	for (i = 0; i<  5; i++) {
> +		/* make sure all irqs are turned off by default */
>   		ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
> -
> -	/* clear all possibly pending interrupts */
> -	ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
> +		/* clear all possibly pending interrupts */
> +		ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
> +	}
>
>   	mips_cpu_irq_init();

WBR, Sergei

Re: [PATCH 08/14] MIPS: lantiq: clear all irqs properly on boot

[John Crispin]

On 01/05/12 01:01, Sergei Shtylyov wrote:
> Hello.
>
> On 30-04-2012 15:33, John Crispin wrote:
>
>> Due to a wrongly placed bracket,
>
>    I don't see a bracket in old code at all.

Wrongly placed in a different file :-)

Thanks, i will make the message more precise

John

Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[John Crispin]

On 30/04/12 18:55, David Daney wrote:
>>       struct pci_ops *pci_ops;
>>       struct resource *mem_resource;
>> @@ -142,4 +148,10 @@ static inline int pci_get_legacy_ide_irq(struct
>> pci_dev *dev, int channel)
>>
>>   extern char * (*pcibios_plat_setup)(char *str);
>>
>> +#ifdef CONFIG_OF
>> +/* this function parses memory ranges from a device node */
>> +extern void __devinit pci_load_OF_ranges(struct pci_controller *hose,
>> +                     struct device_node *node);
>> +#endif
>
> Again, no #ifdef. 


Hi,

are you sure that we don't want to #ifdef this prototype ? The function
is only available when OF is selected.

Thanks,
John

[PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[John Crispin]

Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit
bus width is supported. This function is based on the implementation found on
powerpc.

Signed-off-by: John Crispin <blogic@openwrt.org>

---
Changes in V2
* remove some #ifdefs
* rename to pci_load_of_ranges

Changes in V3
* set pointers to NULL and not 0

 arch/mips/include/asm/pci.h |    6 ++++
 arch/mips/pci/pci.c         |   55 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fcd4060..90bf3b3 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -17,6 +17,7 @@
  */
 
 #include <linux/ioport.h>
+#include <linux/of.h>
 
 /*
  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
@@ -26,6 +27,7 @@
 struct pci_controller {
 	struct pci_controller *next;
 	struct pci_bus *bus;
+	struct device_node *of_node;
 
 	struct pci_ops *pci_ops;
 	struct resource *mem_resource;
@@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 
 extern char * (*pcibios_plat_setup)(char *str);
 
+/* this function parses memory ranges from a device node */
+extern void __devinit pci_load_of_ranges(struct pci_controller *hose,
+					 struct device_node *node);
+
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0514866..a10c951 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/of_address.h>
 
 #include <asm/cpu-info.h>
 
@@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
 			pci_bus_assign_resources(bus);
 			pci_enable_bridges(bus);
 		}
+		bus->dev.of_node = hose->of_node;
 	}
 }
 
+#ifdef CONFIG_OF
+void __devinit pci_load_of_ranges(struct pci_controller *hose,
+				struct device_node *node)
+{
+	const __be32 *ranges;
+	int rlen;
+	int pna = of_n_addr_cells(node);
+	int np = pna + 5;
+
+	pr_info("PCI host bridge %s ranges:\n", node->full_name);
+	ranges = of_get_property(node, "ranges", &rlen);
+	if (ranges == NULL)
+		return;
+	hose->of_node = node;
+
+	while ((rlen -= np * 4) >= 0) {
+		u32 pci_space;
+		struct resource *res = NULL;
+		unsigned long long addr, size;
+
+		pci_space = ranges[0];
+		addr = of_translate_address(node, ranges + 3);
+		size = of_read_number(ranges + pna + 3, 2);
+		ranges += np;
+		switch ((pci_space >> 24) & 0x3) {
+		case 1:		/* PCI IO space */
+			pr_info("  IO 0x%016llx..0x%016llx\n",
+					addr, addr + size - 1);
+			hose->io_map_base =
+				(unsigned long)ioremap(addr, size);
+			res = hose->io_resource;
+			res->flags = IORESOURCE_IO;
+			break;
+		case 2:		/* PCI Memory space */
+		case 3:		/* PCI 64 bits Memory space */
+			pr_info(" MEM 0x%016llx..0x%016llx\n",
+					addr, addr + size - 1);
+			res = hose->mem_resource;
+			res->flags = IORESOURCE_MEM;
+			break;
+		}
+		if (res != NULL) {
+			res->start = addr;
+			res->name = node->full_name;
+			res->end = res->start + size - 1;
+			res->parent = NULL;
+			res->sibling = NULL;
+			res->child = NULL;
+		}
+	}
+}
+#endif
+
 static DEFINE_MUTEX(pci_scan_mutex);
 
 void __devinit register_pci_controller(struct pci_controller *hose)
-- 
1.7.9.1

Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[Geert Uytterhoeven]

On Thu, May 3, 2012 at 7:42 PM, John Crispin <blogic@openwrt.org> wrote:
> Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit
> bus width is supported. This function is based on the implementation found on
> powerpc.

There's no pci_load_of_ranges() in arch/powerpc/?

> +void __devinit pci_load_of_ranges(struct pci_controller *hose,
> +                               struct device_node *node)
> +{
> +       const __be32 *ranges;
> +       int rlen;
> +       int pna = of_n_addr_cells(node);
> +       int np = pna + 5;
> +
> +       pr_info("PCI host bridge %s ranges:\n", node->full_name);
> +       ranges = of_get_property(node, "ranges", &rlen);
> +       if (ranges == NULL)
> +               return;
> +       hose->of_node = node;
> +
> +       while ((rlen -= np * 4) >= 0) {
> +               u32 pci_space;
> +               struct resource *res = NULL;
> +               unsigned long long addr, size;

You better use u64, as that's what of_translate_address() and
of_read_number() return.

> +
> +               pci_space = ranges[0];

pci_space = be32_to_cpup(&ranges[0])

> +               addr = of_translate_address(node, ranges + 3);
> +               size = of_read_number(ranges + pna + 3, 2);

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/14] MIPS: pci: parse memory ranges from devicetree

[John Crispin]

Hi Geert,


> There's no pci_load_of_ranges() in arch/powerpc/?
>

Sorry, its based on pci_process_bridge_OF_ranges.

I will fold your comments into the patch,

Thanks,
John