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From: Vaibhav Hiremath <hvaibhav@ti.com>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: tony@atomide.com, linux-arm-kernel@lists.infradead.org,
	linux-omap@vger.kernel.org, R Sricharan <r.sricharan@ti.com>
Subject: Re: [PATCH v2 02/14] ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme.
Date: Mon, 9 Jul 2012 14:20:52 +0530	[thread overview]
Message-ID: <4FFA9B6C.7050003@ti.com> (raw)
In-Reply-To: <1341566515-22665-3-git-send-email-santosh.shilimkar@ti.com>



On 7/6/2012 2:51 PM, Santosh Shilimkar wrote:
> From: R Sricharan <r.sricharan@ti.com>
> 
> OMAP socs has a legacy and a highlander version of the
> 32k sync counter IP. The register offsets vary between the
> highlander and the legacy scheme. So use the 'SCHEME'
> bits(30-31) of the revision register to distinguish between


Just for my understanding, can we get further information on SCHEME
bit-fields? What kind of information we have it here.

I may need this info to pass on to design team here.

Thanks,
Vaibhav
> the two versions and choose the CR register offset accordingly.
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/plat-omap/counter_32k.c |   16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
> index 2132c4f..dbf1e03 100644
> --- a/arch/arm/plat-omap/counter_32k.c
> +++ b/arch/arm/plat-omap/counter_32k.c
> @@ -29,7 +29,10 @@
>  #include <plat/clock.h>
>  
>  /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
> -#define OMAP2_32KSYNCNT_CR_OFF		0x10
> +#define OMAP2_32KSYNCNT_REV_OFF		0x0
> +#define OMAP2_32KSYNCNT_REV_SCHEME	(0x3 << 30)
> +#define OMAP2_32KSYNCNT_CR_OFF_LOW	0x10
> +#define OMAP2_32KSYNCNT_CR_OFF_HIGH	0x30
>  
>  /*
>   * 32KHz clocksource ... always available, on pretty most chips except
> @@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
>  	int ret;
>  
>  	/*
> -	 * 32k sync Counter register offset is at 0x10
> +	 * 32k sync Counter IP register offsets vary between the
> +	 * highlander version and the legacy ones.
> +	 * The 'SCHEME' bits(30-31) of the revision register is used
> +	 * to identify the version.
>  	 */
> -	sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
> +	if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
> +						OMAP2_32KSYNCNT_REV_SCHEME)
> +		sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
> +	else
> +		sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
>  
>  	/*
>  	 * 120000 rough estimate from the calculations in
> 


WARNING: multiple messages have this Message-ID (diff)
From: hvaibhav@ti.com (Vaibhav Hiremath)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 02/14] ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme.
Date: Mon, 9 Jul 2012 14:20:52 +0530	[thread overview]
Message-ID: <4FFA9B6C.7050003@ti.com> (raw)
In-Reply-To: <1341566515-22665-3-git-send-email-santosh.shilimkar@ti.com>



On 7/6/2012 2:51 PM, Santosh Shilimkar wrote:
> From: R Sricharan <r.sricharan@ti.com>
> 
> OMAP socs has a legacy and a highlander version of the
> 32k sync counter IP. The register offsets vary between the
> highlander and the legacy scheme. So use the 'SCHEME'
> bits(30-31) of the revision register to distinguish between


Just for my understanding, can we get further information on SCHEME
bit-fields? What kind of information we have it here.

I may need this info to pass on to design team here.

Thanks,
Vaibhav
> the two versions and choose the CR register offset accordingly.
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
>  arch/arm/plat-omap/counter_32k.c |   16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
> index 2132c4f..dbf1e03 100644
> --- a/arch/arm/plat-omap/counter_32k.c
> +++ b/arch/arm/plat-omap/counter_32k.c
> @@ -29,7 +29,10 @@
>  #include <plat/clock.h>
>  
>  /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
> -#define OMAP2_32KSYNCNT_CR_OFF		0x10
> +#define OMAP2_32KSYNCNT_REV_OFF		0x0
> +#define OMAP2_32KSYNCNT_REV_SCHEME	(0x3 << 30)
> +#define OMAP2_32KSYNCNT_CR_OFF_LOW	0x10
> +#define OMAP2_32KSYNCNT_CR_OFF_HIGH	0x30
>  
>  /*
>   * 32KHz clocksource ... always available, on pretty most chips except
> @@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
>  	int ret;
>  
>  	/*
> -	 * 32k sync Counter register offset is at 0x10
> +	 * 32k sync Counter IP register offsets vary between the
> +	 * highlander version and the legacy ones.
> +	 * The 'SCHEME' bits(30-31) of the revision register is used
> +	 * to identify the version.
>  	 */
> -	sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
> +	if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
> +						OMAP2_32KSYNCNT_REV_SCHEME)
> +		sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
> +	else
> +		sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
>  
>  	/*
>  	 * 120000 rough estimate from the calculations in
> 

  reply	other threads:[~2012-07-09  8:51 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-06  9:21 [PATCH v2 00/14] ARM: OMAP5: Add minimal OMAP5 SOC support Santosh Shilimkar
2012-07-06  9:21 ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 01/14] ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 02/14] ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-09  8:50   ` Vaibhav Hiremath [this message]
2012-07-09  8:50     ` Vaibhav Hiremath
2012-07-09 10:42     ` Shilimkar, Santosh
2012-07-09 10:42       ` Shilimkar, Santosh
2012-07-10  6:41       ` Hiremath, Vaibhav
2012-07-10  6:41         ` Hiremath, Vaibhav
2012-07-10  7:12         ` Shilimkar, Santosh
2012-07-10  7:12           ` Shilimkar, Santosh
2012-07-10  7:25           ` Hiremath, Vaibhav
2012-07-10  7:25             ` Hiremath, Vaibhav
2012-07-09 16:47   ` Kevin Hilman
2012-07-09 16:47     ` Kevin Hilman
2012-07-09 23:21     ` Jon Hunter
2012-07-09 23:21       ` Jon Hunter
2012-07-10  5:50       ` Shilimkar, Santosh
2012-07-10  5:50         ` Shilimkar, Santosh
2012-07-09 23:52     ` Jon Hunter
2012-07-09 23:52       ` Jon Hunter
2012-07-06  9:21 ` [PATCH v2 03/14] ARM: OMAP5: id: Add cpu id for ES versions Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-11-02 10:03   ` Roger Quadros
2012-11-02 10:03     ` Roger Quadros
2012-11-06 18:18     ` Tony Lindgren
2012-11-06 18:18       ` Tony Lindgren
2012-07-06  9:21 ` [PATCH v2 04/14] ARM: OMAP5: Add minimal support for OMAP5430 SOC Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-09  8:50   ` Vaibhav Hiremath
2012-07-09  8:50     ` Vaibhav Hiremath
2012-07-09 10:39     ` Shilimkar, Santosh
2012-07-09 10:39       ` Shilimkar, Santosh
2012-07-10  5:57       ` Hiremath, Vaibhav
2012-07-10  5:57         ` Hiremath, Vaibhav
2012-07-10  6:06         ` Shilimkar, Santosh
2012-07-10  6:06           ` Shilimkar, Santosh
2012-07-10  6:11           ` Hiremath, Vaibhav
2012-07-10  6:11             ` Hiremath, Vaibhav
2012-07-09 13:11     ` Tony Lindgren
2012-07-09 13:11       ` Tony Lindgren
2012-07-09 13:25       ` Tony Lindgren
2012-07-09 13:25         ` Tony Lindgren
2012-07-09 13:26         ` Shilimkar, Santosh
2012-07-09 13:26           ` Shilimkar, Santosh
2012-07-09 14:26           ` Shilimkar, Santosh
2012-07-09 14:26             ` Shilimkar, Santosh
2012-07-10  6:25       ` Hiremath, Vaibhav
2012-07-10  6:25         ` Hiremath, Vaibhav
2012-07-10  8:18         ` Tony Lindgren
2012-07-10  8:18           ` Tony Lindgren
2012-07-10  8:30           ` Hiremath, Vaibhav
2012-07-10  8:30             ` Hiremath, Vaibhav
2012-07-10  8:37             ` Tony Lindgren
2012-07-10  8:37               ` Tony Lindgren
2012-08-15 22:26       ` Paul Walmsley
2012-08-15 22:26         ` Paul Walmsley
2012-08-16  8:39         ` Tony Lindgren
2012-08-16  8:39           ` Tony Lindgren
2012-08-16  9:36         ` Hiremath, Vaibhav
2012-08-16  9:36           ` Hiremath, Vaibhav
2012-07-06  9:21 ` [PATCH v2 05/14] ARM: OMAP5: timer: Add clocksource, clockevent support Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 06/14] ARM: OMAP5: gpmc: Update gpmc_init() Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 07/14] ARM: OMAP5: l3: Add l3 error handler support for omap5 Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 08/14] ARM: OMAP5: Add the WakeupGen IP updates Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 09/14] ARM: OMAP5: Add SMP support Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 10/14] ARM: omap2+: board-generic: clean up the irq data from board file Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 11/14] ARM: OMAP5: board-generic: Add device tree support Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 12/14] arm/dts: OMAP5: Add omap5 dts files Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 13/14] ARM: OMAP5: Add the build support Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06  9:21 ` [PATCH v2 14/14] ARM: Kconfig update to support additional GPIOs in OMAP5 Santosh Shilimkar
2012-07-06  9:21   ` Santosh Shilimkar
2012-07-06 12:36 ` [PATCH v2 00/14] ARM: OMAP5: Add minimal OMAP5 SOC support Tony Lindgren
2012-07-06 12:36   ` Tony Lindgren
2012-07-06 12:47   ` Shilimkar, Santosh
2012-07-06 12:47     ` Shilimkar, Santosh

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