* [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset
@ 2012-07-22 6:55 John Crispin
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: John Crispin @ 2012-07-22 6:55 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
The XRX200 based SoC have a different register offset for the interface clock
and PCI control registers. This patch detects the SoC and sets the register
offset at runtime. This make PCI work on the VR9 SoC.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/sysctrl.c | 49 ++++++++++++++++++++++----------------
1 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 83780f7..befbb76 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -20,10 +20,12 @@
/* clock control register */
#define CGU_IFCCR 0x0018
+#define CGU_IFCCR_VR9 0x0024
/* system clock register */
#define CGU_SYS 0x0010
/* pci control register */
#define CGU_PCICR 0x0034
+#define CGU_PCICR_VR9 0x0038
/* ephy configuration register */
#define CGU_EPHY 0x10
/* power control register */
@@ -80,6 +82,9 @@ static void __iomem *pmu_membase;
void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
+static u32 ifccr = CGU_IFCCR;
+static u32 pcicr = CGU_PCICR;
+
/* legacy function kept alive to ease clkdev transition */
void ltq_pmu_enable(unsigned int module)
{
@@ -103,14 +108,14 @@ EXPORT_SYMBOL(ltq_pmu_disable);
/* enable a hw clock */
static int cgu_enable(struct clk *clk)
{
- ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
+ ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
return 0;
}
/* disable a hw clock */
static void cgu_disable(struct clk *clk)
{
- ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
+ ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
}
/* enable a clock gate */
@@ -138,22 +143,22 @@ static void pmu_disable(struct clk *clk)
/* the pci enable helper */
static int pci_enable(struct clk *clk)
{
- unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+ unsigned int val = ltq_cgu_r32(ifccr);
/* set bus clock speed */
if (of_machine_is_compatible("lantiq,ar9")) {
- ifccr &= ~0x1f00000;
+ val &= ~0x1f00000;
if (clk->rate == CLOCK_33M)
- ifccr |= 0xe00000;
+ val |= 0xe00000;
else
- ifccr |= 0x700000; /* 62.5M */
+ val |= 0x700000; /* 62.5M */
} else {
- ifccr &= ~0xf00000;
+ val &= ~0xf00000;
if (clk->rate == CLOCK_33M)
- ifccr |= 0x800000;
+ val |= 0x800000;
else
- ifccr |= 0x400000; /* 62.5M */
+ val |= 0x400000; /* 62.5M */
}
- ltq_cgu_w32(ifccr, CGU_IFCCR);
+ ltq_cgu_w32(val, ifccr);
pmu_enable(clk);
return 0;
}
@@ -161,18 +166,16 @@ static int pci_enable(struct clk *clk)
/* enable the external clock as a source */
static int pci_ext_enable(struct clk *clk)
{
- ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
- CGU_IFCCR);
- ltq_cgu_w32((1 << 30), CGU_PCICR);
+ ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
+ ltq_cgu_w32((1 << 30), pcicr);
return 0;
}
/* disable the external clock as a source */
static void pci_ext_disable(struct clk *clk)
{
- ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
- CGU_IFCCR);
- ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
+ ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
+ ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
}
/* enable a clockout source */
@@ -184,11 +187,11 @@ static int clkout_enable(struct clk *clk)
for (i = 0; i < 4; i++) {
if (clk->rates[i] == clk->rate) {
int shift = 14 - (2 * clk->module);
- unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+ unsigned int val = ltq_cgu_r32(ifccr);
- ifccr &= ~(3 << shift);
- ifccr |= i << shift;
- ltq_cgu_w32(ifccr, CGU_IFCCR);
+ val &= ~(3 << shift);
+ val |= i << shift;
+ ltq_cgu_w32(val, ifccr);
return 0;
}
}
@@ -336,8 +339,12 @@ void __init ltq_soc_init(void)
clkdev_add_clkout();
/* add the soc dependent clocks */
- if (!of_machine_is_compatible("lantiq,vr9"))
+ if (of_machine_is_compatible("lantiq,vr9")) {
+ ifccr = CGU_IFCCR_VR9;
+ pcicr = CGU_PCICR_VR9;
+ } else {
clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
+ }
if (!of_machine_is_compatible("lantiq,ase")) {
clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
--
1.7.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay
2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
@ 2012-07-22 6:55 ` John Crispin
2012-07-22 16:04 ` Sergei Shtylyov
2012-07-22 6:55 ` [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper John Crispin
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: John Crispin @ 2012-07-22 6:55 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
The PCI core has a register that allows us to set the nanosecond delay of the
PCI clock lane. This patch adds a helper function to allow setting this value.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++
arch/mips/lantiq/xway/sysctrl.c | 14 ++++++++++++++
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 6a2df70..0c2d67d 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase;
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
+/* allow pci driver to set the pci clk delay */
+void ltq_pci_set_delay(u32 delay);
+
#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index befbb76..91bb435 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -41,6 +41,10 @@
/* power status register */
#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
+/* pci delay is 6 bit wide and 18 bit into the register*/
+#define PCI_DLY_MASK 0x3f
+#define PCI_DLY_SHIFT 18
+
/* clock gates that we can en/disable */
#define PMU_USB0_P BIT(0)
#define PMU_PCI BIT(4)
@@ -258,6 +262,16 @@ static void clkdev_add_pci(void)
clkdev_add(&clk_ext->cl);
}
+/* allow PCI driver to specify the clock delay. This is a 6 bit value */
+void ltq_pci_set_delay(u32 delay)
+{
+ u32 val = ltq_cgu_r32(pcicr);
+
+ val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT);
+ val |= (delay & PCI_DLY_MASK) << PCI_DLY_SHIFT;
+ ltq_cgu_w32(val, pcicr);
+}
+
/* xway socs can generate clocks on gpio pins */
static unsigned long valid_clkout_rates[4][5] = {
{CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
--
1.7.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
@ 2012-07-22 16:04 ` Sergei Shtylyov
2012-07-22 16:08 ` John Crispin
0 siblings, 1 reply; 7+ messages in thread
From: Sergei Shtylyov @ 2012-07-22 16:04 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, linux-mips
Hello.
On 22-07-2012 10:55, John Crispin wrote:
> The PCI core has a register that allows us to set the nanosecond delay of the
> PCI clock lane. This patch adds a helper function to allow setting this value.
> Signed-off-by: John Crispin <blogic@openwrt.org>
[...]
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index befbb76..91bb435 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
[...]
> @@ -258,6 +262,16 @@ static void clkdev_add_pci(void)
> clkdev_add(&clk_ext->cl);
> }
>
> +/* allow PCI driver to specify the clock delay. This is a 6 bit value */
WHy make it 'u32' then?
> +void ltq_pci_set_delay(u32 delay)
> +{
> + u32 val = ltq_cgu_r32(pcicr);
> +
> + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT);
> + val |= (delay & PCI_DLY_MASK) << PCI_DLY_SHIFT;
> + ltq_cgu_w32(val, pcicr);
> +}
> +
WBR, Sergei
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper
2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
@ 2012-07-22 6:55 ` John Crispin
2012-07-22 6:56 ` [PATCH 4/5] MIPS: lantiq: adds device_tree_init function John Crispin
2012-07-22 6:56 ` [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup John Crispin
3 siblings, 0 replies; 7+ messages in thread
From: John Crispin @ 2012-07-22 6:55 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
Make use of the new helper function that allows us to set the PCI clock delay
inside the PCI driver.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/pci/pci-lantiq.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 075d87a..dae4349 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -98,7 +98,7 @@ static inline u32 ltq_calc_bar11mask(void)
static int __devinit ltq_pci_startup(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
- const __be32 *req_mask, *bus_clk;
+ const __be32 *req_mask, *bus_clk, *delay;
u32 temp_buffer;
/* get our clocks */
@@ -127,6 +127,11 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
else
clk_disable(clk_external);
+ /* pci ckl delay is a 6 bit value */
+ delay = of_get_property(node, "lantiq,delay", NULL);
+ if (delay)
+ ltq_pci_set_delay(*delay);
+
/* setup reset gpio used by pci */
reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
if (gpio_is_valid(reset_gpio))
--
1.7.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] MIPS: lantiq: adds device_tree_init function
2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
2012-07-22 6:55 ` [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper John Crispin
@ 2012-07-22 6:56 ` John Crispin
2012-07-22 6:56 ` [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup John Crispin
3 siblings, 0 replies; 7+ messages in thread
From: John Crispin @ 2012-07-22 6:56 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
Add a lantiq specific version of device_tree_init. The generic MIPS version
was removed by.
commit 594e966bc412d64eec9282d28ce511bdd62fea39
Author: David Daney <david.daney@cavium.com>
Date: Thu Jul 5 18:12:38 2012 +0200
MIPS: Prune some target specific code out of prom.c
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/prom.c | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 05a3364..e537099 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -8,7 +8,10 @@
#include <linux/export.h>
#include <linux/clk.h>
+#include <linux/bootmem.h>
#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+
#include <asm/bootinfo.h>
#include <asm/time.h>
@@ -74,6 +77,25 @@ void __init plat_mem_setup(void)
__dt_setup_arch(bph);
}
+void __init device_tree_init(void)
+{
+ unsigned long base, size;
+
+ if (!initial_boot_params)
+ return;
+
+ base = virt_to_phys((void *)initial_boot_params);
+ size = be32_to_cpu(initial_boot_params->totalsize);
+
+ /* Before we do anything, lets reserve the dt blob */
+ reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+
+ unflatten_device_tree();
+
+ /* free the space reserved for the dt blob */
+ free_bootmem(base, size);
+}
+
void __init prom_init(void)
{
/* call the soc specific detetcion code and get it to fill soc_info */
--
1.7.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup
2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
` (2 preceding siblings ...)
2012-07-22 6:56 ` [PATCH 4/5] MIPS: lantiq: adds device_tree_init function John Crispin
@ 2012-07-22 6:56 ` John Crispin
3 siblings, 0 replies; 7+ messages in thread
From: John Crispin @ 2012-07-22 6:56 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
As we use CLKDEV_LOOKUP but dont have support for COMMON_CLK yet, we need to
provide our own version of of_clk_get_from_provider().
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/clk.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index d3bcc33..ce2f129 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -135,6 +135,11 @@ void clk_deactivate(struct clk *clk)
}
EXPORT_SYMBOL(clk_deactivate);
+struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
+{
+ return NULL;
+}
+
static inline u32 get_counter_resolution(void)
{
u32 res;
--
1.7.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2012-07-22 16:09 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2012-07-22 6:55 [PATCH 1/5] MIPS: lantiq: fix interface clock and PCI control register offset John Crispin
2012-07-22 6:55 ` [PATCH 2/5] MIPS: lantiq: add helper to set PCI clock delay John Crispin
2012-07-22 16:04 ` Sergei Shtylyov
2012-07-22 16:08 ` John Crispin
2012-07-22 6:55 ` [PATCH 3/5] MIPS: lantiq: make use of new PCI clock helper John Crispin
2012-07-22 6:56 ` [PATCH 4/5] MIPS: lantiq: adds device_tree_init function John Crispin
2012-07-22 6:56 ` [PATCH 5/5] MIPS: lantiq: platform specific CLK fixup John Crispin
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