* [PATCH 1/2] drm/radeon: fix fence related segfault in CS @ 2012-07-31 11:48 Christian König 2012-07-31 11:48 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König 2012-07-31 14:47 ` [PATCH 1/2] drm/radeon: fix fence related segfault in CS Michel Dänzer 0 siblings, 2 replies; 10+ messages in thread From: Christian König @ 2012-07-31 11:48 UTC (permalink / raw) To: dri-devel, airlied Don't return success if scheduling the IB fails, otherwise we end up with an oops in ttm_eu_fence_buffer_objects. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/radeon_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 142f894..17238f4 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -377,7 +377,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev, if (r) { DRM_ERROR("Failed to schedule IB !\n"); } - return 0; + return r; } static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI 2012-07-31 11:48 [PATCH 1/2] drm/radeon: fix fence related segfault in CS Christian König @ 2012-07-31 11:48 ` Christian König 2012-07-31 14:02 ` Alex Deucher 2012-07-31 14:47 ` [PATCH 1/2] drm/radeon: fix fence related segfault in CS Michel Dänzer 1 sibling, 1 reply; 10+ messages in thread From: Christian König @ 2012-07-31 11:48 UTC (permalink / raw) To: dri-devel, airlied The sixteen bank case wasn't handled here, leading to GPU crashes because of userspace miscalculation. Signed-off-by: Christian König <deathsimple@vodafone.de> Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/si.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 0b02792..0182fc8 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev) /* XXX what about 12? */ rdev->config.si.tile_config |= (3 << 0); break; - } - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) - rdev->config.si.tile_config |= 1 << 4; - else + } + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { + case 0: /* four banks */ rdev->config.si.tile_config |= 0 << 4; + break; + case 1: /* eight banks */ + rdev->config.si.tile_config |= 1 << 4; + break; + case 2: /* sixteen banks */ + default: + rdev->config.si.tile_config |= 2 << 4; + break; + } rdev->config.si.tile_config |= ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; rdev->config.si.tile_config |= -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI 2012-07-31 11:48 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König @ 2012-07-31 14:02 ` Alex Deucher 2012-07-31 14:21 ` Christian König 0 siblings, 1 reply; 10+ messages in thread From: Alex Deucher @ 2012-07-31 14:02 UTC (permalink / raw) To: Christian König; +Cc: dri-devel On Tue, Jul 31, 2012 at 7:48 AM, Christian König <deathsimple@vodafone.de> wrote: > The sixteen bank case wasn't handled here, leading to GPU > crashes because of userspace miscalculation. You mean a GPU hang or a segfault in userspace? IIRC, from the hw perspective numbers of banks over 8 are considered 8 for tiling. Alex > > Signed-off-by: Christian König <deathsimple@vodafone.de> > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/radeon/si.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c > index 0b02792..0182fc8 100644 > --- a/drivers/gpu/drm/radeon/si.c > +++ b/drivers/gpu/drm/radeon/si.c > @@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev) > /* XXX what about 12? */ > rdev->config.si.tile_config |= (3 << 0); > break; > - } > - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) > - rdev->config.si.tile_config |= 1 << 4; > - else > + } > + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { > + case 0: /* four banks */ > rdev->config.si.tile_config |= 0 << 4; > + break; > + case 1: /* eight banks */ > + rdev->config.si.tile_config |= 1 << 4; > + break; > + case 2: /* sixteen banks */ > + default: > + rdev->config.si.tile_config |= 2 << 4; > + break; > + } > rdev->config.si.tile_config |= > ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; > rdev->config.si.tile_config |= > -- > 1.7.9.5 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI 2012-07-31 14:02 ` Alex Deucher @ 2012-07-31 14:21 ` Christian König 2012-07-31 14:42 ` Alex Deucher 0 siblings, 1 reply; 10+ messages in thread From: Christian König @ 2012-07-31 14:21 UTC (permalink / raw) To: Alex Deucher; +Cc: dri-devel On 31.07.2012 16:02, Alex Deucher wrote: > On Tue, Jul 31, 2012 at 7:48 AM, Christian König > <deathsimple@vodafone.de> wrote: >> The sixteen bank case wasn't handled here, leading to GPU >> crashes because of userspace miscalculation. > You mean a GPU hang or a segfault in userspace? IIRC, from the hw > perspective numbers of banks over 8 are considered 8 for tiling. Well it was a GPU segfault :) The GPU was accessing memory regions that weren't VM mapped. As far as i could figure it out it wasn't happy with the alignment of the color buffer. The number of banks we used for that calculation seemed to be different from what the kernel programmed into the tiling config registers. So I tried changing it from 8 to 16 and hurray it started working (ok, more or less currently digging into the next problem). It is possible that this is just masquerading another bug, but as far as I can see it is the most logical explanation. Why are 16 banks equal to 8 banks on the hw side? Christian. > > Alex > >> Signed-off-by: Christian König <deathsimple@vodafone.de> >> Cc: stable@vger.kernel.org >> --- >> drivers/gpu/drm/radeon/si.c | 16 ++++++++++++---- >> 1 file changed, 12 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c >> index 0b02792..0182fc8 100644 >> --- a/drivers/gpu/drm/radeon/si.c >> +++ b/drivers/gpu/drm/radeon/si.c >> @@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev) >> /* XXX what about 12? */ >> rdev->config.si.tile_config |= (3 << 0); >> break; >> - } >> - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) >> - rdev->config.si.tile_config |= 1 << 4; >> - else >> + } >> + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { >> + case 0: /* four banks */ >> rdev->config.si.tile_config |= 0 << 4; >> + break; >> + case 1: /* eight banks */ >> + rdev->config.si.tile_config |= 1 << 4; >> + break; >> + case 2: /* sixteen banks */ >> + default: >> + rdev->config.si.tile_config |= 2 << 4; >> + break; >> + } >> rdev->config.si.tile_config |= >> ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; >> rdev->config.si.tile_config |= >> -- >> 1.7.9.5 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI 2012-07-31 14:21 ` Christian König @ 2012-07-31 14:42 ` Alex Deucher 2012-07-31 15:07 ` [PATCH 1/2] drm/radeon: fix bank tiling parameters on evergreen alexdeucher 2012-07-31 15:21 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König 0 siblings, 2 replies; 10+ messages in thread From: Alex Deucher @ 2012-07-31 14:42 UTC (permalink / raw) To: Christian König; +Cc: dri-devel On Tue, Jul 31, 2012 at 10:21 AM, Christian König <deathsimple@vodafone.de> wrote: > On 31.07.2012 16:02, Alex Deucher wrote: >> >> On Tue, Jul 31, 2012 at 7:48 AM, Christian König >> <deathsimple@vodafone.de> wrote: >>> >>> The sixteen bank case wasn't handled here, leading to GPU >>> crashes because of userspace miscalculation. >> >> You mean a GPU hang or a segfault in userspace? IIRC, from the hw >> perspective numbers of banks over 8 are considered 8 for tiling. > > Well it was a GPU segfault :) The GPU was accessing memory regions that > weren't VM mapped. > > As far as i could figure it out it wasn't happy with the alignment of the > color buffer. The number of banks we used for that calculation seemed to be > different from what the kernel programmed into the tiling config registers. > So I tried changing it from 8 to 16 and hurray it started working (ok, more > or less currently digging into the next problem). > > It is possible that this is just masquerading another bug, but as far as I > can see it is the most logical explanation. Seems reasonable. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > > Why are 16 banks equal to 8 banks on the hw side? I was talking to one of the hw guys about some issues with tiling. Certain 6xx or 7xx chips report more than 8 banks in the MC config, but the tiling configuration on them only supports 4 and 8 banks. IIRC, he said number of banks above 8 should be treated as 8 at least for 6xx-9xx. Although, looking at it again it looks like maybe we want 16 bank support for evergreen/cayman as well after all. It shouldn't hurt other than possibly over allocating a bit. Alex > > Christian. > > >> >> Alex >> >>> Signed-off-by: Christian König <deathsimple@vodafone.de> >>> Cc: stable@vger.kernel.org >>> --- >>> drivers/gpu/drm/radeon/si.c | 16 ++++++++++++---- >>> 1 file changed, 12 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c >>> index 0b02792..0182fc8 100644 >>> --- a/drivers/gpu/drm/radeon/si.c >>> +++ b/drivers/gpu/drm/radeon/si.c >>> @@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device >>> *rdev) >>> /* XXX what about 12? */ >>> rdev->config.si.tile_config |= (3 << 0); >>> break; >>> - } >>> - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) >>> - rdev->config.si.tile_config |= 1 << 4; >>> - else >>> + } >>> + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { >>> + case 0: /* four banks */ >>> rdev->config.si.tile_config |= 0 << 4; >>> + break; >>> + case 1: /* eight banks */ >>> + rdev->config.si.tile_config |= 1 << 4; >>> + break; >>> + case 2: /* sixteen banks */ >>> + default: >>> + rdev->config.si.tile_config |= 2 << 4; >>> + break; >>> + } >>> rdev->config.si.tile_config |= >>> ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> >>> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; >>> rdev->config.si.tile_config |= >>> -- >>> 1.7.9.5 >>> >>> _______________________________________________ >>> dri-devel mailing list >>> dri-devel@lists.freedesktop.org >>> http://lists.freedesktop.org/mailman/listinfo/dri-devel > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] drm/radeon: fix bank tiling parameters on evergreen 2012-07-31 14:42 ` Alex Deucher @ 2012-07-31 15:07 ` alexdeucher 2012-07-31 15:07 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on cayman alexdeucher 2012-07-31 15:21 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König 1 sibling, 1 reply; 10+ messages in thread From: alexdeucher @ 2012-07-31 15:07 UTC (permalink / raw) To: airlied, dri-devel; +Cc: Alex Deucher, stable From: Alex Deucher <alexander.deucher@amd.com> Handle the 16 bank case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 30f5c31..475984a 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -2005,10 +2005,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_IGP) rdev->config.evergreen.tile_config |= 1 << 4; else { - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) - rdev->config.evergreen.tile_config |= 1 << 4; - else + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { + case 0: /* four banks */ rdev->config.evergreen.tile_config |= 0 << 4; + break; + case 1: /* eight banks */ + rdev->config.evergreen.tile_config |= 1 << 4; + break; + case 2: /* sixteen banks */ + default: + rdev->config.evergreen.tile_config |= 2 << 4; + break; + } } rdev->config.evergreen.tile_config |= 0 << 8; rdev->config.evergreen.tile_config |= -- 1.7.7.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/radeon: fix bank tiling parameters on cayman 2012-07-31 15:07 ` [PATCH 1/2] drm/radeon: fix bank tiling parameters on evergreen alexdeucher @ 2012-07-31 15:07 ` alexdeucher 0 siblings, 0 replies; 10+ messages in thread From: alexdeucher @ 2012-07-31 15:07 UTC (permalink / raw) To: airlied, dri-devel; +Cc: Alex Deucher, stable From: Alex Deucher <alexander.deucher@amd.com> Handle the 16 bank case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/ni.c | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 9945d86..853800e 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -574,10 +574,18 @@ static void cayman_gpu_init(struct radeon_device *rdev) if (rdev->flags & RADEON_IS_IGP) rdev->config.cayman.tile_config |= 1 << 4; else { - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) - rdev->config.cayman.tile_config |= 1 << 4; - else + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { + case 0: /* four banks */ rdev->config.cayman.tile_config |= 0 << 4; + break; + case 1: /* eight banks */ + rdev->config.cayman.tile_config |= 1 << 4; + break; + case 2: /* sixteen banks */ + default: + rdev->config.cayman.tile_config |= 2 << 4; + break; + } } rdev->config.cayman.tile_config |= ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; -- 1.7.7.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI 2012-07-31 14:42 ` Alex Deucher 2012-07-31 15:07 ` [PATCH 1/2] drm/radeon: fix bank tiling parameters on evergreen alexdeucher @ 2012-07-31 15:21 ` Christian König 1 sibling, 0 replies; 10+ messages in thread From: Christian König @ 2012-07-31 15:21 UTC (permalink / raw) To: Alex Deucher; +Cc: dri-devel On 31.07.2012 16:42, Alex Deucher wrote: > On Tue, Jul 31, 2012 at 10:21 AM, Christian König > <deathsimple@vodafone.de> wrote: >> On 31.07.2012 16:02, Alex Deucher wrote: >>> On Tue, Jul 31, 2012 at 7:48 AM, Christian König >>> <deathsimple@vodafone.de> wrote: >>>> The sixteen bank case wasn't handled here, leading to GPU >>>> crashes because of userspace miscalculation. >>> You mean a GPU hang or a segfault in userspace? IIRC, from the hw >>> perspective numbers of banks over 8 are considered 8 for tiling. >> Well it was a GPU segfault :) The GPU was accessing memory regions that >> weren't VM mapped. >> >> As far as i could figure it out it wasn't happy with the alignment of the >> color buffer. The number of banks we used for that calculation seemed to be >> different from what the kernel programmed into the tiling config registers. >> So I tried changing it from 8 to 16 and hurray it started working (ok, more >> or less currently digging into the next problem). >> >> It is possible that this is just masquerading another bug, but as far as I >> can see it is the most logical explanation. > Seems reasonable. > > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > >> Why are 16 banks equal to 8 banks on the hw side? > I was talking to one of the hw guys about some issues with tiling. > Certain 6xx or 7xx chips report more than 8 banks in the MC config, > but the tiling configuration on them only supports 4 and 8 banks. > IIRC, he said number of banks above 8 should be treated as 8 at least > for 6xx-9xx. Although, looking at it again it looks like maybe we > want 16 bank support for evergreen/cayman as well after all. It > shouldn't hurt other than possibly over allocating a bit. The alternative is to reduce the number of banks in the gb_tile_mode* regs. I should also note that I have encountered a couple of more problems with SI and 16 banks, they go away if I reduce the banks to 8. Not sure what the reason is but it is possible that our surface_manager can't handle 16 banks yet. So be careful if you enable that for cayman and evergreen. Cheers, Christian. > > Alex > >> Christian. >> >> >>> Alex >>> >>>> Signed-off-by: Christian König <deathsimple@vodafone.de> >>>> Cc: stable@vger.kernel.org >>>> --- >>>> drivers/gpu/drm/radeon/si.c | 16 ++++++++++++---- >>>> 1 file changed, 12 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c >>>> index 0b02792..0182fc8 100644 >>>> --- a/drivers/gpu/drm/radeon/si.c >>>> +++ b/drivers/gpu/drm/radeon/si.c >>>> @@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device >>>> *rdev) >>>> /* XXX what about 12? */ >>>> rdev->config.si.tile_config |= (3 << 0); >>>> break; >>>> - } >>>> - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) >>>> - rdev->config.si.tile_config |= 1 << 4; >>>> - else >>>> + } >>>> + switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { >>>> + case 0: /* four banks */ >>>> rdev->config.si.tile_config |= 0 << 4; >>>> + break; >>>> + case 1: /* eight banks */ >>>> + rdev->config.si.tile_config |= 1 << 4; >>>> + break; >>>> + case 2: /* sixteen banks */ >>>> + default: >>>> + rdev->config.si.tile_config |= 2 << 4; >>>> + break; >>>> + } >>>> rdev->config.si.tile_config |= >>>> ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> >>>> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; >>>> rdev->config.si.tile_config |= >>>> -- >>>> 1.7.9.5 >>>> >>>> _______________________________________________ >>>> dri-devel mailing list >>>> dri-devel@lists.freedesktop.org >>>> http://lists.freedesktop.org/mailman/listinfo/dri-devel >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/radeon: fix fence related segfault in CS 2012-07-31 11:48 [PATCH 1/2] drm/radeon: fix fence related segfault in CS Christian König 2012-07-31 11:48 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König @ 2012-07-31 14:47 ` Michel Dänzer 2012-07-31 15:05 ` Christian König 1 sibling, 1 reply; 10+ messages in thread From: Michel Dänzer @ 2012-07-31 14:47 UTC (permalink / raw) To: Christian König; +Cc: dri-devel On Die, 2012-07-31 at 13:48 +0200, Christian König wrote: > Don't return success if scheduling the IB fails, otherwise > we end up with an oops in ttm_eu_fence_buffer_objects. > > Signed-off-by: Christian König <deathsimple@vodafone.de> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/radeon/radeon_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c > index 142f894..17238f4 100644 > --- a/drivers/gpu/drm/radeon/radeon_cs.c > +++ b/drivers/gpu/drm/radeon/radeon_cs.c > @@ -377,7 +377,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev, > if (r) { > DRM_ERROR("Failed to schedule IB !\n"); > } > - return 0; > + return r; > } > > static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, AFAICT this fix is already in Linus' tree (commit 93bf888c5c730605e3470f5d2381f296eda88d79). -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/radeon: fix fence related segfault in CS 2012-07-31 14:47 ` [PATCH 1/2] drm/radeon: fix fence related segfault in CS Michel Dänzer @ 2012-07-31 15:05 ` Christian König 0 siblings, 0 replies; 10+ messages in thread From: Christian König @ 2012-07-31 15:05 UTC (permalink / raw) To: Michel Dänzer; +Cc: dri-devel On 31.07.2012 16:47, Michel Dänzer wrote: > On Die, 2012-07-31 at 13:48 +0200, Christian König wrote: >> Don't return success if scheduling the IB fails, otherwise >> we end up with an oops in ttm_eu_fence_buffer_objects. >> >> Signed-off-by: Christian König <deathsimple@vodafone.de> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> >> Cc: stable@vger.kernel.org >> --- >> drivers/gpu/drm/radeon/radeon_cs.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c >> index 142f894..17238f4 100644 >> --- a/drivers/gpu/drm/radeon/radeon_cs.c >> +++ b/drivers/gpu/drm/radeon/radeon_cs.c >> @@ -377,7 +377,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev, >> if (r) { >> DRM_ERROR("Failed to schedule IB !\n"); >> } >> - return 0; >> + return r; >> } >> >> static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, > AFAICT this fix is already in Linus' tree (commit > 93bf888c5c730605e3470f5d2381f296eda88d79). Your right, but why the heck isn't it in drm-fixes? Christian. ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2012-07-31 15:21 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-07-31 11:48 [PATCH 1/2] drm/radeon: fix fence related segfault in CS Christian König 2012-07-31 11:48 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König 2012-07-31 14:02 ` Alex Deucher 2012-07-31 14:21 ` Christian König 2012-07-31 14:42 ` Alex Deucher 2012-07-31 15:07 ` [PATCH 1/2] drm/radeon: fix bank tiling parameters on evergreen alexdeucher 2012-07-31 15:07 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on cayman alexdeucher 2012-07-31 15:21 ` [PATCH 2/2] drm/radeon: fix bank tiling parameters on SI Christian König 2012-07-31 14:47 ` [PATCH 1/2] drm/radeon: fix fence related segfault in CS Michel Dänzer 2012-07-31 15:05 ` Christian König
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