From: Felix Fietkau <nbd@openwrt.org>
To: ath9k-devel@lists.ath9k.org
Subject: [ath9k-devel] [PATCHv2] ath9k_hw: Handle AR_INTR_SYNC_HOST1_FATAL on AR9003
Date: Sat, 06 Oct 2012 11:03:41 +0200 [thread overview]
Message-ID: <506FF3ED.6010906@openwrt.org> (raw)
In-Reply-To: <CAJ-VmomfDr-JAMtgQmbEsSeF62W-dmsK7LRTJxNUUddOTqDayA@mail.gmail.com>
On 2012-10-06 1:48 AM, Adrian Chadd wrote:
> On 5 October 2012 09:51, Sven Eckelmann <sven@narfation.org> wrote:
>
>>> Well, is it a RX chainmask thing, or is it a chip thing?
>>>
>>> It's totally possible to have an RX chainmask of say 0x2 or 0x4..
>>
>> What are you trying to tell us?
>
> That the check for "rx chainmask == 1? Definitely can't do MRC CCK"
> implying "rx chainmask != 1? Definitely can do MRC CCK."
> I think that's the wrong logic. It may be a general chipset problem
> across some/all AR9300 and later chips that doing MRC CCK with only
> one RX chain enabled is a problem, or it may be a single-chain NIC
> problem.
>
> I'm pretty sure we can configure any of the RX antennas; it doesn't
> have to be "one chain == chain 0."
>
> Anywy. I'll double check that.
I'm pretty sure it's an issue specific to single-stream chipsets, where
all MRC functionality was left out (and thus the register access leads
nowhere).
I don't think this needs to consider multi-stream chipsets with only one
enabled chain.
- Felix
WARNING: multiple messages have this Message-ID (diff)
From: Felix Fietkau <nbd@openwrt.org>
To: Adrian Chadd <adrian@freebsd.org>
Cc: Sven Eckelmann <sven@narfation.org>,
Simon Wunderlich <simon.wunderlich@s2003.tu-chemnitz.de>,
linux-wireless@vger.kernel.org, linville@tuxdriver.com,
mcgrof@qca.qualcomm.com, ath9k-devel@lists.ath9k.org,
lindner_marek@yahoo.de
Subject: Re: [ath9k-devel] [PATCHv2] ath9k_hw: Handle AR_INTR_SYNC_HOST1_FATAL on AR9003
Date: Sat, 06 Oct 2012 11:03:41 +0200 [thread overview]
Message-ID: <506FF3ED.6010906@openwrt.org> (raw)
In-Reply-To: <CAJ-VmomfDr-JAMtgQmbEsSeF62W-dmsK7LRTJxNUUddOTqDayA@mail.gmail.com>
On 2012-10-06 1:48 AM, Adrian Chadd wrote:
> On 5 October 2012 09:51, Sven Eckelmann <sven@narfation.org> wrote:
>
>>> Well, is it a RX chainmask thing, or is it a chip thing?
>>>
>>> It's totally possible to have an RX chainmask of say 0x2 or 0x4..
>>
>> What are you trying to tell us?
>
> That the check for "rx chainmask == 1? Definitely can't do MRC CCK"
> implying "rx chainmask != 1? Definitely can do MRC CCK."
> I think that's the wrong logic. It may be a general chipset problem
> across some/all AR9300 and later chips that doing MRC CCK with only
> one RX chain enabled is a problem, or it may be a single-chain NIC
> problem.
>
> I'm pretty sure we can configure any of the RX antennas; it doesn't
> have to be "one chain == chain 0."
>
> Anywy. I'll double check that.
I'm pretty sure it's an issue specific to single-stream chipsets, where
all MRC functionality was left out (and thus the register access leads
nowhere).
I don't think this needs to consider multi-stream chipsets with only one
enabled chain.
- Felix
next prev parent reply other threads:[~2012-10-06 9:03 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-27 14:41 [ath9k-devel] [PATCH] ath9k_hw: Handle AR_INTR_SYNC_HOST1_(FATAL|PERR) on AR9003 Sven Eckelmann
2012-09-27 14:41 ` Sven Eckelmann
2012-10-02 10:33 ` [ath9k-devel] [PATCHv2] ath9k_hw: Handle AR_INTR_SYNC_HOST1_FATAL " Sven Eckelmann
2012-10-02 10:33 ` Sven Eckelmann
2012-10-02 13:13 ` [ath9k-devel] " Adrian Chadd
2012-10-02 13:13 ` Adrian Chadd
2012-10-02 13:33 ` [ath9k-devel] " Felix Fietkau
2012-10-02 13:33 ` Felix Fietkau
2012-10-02 13:35 ` Simon Wunderlich
2012-10-02 13:35 ` Simon Wunderlich
2012-10-02 14:06 ` [ath9k-devel] " Adrian Chadd
2012-10-02 14:06 ` Adrian Chadd
2012-10-02 15:02 ` [ath9k-devel] " Sven Eckelmann
2012-10-02 15:02 ` Sven Eckelmann
2012-10-02 15:20 ` [ath9k-devel] " Felix Fietkau
2012-10-02 15:20 ` Felix Fietkau
2012-10-03 14:51 ` Adrian Chadd
2012-10-03 14:51 ` Adrian Chadd
2012-10-05 11:08 ` Sven Eckelmann
2012-10-05 11:08 ` Sven Eckelmann
2012-10-05 12:34 ` Felix Fietkau
2012-10-05 12:34 ` Felix Fietkau
2012-10-05 13:07 ` Sven Eckelmann
2012-10-05 13:07 ` Sven Eckelmann
2012-10-05 13:24 ` Felix Fietkau
2012-10-05 13:24 ` Felix Fietkau
2012-10-05 15:03 ` Sven Eckelmann
2012-10-05 15:03 ` Sven Eckelmann
2012-10-05 15:15 ` Felix Fietkau
2012-10-05 15:15 ` Felix Fietkau
2012-10-05 16:05 ` Sven Eckelmann
2012-10-05 16:05 ` Sven Eckelmann
2012-10-05 16:21 ` Adrian Chadd
2012-10-05 16:21 ` Adrian Chadd
2012-10-05 16:51 ` Sven Eckelmann
2012-10-05 16:51 ` Sven Eckelmann
2012-10-05 23:48 ` Adrian Chadd
2012-10-05 23:48 ` Adrian Chadd
2012-10-06 9:03 ` Felix Fietkau [this message]
2012-10-06 9:03 ` Felix Fietkau
2013-02-21 11:14 ` Felix Liao
2013-02-21 11:14 ` Felix Liao
2013-02-21 20:38 ` Adrian Chadd
2013-02-22 1:19 ` Felix Liao
2013-02-22 5:16 ` Adrian Chadd
2013-02-22 6:43 ` Felix Liao
2013-02-22 7:18 ` Adrian Chadd
2013-02-22 7:31 ` Felix Liao
2013-02-22 8:08 ` Felix Liao
2013-02-22 1:33 ` Felix Liao
2013-02-22 2:22 ` Felix Liao
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