* [U-Boot] [PATCH v1 1/8] OMAP: include sys_proto.h from boot-common
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition Ilya Yanok
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
Include asm/arch/sys_proto.h for gpmc_init prototype.
Without this we get a warning while building for AM335x.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
arch/arm/cpu/armv7/omap-common/boot-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0f19141..2b584e0 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -21,6 +21,7 @@
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
/*
* This is used to verify if the configuration header
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 1/8] OMAP: include sys_proto.h from boot-common Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 23:45 ` Tom Rini
2012-10-30 22:47 ` [U-Boot] [PATCH v1 3/8] am33xx: NAND support Ilya Yanok
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
Add NAND pins mux settings for AM335X devices. Enable NAND pins
for AM335X EVM board.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
board/ti/am335x/mux.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 80becd5..a46c680 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -362,6 +362,27 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_NAND_OMAP_GPMC
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+
/*
* Configure the pin mux for the module
*/
@@ -435,11 +456,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
unsigned short profile = detect_daughter_board_profile();
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
+#ifdef CONFIG_NAND_OMAP_GPMC
+ configure_module_pin_mux(nand_pin_mux);
+#endif
/* In profile #2 i2c1 and spi0 conflict. */
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
else if (profile == PROFILE_2) {
+#ifndef CONFIG_NAND_OMAP_GPMC
configure_module_pin_mux(mmc1_pin_mux);
+#endif
configure_module_pin_mux(spi0_pin_mux);
}
} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition
2012-10-30 22:47 ` [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition Ilya Yanok
@ 2012-10-30 23:45 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2012-10-30 23:45 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/30/12 15:47, Ilya Yanok wrote:
> Add NAND pins mux settings for AM335X devices. Enable NAND pins for
> AM335X EVM board.
>
> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
[snip]
> @@ -435,11 +456,16 @@ void enable_board_pin_mux(struct
> am335x_baseboard_id *header) unsigned short profile =
> detect_daughter_board_profile();
> configure_module_pin_mux(rgmii1_pin_mux);
> configure_module_pin_mux(mmc0_pin_mux); +#ifdef
> CONFIG_NAND_OMAP_GPMC + configure_module_pin_mux(nand_pin_mux);
> +#endif /* In profile #2 i2c1 and spi0 conflict. */ if (profile &
> ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); else if
> (profile == PROFILE_2) { +#ifndef CONFIG_NAND_OMAP_GPMC
> configure_module_pin_mux(mmc1_pin_mux); +#endif
Minor problem, NAND just isn't available in PROFILE_2 or PROFILE_3.
We should just do the pinmux when we're in anything but those profiles.
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQkGavAAoJENk4IS6UOR1Wdv4P/1ZmDv0YbStiacEE/Aa8Oklg
VrAWz6rgB5PyIaIDwOWvQ01Y8YpzPgOKUtixya8vyBp1f/guBwAIEnSlqbZzjo2R
OmZmhWWUfagmhXgUgz8bC8sKlmtAK4YtHE0zQaujXjNg7sKJ1UM6JS0PtqvM338o
56KvGK/ngmx/EU4K/VJ6FgRzJcbZmkXWu71e+6d/cPIjZdbmdqvIGEZUxrc865I6
n//3UYOyGujW+Z/fOswpZGNXAVOSyieYThXyY9wLtPgv2cnLDa6GC6E9QwN53Lat
6oV0+ub6jjY1A0BRsoKwMzJ1klTePJ9LFRVJsuzivRC+CH9tLNiq+uvmTFtRDdRh
Vh0Bh3+dNmNiQeJKVAOmLMNylpdF5+FRDEqdYd5V3S9h/InApL3u2mTafr2AHgEK
Dl/QouttvRBdvdAUIFMy6khaH3chMojUEuNUNSOWGkSHNYV6KELAohMuRrtAHHak
95iSUiT5mP+JTlX0ltI/8LqLUapbeu6xWxRkRRaLOuCCCPRUuP5fNBr7gpEHUvsx
uIzYrkjLJ7p8qcgpjmnMZZgB3fpYFAiL7B6c8eDJ0u+vX5cUvtkpE9yMwUzYvnnH
MlVKY6nBUE4VDYayFF9R8czGBFNb+recaGm86swpprSsWlzh+RnfFD4QplI1g112
g9fdnSHIHPiJq/TygkWk
=8JAH
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v1 3/8] am33xx: NAND support
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 1/8] OMAP: include sys_proto.h from boot-common Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 23:51 ` Tom Rini
2012-10-30 22:47 ` [U-Boot] [PATCH v1 4/8] am335x_evm: enable " Ilya Yanok
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 1 +
arch/arm/cpu/armv7/am33xx/board.c | 34 +++++
arch/arm/cpu/armv7/am33xx/clock.c | 5 +
arch/arm/cpu/armv7/am33xx/mem.c | 104 +++++++++++++++
arch/arm/include/asm/arch-am33xx/cpu.h | 53 ++++++++
arch/arm/include/asm/arch-am33xx/hardware.h | 3 +
arch/arm/include/asm/arch-am33xx/mem.h | 174 ++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 130 +++++++++++++++++++
arch/arm/include/asm/arch-am33xx/sys_proto.h | 3 +
9 files changed, 507 insertions(+)
create mode 100644 arch/arm/cpu/armv7/am33xx/mem.c
create mode 100644 arch/arm/include/asm/arch-am33xx/mem.h
create mode 100644 arch/arm/include/asm/arch-am33xx/omap_gpmc.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7768912..c93ac19 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o
COBJS += clock.o
COBJS += sys_info.o
+COBJS += mem.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184..71f66ef 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -25,6 +25,7 @@
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
@@ -220,6 +221,8 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gpmc_init();
+
return 0;
}
@@ -298,3 +301,34 @@ int board_eth_init(bd_t *bis)
return cpsw_register(&cpsw_data);
}
#endif
+
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
+/******************************************************************************
+ * AM33xx specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int
+do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2)
+ goto usage;
+ if (strncmp(argv[1], "hw", 2) == 0)
+ omap_nand_switch_ecc(1);
+ else if (strncmp(argv[1], "sw", 2) == 0)
+ omap_nand_switch_ecc(0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 1, do_switch_ecc,
+ "switch OMAP3 NAND ECC calculation algorithm",
+ "[bch8/hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+);
+
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506..75ec860 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -114,6 +114,11 @@ static void enable_per_clocks(void)
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
;
+ /* GPMC */
+ writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+ while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+ ;
+
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
new file mode 100644
index 0000000..e7f1cf7
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6, 0
+};
+
+#define GPMC_CS 0
+
+#endif
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size)
+{
+ writel(0, &cs->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
+ /* Enable the config */
+ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), &cs->config7);
+ sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ /* putting a blanket check on GPMC based on ZeBu for now */
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ const u32 *gpmc_config = NULL;
+ u32 base = 0;
+ u32 size = 0;
+#endif
+ /* global settings */
+ writel(0x00000008, &gpmc_cfg->sysconfig);
+ writel(0x00000100, &gpmc_cfg->irqstatus);
+ writel(0x00000200, &gpmc_cfg->irqenable);
+ writel(0x00000012, &gpmc_cfg->config);
+ /*
+ * Disable the GPMC0 config set by ROM code
+ */
+ writel(0, &gpmc_cfg->cs[0].config7);
+ sdelay(1000);
+
+#if defined(CONFIG_CMD_NAND) /* CS 0 */
+ gpmc_config = gpmc_m_nand;
+
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef7..90828e5 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -60,6 +60,59 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+ u32 bch_result_x[4];
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+ u8 res7[12]; /* 0x224 */
+ u32 testmomde_ctrl; /* 0x230 */
+ u8 res8[12]; /* 0x234 */
+ struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2..a7cf66e 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -79,6 +79,9 @@
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+/* GPMC Base address */
+#define GPMC_BASE 0x50000000
+
/* CPSW Config space */
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
new file mode 100644
index 0000000..c6aae1d
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#ifndef __ASSEMBLY__
+enum {
+ STACKED = 0,
+ IP_DDR = 1,
+ COMBO_DDR = 2,
+ IP_SDR = 3,
+};
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT 1
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ * GPMC_SIZE_128M - 0x8
+ * GPMC_SIZE_64M - 0xC
+ * GPMC_SIZE_32M - 0xE
+ * GPMC_SIZE_16M - 0xF
+ * MAP - Map this CS to which address(GPMC address space)- Absolute address
+ * >>24 before being used.
+ */
+#define GPMC_SIZE_256M 0x0
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+#define SMNAND_GPMC_CONFIG1 0x00000800
+#define SMNAND_GPMC_CONFIG2 0x00141400
+#define SMNAND_GPMC_CONFIG3 0x00141400
+#define SMNAND_GPMC_CONFIG4 0x0F010F01
+#define SMNAND_GPMC_CONFIG5 0x010C1414
+#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7 0x00000C44
+
+
+#define M_NAND_GPMC_CONFIG1 0x00000800
+#define M_NAND_GPMC_CONFIG2 0x001e1e00
+#define M_NAND_GPMC_CONFIG3 0x001e1e00
+#define M_NAND_GPMC_CONFIG4 0x16051807
+#define M_NAND_GPMC_CONFIG5 0x00151e1e
+#define M_NAND_GPMC_CONFIG6 0x16000f80
+#define M_NAND_GPMC_CONFIG7 0x00000008
+
+#define STNOR_GPMC_CONFIG1 0x3
+#define STNOR_GPMC_CONFIG2 0x00151501
+#define STNOR_GPMC_CONFIG3 0x00060602
+#define STNOR_GPMC_CONFIG4 0x11091109
+#define STNOR_GPMC_CONFIG5 0x01141F1F
+#define STNOR_GPMC_CONFIG6 0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1 0x1200
+#define SIBNOR_GPMC_CONFIG2 0x001f1f00
+#define SIBNOR_GPMC_CONFIG3 0x00080802
+#define SIBNOR_GPMC_CONFIG4 0x1C091C09
+#define SIBNOR_GPMC_CONFIG5 0x01131F1F
+#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1 0x00011000
+#define MPDB_GPMC_CONFIG2 0x001f1f01
+#define MPDB_GPMC_CONFIG3 0x00080803
+#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5 0x041f1F1F
+#define MPDB_GPMC_CONFIG6 0x1F0F04C4
+
+#define P2_GPMC_CONFIG1 0x0
+#define P2_GPMC_CONFIG2 0x0
+#define P2_GPMC_CONFIG3 0x0
+#define P2_GPMC_CONFIG4 0x0
+#define P2_GPMC_CONFIG5 0x0
+#define P2_GPMC_CONFIG6 0x0
+
+#define ONENAND_GPMC_CONFIG1 0x00001200
+#define ONENAND_GPMC_CONFIG2 0x000F0F01
+#define ONENAND_GPMC_CONFIG3 0x00030301
+#define ONENAND_GPMC_CONFIG4 0x0F040F04
+#define ONENAND_GPMC_CONFIG5 0x010F1010
+#define ONENAND_GPMC_CONFIG6 0x1F060000
+
+#define NET_GPMC_CONFIG1 0x00001000
+#define NET_GPMC_CONFIG2 0x001e1e01
+#define NET_GPMC_CONFIG3 0x00080300
+#define NET_GPMC_CONFIG4 0x1c091c09
+#define NET_GPMC_CONFIG5 0x04181f1f
+#define NET_GPMC_CONFIG6 0x00000FCF
+#define NET_GPMC_CONFIG7 0x00000f6c
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define PISMO1_NOR 1
+#define PISMO1_NAND 2
+#define PISMO2_CS0 3
+#define PISMO2_CS1 4
+#define PISMO1_ONENAND 5
+#define DBG_MPDB 6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE FLASH_BASE
+#define PISMO1_NAND_BASE NAND_BASE
+#define PISMO1_NAND_SIZE GPMC_SIZE_256M
+
+#endif /* endif _MEM_H_ */
+
diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
new file mode 100644
index 0000000..3576984
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ 9, 10, 11, 12},\
+ .oobfree = {\
+ {.offset = 13,\
+ .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13},\
+ .oobfree = {\
+ {.offset = 14,\
+ .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {1, 2, 3},\
+ .oobfree = {\
+ {.offset = 4,\
+ .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {2, 3, 4},\
+ .oobfree = {\
+ {.offset = 5,\
+ .length = 11 } } \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+ .eccbytes = 32,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33},\
+ .oobfree = {\
+ {.offset = 34,\
+ .length = 30 } } \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+ .eccbytes = 56,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57},\
+ .oobfree = {\
+ {.offset = 58,\
+ .length = 6 } } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+ .eccbytes = 104,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+ 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+ 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+ 100, 101, 102, 103, 104, 105},\
+ .oobfree = {\
+ {.offset = 106,\
+ .length = 8 } } \
+}
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00060700
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x06000700
+#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea65..b07ec18 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -60,4 +60,7 @@ void ddr_pll_config(unsigned int ddrpll_M);
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(struct am335x_baseboard_id *header);
+void sdelay(unsigned long);
+void gpmc_init(void);
+void omap_nand_switch_ecc(int);
#endif
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 3/8] am33xx: NAND support
2012-10-30 22:47 ` [U-Boot] [PATCH v1 3/8] am33xx: NAND support Ilya Yanok
@ 2012-10-30 23:51 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2012-10-30 23:51 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/30/12 15:47, Ilya Yanok wrote:
> TI AM33XX has the same GPMC controller as OMAP3 so we could just
> use the existing omap_gpmc driver. This patch adds adds required
> definitions/intialization.
[snip]
> --- a/arch/arm/cpu/armv7/am33xx/board.c +++
> b/arch/arm/cpu/armv7/am33xx/board.c
[snip]
> +U_BOOT_CMD( + nandecc, 2, 1, do_switch_ecc, + "switch OMAP3 NAND
> ECC calculation algorithm", + "[bch8/hw/sw] - Switch between NAND
> hardware (hw) or software (sw) ecc algorithm" +);
While useful for testing, I don't want to add this command to am33xx
since we don't need it like we do on omap3. We can be consistent and
be whole chip BCH8, or later BCH16 (and use the same logic ROM does
and Linux does or will).
[snip]
> +++ b/arch/arm/cpu/armv7/am33xx/mem.c +#if defined(CONFIG_CMD_NAND)
> || defined(CONFIG_CMD_ONENAND)
There will be no ONENAND. ANd please fixup comment style issues that
we're copying from omap3.
[snip]
> +++ b/arch/arm/include/asm/arch-am33xx/mem.h +#ifndef __ASSEMBLY__
> +enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR =
> 3, +}; +#endif /* __ASSEMBLY__ */ + +#define EARLY_INIT 1 +
We don't need that enum I think. We shouldn't need EARLY_INIT either.
> +/* + * GPMC settings - + * Definitions is as per the following
> format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + *
> PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC
> config registers from 1 to 6 (there will be 6 macros) + * Value is
> corresponding value + * + * For every valid PRCM configuration
> there should be only one definition of + * the same. if values are
> independent of the board, this definition will be + * present in
> this file if values are dependent on the board, then this should +
> * go into corresponding mem-boardName.h file + * + * Currently
> valid part Names are (PART): + * STNOR - Intel Strata Flash + *
> SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley
> NOR + * MNAND - Micron Large page x16 NAND + * ONNAND - Samsung One
> NAND + * + * include/configs/file.h contains the defn - for all CS
> we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define
> OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map +
> * Where: + * x - CS number + * PART - Part Name as defined above +
> * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 +
> * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + *
> GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC
> address space)- Absolute address + * >>24 before being used. +
> */
Lets correct this comment and drop out the GPMC values for chips other
than what we have available on the GP EVM. We can add in more later
as needed.
[snip]
> +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller
> */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define
> NET_LAN9221_GPMC_CONFIG2 0x00060700 +#define
> NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define
> NET_LAN9221_GPMC_CONFIG4 0x06000700 +#define
> NET_LAN9221_GPMC_CONFIG5 0x0006090A +#define
> NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define
> NET_LAN9221_GPMC_CONFIG7 0x00000f6c + +#endif /*
> __ASM_ARCH_OMAP_GPMC_H */
Also don't need those, right?
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQkGgdAAoJENk4IS6UOR1WF9EP/0e48UQ3De3OeWwk0Lg8Y777
I1lFdRx7KaEDaKqQ5O7VSZCA2xHLXCody2VypPWrqB2GaVBuhuCnExjux3s2ltNB
NrIGgwV00hc3fMyYvZHHKLJEhwj8PppgJubB1Ai2yE5yYaTlXiDMAcPYs9JKxpIq
4ShuWAQTI2swulahxyCxTdVrhGPiEhiR3FVOkh7xr8JGzYl4nAqdSYAq7DHaHqCu
TTPCuar/LPgxxN2BR7rSv7KHMih1MSq2x524tt2oKU95+176BllgwUiiW8FHEHHS
uIK9NzdjdDJt5u7IYYzMiPjKi0YqwhwBGb3wc1XzgHx0m6bAORHAbD1+XIclqt2T
x8LHs6f1MmZP2nWatBr6dY1NTrDUXE2hn9zdNkTavq8Aczzj8BQbz4udsNjbp/BW
BoTQ5GZnqvHX/B+xVn44hAM1Gx7aqLDTHy65jE4E3z3NPNTd0QhmsRgqVwNeL+zL
vUU6W8r9Y3UXlhQtJSZhomHwxTbH8/VOmMFTIueErZuVwa/8naDzWL05KqtHxzzp
zOpOBbK7CkF6NGQGxmF5CrBJFgyGaSIEsMKFqWYkvVQvIkCxVgygxYe79b6mvj+P
WQHzcTC3bnAZ+iw1PME6j7aFaMPT2wXuq4PhgBvVolV6SVMNKM8NSzCAMH+ifapD
3JdN6wRkxGn707idqgsE
=sfIs
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v1 4/8] am335x_evm: enable NAND support
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
` (2 preceding siblings ...)
2012-10-30 22:47 ` [U-Boot] [PATCH v1 3/8] am33xx: NAND support Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 23:53 ` Tom Rini
2012-10-30 22:47 ` [U-Boot] [PATCH v1 5/8] am33xx: add ELM support Ilya Yanok
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
Enable NAND support for AM335X boards.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
include/configs/am335x_evm.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 339d4bd..a89cdcd 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -254,4 +254,19 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+#define CONFIG_NAND
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define NAND_BASE (0x08000000)
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+#endif /* devices */
+
#endif /* ! __CONFIG_AM335X_EVM_H */
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 4/8] am335x_evm: enable NAND support
2012-10-30 22:47 ` [U-Boot] [PATCH v1 4/8] am335x_evm: enable " Ilya Yanok
@ 2012-10-30 23:53 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2012-10-30 23:53 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/30/12 15:47, Ilya Yanok wrote:
> Enable NAND support for AM335X boards.
>
> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com> ---
> include/configs/am335x_evm.h | 15 +++++++++++++++ 1 file changed,
> 15 insertions(+)
>
> diff --git a/include/configs/am335x_evm.h
> b/include/configs/am335x_evm.h index 339d4bd..a89cdcd 100644 ---
> a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h
> @@ -254,4 +254,19 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC
>
> +#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND
> +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define
> GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define NAND_BASE (0x08000000)
> +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ +
> /* to access nand */
This is unused
> +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
So just define this to 0x08000000
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQkGhlAAoJENk4IS6UOR1WbTgP/ir7Qqw6MSIX6nhe+tHH2Jn+
g7J5zMSFYrSrv5dCfVGKukYRoYf7ed9sMrGQJruviSpcm0NEt7HOak9MOd4n7zyk
mUSRwe8F9scoJ4X36+Ld53UoeVerk4ZS6qPKdBFMelaiDCNLhvhTfueEIdIrQkJO
AJ7+A9baa41zUID0cCoT2KDvFZGpdnVym+D22VjYhELakbdLPvopPyuEAAAS4YuK
PANH1ZsZH+gQiyghEL2FWZv9WrlZdcioe94J6vlV6rZBZGm/88hsKLFGQs+lI1NI
eAhN61y/4H8Y5+0uODws5JVFDh2Svdi1vjac21y2udnW4S65db9O7+v4xeMI/AKZ
MGEop7s38lYNGaRtNW7805iirMPl8NcIKPZFX5GMwe9QaYYliKGGrZNKD1hbErtj
6PdkAKJRisTW474RWGsg6jS3OZnVC6cnLyViO7NIGBuoSWn50g8u0EpxG8nA2ueC
kTdo8bFz8dVRGhrJK4KjXTsl8Ut+tPZ2M3XFGzsV3f5faF/DV1v63t81UWzZjQKG
tGyV4lWozfVeZgwRfMQoKmgsDmho3a6pTzRNhSwerom5bYURyLM+unwK3MHPFwFj
5HQiwiekLDopftmoOIl6mdvbpVDmMMUhfdosYOvEBz6yHCrZUt86VoQgHOCQzeXk
b/ngO5LTWHh+Gf2r7xsU
=uwkX
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v1 5/8] am33xx: add ELM support
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
` (3 preceding siblings ...)
2012-10-30 22:47 ` [U-Boot] [PATCH v1 4/8] am335x_evm: enable " Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 23:54 ` Tom Rini
2012-10-30 22:47 ` [U-Boot] [PATCH v1 6/8] omap_gpmc: BCH8 support (ELM based) Ilya Yanok
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
From: Mansoor Ahamed <mansoor.ahamed@ti.com>
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
arch/arm/cpu/armv7/am33xx/Makefile | 1 +
arch/arm/cpu/armv7/am33xx/clock.c | 5 +
arch/arm/cpu/armv7/am33xx/elm.c | 213 ++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-am33xx/elm.h | 93 ++++++++++++++
4 files changed, 312 insertions(+)
create mode 100644 arch/arm/cpu/armv7/am33xx/elm.c
create mode 100644 arch/arm/include/asm/arch-am33xx/elm.h
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index c93ac19..96d7304 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -22,6 +22,7 @@ COBJS += mem.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
+COBJS-${CONFIG_NAND_OMAP_GPMC} += elm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 75ec860..ec46f0b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -119,6 +119,11 @@ static void enable_per_clocks(void)
while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
;
+ /* ELM */
+ writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+ while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+ ;
+
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c
new file mode 100644
index 0000000..9586553
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/elm.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * BCH Error Location Module (ELM) support.
+ *
+ * NOTE:
+ * 1. Supports only continuous mode. Dont see need for page mode in uboot
+ * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
+ * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
+ * sets in uboot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/arch/elm.h>
+
+#define ELM_DEFAULT_POLY (0)
+
+struct elm *elm_cfg;
+
+/**
+ * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @poly: Syndrome Polynomial set to use
+ *
+ * Load BCH syndromes based on nibble selection
+ */
+static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+{
+ u32 *ptr;
+ u32 val;
+
+ /* reg 0 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
+ val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
+ (syndrome[3] << 24);
+ writel(val, ptr);
+ /* reg 1 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
+ val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
+ (syndrome[7] << 24);
+ writel(val, ptr);
+
+ /* BCH 8-bit with 26 nibbles (4*8=32) */
+ if (nibbles > 13) {
+ /* reg 2 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
+ val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
+ (syndrome[11] << 24);
+ writel(val, ptr);
+ /* reg 3 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
+ val = syndrome[12] | (syndrome[13] << 8) |
+ (syndrome[14] << 16) | (syndrome[15] << 24);
+ writel(val, ptr);
+ }
+
+ /* BCH 16-bit with 52 nibbles (7*8=56) */
+ if (nibbles > 26) {
+ /* reg 4 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
+ val = syndrome[16] | (syndrome[17] << 8) |
+ (syndrome[18] << 16) | (syndrome[19] << 24);
+ writel(val, ptr);
+
+ /* reg 5 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
+ val = syndrome[20] | (syndrome[21] << 8) |
+ (syndrome[22] << 16) | (syndrome[23] << 24);
+ writel(val, ptr);
+
+ /* reg 6 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
+ val = syndrome[24] | (syndrome[25] << 8) |
+ (syndrome[26] << 16) | (syndrome[27] << 24);
+ writel(val, ptr);
+ }
+}
+
+/**
+ * elm_check_errors - Check for BCH errors and return error locations
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @error_count: Returns number of errrors in the syndrome
+ * @error_locations: Returns error locations (in decimal) in this array
+ *
+ * Check the provided syndrome for BCH errors and return error count
+ * and locations in the array passed. Returns -1 if error is not correctable,
+ * else returns 0
+ */
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations)
+{
+ u8 poly = ELM_DEFAULT_POLY;
+ s8 i;
+ u32 location_status;
+
+ elm_load_syndromes(syndrome, nibbles, poly);
+
+ /* start processing */
+ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
+ | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
+ &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+
+ /* wait for processing to complete */
+ while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
+ ;
+ /* clear status */
+ writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
+ &elm_cfg->irqstatus);
+
+ /* check if correctable */
+ location_status = readl(&elm_cfg->error_location[poly].location_status);
+ if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
+ return -1;
+
+ /* get error count */
+ *error_count = readl(&elm_cfg->error_location[poly].location_status) &
+ ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+
+ for (i = 0; i < *error_count; i++) {
+ error_locations[i] =
+ readl(&elm_cfg->error_location[poly].error_location_x[i]);
+ }
+
+ return 0;
+}
+
+
+/**
+ * elm_config - Configure ELM module
+ * @level: 4 / 8 / 16 bit BCH
+ *
+ * Configure ELM module based on BCH level.
+ * Set mode as continuous mode.
+ * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
+ * Also, the mode is set only for syndrome 0
+ */
+int elm_config(enum bch_level level)
+{
+ u32 val;
+ u8 poly = ELM_DEFAULT_POLY;
+ u32 buffer_size = 0x7FF;
+
+ /* config size and level */
+ val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
+ val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
+ ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
+ writel(val, &elm_cfg->location_config);
+
+ /* config continous mode */
+ /* enable interrupt generation for syndrome polynomial set */
+ writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
+ &elm_cfg->irqenable);
+ /* set continuous mode for the syndrome polynomial set */
+ writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
+ &elm_cfg->page_ctrl);
+
+ return 0;
+}
+
+/**
+ * elm_reset - Do a soft reset of ELM
+ *
+ * Perform a soft reset of ELM and return after reset is done.
+ */
+void elm_reset(void)
+{
+ /* initiate reset */
+ writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
+ &elm_cfg->sysconfig);
+
+ /* wait for reset complete and normal operation */
+ while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
+ ELM_SYSSTATUS_RESETDONE)
+ ;
+}
+
+/**
+ * elm_init - Initialize ELM module
+ *
+ * Initialize ELM support. Currently it does only base address init
+ * and ELM reset.
+ */
+void elm_init(void)
+{
+ elm_cfg = (struct elm *)ELM_BASE;
+ elm_reset();
+}
+
diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/arch-am33xx/elm.h
new file mode 100644
index 0000000..e80f7d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/elm.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2)
+#define ELM_SYSCONFIG_SOFTRESET (0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK (0x1)
+#define ELM_SYSSTATUS_RESETDONE (0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+ BCH_4_BIT = 0,
+ BCH_8_BIT,
+ BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+ u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */
+ u8 res1[36]; /* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+ u32 location_status; /* 0x800 */
+ u8 res1[124]; /* 0x804 */
+ u32 error_location_x[16]; /* 0x880.... */
+ u8 res2[64]; /* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+ u32 rev; /* 0x000 */
+ u8 res1[12]; /* 0x004 */
+ u32 sysconfig; /* 0x010 */
+ u32 sysstatus; /* 0x014 */
+ u32 irqstatus; /* 0x018 */
+ u32 irqenable; /* 0x01c */
+ u32 location_config; /* 0x020 */
+ u8 res2[92]; /* 0x024 */
+ u32 page_ctrl; /* 0x080 */
+ u8 res3[892]; /* 0x084 */
+ struct syndrome syndrome_fragments[8]; /* 0x400 */
+ u8 res4[512]; /* 0x600 */
+ struct location error_location[8]; /* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 5/8] am33xx: add ELM support
2012-10-30 22:47 ` [U-Boot] [PATCH v1 5/8] am33xx: add ELM support Ilya Yanok
@ 2012-10-30 23:54 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2012-10-30 23:54 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/30/12 15:47, Ilya Yanok wrote:
> From: Mansoor Ahamed <mansoor.ahamed@ti.com>
>
> AM33XX has Error Location Module (ELM) that can be used in
> conjuction with GPMC controller to implement BCH codes fully in
> hardware. This code is mostly taken from arago tree.
>
> Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com> ---
> arch/arm/cpu/armv7/am33xx/Makefile | 1 +
> arch/arm/cpu/armv7/am33xx/clock.c | 5 +
> arch/arm/cpu/armv7/am33xx/elm.c | 213
> ++++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-am33xx/elm.h | 93 ++++++++++++++ 4
> files changed, 312 insertions(+) create mode 100644
> arch/arm/cpu/armv7/am33xx/elm.c create mode 100644
> arch/arm/include/asm/arch-am33xx/elm.h
>
> diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
> b/arch/arm/cpu/armv7/am33xx/Makefile index c93ac19..96d7304 100644
> --- a/arch/arm/cpu/armv7/am33xx/Makefile +++
> b/arch/arm/cpu/armv7/am33xx/Makefile @@ -22,6 +22,7 @@ COBJS +=
> mem.o COBJS += ddr.o COBJS += emif4.o COBJS += board.o
> +COBJS-${CONFIG_NAND_OMAP_GPMC} += elm.o
Wrong braces.
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQkGivAAoJENk4IS6UOR1WJvgP/Rp8PSUX4mXyqJl4tXIo0CRU
jW/wqfLqPMp9Gilg5X1CnihgLJ76iqTgxnsdWoui1Xla9shv4qq5zUF7oxvatDyC
6vw2t3PbVxJigt+j7EeiXsRo1SpwNLxG3LRRBZqa8bt/oB3915Fe9u2kD6DSnxlT
apeoeTRyN2epHL2wKPYNumwUzZ2MlzkudMTIdTkAhhcNW9klpVbGfQlpLaBvpPDD
0zPGH9GqAorZ+ztDYy6zd5uym4kmGx/DIvJZj8dEYpcHMPVefNEhZhwxYg7SDJb2
zTtNpvDCntYBdVIAxoSsIu9eEr0kWtBezMsyjrKf3ezviGu7rKAKFVGxPvnNMH4A
DIW+d7hXbXM4scU5woNXLE+QVstcKZvpGpXaKBj1KelJ3879asWxHxY4MHobw4HM
UTGkMbumUwjMVWOcW8nVIBTwX8OYfmgOq3xlW0Zk37f1AholljIsh6as8lq6ZcZi
LAL0FyZvN00YFk8Futw+pm1tujPyOL/IsxES2vKNHjg595gxCaI/8ArEN+o50Fd4
DEf89osTzUXBQ8gHfw4plFXBoSXzYrwSN/kc84smotll+JG0rghFkNgM4gyqzXkI
46xyXXJW/AB7yO6ahDopCkRobgsQOT6jrjzDYXjjFKKrL/wKcxcAa1EmA98NbtOH
WGafDRFYjlnCRjlwA3CG
=wE+y
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v1 6/8] omap_gpmc: BCH8 support (ELM based)
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
` (4 preceding siblings ...)
2012-10-30 22:47 ` [U-Boot] [PATCH v1 5/8] am33xx: add ELM support Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX Ilya Yanok
2012-10-30 22:47 ` [U-Boot] [PATCH v1 8/8] am335x_evm: enable SPL NAND support Ilya Yanok
7 siblings, 0 replies; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
From: Mansoor Ahamed <mansoor.ahamed@ti.com>
This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
arch/arm/cpu/armv7/am33xx/board.c | 4 +-
drivers/mtd/nand/omap_gpmc.c | 403 ++++++++++++++++++++++++++++++++++++-
2 files changed, 405 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 71f66ef..eed0c0a 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -311,7 +311,9 @@ do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
goto usage;
- if (strncmp(argv[1], "hw", 2) == 0)
+ if (strncmp(argv[1], "bch8", 4) == 0)
+ omap_nand_switch_ecc(2);
+ else if (strncmp(argv[1], "hw", 2) == 0)
omap_nand_switch_ecc(1);
else if (strncmp(argv[1], "sw", 2) == 0)
omap_nand_switch_ecc(0);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index f1469d1..cee394e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -29,6 +29,9 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/compiler.h>
#include <nand.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/elm.h>
+#endif
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
@@ -234,6 +237,370 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
}
}
+/*
+ * BCH8 support (needs ELM and thus AM33xx-only)
+ */
+#ifdef CONFIG_AM33XX
+struct nand_bch_priv {
+ uint8_t mode;
+ uint8_t type;
+ uint8_t nibbles;
+};
+
+/* bch types */
+#define ECC_BCH4 0
+#define ECC_BCH8 1
+#define ECC_BCH16 2
+
+/* BCH nibbles for diff bch levels */
+#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
+#define ECC_BCH4_NIBBLES 13
+#define ECC_BCH8_NIBBLES 26
+#define ECC_BCH16_NIBBLES 52
+
+static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+
+static struct nand_bch_priv bch_priv = {
+ .mode = NAND_ECC_HW_BCH,
+ .type = ECC_BCH8,
+ .nibbles = ECC_BCH8_NIBBLES
+};
+
+/*
+ * omap_read_bch8_result - Read BCH result for BCH8 level
+ *
+ * @mtd: MTD device structure
+ * @big_endian: When set read register 3 first
+ * @ecc_code: Read syndrome from BCH result registers
+ */
+static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+ uint8_t *ecc_code)
+{
+ uint32_t *ptr;
+ int8_t i = 0, j;
+
+ if (big_endian) {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ }
+ } else {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ptr++;
+ }
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ecc_code[i++] = 0; /* 14th byte is always zero */
+ }
+}
+
+/*
+ * omap_ecc_disable - Disable H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ *
+ */
+static void omap_ecc_disable(struct mtd_info *mtd)
+{
+ writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
+ &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_rotate_ecc_bch - Rotate the syndrome bytes
+ *
+ * @mtd: MTD device structure
+ * @calc_ecc: ECC read from ECC registers
+ * @syndrome: Rotated syndrome will be retuned in this array
+ *
+ */
+static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
+ uint8_t *syndrome)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t n_bytes = 0;
+ int8_t i, j;
+
+ switch (bch->type) {
+ case ECC_BCH4:
+ n_bytes = 8;
+ break;
+
+ case ECC_BCH16:
+ n_bytes = 28;
+ break;
+
+ case ECC_BCH8:
+ default:
+ n_bytes = 13;
+ break;
+ }
+
+ for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
+ syndrome[i] = calc_ecc[j];
+}
+
+/*
+ * omap_calculate_ecc_bch - Read BCH ECC result
+ *
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t big_endian = 1;
+ int8_t ret = 0;
+
+ if (bch->type == ECC_BCH8)
+ omap_read_bch8_result(mtd, big_endian, ecc_code);
+ else /* BCH4 and BCH16 currently not supported */
+ ret = -1;
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ omap_ecc_disable(mtd);
+
+ return ret;
+}
+
+/*
+ * omap_fix_errors_bch - Correct bch error in the data
+ *
+ * @mtd: MTD device structure
+ * @data: Data read from flash
+ * @error_count:Number of errors in data
+ * @error_loc: Locations of errors in the data
+ *
+ */
+static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
+ uint32_t error_count, uint32_t *error_loc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t count = 0;
+ uint32_t error_byte_pos;
+ uint32_t error_bit_mask;
+ uint32_t last_bit = (bch->nibbles * 4) - 1;
+
+ /* Flip all bits as specified by the error location array. */
+ /* FOR( each found error location flip the bit ) */
+ for (count = 0; count < error_count; count++) {
+ if (error_loc[count] > last_bit) {
+ /* Remove the ECC spare bits from correction. */
+ error_loc[count] -= (last_bit + 1);
+ /* Offset bit in data region */
+ error_byte_pos = ((512 * 8) -
+ (error_loc[count]) - 1) / 8;
+ /* Error Bit mask */
+ error_bit_mask = 0x1 << (error_loc[count] % 8);
+ /* Toggle the error bit to make the correction. */
+ data[error_byte_pos] ^= error_bit_mask;
+ }
+ }
+}
+
+/*
+ * omap_correct_data_bch - Compares the ecc read from nand spare area
+ * with ECC registers values and corrects one bit error if it has occured
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash (ignored)
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t syndrome[28];
+ uint32_t error_count = 0;
+ uint32_t error_loc[8];
+ uint32_t i, ecc_flag;
+
+ ecc_flag = 0;
+ for (i = 0; i < chip->ecc.bytes; i++)
+ if (read_ecc[i] != 0xff)
+ ecc_flag = 1;
+
+ if (!ecc_flag)
+ return 0;
+
+ elm_reset();
+ elm_config((enum bch_level)(bch->type));
+
+ /*
+ * while reading ECC result we read it in big endian.
+ * Hence while loading to ELM we have rotate to get the right endian.
+ */
+ omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
+
+ /* use elm module to check for errors */
+ if (elm_check_error(syndrome, bch->nibbles, &error_count,
+ error_loc) != 0) {
+ printf("ECC: uncorrectable.\n");
+ return -1;
+ }
+
+ /* correct bch error */
+ if (error_count > 0)
+ omap_fix_errors_bch(mtd, dat, error_count, error_loc);
+
+ return 0;
+}
+/*
+ * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+{
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+ uint32_t unused_length = 0;
+ struct nand_bch_priv *bch = chip->priv;
+
+ switch (bch->nibbles) {
+ case ECC_BCH4_NIBBLES:
+ unused_length = 3;
+ break;
+ case ECC_BCH8_NIBBLES:
+ unused_length = 2;
+ break;
+ case ECC_BCH16_NIBBLES:
+ unused_length = 0;
+ break;
+ }
+
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ switch (mode) {
+ case NAND_ECC_WRITE:
+ /* eccsize1 config */
+ val = ((unused_length + bch->nibbles) << 22);
+ break;
+
+ case NAND_ECC_READ:
+ default:
+ /* by default eccsize0 selected for ecc1resultsize */
+ /* eccsize0 config */
+ val = (bch->nibbles << 12);
+ /* eccsize1 config */
+ val |= (unused_length << 22);
+ break;
+ }
+ /* ecc size configuration */
+ writel(val, &gpmc_cfg->ecc_size_config);
+ /* by default 512bytes sector page is selected */
+ /* set bch mode */
+ val = (1 << 16);
+ /* bch4 / bch8 / bch16 */
+ val |= (bch->type << 12);
+ /* set wrap mode to 1 */
+ val |= (1 << 8);
+ val |= (dev_width << 7);
+ val |= (cs << 1);
+ writel(val, &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ *
+ */
+static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ omap_hwecc_init_bch(chip, mode);
+ /* enable ecc */
+ writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
+}
+
+/**
+ * omap_read_page_bch - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ */
+static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint8_t *oob = chip->oob_poi;
+ uint32_t data_pos;
+ uint32_t oob_pos;
+
+ data_pos = 0;
+ /* oob area start */
+ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
+ oob += chip->ecc.layout->eccpos[0];
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
+ oob += eccbytes) {
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ /* read data */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
+ chip->read_buf(mtd, p, eccsize);
+
+ /* read respective ecc from oob area */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
+ chip->read_buf(mtd, oob, eccbytes);
+ /* read syndrome */
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ }
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+#endif /* CONFIG_AM33XX */
+
#ifndef CONFIG_SPL_BUILD
/*
* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
@@ -269,7 +636,7 @@ void omap_nand_switch_ecc(int32_t hardware)
nand->ecc.calculate = NULL;
/* Setup the ecc configurations again */
- if (hardware) {
+ if (hardware == 1) {
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = &hw_nand_oob;
nand->ecc.size = 512;
@@ -279,6 +646,19 @@ void omap_nand_switch_ecc(int32_t hardware)
nand->ecc.calculate = omap_calculate_ecc;
omap_hwecc_init(nand);
printf("HW ECC selected\n");
+#ifdef CONFIG_AM33XX
+ } else if (hardware == 2) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 14;
+ nand->ecc.read_page = omap_read_page_bch;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+ printf("HW BCH8 selected\n");
+#endif
} else {
nand->ecc.mode = NAND_ECC_SOFT;
/* Use mtd default settings */
@@ -350,7 +730,27 @@ int board_nand_init(struct nand_chip *nand)
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
+
+#ifdef CONFIG_AM33XX
+ /* required in case of BCH */
+ elm_init();
+
+ /* BCH info that will be correct for SPL or overridden otherwise. */
+ nand->priv = &bch_priv;
+#endif
+
/* Default ECC mode */
+#ifdef CONFIG_AM33XX
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ nand->ecc.read_page = omap_read_page_bch;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+#else
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
nand->ecc.mode = NAND_ECC_SOFT;
#else
@@ -363,6 +763,7 @@ int board_nand_init(struct nand_chip *nand)
nand->ecc.calculate = omap_calculate_ecc;
omap_hwecc_init(nand);
#endif
+#endif
#ifdef CONFIG_SPL_BUILD
if (nand->options & NAND_BUSWIDTH_16)
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
` (5 preceding siblings ...)
2012-10-30 22:47 ` [U-Boot] [PATCH v1 6/8] omap_gpmc: BCH8 support (ELM based) Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
2012-10-31 0:03 ` Tom Rini
2012-10-30 22:47 ` [U-Boot] [PATCH v1 8/8] am335x_evm: enable SPL NAND support Ilya Yanok
7 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
AM33XX with BCH8 can't work with nand_spl_simple correctly
because custom read_page implementation is required for proper
syndrome generation.
This simple driver mostly duplicates nand_spl_simple but has
nand_read_page changed to suit our needs.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/am335x_spl_bch.c | 238 +++++++++++++++++++++++++++++++++++++
2 files changed, 239 insertions(+)
create mode 100644 drivers/mtd/nand/am335x_spl_bch.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index beb99ca..5322f3a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -30,6 +30,7 @@ ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_NAND_SIMPLE
COBJS-y += nand_spl_simple.o
endif
+COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
ifdef CONFIG_SPL_NAND_LOAD
COBJS-y += nand_spl_load.o
endif
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
new file mode 100644
index 0000000..b84528b
--- /dev/null
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2012
+ * Konstantin Kozhevnikov, Cogent Embedded
+ *
+ * based on nand_spl_simple code
+ *
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/nand_ecc.h>
+
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+
+
+/*
+ * NAND command for large page NAND devices (2k)
+ */
+static int nand_command(int block, int page, uint32_t offs,
+ u8 cmd)
+{
+ struct nand_chip *this = mtd.priv;
+ int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ void (*hwctrl)(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl) = this->cmd_ctrl;
+
+ while (!this->dev_ready(&mtd))
+ ;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (cmd == NAND_CMD_READOOB) {
+ offs += CONFIG_SYS_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
+ /* Begin command latch cycle */
+ hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+
+ if (cmd == NAND_CMD_RESET) {
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(&mtd))
+ ;
+ return 0;
+ }
+
+ /* Shift the offset from byte addressing to word addressing. */
+ if (this->options & NAND_BUSWIDTH_16)
+ offs >>= 1;
+
+ /* Set ALE and clear CLE to start address cycle */
+ /* Column address */
+ hwctrl(&mtd, offs & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ /* Row address */
+ hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+ NAND_CTRL_ALE); /* A[27:20] */
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices > 128MiB */
+ hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ NAND_CTRL_ALE); /* A[31:28] */
+#endif
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ if (cmd == NAND_CMD_READ0) {
+ /* Latch in address */
+ hwctrl(&mtd, NAND_CMD_READSTART,
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ while (!this->dev_ready(&mtd))
+ ;
+ } else if (cmd == NAND_CMD_RNDOUT) {
+ hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ NAND_CTRL_CHANGE);
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ }
+
+ return 0;
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct nand_chip *this = mtd.priv;
+
+ nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+ NAND_CMD_READOOB);
+
+ /*
+ * Read one byte (or two if it's a 16 bit chip).
+ */
+ if (this->options & NAND_BUSWIDTH_16) {
+ if (readw(this->IO_ADDR_R) != 0xffff)
+ return 1;
+ } else {
+ if (readb(this->IO_ADDR_R) != 0xff)
+ return 1;
+ }
+
+ return 0;
+}
+
+static int nand_read_page(int block, int page, void *dst)
+{
+ struct nand_chip *this = mtd.priv;
+ u_char ecc_calc[ECCTOTAL];
+ u_char ecc_code[ECCTOTAL];
+ u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
+ int i;
+ int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+ int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsteps = ECCSTEPS;
+ uint8_t *p = dst;
+ uint32_t data_pos = 0;
+ uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
+ uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
+
+ nand_command(block, page, 0, NAND_CMD_READ0);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
+
+ this->read_buf(&mtd, p, eccsize);
+
+ nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
+
+ this->read_buf(&mtd, oob, eccbytes);
+ this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ oob += eccbytes;
+ }
+
+ /* Pick the ECC bytes out of the oob data */
+ for (i = 0; i < ECCTOTAL; i++)
+ ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+ eccsteps = ECCSTEPS;
+ p = dst;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ /* No chance to do something with the possible error message
+ * from correct_data(). We just hope that all possible errors
+ * are corrected by this routine.
+ */
+ this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ }
+
+ return 0;
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ unsigned int block, lastblock;
+ unsigned int page;
+
+ /*
+ * offs has to be aligned to a page address!
+ */
+ block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
+ lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
+ page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+
+ while (block <= lastblock) {
+ if (!nand_is_bad_block(block)) {
+ /*
+ * Skip bad blocks
+ */
+ while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+ nand_read_page(block, page, dst);
+ dst += CONFIG_SYS_NAND_PAGE_SIZE;
+ page++;
+ }
+
+ page = 0;
+ } else {
+ lastblock++;
+ }
+
+ block++;
+ }
+
+ return 0;
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+ /*
+ * Init board specific nand support
+ */
+ mtd.priv = &nand_chip;
+ nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
+ (void __iomem *)CONFIG_SYS_NAND_BASE;
+ board_nand_init(&nand_chip);
+
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, 0);
+
+ /* NAND chip may require reset after power-on */
+ nand_command(0, 0, 0, NAND_CMD_RESET);
+}
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, -1);
+}
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX
2012-10-30 22:47 ` [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX Ilya Yanok
@ 2012-10-31 0:03 ` Tom Rini
2012-11-03 16:21 ` Ilya Yanok
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2012-10-31 0:03 UTC (permalink / raw)
To: u-boot
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 10/30/12 15:47, Ilya Yanok wrote:
> AM33XX with BCH8 can't work with nand_spl_simple correctly because
> custom read_page implementation is required for proper syndrome
> generation.
>
> This simple driver mostly duplicates nand_spl_simple but has
> nand_read_page changed to suit our needs.
[snip]
> + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> + this->ecc.hwctl(&mtd, NAND_ECC_READ); + nand_command(block,
> page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
> eccsize); + + nand_command(block, page, oob_pos,
> NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
> this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
> eccsize; + oob_pos += eccbytes; + oob += eccbytes; + }
This is where the function differs. If we can't merge things
together, I'd like to see about putting just this function into
nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow
what's going on, and I need to play with the code to confirm I do,
it's a generic change related to how much more we're reading back out
now. But good catch finding what was going wrong with nand_spl_simple
here.
- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
iQIcBAEBAgAGBQJQkGrJAAoJENk4IS6UOR1WnqMP/3i/zWcvB7iZhjl5HvrlrYuQ
+6ijXtQzWCROKP/gERTQjKlVOj09jEGvHY5Ac5xpiMqtxvCAxDyz88fu5CWJgtlT
gZJqq7WPaR21FHJzS5GinL7oQBNMY9/m1wNVCVHq971Lq4VxgfYPXdPMytiMPxOy
ExoB034z6KkaFR7FdRFLMZeT9ri292jFlmZuNpyKjjEYigI4+WH4FvlkFxEpL18w
F+bXWzp4Krd8ndgM3OjvzJWmPZxU3M1YjHKOn631W8T2Q7bMe6yOH9PEYKiqQuTG
wniwcmxB6n2vT04enyuUPCfyNA9OPJv7w+pGWdrYXjU22CHUbNfywJZC7sqmYeht
uUhvvdF8jtJFHpK1RScF69Gy2xcmtIa7PPMmLkv3JbtnLgw91NyeM+tuzty2/MIA
icsbE1PwxvLGSMlvJJhag82oKb4kYZ1I5SSmd5aJkyt21CbXiBKf6M+Vsx8TmyCh
03XTuN7iuMpm4jlEed4bv64yLZ7suJxu60XtKAH5yX5S6L8PI+SAEpzknLdqCf7j
A2z8YyLZEaxa27oxOmY4/G8KTpZrPNkei4jL9VOd7wkZ/j9TRUZ6rzrIHVuwWlqS
oVJt/qHq+zznQFZF3iI3kPUtiU1FpiPycPzSevH+V3gZNFdNF1Ze9+VqEyW2QV60
nVRZjXS9VSKeR43dXBgg
=giFN
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX
2012-10-31 0:03 ` Tom Rini
@ 2012-11-03 16:21 ` Ilya Yanok
2012-11-05 16:57 ` Tom Rini
0 siblings, 1 reply; 16+ messages in thread
From: Ilya Yanok @ 2012-11-03 16:21 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Wed, Oct 31, 2012 at 1:03 AM, Tom Rini <trini@ti.com> wrote:
>
> > + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> > + this->ecc.hwctl(&mtd, NAND_ECC_READ); +
> nand_command(block,
> > page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
> > eccsize); + + nand_command(block, page, oob_pos,
> > NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
> > this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
> > eccsize; + oob_pos += eccbytes; + oob += eccbytes; +
> }
>
> This is where the function differs. If we can't merge things
> together, I'd like to see about putting just this function into
> nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow
> what's going on, and I need to play with the code to confirm I do,
> it's a generic change related to how much more we're reading back out
>
Not exactly. This change is rather GPMC-specific: we have to read data
block then it's ecc code to get the syndrome. And even with GPMC in another
configuration we will need another reading order...
I'm not sure if we can do this in some generic way...
Regards, Ilya.
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX
2012-11-03 16:21 ` Ilya Yanok
@ 2012-11-05 16:57 ` Tom Rini
0 siblings, 0 replies; 16+ messages in thread
From: Tom Rini @ 2012-11-05 16:57 UTC (permalink / raw)
To: u-boot
On Sat, Nov 03, 2012 at 05:21:46PM +0100, Ilya Yanok wrote:
> Hi Tom,
>
> On Wed, Oct 31, 2012 at 1:03 AM, Tom Rini <trini@ti.com> wrote:
> >
> > > + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
> > > + this->ecc.hwctl(&mtd, NAND_ECC_READ); +
> > nand_command(block,
> > > page, data_pos, NAND_CMD_RNDOUT); + + this->read_buf(&mtd, p,
> > > eccsize); + + nand_command(block, page, oob_pos,
> > > NAND_CMD_RNDOUT); + + this->read_buf(&mtd, oob, eccbytes); +
> > > this->ecc.calculate(&mtd, p, &ecc_calc[i]); + + data_pos +=
> > > eccsize; + oob_pos += eccbytes; + oob += eccbytes; +
> > }
> >
> > This is where the function differs. If we can't merge things
> > together, I'd like to see about putting just this function into
> > nand_spl_simple.c under CONFIG_SYS_NAND_HW_BCH8 since if I follow
> > what's going on, and I need to play with the code to confirm I do,
> > it's a generic change related to how much more we're reading back out
>
> Not exactly. This change is rather GPMC-specific: we have to read data
> block then it's ecc code to get the syndrome. And even with GPMC in another
> configuration we will need another reading order...
> I'm not sure if we can do this in some generic way...
OK, lets just leave that part alone for now. Maybe we need to allow for
some abstraction or __weak in the SPL read case, but we can revisit this
a little later on once we're able to see how say BCH16 behaves too.
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20121105/bb19fb13/attachment.pgp>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v1 8/8] am335x_evm: enable SPL NAND support
2012-10-30 22:47 [U-Boot] [PATCH v1 0/8] NAND support for AM33XX Ilya Yanok
` (6 preceding siblings ...)
2012-10-30 22:47 ` [U-Boot] [PATCH v1 7/8] am33xx_spl_bch: simple SPL nand loader for AM33XX Ilya Yanok
@ 2012-10-30 22:47 ` Ilya Yanok
7 siblings, 0 replies; 16+ messages in thread
From: Ilya Yanok @ 2012-10-30 22:47 UTC (permalink / raw)
To: u-boot
Enable booting from NAND support from AM335x boards as well as
environment in NAND.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
include/configs/am335x_evm.h | 38 ++++++++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a89cdcd..67e99aa 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -220,6 +220,35 @@
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+
+#define CONFIG_SYS_NAND_ECCSTEPS 4
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
@@ -266,7 +295,12 @@
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
-#endif /* devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
+ devices */
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#endif
#endif /* ! __CONFIG_AM335X_EVM_H */
--
1.7.10.2 (Apple Git-33)
^ permalink raw reply related [flat|nested] 16+ messages in thread