From: "Andreas Färber" <afaerber@suse.de>
To: will.auld@intel.com
Cc: Will Auld <will.auld.intel@gmail.com>,
qemu-devel <qemu-devel@nongnu.org>, Gleb <gleb@redhat.com>,
"mtosatti@redhat.com" <mtosatti@redhat.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"donald.d.dugger@intel.com" <donald.d.dugger@intel.com>,
"jinsong.liu@intel.com" <jinsong.liu@intel.com>,
"xiantao.zhang@intel.com" <xiantao.zhang@intel.com>,
"avi@redhat.com" <avi@redhat.com>
Subject: Re: [Qemu-devel] [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs
Date: Fri, 30 Nov 2012 15:35:54 +0100 [thread overview]
Message-ID: <50B8C44A.6080404@suse.de> (raw)
In-Reply-To: <1353994338.31363.15.camel@WillAuldHomeLinux>
Am 27.11.2012 06:32, schrieb Will Auld:
> CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated MSRs.
> In this way the IA32_TSC_ADJUST value will be included in all reads to
> the TSC MSR whether through rdmsr or rdtsc.
>
> As this is a new MSR that the guest may access and modify its value needs
> to be migrated along with the other MRSs. The changes here are specifically
> for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
> for migrating its value.
>
> Signed-off-by: Will Auld <will.auld@intel.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
from the CPU perspective.
Thanks,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
WARNING: multiple messages have this Message-ID (diff)
From: "Andreas Färber" <afaerber@suse.de>
To: will.auld@intel.com
Cc: "jinsong.liu@intel.com" <jinsong.liu@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
Gleb <gleb@redhat.com>,
"mtosatti@redhat.com" <mtosatti@redhat.com>,
Will Auld <will.auld.intel@gmail.com>,
qemu-devel <qemu-devel@nongnu.org>,
"donald.d.dugger@intel.com" <donald.d.dugger@intel.com>,
"avi@redhat.com" <avi@redhat.com>
Subject: Re: [Qemu-devel] [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs
Date: Fri, 30 Nov 2012 15:35:54 +0100 [thread overview]
Message-ID: <50B8C44A.6080404@suse.de> (raw)
In-Reply-To: <1353994338.31363.15.camel@WillAuldHomeLinux>
Am 27.11.2012 06:32, schrieb Will Auld:
> CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated MSRs.
> In this way the IA32_TSC_ADJUST value will be included in all reads to
> the TSC MSR whether through rdmsr or rdtsc.
>
> As this is a new MSR that the guest may access and modify its value needs
> to be migrated along with the other MRSs. The changes here are specifically
> for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
> for migrating its value.
>
> Signed-off-by: Will Auld <will.auld@intel.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
from the CPU perspective.
Thanks,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2012-11-30 14:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-27 5:32 [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs Will Auld
2012-11-27 5:32 ` [Qemu-devel] " Will Auld
2012-11-30 14:35 ` Andreas Färber [this message]
2012-11-30 14:35 ` Andreas Färber
2012-11-30 20:39 ` Marcelo Tosatti
2012-11-30 20:39 ` [Qemu-devel] " Marcelo Tosatti
2012-11-30 20:45 ` Auld, Will
2012-11-30 20:45 ` [Qemu-devel] " Auld, Will
2013-02-06 22:22 ` Auld, Will
2013-02-06 23:35 ` Marcelo Tosatti
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