* [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
@ 2012-12-13 22:15 Steven J. Hill
2012-12-13 23:27 ` Maciej W. Rozycki
0 siblings, 1 reply; 6+ messages in thread
From: Steven J. Hill @ 2012-12-13 22:15 UTC (permalink / raw)
To: linux-mips; +Cc: Steven J. Hill, ralf
From: "Steven J. Hill" <sjhill@mips.com>
Allow reading of CP0 config registers via sysfs for each core
in the system. The registers will show up in sysfs at the path:
/sys/devices/system/cpu/cpuX/configX
Hotplugging of CPUs is also supported.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
---
arch/mips/kernel/Makefile | 1 +
arch/mips/kernel/sysfs.c | 118 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 119 insertions(+)
create mode 100644 arch/mips/kernel/sysfs.c
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index cc5eec6..0c3eb97 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
+obj-y += sysfs.o
ifeq ($(CONFIG_CPU_MIPS32), y)
#
diff --git a/arch/mips/kernel/sysfs.c b/arch/mips/kernel/sysfs.c
new file mode 100644
index 0000000..1c02471
--- /dev/null
+++ b/arch/mips/kernel/sysfs.c
@@ -0,0 +1,118 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
+ */
+#include <linux/sched.h>
+#include <linux/device.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/stat.h>
+
+#include <asm/page.h>
+
+#define read_c0_config0() read_c0_config()
+
+#define __BUILD_CP0_SYSFS(reg) \
+static ssize_t show_config##reg(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
+{ \
+ int n = snprintf(buf, PAGE_SIZE-2, "%x\n", \
+ read_c0_config##reg()); \
+ return n; \
+} \
+static DEVICE_ATTR(config##reg, S_IRUGO, show_config##reg, NULL);
+
+__BUILD_CP0_SYSFS(0)
+__BUILD_CP0_SYSFS(1)
+__BUILD_CP0_SYSFS(2)
+__BUILD_CP0_SYSFS(3)
+__BUILD_CP0_SYSFS(4)
+__BUILD_CP0_SYSFS(5)
+__BUILD_CP0_SYSFS(6)
+__BUILD_CP0_SYSFS(7)
+
+static DEFINE_PER_CPU(unsigned int, nregs);
+
+#define __CREATE_CONFIG_ENTRY(reg) \
+if (ok) { \
+ device_create_file(dev, &dev_attr_config##reg); \
+ ok = read_c0_config##reg() & MIPS_CONF_M; \
+ per_cpu(nregs, cpu)++; \
+}
+
+#define __DELETE_CONFIG_ENTRY(reg) \
+if (reg < per_cpu(nregs, cpu)) \
+ device_remove_file(dev, &dev_attr_config##reg);
+
+static void create_cp0_entries(unsigned int cpu)
+{
+ struct device *dev = get_cpu_device(cpu);
+ int ok = 1;
+
+ per_cpu(nregs, cpu) = 0;
+ __CREATE_CONFIG_ENTRY(0);
+ __CREATE_CONFIG_ENTRY(1);
+ __CREATE_CONFIG_ENTRY(2);
+ __CREATE_CONFIG_ENTRY(3);
+ __CREATE_CONFIG_ENTRY(4);
+ __CREATE_CONFIG_ENTRY(5);
+ __CREATE_CONFIG_ENTRY(6);
+ __CREATE_CONFIG_ENTRY(7);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void delete_cp0_entries(unsigned int cpu)
+{
+ struct device *dev = get_cpu_device(cpu);
+
+ __DELETE_CONFIG_ENTRY(0);
+ __DELETE_CONFIG_ENTRY(1);
+ __DELETE_CONFIG_ENTRY(2);
+ __DELETE_CONFIG_ENTRY(3);
+ __DELETE_CONFIG_ENTRY(4);
+ __DELETE_CONFIG_ENTRY(5);
+ __DELETE_CONFIG_ENTRY(6);
+ __DELETE_CONFIG_ENTRY(7);
+}
+#endif
+
+static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ unsigned int cpu = (unsigned int)(long)hcpu;
+
+ switch (action) {
+ case CPU_ONLINE:
+ case CPU_ONLINE_FROZEN:
+ create_cp0_entries(cpu);
+ break;
+#ifdef CONFIG_HOTPLUG_CPU
+ case CPU_DEAD:
+ case CPU_DEAD_FROZEN:
+ delete_cp0_entries(cpu);
+ break;
+#endif
+ }
+ return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
+ .notifier_call = sysfs_cpu_notify,
+};
+
+static int __init sysfs_mips_config_registers(void)
+{
+ int i;
+
+ for_each_online_cpu(i)
+ create_cp0_entries(i);
+ register_cpu_notifier(&sysfs_cpu_nb);
+ return 0;
+}
+subsys_initcall(sysfs_mips_config_registers);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
2012-12-13 22:15 [PATCH v4] MIPS: Make CP0 config registers readable via sysfs Steven J. Hill
@ 2012-12-13 23:27 ` Maciej W. Rozycki
2012-12-13 23:38 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: Maciej W. Rozycki @ 2012-12-13 23:27 UTC (permalink / raw)
To: Steven J. Hill; +Cc: linux-mips, Ralf Baechle
On Thu, 13 Dec 2012, Steven J. Hill wrote:
> Allow reading of CP0 config registers via sysfs for each core
> in the system. The registers will show up in sysfs at the path:
>
> /sys/devices/system/cpu/cpuX/configX
You're exporting privileged context outside the kernel -- have all the
security implications been considered? At the very least I don't think
these files should be word-readable.
Maciej
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
2012-12-13 23:27 ` Maciej W. Rozycki
@ 2012-12-13 23:38 ` David Daney
2013-01-04 18:38 ` Hill, Steven
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2012-12-13 23:38 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Steven J. Hill, linux-mips, Ralf Baechle
On 12/13/2012 03:27 PM, Maciej W. Rozycki wrote:
> On Thu, 13 Dec 2012, Steven J. Hill wrote:
>
>> Allow reading of CP0 config registers via sysfs for each core
>> in the system. The registers will show up in sysfs at the path:
>>
>> /sys/devices/system/cpu/cpuX/configX
>
> You're exporting privileged context outside the kernel -- have all the
> security implications been considered?
Can you give an example of what would be risky?
> At the very least I don't think
> these files should be word-readable.
>
According to Steven's earlier comments, all he really cares about are
the ASEs implemented.
We have a patch (that I will send soon) that exports the Cache
configurations via the same method that x86 Cache information is
reported, so that part of the config register information would be
reported separately.
The rest of the CP0_ConfigX bits really report things that are only
useful to privileged mode software, so perhaps they shouldn't be reported.
David Daney
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
2012-12-13 23:38 ` David Daney
@ 2013-01-04 18:38 ` Hill, Steven
2013-01-04 19:05 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: Hill, Steven @ 2013-01-04 18:38 UTC (permalink / raw)
To: David Daney, Maciej W. Rozycki
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
> You're exporting privileged context outside the kernel -- have all the
> security implications been considered?
>
Maciej,
I have gone through the config registers bit-by-bit and I do not see where there are any security implications. There are maybe 7 bits total in config registers 0 through 5 that are R/W and this patch, of course, is providing RO access. A motivated person could download the PRA documents from our website even without this patch to discover what was implemented in the system. I could certainly see security implications if we were exporting the STATUS, CAUSE, and other critical registers. Unless you can provide a counterexample, this patch does not compromise the system in anyway.
-Steve
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
2013-01-04 18:38 ` Hill, Steven
@ 2013-01-04 19:05 ` David Daney
2013-01-04 19:30 ` Hill, Steven
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2013-01-04 19:05 UTC (permalink / raw)
To: Hill, Steven
Cc: Maciej W. Rozycki, linux-mips@linux-mips.org, ralf@linux-mips.org
On 01/04/2013 10:38 AM, Hill, Steven wrote:
>> You're exporting privileged context outside the kernel -- have all the
>> security implications been considered?
>>
> Maciej,
>
> I have gone through the config registers bit-by-bit and I do not see
> where there are any security implications.
[...]
> Unless you can provide a counterexample,
> this patch does not compromise the system in anyway.
>
The patch stands alone. Any security problems it might have are
completely unrelated to any hypothetical Counter Examples.
David Daney
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4] MIPS: Make CP0 config registers readable via sysfs.
2013-01-04 19:05 ` David Daney
@ 2013-01-04 19:30 ` Hill, Steven
0 siblings, 0 replies; 6+ messages in thread
From: Hill, Steven @ 2013-01-04 19:30 UTC (permalink / raw)
To: David Daney
Cc: Maciej W. Rozycki, linux-mips@linux-mips.org, ralf@linux-mips.org
> The patch stands alone. Any security problems it might have are
> completely unrelated to any hypothetical Counter Examples.
>
Indeed. So, can I get an ACK or what next? Thanks.
-Steve
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-01-04 19:30 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-12-13 22:15 [PATCH v4] MIPS: Make CP0 config registers readable via sysfs Steven J. Hill
2012-12-13 23:27 ` Maciej W. Rozycki
2012-12-13 23:38 ` David Daney
2013-01-04 18:38 ` Hill, Steven
2013-01-04 19:05 ` David Daney
2013-01-04 19:30 ` Hill, Steven
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.